KR20230103571A - Pixel circuit, display device and driving method - Google Patents

Abstract

Embodiments of the present disclosure relate to a pixel circuit, a display device, and a driving method thereof capable of reducing a current deviation due to a difference in mobility of driving transistors by inducing a voltage programmed for each sub-pixel.

Description

Pixel circuit, display device and driving method thereof {PIXEL CIRCUIT, DISPLAY DEVICE AND DRIVING METHOD}

Embodiments of the present disclosure relate to a pixel circuit, a display device, and a driving method thereof.

Among display devices currently being developed, there is a self-emitting display device in which sub-pixels disposed on a display panel include light emitting elements. Each sub-pixel disposed on a display panel of such a self-emitting display device may include a light emitting element that emits light itself and a driving transistor for driving the light emitting element.

Driving transistors disposed on a display panel of a self-emitting display device may include a threshold voltage and mobility as unique characteristic values. If the threshold voltages and mobilities of the driving transistors disposed on the display panel are different from each other, a luminance deviation may occur between subpixels. Accordingly, luminance uniformity of the display panel may deteriorate and image quality may deteriorate.

Embodiments of the present disclosure may provide a pixel circuit, a display device, and a driving method capable of compensating for variations in characteristic values of driving transistors using an internal compensation method.

Embodiments of the present disclosure may provide a pixel circuit, a display device, and a driving method capable of compensating for a current deviation supplied through driving transistors.

Embodiments of the present disclosure may provide a pixel circuit, a display device, and a driving method thereof capable of reducing a current deviation due to a difference in mobility of driving transistors by inducing a voltage programmed for each sub-pixel.

A display device according to embodiments of the present disclosure includes a plurality of subpixels, and each of the plurality of subpixels has a light emitting element, a driving transistor for driving the light emitting element, and an ON/OFF control of the driving transistor by a scan signal. A scan transistor for switching the connection between the gate node and the data line, a sensing transistor for switching the connection between the source node of the driving transistor and the initialization voltage line whose on-off control is controlled by a sensing signal, and the gate node and driving of the driving transistor A storage capacitor may be included between source nodes of the transistors.

The driving period of each of the plurality of subpixels may include a first period, a second period, a third period, a fourth period, and a fifth period.

During the first period, a reference voltage may be applied to a gate node of the driving transistor, and an initialization voltage may be applied to a source node of the driving transistor.

During the second period after the first period, the reference voltage is continuously applied to the gate node of the driving transistor, the source node of the driving transistor is electrically floated, and the voltage of the source node of the driving transistor may increase.

During the third period after the second period, the source node of the driving transistor is maintained in a floating state, and a pilot voltage different from the reference voltage may be applied to the gate node of the driving transistor.

During the fourth period after the third period, the source node of the driving transistor and the gate node of the driving transistor may be electrically floated, and the voltage of the gate node of the driving transistor and the voltage of the source node of the driving transistor may rise together.

During the fifth period after the fourth period, the image data voltage may be applied to the gate node of the driving transistor.

In the display device according to example embodiments of the present disclosure, each of a plurality of subpixels is turned on and off by a light emission control signal to switch a connection between a drain node of a driving transistor and a driving voltage line; and The device may further include a sampling transistor configured to switch a connection between a drain node of the driving transistor and a body node of the driving transistor by being turned on and off by the sampling signal.

In this case, each of the plurality of subpixels may further include at least one of a first control capacitor between the source node of the driving transistor and the first control node, and a second control capacitor between the body node of the driving transistor and the source node of the driving transistor. can

The first control node may be electrically connected to the driving voltage line.

The second control capacitor may be a built-in capacitor of the driving transistor or an external capacitor of the driving transistor.

In the display device according to example embodiments of the present disclosure, each of a plurality of subpixels is controlled to be turned on or off by a light emission control signal, and further includes a light emission control transistor for switching a connection between a drain node of a driving transistor and a driving voltage line. can include

In the display device according to example embodiments of the present disclosure, each of a plurality of subpixels is turned on and off by a light emission control signal to switch a connection between a drain node of a driving transistor and a driving voltage line; and A reference control transistor for switching a connection between the gate node of the driving transistor and the reference voltage line by being turned on and off controlled by the reference control signal may be further included.

In this case, each of the plurality of subpixels may further include a first control capacitor between the source node of the driving transistor and the first control node.

A method of driving a display device according to embodiments of the present disclosure includes applying a reference voltage to a gate node of a driving transistor in a subpixel and applying an initialization voltage to a source node of a driving transistor in a subpixel during a first period; During a second period thereafter, continuously applying a reference voltage to the gate node of the driving transistor and electrically floating the source node of the driving transistor to increase the voltage of the source node of the driving transistor; maintaining the source node of the driving transistor in a floating state during the period, and applying a pilot voltage different from the reference voltage to the gate node of the driving transistor, during a fourth period after the third period, together with the source node of the driving transistor, The step of electrically floating the gate node of the driving transistor to increase the voltage of the gate node of the driving transistor and the voltage of the source node of the driving transistor together, and during a fifth period after the fourth period, the image data voltage of the driving transistor It may include applying to the gate node.

A pixel circuit according to embodiments of the present disclosure includes a light emitting device, a driving transistor for driving the light emitting device, a scan transistor for switching a connection between a gate node of the driving transistor and a data line by being turned on/off controlled by a scan signal, A sensing transistor for switching the connection between the source node of the driving transistor and the initialization voltage line by controlling on-off by a sensing signal, and switching the connection between the drain node of the driving transistor and the driving voltage line by controlling on-off by a light emitting control signal. A light emitting control transistor for switching the connection, a reference control transistor for switching the connection between the gate node of the driving transistor and the reference voltage line, the gate node of the driving transistor and the source of the driving transistor having ON-OFF controlled by a reference control signal. It may include a storage capacitor between nodes, and a first control capacitor between a source node of a driving transistor and a first control node.

According to the exemplary embodiments of the present disclosure, a pixel circuit, a display device, and a driving method thereof capable of compensating for variations in characteristic values of driving transistors using an internal compensation method may be provided.

According to the exemplary embodiments of the present disclosure, a pixel circuit capable of compensating for a current deviation supplied through driving transistors, a display device, and a driving method thereof may be provided.

According to the exemplary embodiments of the present disclosure, a pixel circuit, a display device, and a driving method thereof capable of reducing a current deviation due to a difference in mobility of driving transistors by inducing a voltage programmed for each sub-pixel may be provided.

1 illustrates a display device according to example embodiments of the present disclosure.
2 is a schematic equivalent circuit of a subpixel of a display device according to example embodiments of the present disclosure.
3 are graphs for explaining a luminance non-uniformity factor of a display device according to example embodiments of the present disclosure.
4 is a driving timing diagram for improving luminance non-uniformity of a display device according to embodiments of the present disclosure.
5 is a pixel circuit of a display device according to example embodiments.
6 and 7 are driving timing diagrams of the pixel circuit of FIG. 5 .
8 is another pixel circuit of a display device according to example embodiments.
9 and 10 are driving timing diagrams of the pixel circuit of FIG. 8 .
11 is another pixel circuit of a display device according to example embodiments.
12 is a driving timing diagram of the pixel circuit of FIG. 11;
13 is a graph illustrating a pilot voltage according to an image data voltage in a display device according to example embodiments.
14 is a graph showing current according to an S factor in a display device according to example embodiments of the present disclosure.
15 is a graph illustrating a current deviation before and after applying compensation driving of a display device according to example embodiments of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present disclosure, when it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When "comprises", "has", "consists of", etc. mentioned in this specification is used, other parts may be added unless "only" is used. In the case where a component is expressed in the singular, it may include the case of including the plural unless otherwise explicitly stated.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present disclosure. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term.

In the description of the positional relationship of components, when it is described that two or more components are "connected", "coupled" or "connected", the two or more components are directly "connected", "coupled" or "connected". ", but it will be understood that two or more components and other components may be further "interposed" and "connected", "coupled" or "connected". Here, other components may be included in one or more of two or more components that are “connected”, “coupled” or “connected” to each other.

In the description of the temporal flow relationship related to components, operation methods, production methods, etc., for example, "after", "continued to", "after", "before", etc. Alternatively, when a flow sequence relationship is described, it may also include non-continuous cases unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (eg, level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or its corresponding information is not indicated by various factors (eg, process factors, internal or external shocks, noise, etc.) may be interpreted as including an error range that may occur.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 shows a display device 100 according to example embodiments.

Referring to FIG. 1 , a display driving system of a display device 100 according to example embodiments may include a display panel 110 and a driving circuit for driving the display panel 110 .

The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The display panel 110 may include a plurality of sub-pixels SP to display an image. For example, a plurality of subpixels SP may be disposed in the display area DA. In some cases, at least one sub-pixel SP may be disposed in the non-display area NDA. At least one subpixel SP disposed in the non-display area NDA is also referred to as a dummy subpixel.

The display panel 110 may include a plurality of signal wires for driving a plurality of subpixels SP. For example, the plurality of signal lines may include a plurality of data lines DL and a plurality of gate lines GL. The signal wires may further include signal wires other than the plurality of data lines DL and the plurality of gate lines GL according to the structure of the subpixel SP. For example, other signal lines may include driving voltage lines and reference voltage lines.

The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be disposed while extending in the first direction. Each of the plurality of gate lines GL may be disposed while extending in the second direction. Here, the first direction may be a column direction and the second direction may be a row direction. In this specification, the column direction and the row direction are relative. For example, a column direction may be a vertical direction and a row direction may be a horizontal direction. For another example, the column direction may be a horizontal direction and the row direction may be a vertical direction.

The driving circuit may include a data driving circuit 120 for driving the plurality of data lines DL and a gate driving circuit 130 for driving the plurality of gate lines GL. The driving circuit may further include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130 .

The data driving circuit 120 is a circuit for driving the plurality of data lines DL, and may output data signals (also referred to as data voltages) corresponding to image signals to the plurality of data lines DL. there is. The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL, and may generate gate signals and output the gate signals to the plurality of gate lines GL.

The controller 140 may start a scan according to the timing implemented in each frame and control data driving at an appropriate time according to the scan. The controller 140 may convert input image data input from the outside to suit a data signal format used by the data driving circuit 120 and supply the converted image data to the data driving circuit 120 .

The controller 140 may receive display driving control signals from the external host system 150 together with input image data. For example, the display driving control signals may include a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal.

The controller 140 may generate data driving control signals DCS and gate driving control signals GCS based on display driving control signals input from the host system 150 . The controller 140 may control the driving operation and driving timing of the data driving circuit 120 by supplying the data driving control signals DCS to the data driving circuit 120 . The controller 140 may control the driving operation and driving timing of the gate driving circuit 130 by supplying the gate driving control signals GCS to the gate driving circuit 130 .

The data driving circuit 120 may include one or more Source Driver Integrated Circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, and the like. In some cases, each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC).

For example, each source driver integrated circuit (SDIC) is connected to the display panel 110 using a tape automated bonding (TAB) method, or a chip on glass (COG) or chip on panel ( It may be connected to the bonding pad of the display panel 110 using a chip on panel (COP) method or may be connected to the display panel 110 by implementing a chip on film (COF) method.

The gate driving circuit 130 may output a gate signal of a turn-on level voltage or output a gate signal of a turn-off level voltage under the control of the controller 140 . The gate driving circuit 130 may sequentially drive the plurality of gate lines GL by sequentially supplying gate signals having turn-on level voltages to the plurality of gate lines GL.

The gate driving circuit 130 is connected to the display panel 110 using a tape automated bonding (TAB) method or is bonded to the display panel 110 using a chip on glass (COG) or chip on panel (COP) method. pad) or connected to the display panel 110 according to a chip on film (COF) method. Alternatively, the gate driving circuit 130 may be formed in the non-display area NDA of the display panel 110 in a gate-in-panel (GIP) type. The gate driving circuit 130 may be disposed on or connected to the substrate. That is, in the case of the GIP type, the gate driving circuit 130 may be disposed in the non-display area NDA of the substrate. The gate driving circuit 130 may be connected to a substrate in the case of a chip on glass (COG) type or a chip on film (COF) type.

Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one driving circuit of the data driving circuit 120 and the gate driving circuit 130 may be disposed not to overlap with the subpixels SP, or partially or entirely with the subpixels SP. They may be arranged overlapping.

The data driving circuit 120 may be connected to one side (eg, upper or lower side) of the display panel 110 . Depending on the driving method and the panel design method, the data driving circuit 120 may be connected to both sides (eg, upper and lower sides) of the display panel 110 or to two or more of the four sides of the display panel 110. may be

The gate driving circuit 130 may be connected to one side (eg, the left or right side) of the display panel 110 . Depending on the driving method and the panel design method, the gate driving circuit 130 may be connected to both sides (eg, left and right) of the display panel 110 or may be connected to two or more of the four sides of the display panel 110. may be

The controller 140 may be implemented as a component separate from the data driving circuit 120 or integrated with the data driving circuit 120 and implemented as an integrated circuit. The controller 140 may be a timing controller used in a typical display technology, a control device capable of further performing other control functions including a timing controller, or a control device different from the timing controller. , or a circuit in a control device. The controller 140 may be implemented with various circuits or electronic components such as an Integrated Circuit (IC), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or a processor.

The controller 140 may be mounted on a printed circuit board or a flexible printed circuit and electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board or the flexible printed circuit. The controller 140 may transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces. Here, for example, the interface may include a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, or a Serial Peripheral Interface (SP).

The display device 100 according to embodiments of the present disclosure may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to embodiments of the present disclosure is a self-emitting display device, each of the plurality of subpixels SP may include a light emitting element ED. For example, the display device 100 according to embodiments of the present disclosure may be an organic light emitting display device in which the light emitting element ED is implemented as an organic light emitting diode (OLED). For another example, the display device 100 according to embodiments of the present disclosure may be an inorganic light emitting display device in which the light emitting element ED is implemented as an inorganic light emitting diode. As another example, the display device 100 according to embodiments of the present disclosure may be a quantum dot display device implemented with quantum dots, which are semiconductor crystals in which the light emitting element ED emits light itself.

Referring to FIG. 1 , each subpixel SP in the display panel 110 includes a light emitting element ED, a driving transistor DRT for driving the light emitting element ED, and a gate node of the driving transistor DRT. It may include a storage capacitor (Cst) between (G) and the source node (S).

The light emitting element ED may include a pixel electrode PE and a common electrode CE, and a light emitting layer EL positioned between the pixel electrode PE and the common electrode CE. The pixel electrode PE of the light emitting device ED may be an anode electrode or a cathode electrode. The common electrode CE of the light emitting element ED may be a cathode electrode or an anode electrode. The base voltage EVSS corresponding to the common voltage may be applied to the common electrode CE of the light emitting device ED. Here, the base voltage EVSS may be, for example, a ground voltage or a voltage similar to the ground voltage.

For example, the light emitting device ED may be an organic light emitting diode (OLED), an inorganic light emitting diode (LED), or a quantum dot light emitting device.

The driving transistor DRT is a transistor for driving the light emitting device ED, and may include a gate node G, a source node S, and a drain node D. A data voltage may be applied from the data line DL to the gate node G of the driving transistor DRT. The source node S of the driving transistor DRT may be electrically connected to the pixel electrode PE of the light emitting element ED, and an initialization voltage may be applied. The driving voltage EVDD may be applied to the drain node D of the driving transistor DRT.

In FIG. 1 , the driving transistor DRT is shown as an n-type transistor, but may also be a p-type transistor. However, for convenience of description, in this specification, it is assumed that the driving transistor DRT is an n-type transistor.

In this specification, the light emitting element ED is illustrated as being connected to the source node S of the driving transistor DRT, but may be connected to the drain node D of the driving transistor DRT in some cases. The storage capacitor (Cst) may be formed between the gate node (G) and the source node (S) of the driving transistor (DRT), and the image data voltage corresponding to the image signal voltage or another voltage is maintained for one frame time. can play a role

The storage capacitor Cst is not a parasitic capacitor (eg, Cgs or Cgd) that is an internal capacitor existing between the gate node G and the source node S of the driving transistor DRT, but the driving transistor ( It may be an external capacitor intentionally designed outside the DRT).

2 is a schematic equivalent circuit of a subpixel SP of the display device 100 according to example embodiments of the present disclosure.

Referring to FIG. 2 , in the display device 100 according to embodiments of the present disclosure, each sub-pixel SP is driven by the light emitting element ED for driving the light emitting element ED. It may include a driving transistor DRT for supplying current and a storage capacitor Cst for maintaining a voltage for a certain period of time, and may further include a scan transistor SCT and a sensing transistor SENT.

The scan transistor SCT may control the voltage state of the gate node G of the driving transistor DRT in order to control the driving state of the sub-pixel SP, and may control the voltage state of the gate node G of the driving transistor DRT. The data voltage (Vdata) can be delivered as .

The data voltage Vdata transmitted to the gate node G of the driving transistor DRT may be the image data voltage Vd corresponding to the image signal. Alternatively, the data voltage Vdata transmitted to the gate node G of the driving transistor DRT is independent of the image signal and may be an initialization voltage Vini required for driving. The data voltage Vdata transmitted to the gate node G of the driving transistor DRT may be another voltage required for driving (eg, a pilot voltage to be described below).

The sensing transistor SENT may control the voltage state of the source node S of the driving transistor DRT in order to control the driving state of the subpixel SP, and the source node S of the driving transistor DRT. ) to deliver the initialization voltage Vini.

Since the subpixel SP illustrated in FIG. 2 has three transistors DRT, SCT, and SENT and one capacitor Cst to drive the light emitting element ED, 3T (transistor) 1C (capacitor ) is said to have a structure.

The light emitting element ED may include a pixel electrode PE and a common electrode CE, and a light emitting layer EL positioned between the pixel electrode PE and the common electrode CE. For example, the light emitting device ED may be an organic light emitting diode (OLED), an inorganic light emitting diode (LED), or a quantum dot light emitting device.

The driving transistor DRT is a transistor for driving the light emitting device ED, and may include a gate node G, a source node S, and a drain node D. A gate node G of the driving transistor DRT may be electrically connected to a source or drain node of the scan transistor SCT. The source node S of the driving transistor DRT may be electrically connected to the source or drain node of the sensing transistor SENT and may be electrically connected to the pixel electrode PE of the light emitting element ED. The drain node D of the driving transistor DRT may be electrically connected to a driving voltage line (DVL) that supplies the driving voltage EVDD.

The scan transistor SCT may be connected between the data line DL and the gate node G of the driving transistor DRT. The scan transistor SCT is the gate of the driving transistor DRT in response to the scan signal SCAN supplied from the corresponding scan signal line SCL among the plurality of scan signal lines SCL, which is a kind of gate line GL. A connection between the node G and a corresponding data line DL among the plurality of data lines DL may be controlled.

A drain node or a source node of the scan transistor SCT may be electrically connected to the corresponding data line DL. A source node or a drain node of the scan transistor SCT may be electrically connected to the gate node G of the driving transistor DRT. A gate node of the scan transistor SCT may be electrically connected to a scan signal line SCL, which is one type of gate line GL, to receive a scan signal SCAN.

The scan transistor SCT is turned on by the scan signal SCAN of the turn-on level voltage, and transmits the data signal Vdata supplied from the corresponding data line DL to the gate node G of the driving transistor DRT. can be forwarded to The scan transistor SCT is turned on by the scan signal SCAN of the turn-on level voltage and turned off by the scan signal SCAN of the turn-off level voltage. Here, when the scan transistor SCT is n-type, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. When the scan transistor SCT is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

The sensing transistor SENT may be connected between the source node S of the driving transistor DRT and the initialization voltage line IVL. The sensing transistor SENT is a pixel of the light emitting device ED in response to a sensing signal SENSE supplied from a corresponding sensing signal line SENL among a plurality of sensing signal lines SENL, which is a kind of gate line GL. A connection between the source node S of the driving transistor DRT electrically connected to the electrode PE and a corresponding initialization voltage line IVL among the plurality of initialization voltage lines IVL may be controlled.

A drain node or a source node of the sensing transistor SENT may be electrically connected to the initialization voltage line IVL. A source node or drain node of the sensing transistor SENT may be electrically connected to the source node S of the driving transistor DRT and may be electrically connected to the pixel electrode PE of the light emitting element ED. A gate node of the sensing transistor SENT is electrically connected to the sensing signal line SENL, which is a kind of gate line GL, to receive the sensing signal SENSE.

The sensing transistor SENT may be turned on to apply the initialization voltage Vini supplied from the initialization voltage line IVL to the source node S of the driving transistor DRT. The sensing transistor SENT is turned on by the sensing signal SENSE of the turn-on level voltage and turned off by the sensing signal SENSE of the turn-off level voltage. When the sensing transistor SENT is n-type, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. When the sensing transistor SENT is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

Each of the driving transistor DRT, scan transistor SCT, and sensing transistor SENT may be an n-type transistor or a p-type transistor. All of the driving transistor DRT, scan transistor SCT, and sensing transistor SENT may be n-type transistors or p-type transistors. At least one of the driving transistor DRT, scan transistor SCT, and sensing transistor SENT may be an n-type transistor (or p-type transistor) and the others may be p-type transistors (or n-type transistors).

The scan signal line SCL and the sensing signal line SENL may be different gate lines GL. In this case, the scan signal SCAN and the sensing signal SENSE may be separate gate signals, and the on-off timing of the scan transistor SCT in one sub-pixel SP and the on-off timing of the sensing transistor SENT in one sub-pixel SP. Off timing can be independent. That is, the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP may be the same or different.

Alternatively, the scan signal line SCL and the sensing signal line SENL may be the same gate line GL. That is, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in one sub-pixel SP may be connected to one gate line GL. In this case, the scan signal SCAN and the sensing signal SENSE may be the same gate signal, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT in one sub-pixel SP. may be the same.

The initialization voltage line IVL may be disposed in each subpixel column.

Alternatively, the initialization voltage line IVL may be disposed in every two or more sub-pixel columns. When the initialization voltage line IVL is disposed in every two or more subpixel columns, the plurality of subpixels SP may receive the initialization voltage Vini from one initialization voltage line IVL. For example, one initialization voltage line IVL may be disposed for every four sub-pixel columns. That is, one initialization voltage line IVL may be shared by subpixels SP included in four subpixel columns.

The driving voltage line DVL may be disposed in each subpixel column. Alternatively, the driving voltage line DVL may be disposed in every two or more sub-pixel columns. When the driving voltage line DVL is disposed in every two or more sub-pixel columns, the plurality of sub-pixels SP is one driving voltage line. The driving voltage EVDD may be supplied from DVL. For example, one driving voltage line DVL may be disposed for every four sub-pixel columns. That is, one driving voltage line DVL may be shared by subpixels SP included in four subpixel columns.

The 3T1C structure of the sub-pixel SP illustrated in FIG. 2 is only an example for explanation, and may further include one or more transistors or, in some cases, one or more capacitors. Alternatively, each of a plurality of subpixels may have the same structure, and some of the plurality of subpixels may have a different structure.

Meanwhile, the display device 100 according to embodiments of the present disclosure may have a top emission structure or a bottom emission structure.

Meanwhile, circuit elements such as the driving transistor DRT included in each of the plurality of subpixels SP may have unique characteristic values. For example, each driving transistor DRT may have unique characteristic values such as threshold voltage and mobility.

As the driving time of the driving transistors DRT increases, characteristic values of the driving transistors DRT may change.

The plurality of subpixels SP may have different driving times. Accordingly, the variation amount of the characteristic value of the driving transistor DRT included in each of the plurality of subpixels SP may be different from each other. Accordingly, a characteristic value deviation may occur between the driving transistors DRT.

Differences in characteristic values between driving transistors DRT may cause luminance deviations between subpixels SP. Accordingly, luminance uniformity of the display panel 110 may deteriorate, and image quality may deteriorate.

Accordingly, the display device 100 according to embodiments of the present disclosure may compensate for characteristic value deviations between the driving transistors DRT in order to improve luminance non-uniformity. A method and pixel circuits therefor are newly disclosed. Here, the pixel circuit may mean an equivalent circuit of the subpixel SP.

3 is first to third graphs GRP1 , GRP2 , and GRP3 for explaining luminance non-uniformity factors of the display device 100 according to example embodiments of the present disclosure.

Referring to FIG. 3 , first and second graphs GRP1 and GRP2 are current-voltage characteristic graphs of the driving transistor DRT, and the driving transistor according to a change in the source-gate voltage Vgs of the driving transistor DRT. These are graphs showing changes in the drain-source current (Id) of (DRT), and the third graph (GRP3) is a graph obtained by enlarging a partial region of the second graph (GRP2).

The source-gate voltage Vgs of the driving transistor DRT may refer to a voltage difference between the source voltage Vs of the driving transistor DRT and the gate voltage Vg of the driving transistor DRT.

The drain-source current Id of the driving transistor DRT may refer to a current flowing from the drain node D of the driving transistor DRT to the source node S of the driving transistor DRT. ) may mean a driving current output.

Referring to FIG. 3 , a first graph GRP1 is a current-voltage characteristic graph of the driving transistor DRT when compensation for both the threshold voltage and mobility of the driving transistor DRT is not performed.

Referring to the first graph GRP1 of FIG. 3 , when the source-gate voltages Vgs of the driving transistors DRT are the same, the drain-source currents Id of the driving transistors DRT may be different. Conversely, even if the drain-source current Id of the driving transistor DRT is the same, the source-gate voltage Vgs of the driving transistor DRT for this purpose may be different. Here, that the source-gate voltage Vgs of the driving transistor DRT is the same may mean that the data voltage Vdata applied to the gate node G of the driving transistor DRT is the same.

Referring to FIG. 3 , a second graph GRP2 is a current-voltage characteristic graph of the driving transistor DRT when only the threshold voltage is compensated for among the threshold voltage and mobility of the driving transistor DRT.

Referring to the second graph GRP2 of FIG. 3 , macroscopically, when the source-gate voltage Vgs of the driving transistor DRT is the same, the drain-source current Id of the driving transistor DRT is the same. can be seen

However, looking at the third graph GRP3 obtained by enlarging a part of the second graph GRP2 (the dotted line box area), even if the source-gate voltage Vgs of the driving transistor DRT is the same, the driving transistor DRT The drain-source current (Id) of may be different from each other.

Accordingly, even if the threshold voltage compensation is performed, if the mobility compensation is not performed, current deviation of the driving transistors DRT may occur. That is, when threshold voltage compensation is performed and mobility compensation is not performed, even though the same data voltage Vdata is applied to the gate node G of the driving transistor DRT, it is supplied by the driving transistors DRT. A current deviation (hereinafter referred to as a current deviation) may occur.

Meanwhile, the mobility of the driving transistor DRT may be related to a subthreshold swing value (SS), which is one of transistor characteristics. The sub-threshold swing value SS may have the following definition. As the gate-source voltage (Vgs), which is the voltage difference between the gate node (G) and the source node (S) of the driving transistor (DRT) increases, the drain-source current (Ids) is at a voltage below the threshold voltage (Vth). In this case, the gate-source voltage (Vgs) required to increase the drain-source current (Ids) by 10 times is called the sub-threshold swing value. The sub-critical swing value is also referred to as S-Factor.

In the current-voltage characteristic graphs GRP1, GRP2, and GRP3, the slope of the curve of the drain-source current (Ids) change according to the change of the gate-source voltage (Vgs) is the reciprocal of the sub-threshold swing value (SS). may be proportional to (i.e., SS = 1/slope, slope = 1/SS).

A small sub-threshold swing value SS means that the slope of the curve is steep, and that the drain-source current Ids increases more quickly as the gate-source voltage Vgs increases. This may correspond to the meaning that the mobility of the driving transistor DRT is high.

The fact that the sub-threshold swing value SS is large means that the slope of the curve is gentle, and that the drain-source current Ids increases relatively slowly as the gate-source voltage Vgs increases. This may correspond to the meaning that the mobility of the driving transistor DRT is small.

Accordingly, when the sub-threshold swing value (SS, ie S factor) is large, the mobility of the driving transistor DRT may be small, and when the sub-threshold swing value (SS, ie S factor) is small, the driving transistor DRT moves. degree can be large.

The current deviation of the driving transistor DRT according to the aforementioned mobility deviation may be a factor that still causes luminance non-uniformity of the display panel 110 . Below, a compensation method capable of compensating both the threshold voltage and mobility of the driving transistor DRT and pixel circuits therefor will be described.

The compensation method of the display device 100 according to the exemplary embodiments of the present disclosure does not require separate components (eg, an analog-to-digital converter, a switching element, etc.) for compensation, and uses a driving transistor only by driving the sub-pixel SP. It may be an internal compensation scheme in which the threshold voltage and mobility of (DRT) can be compensated.

The fact that the threshold voltage and mobility of the driving transistor DRT are compensated means that the display is driven without being affected by the threshold voltage deviation and mobility deviation even if there is a threshold voltage deviation and mobility deviation between the driving transistors DRT. that can mean

4 is a driving timing diagram for improving luminance non-uniformity of the display device 100 according to example embodiments. However, referring to FIG. 4 , the pixel circuit of FIG. 2 may be referred to when describing a driving method for improving luminance non-uniformity according to embodiments of the present disclosure.

Briefly describing the pixel circuit of FIG. 2 again, the pixel circuit for each sub-pixel SP includes a light emitting element ED, a driving transistor DRT for driving the light emitting element ED, and a scan signal SCAN. On-off is controlled by the scan transistor (SCT) for switching the connection between the gate node (G) of the driving transistor (DRT) and the data line (DL), and the on-off is controlled by the sensing signal (SENSE) The sensing transistor SENT for switching the connection between the source node S of the driving transistor DRT and the initialization voltage line IVL, and the gate node G of the driving transistor DRT and the source of the driving transistor DRT. A storage capacitor Cst between nodes S may be included.

The driving period of each sub-pixel SP may include first to sixth periods S10 to S60 and the like. Below, each of the first to sixth periods S10 to S60 will be described.

Referring to FIG. 4 , the first period S10 may be an initialization period for initializing the voltages Vg and Vs of the gate node G and the source node S of the driving transistor DRT.

For example, during the first period S10 , the reference voltage Vref may be applied to the gate node G of the driving transistor DRT, and the initialization voltage Vini may be applied to the source node of the driving transistor DRT ( S) can be applied. Below, the voltage Vg of the gate node G of the driving transistor DRT is also referred to as the gate voltage Vg, and the voltage Vs of the source node S of the driving transistor DRT is referred to as the source voltage Vs. Also called

Referring to FIG. 4 , a second period S20 that proceeds after the first period S10 may be a threshold voltage sensing (sampling) period in which the threshold voltage of the driving transistor DRT is sensed (sampled).

During the second period S20, the reference voltage Vref may be continuously applied to the gate node G of the driving transistor DRT, and the source node S of the driving transistor DRT may be electrically floating. ) can be The electrical floating of the source node S of the driving transistor DRT indicates that no power including the initialization voltage Vini is applied to the source node S of the driving transistor DRT during the second period S20. that can mean The voltage of the source node S of the driving transistor DRT may increase according to the electrical floating of the source node S of the driving transistor DRT.

Referring to FIG. 4 , a third period S30 that proceeds after the second period S20 may be a pilot voltage application period in which the pilot voltage Vp is applied to the gate node G of the driving transistor DRT. .

During the third period S30 , the source node S of the driving transistor DRT may be maintained in a floating state, and the pilot voltage Vp, which is different from the reference voltage Vref, may be applied to the gate node of the driving transistor DRT ( G) can be applied.

The gate node G and the source node S of the driving transistor DRT are coupled capacitively by the storage capacitor Cst. Accordingly, as the voltage Vg of the gate node G of the driving transistor DRT changes from the reference voltage Vref to the pilot voltage Vp during the third period S30, the The voltage Vs of the source node S may change.

For example, during the third period S30, the voltage Vs of the source node S of the driving transistor DRT rises by a predetermined voltage value (variation amount) from the voltage at the end of the second period S2. can do. Here, the constant voltage value (variation amount) corresponds to the voltage variation amount of the gate node G of the driving transistor DRT during the third period S30, and the voltage difference between the pilot voltage Vp and the reference voltage Vref ( Vp_Vref).

Referring to FIG. 4 , the pilot voltage Vp applied to the gate node G of the driving transistor DRT may have a constant fixed voltage value during the third period S30 , which is the pilot voltage application period, or the image data It may also be a voltage value that varies according to the voltage Vd.

For example, during the third period S30 , the pilot voltage Vp applied to the gate node G of the driving transistor DRT may be varied in real time according to the image data voltage Vd.

The display device 100 according to embodiments of the present disclosure may further include a look-up table for storing a correspondence between image data voltages Vd and pilot voltages Vp, and the pilot voltage Vp may be a value extracted from the look-up table by the controller 140 or the data driving circuit 120.

The third period S30 may be included within one horizontal time period HT or may span two adjacent horizontal times HT.

Referring to FIG. 4 , in a fourth period S40 that proceeds after the third period S30 , the voltage Vg of the gate node G of the driving transistor DRT is offset, and the voltage is reduced by the offset voltage Vofs. It may be an offset formation period in which fluctuations occur. The offset forming period, the fourth period S40 , may be a mobility compensation period in which the mobility of the driving transistor DRT is compensated.

During the fourth period S40 after the third period S30, the gate node G of the driving transistor DRT may be electrically floated together with the source node S of the driving transistor DRT, and the driving transistor DRT may be in a floating state. The voltage Vg of the gate node G of the DRT and the voltage Vs of the source node S of the driving transistor DRT may both rise.

During the fourth period S40 , an increase in the voltage Vg of the gate node G of the driving transistor DRT is referred to as an offset voltage Vofs.

The source node S and the gate node G of the driving transistor DRT are capacitively coupled, and the source node S and the gate node G of the driving transistor DRT are coupled during the fourth period S40. Since all are in an electrically floating state, the voltage Vs of the source node S of the driving transistor DRT may also rise by the offset voltage Vofs during the fourth period S40 .

Referring to FIG. 4 , in a fifth period (S50), which proceeds after the fourth period (S40), data writing in which the image data voltage (Vd) is applied to the gate node (DRT) of the driving transistor (DRT). may be a period.

During the fifth period S50 after the fourth period S40 , the image data voltage Vd may be applied to the gate node G of the driving transistor DRT.

During the sixth period S60 after the fifth period S50, when the voltages Vs and Vg of the source node S and the gate node G of the driving transistor DRT rise, at a certain point in time, light is emitted. A driving current may be supplied to the device ED. Accordingly, the light emitting element ED may emit light.

Referring to FIG. 4 , during the second period S20 , which is the threshold voltage sensing (sampling) period, the voltage Vs of the source node S of the driving transistor DRT may rise in a first rising pattern. During the fourth period S40, which is the offset formation period, the voltage of the source node S of the driving transistor DRT may rise in a second rising pattern different from the first rising pattern.

For example, the first rising pattern may be a non-linear pattern in which the source voltage Vs rises non-linearly with time, and the rising rate of the source voltage Vs slows down over time to a specific voltage value. It may be a pattern that converges (saturates) to . Here, a specific voltage value at which the source voltage Vs is saturated may have a difference between the reference voltage Vref and the threshold voltage Vth of the driving transistor DRT (Vref - saturated Vs=Vth).

For example, the second rising pattern may be a linear pattern in which the source voltage Vs rises linearly with time, and the source voltage Vs may increase at a constant rising rate as time elapses. Here, the voltage rising speed of the source voltage Vs may be proportional to the mobility of the driving transistor DRT.

As described above, during the second period S20 , which is the threshold voltage sensing period, as time elapses, the speed of voltage increase at the source node S of the driving transistor DRT may decrease. During the fourth period ( S40 ), which is the offset forming period, even if time elapses, the speed of voltage increase of the source node (S) of the driving transistor (DRT) may be constant.

Referring to FIG. 4 , at the end of the second period S20, which is the threshold voltage sensing period, the voltage Vs of the source node S of the driving transistor DRT is equal to the reference voltage Vref and the first voltage value. can be different. For example, the first voltage value may correspond to the threshold voltage Vth of the driving transistor DRT. That is, at the end of the second period S20, which is the threshold voltage sensing period, the voltage Vs of the source node S of the driving transistor DRT changes from the reference voltage Vref to the threshold voltage of the driving transistor DRT ( Vth) may be subtracted (Vref-Vth).

4, as the pilot voltage Vp is applied to the gate node G of the driving transistor DRT during the third period S30, which is the pilot voltage application period, the gate node ( The variation of the voltage Vg of G) may be a difference value (Vp-Vref) between the pilot voltage Vp and the reference voltage Vref.

During the third period S30, which is the pilot voltage application period, the voltage Vg of the gate node G of the driving transistor DRT is coupled in a capacitive manner to the gate node G of the driving transistor DRT by a change in voltage Vg. The voltage Vs of the source node S of the ringed driving transistor DRT may vary by the variation amount Vp-Vref of the voltage Vg of the gate node G of the driving transistor DRT.

Accordingly, during the third period S30, which is the pilot voltage application period, the voltage Vs of the source node S of the driving transistor DRT becomes the source of the driving transistor DRT at the end of the second period S20. The voltage value Vref-Vth+(Vp-Vref) obtained by adding the variation amount (Vp-Vref) of the voltage Vg of the gate node G of the driving transistor DRT to the voltage Vs=Vref-Vth of the node S. = Vp-Vth).

Referring to FIG. 4 , during the fourth period S40 , which is the offset forming period, the voltage Vg of the gate node G of the driving transistor DRT may increase by the offset voltage Vofs from the pilot voltage Vp. there is. That is, at the end of the fourth period S40, the voltage Vg of the gate node G of the driving transistor DRT is the voltage value obtained by adding the offset voltage Vofs to the pilot voltage Vp (Vp+Vofs). can be

Accordingly, the voltage Vs of the source node S of the driving transistor DRT during the fourth period S40 is the voltage Vref-Vth+(Vp-Vref)=Vp-Vth in the third period S30. , Vth: the threshold voltage of the driving transistor DRT) may increase by the offset voltage Vofs. That is, during the fourth period S40, the voltage Vs of the source node S of the driving transistor DRT is the offset voltage at the voltage value Vp-Vth obtained by subtracting the threshold voltage Vth from the pilot voltage Vp. It may be a voltage value (Vp−Vth+Vofs) obtained by adding (Vofs).

Referring to FIG. 4 , a fourth period S40 that is an offset forming period may have a preset temporal length Tf. The voltage rising slope (voltage rising speed) of the gate node G of the driving transistor DRT may be a value obtained by dividing the offset voltage Vofs by the temporal length Tf of the fourth period S40 (Vofs/Tf). . A value obtained by dividing the offset voltage Vofs by the temporal length Tf of the fourth period S40 (Vofs/Tf) may correspond to the mobility of the driving transistor DRT.

A voltage rising slope (voltage rising speed) of the source node S of the driving transistor DRT may correspond to a voltage rising slope (voltage rising speed) of the gate node G of the driving transistor DRT.

Referring to FIG. 4 , for example, the temporal length Tf of the fourth period S40 may be shorter than one horizontal time period HT.

A brief description of the aforementioned driving method is as follows. In the pixel circuit according to example embodiments, current flows according to a voltage stored in the storage capacitor Cst between the gate node G and the source node S of the driving transistor DRT, and It may have a pixel structure in which a voltage is induced in the storage capacitor Cst according to a transmission rate for a change in voltage (potential) generated at the gate node G.

When the image data voltage Vd is applied to the sub-pixel SP, the pilot voltage Vp determined according to the image data voltage Vd is applied to the gate node G of the driving transistor DRT. Accordingly, the current corresponding to the voltage (corresponding to the pilot voltage Vp) induced by the storage capacitor Cst may cause a variation (Vofs) of the gate node G of the driving transistor DRT for a certain period of time. At this time, the gate node G of the driving transistor DRT may be in a high impedance state. The high impedance state may have the same meaning as the floating state.

As described above, in the fifth period (S50), which is the data writing period, a voltage is induced in the storage capacitor (Cst) by a change in the voltage difference (Vd-Vofs) between the image data voltage (Vd) and the offset voltage (Ofs). It can be.

The high-impedance state of the gate node G of the driving transistor DRT may be formed mainly when the scan transistor SCT between the data line and the gate node G is turned off.

During the fifth period S50, which is the data writing period, the source node S of the driving transistor DRT may maintain a high impedance state (floating state).

During the third period S30, which is the pilot voltage application period, the source node S of the driving transistor DRT may be in a high impedance state or a low impedance state.

Hereinafter, pixel circuits to which the above-described driving method according to the exemplary embodiments of the present disclosure may be applied and an applied driving method thereof will be described. However, it is exemplified that all transistors included in the pixel circuit illustrated below are n-type transistors. Therefore, the voltage (gate voltage) of the gate signal (e.g., SCAN, SENSE, EM, SMP, REF) capable of turning on each of all the transistors included in the pixel circuit illustrated below is a high level voltage, A voltage (gate voltage) of a gate signal (eg, SCAN, SENSE, EM, SMP, REF) capable of turning off each of all transistors included in the pixel circuit illustrated in may be a low level voltage. Considering this point, if the voltages of various gate signals (e.g., SCAN, SENSE, EM, SMP, REF) in the driving timing diagrams illustrated below are considered as one of a turn-on level voltage and a turn-off level voltage do. In addition, below, the voltage of various gate signals (eg, SCAN, SENSE, EM, SMP, REF) is a turn-on level voltage or a turn-off level voltage, and corresponding transistors (eg, SCT, SENT, EMT, SMPT, REFT) is also described as being turned on or turned off.

5 is a pixel circuit that is an equivalent circuit for the sub-pixel SP of the display device 100 according to embodiments of the present disclosure, and FIGS. 6 and 7 are driving timing diagrams of the pixel circuit of FIG. 5 .

Referring to FIG. 5 , in the display device 100 according to example embodiments, the pixel circuit of each sub-pixel SP includes a light emitting element ED, a driving transistor DRT, a scan transistor SCT, and a sensing circuit. A transistor SENT and a storage capacitor Cst may be included.

Referring to FIG. 5 , the on/off of the pixel circuit of each sub-pixel SP is controlled by the emission control signal EM, and the drain node D of the driving transistor DRT and the driving voltage line DVL are connected. On-off is controlled by the emission control transistor (EMT) for switching the connection between them and the sampling signal (SMP), so that the drain node (D) of the driving transistor (DRT) and the body node (BDY) of the driving transistor (DRT) ) may further include a sampling transistor (SMPT) for switching the connection between them.

Referring to FIG. 5 , the gate node of the scan transistor SCT may be connected to the scan signal line SCL and receive the scan signal SCAN from the scan signal line SCL.

Referring to FIG. 5 , the gate node of the sensing transistor SENT may be connected to the sensing signal line SENL and receive the sensing signal SENSE from the sensing signal line SENL.

Referring to FIG. 5 , the gate node of the emission control transistor EMT may be connected to the emission control signal line EML and receive the emission control signal EM from the emission control signal line EML.

Referring to FIG. 5 , the gate node of the sampling transistor SMPT may be connected to the sampling signal line SMPL and receive the sampling signal SMP from the sampling signal line SMPL.

Referring to FIG. 5 , a pixel circuit of each sub-pixel SP may have a 5T structure including 5 transistors DRT, SCT, SENT, EMT, and SMPT.

Referring to FIG. 5 , the pixel circuit of each sub-pixel SP includes a first control capacitor Ca between the source node S of the driving transistor DRT and the first control node Na, and the body of the driving transistor. At least one of second control capacitors Cb between the node BDY and the source node S of the driving transistor DRT may be further included.

Referring to FIG. 5 , for example, the first control node Na may be electrically connected to the driving voltage line DVL.

Referring to FIG. 5 , for example, the second control capacitor Cb may be an internal capacitor of the driving transistor DRT or an external capacitor of the driving transistor DRT.

The pixel circuit of FIG. 5 can be driven according to the driving timing diagram of FIG. 6 or the driving timing diagram of FIG. 7 . The driving timing diagram of FIG. 6 is a driving timing diagram without the third period S30 and the fourth period S40 among the first to sixth periods S10 to S60, and the driving timing diagram of FIG. 7 shows the first to sixth periods S10 to S60. It may be a driving timing diagram including all six periods (S10 to S60). However, for convenience of explanation, the driving timing part of the sixth period ( S60 ) is omitted.

Referring to FIGS. 6 and 7 , during the first period S10, the emission control transistor EMT, scan transistor SCT, sampling transistor SMPT, and sensing transistor SENT may be turned on. .

Accordingly, the reference voltage Vref may be applied to the gate node G of the driving transistor DRT, and the initialization voltage Vini may be applied to the source node S of the driving transistor DRT. The driving voltage EVDD may be applied to the drain node D of the driving transistor DRT.

Accordingly, the storage capacitor Cst may be initialized in a state in which the reference voltage Vref and the initialization voltage Vini are applied to both ends of the storage capacitor Cst. The second control capacitor Cb may be initialized with the driving voltage EVDD and the initialization voltage Vini applied to both ends of the second control capacitor Cb.

Referring to FIGS. 6 and 7 , in a second period S20 after the first period S10, the emission control transistor EMT may be turned off, and the voltage difference between both ends of the second control capacitor Cb is It can change. The sampling transistor SMPT is turned off to end the second period S20.

During the second period S20 , the light emitting control transistor EMT is turned off so that the body node BDY of the driving transistor DRT can be in a floating state (high impedance state). Accordingly, voltage sampling may occur in the second control capacitor Cb. That is, a voltage difference between both ends of the second control capacitor Cb may be the threshold voltage Vth of the driving transistor DRT.

After the sampling transistor SMPT is turned off and the second period S20 ends, that is, after the voltage sampling is completed, the scan transistor SCT is turned on, and the turned-on scan transistor SCT is turned on. Through this, the black data voltage Vblack may be applied to the gate node G of the driving transistor DRT.

Referring to FIG. 6 , an anchoring period ( S51 ) may be selectively added during the fifth period ( S50 ), which is a data writing period. In the anchoring period S51, the scan transistor SCT and the sensing transistor SENT are turned on so that the gate node G and the source node S of the driving transistor DRT are connected to the reference voltage Vref and the initialization voltage. (Vini).

Referring to FIG. 6 , in a period after the anchoring period S51 in the fifth period S50, when the emission control transistor EMT, the sensing transistor SENT, and the sampling transistor SMPT are turned off, When the scan transistor SCT is turned on, the image data voltage Vd(n) may be applied to the gate node G of the driving transistor DRT. In Vd(n) and Vd(n−1) in FIG. 6, (n) and (n−1) may mean driving sequences, and may be omitted below.

At this time, the source node S of the driving transistor DRT may be in a floating state, and the potential difference between both ends of the storage capacitor Cst is a voltage difference between the image data voltage Vd and the reference voltage Vref (Vd-Vref). may be a value multiplied by the delivery rate. Here, the transfer rate may be a constant value.

Referring to FIG. 7 , during the third period S30 , which is the pilot voltage application period, the light emitting control transistor EMT and the sampling transistor SMPT are turned off, and the sensing transistor SENT is turned on or turned on. - In an off state, the scan transistor SCT may be in a turn-on state. Accordingly, the pilot voltage Vp(n) may be applied to the gate node G of the driving transistor DRT. Vp(n), Vd(n−1), and (n) and (n−1) in Vd(n) in FIG. 7 may mean driving sequences, and may be omitted below.

In the fourth period S40 after the third period S30, the scan transistor SCT, the sensing transistor SENT, and the sampling transistor SMPT may be turned off, and the emission control transistor EMT may be turned off. can be on At this time, the gate node G of the driving transistor DRT becomes a high impedance state (floating state), and a voltage rise may occur.

Referring to FIG. 7 , during the third period S30 , which is the pilot voltage application period, the sensing transistor SENT may be in a turn-off state or a turn-on state.

Referring to FIG. 7 , during the fifth period ( S50 ), which is the data writing period, when the emission control transistor (EMT), sensing transistor (SENT), and sampling transistor (SMPT) are turned off, the scan transistor (SCT) When turned on, the image data voltage Vd(n) may be applied to the gate node G of the driving transistor DRT.

At this time, the source node S of the driving transistor DRT may be in a floating state, and the potential difference between both ends of the storage capacitor Cst is a voltage difference between the image data voltage Vd and the reference voltage Vref (Vd-Vref). may be a value multiplied by the delivery rate. Here, the transfer rate may be a constant value.

FIG. 8 is another pixel circuit for the sub-pixel SP of the display device 100 according to embodiments of the present disclosure, and FIGS. 9 and 10 are driving timing diagrams of the pixel circuit of FIG. 8 .

Referring to FIG. 8 , in the display device 100 according to example embodiments, the pixel circuit of each sub-pixel SP includes a light emitting element ED, a driving transistor DRT, a scan transistor SCT, and a sensing circuit. A transistor SENT and a storage capacitor Cst may be included.

Referring to FIG. 8 , the on-off of the pixel circuit of each sub-pixel SP is controlled by the emission control signal EM, and the drain node D of the driving transistor DRT and the driving voltage line DVL are connected. A light emitting control transistor (EMT) for switching the connection between them may be further included.

Referring to FIG. 8 , the gate node of the scan transistor SCT may be connected to the scan signal line SCL and receive the scan signal SCAN from the scan signal line SCL.

Referring to FIG. 8 , the gate node of the sensing transistor SENT may be connected to the sensing signal line SENL and receive the sensing signal SENSE from the sensing signal line SENL.

Referring to FIG. 8 , the gate node of the emission control transistor EMT may be connected to the emission control signal line EML and receive the emission control signal EM from the emission control signal line EML.

Below, a driving method for the pixel circuit of FIG. 8 will be described with reference to FIGS. 9 and 10 .

Referring to FIGS. 9 and 10 , for example, among driving periods S10 to S60 for the pixel circuit of FIG. 8 , a second period S20 and a third period S30 may overlap. For example, the second half of the second period S20 may overlap with the third period S30 or may be the third period S30.

Referring to FIG. 9 , during the first period S10 , the scan transistor SCT and the sensing transistor SENT may be turned on. Accordingly, the reference voltage Vref and the initialization voltage Vini may be applied to the gate node G and the source node S of the driving transistor DRT. Accordingly, the storage capacitor Cst may store the voltage difference Vini between the reference voltage Vref and the initialization voltage Vini.

Referring to FIG. 9 , during the second period S20 , the scan transistor SCT and the emission control transistor EMT may be turned on, and the sensing transistor SENT may be turned off.

Accordingly, the gate node G of the driving transistor DRT is in a state in which the reference voltage Vref is applied, and the source node S of the driving transistor DRT is saturated (converged) to a specific voltage as the voltage rises. It can be. The saturated voltage of the source node S of the driving transistor DRT may be a voltage value (Vref-Vth) obtained by subtracting the threshold voltage (Vth) from the reference voltage (Vref). Also, a voltage difference between the gate node G and the source node S of the driving transistor DRT may be the threshold voltage Vth of the driving transistor DRT or a voltage close thereto. Accordingly, the threshold voltage Vth to be sensed or a voltage close thereto may be stored in the storage capacitor Cst.

Referring to FIG. 9 , during the third period S30 , the scan transistor SCT and the emission control transistor EMT may be turned on, and the sensing transistor SENT may be turned off. Accordingly, the pilot voltage Vp may be applied to the gate node G of the driving transistor DRT.

Referring to FIG. 9 , during the third period S30 , the second period S20 continues and the sensing operation may proceed.

Referring to FIG. 9 , during the fourth period S40 , the scan transistor SCT and the sensing transistor SENT may be turned off, and the emission control transistor EMT may be turned on. Accordingly, the gate node G of the driving transistor DRT becomes a high-impedance state, so that a voltage rise of the gate node G of the driving transistor DRT may occur. A voltage increase level of the gate node G of the driving transistor DRT may correspond to the offset voltage Vofs.

Referring to FIG. 9 , the emission control transistor EMT is turned off, and the fourth period S40 may end. That is, the time length Tf of the fourth period S40 may be adjusted by controlling the turn-off timing of the emission control transistor EMT, and accordingly, the magnitude of the offset voltage Vofs may be adjusted. there is.

Referring to FIG. 9 , during the fifth period S50 , which is the data writing period, the sensing transistor SENT is turned off and the scan transistor SCT is turned on, and thus the driving transistor DRT The image data voltage Vd(n) may be applied to the gate node G of . At this time, the source node S of the driving transistor DRT may be in a floating state, and the potential difference between both ends of the storage capacitor Cst is a voltage difference between the image data voltage Vd and the reference voltage Vref (Vd-Vref). may be a value multiplied by the delivery rate. Here, the transfer rate may be a constant value.

Referring to FIG. 9 , the image data voltage Vd(n) may be applied to the gate node G of the driving transistor DRT during the fifth period S50 , which is the data writing period. At this time, the voltage value (a*(Vd-Vofs)) obtained by multiplying the voltage difference (Vd-Vofs) between the image data voltage (Vd) and the offset voltage (Vofs) by the transmission factor (a) is added to the storage capacitor (Cst) to obtain a voltage. can be saved Here, the transfer rate (a) may be a constant value.

Referring to FIG. 9, the variation sequence of the data voltage Vdata is based on the reference voltage Vref, the pilot voltage Vp(n) supplied to the currently driven subpixel SP, and the pre-driven subpixel SP. The supplied image data voltage (Vd(n-1)), the reference voltage (Vref), the pilot voltage (Vp(n+1)) supplied to the subsequently driven subpixel (SP), and the currently driven subpixel (SP) may be the image data voltage Vd(n) supplied to .

Referring to FIG. 10 , during the first period S10 , the scan transistor SCT and the sensing transistor SENT may be turned on. Accordingly, the reference voltage Vref and the initialization voltage Vini may be applied to the gate node G and the source node S of the driving transistor DRT. Accordingly, the storage capacitor Cst may store the voltage difference Vini between the reference voltage Vref and the initialization voltage Vini.

Referring to FIG. 10 , during the second period S20 , the scan transistor SCT and the emission control transistor EMT may be turned on, and the sensing transistor SENT may be turned off.

Accordingly, the gate node G of the driving transistor DRT may be in a state in which the reference voltage Vref is applied. The source node S of the driving transistor DRT becomes a floating state (high impedance state), and the source node S of the driving transistor DRT rises in voltage and saturates (converges) to a specific voltage over time. It can be.

The saturated voltage of the source node S of the driving transistor DRT may be a voltage value (Vref-Vth) obtained by subtracting the threshold voltage (Vth) from the reference voltage (Vref). Also, a voltage difference between the gate node G and the source node S of the driving transistor DRT may be the threshold voltage Vth of the driving transistor DRT or a voltage close thereto. Accordingly, the threshold voltage Vth to be sensed or a voltage close thereto may be stored in the storage capacitor Cst.

Referring to FIG. 10 , during the third period S30 , the scan transistor SCT and the emission control transistor EMT may be turned on, and the sensing transistor SENT may be turned off. Accordingly, the pilot voltage Vp may be applied to the gate node G of the driving transistor DRT.

Referring to FIG. 10 , during the third period S30 , the second period S20 continues and the sensing operation may proceed.

Referring to FIG. 10 , during the fourth period S40 , the scan transistor SCT and the sensing transistor SENT may be turned off, and the emission control transistor EMT may be turned on. Accordingly, the gate node G of the driving transistor DRT becomes a high-impedance state, so that a voltage rise of the gate node G of the driving transistor DRT may occur. A voltage increase level of the gate node G of the driving transistor DRT may correspond to the offset voltage Vofs.

Referring to FIG. 10 , the emission control transistor EMT is turned off and the fourth period S40 may end. That is, the time length Tf of the fourth period S40 may be adjusted by controlling the turn-off timing of the emission control transistor EMT, and accordingly, the magnitude of the offset voltage Vofs may be adjusted. there is.

Referring to FIG. 10 , during a fifth period S50 that is a data writing period, the sensing transistor SENT may be turned off and the scan transistor SCT may be turned on.

Referring to FIG. 10 , the image data voltage Vd(n) may be applied to the gate node G of the driving transistor DRT during the fifth period S50 , which is the data writing period. At this time, the voltage value (a*(Vd-Vofs)) obtained by multiplying the voltage difference (Vd-Vofs) between the image data voltage (Vd) and the offset voltage (Vofs) by the transmission factor (a) is added to the storage capacitor (Cst) to obtain a voltage. can be saved Here, the transfer rate (a) may be a constant value.

Referring to FIG. 10, the variation sequence of the data voltage Vdata is a reference voltage Vref, a pilot voltage Vp(n-1) supplied to the pre-driven sub-pixel SP, and a pre-driven sub-pixel SP. ), the reference voltage Vref, the pilot voltage Vp(n) supplied to the currently driving sub-pixel SP, and the currently driving sub-pixel SP may be the image data voltage Vd(n) supplied to .

FIG. 11 is another pixel circuit for the sub-pixel SP of the display device 100 according to example embodiments, and FIG. 12 is a driving timing diagram of the pixel circuit of FIG. 11 .

Referring to FIG. 11 , in the display device 100 according to embodiments of the present disclosure, the pixel circuit of each sub-pixel SP includes a light emitting element ED, a driving transistor DRT, a scan transistor SCT, and a sensing circuit. A transistor SENT and a storage capacitor Cst may be included.

Referring to FIG. 11 , the on/off of the pixel circuit of each sub-pixel SP is controlled by the emission control signal EM, and the drain node D of the driving transistor DRT and the driving voltage line DVL are connected. A light emitting control transistor (EMT) for switching the connection between, and

A reference control transistor REFT for switching the connection between the gate node G of the driving transistor DRT and the reference voltage line RVL by being turned on and off controlled by the reference control signal REF may be further included. there is.

Referring to FIG. 11 , the gate node of the scan transistor SCT may be connected to the scan signal line SCL and receive the scan signal SCAN from the scan signal line SCL.

Referring to FIG. 11 , the gate node of the sensing transistor SENT may be connected to the sensing signal line SENL and receive the sensing signal SENSE from the sensing signal line SENL.

Referring to FIG. 11 , the gate node of the emission control transistor EMT may be connected to the emission control signal line EML, and may receive the emission control signal EM from the emission control signal line EML.

Referring to FIG. 11 , the gate node of the reference control transistor REFT may be connected to the reference control signal line REFL and receive the reference control signal REF from the reference control signal line REFL.

Referring to FIG. 11 , the pixel circuit of each sub-pixel SP may further include a first control capacitor Ca between the source node S of the driving transistor DRT and the first control node Na. .

Referring to FIG. 12 , during the first period S10 , the reference control transistor REFT and the sensing transistor SENT may be turned on.

Accordingly, the gate node G of the driving transistor DRT can receive the reference voltage Vref through the reference voltage transistor REFT, and the source node S of the driving transistor DRT can receive the sensing transistor SENT. ) through which the initialization voltage Vini can be applied. Accordingly, the storage capacitor Cst may store a voltage Vref-Vini corresponding to a voltage difference between the reference voltage Vref and the initialization voltage Vini.

Referring to FIG. 12 , during the second period S20 , the reference control transistor REFT and the emission control transistor EMT may be turned on, and the sensing transistor SENT may be turned off.

Accordingly, the gate node G of the driving transistor DRT may be in a state in which the reference voltage Vref is applied. The source node S of the driving transistor DRT becomes a floating state (high impedance state), and the source node S of the driving transistor DRT rises in voltage and saturates (converges) to a specific voltage over time. It can be.

The saturated voltage of the source node S of the driving transistor DRT may be a voltage value (Vref-Vth) obtained by subtracting the threshold voltage (Vth) from the reference voltage (Vref). Also, a voltage difference between the gate node G and the source node S of the driving transistor DRT may be the threshold voltage Vth of the driving transistor DRT or a voltage close thereto. Accordingly, the threshold voltage Vth to be sensed or a voltage close thereto may be stored in the storage capacitor Cst.

Referring to FIG. 12 , during the third period S30 , the emission control transistor EMT, reference control transistor REFT, and sensing transistor SENT are turned off, and the scan transistor SCT is turned on. may be in a state Accordingly, the pilot voltage Vp may be applied to the gate node G of the driving transistor DRT.

Referring to FIG. 12 , during the fourth period S40 , the emission control transistor EMT is turned on, and the scan transistor SCT, sensing transistor SENT, and reference control transistor REFT are turned off. may be in a state

Accordingly, the gate node G of the driving transistor DRT becomes a high-impedance state, so that a voltage rise of the gate node G of the driving transistor DRT may occur. A voltage increase level of the gate node G of the driving transistor DRT may correspond to the offset voltage Vofs.

Referring to FIG. 12 , the emission control transistor EMT is turned off and the fourth period S40 may end. That is, the time length Tf of the fourth period S40 may be adjusted by controlling the turn-off timing of the emission control transistor EMT, and accordingly, the magnitude of the offset voltage Vofs may be adjusted. there is.

Referring to FIG. 12 , during a fifth period S50 that is a data writing period, the reference control transistor REFT and the sensing transistor SENT are turned off, and the scan transistor SCT is turned on. At this time, the light emission control transistor (EMT) turns -?? may be in a state

Referring to FIG. 12 , the image data voltage Vd(n) may be applied to the gate node G of the driving transistor DRT during the fifth period S50 , which is the data writing period. In this case, the storage capacitor Cst may be a value (a*(Vd-Vofs)) obtained by multiplying a voltage difference (Vd-Vofs) between the image data voltage (Vd) and the offset voltage (Vofs) by the transfer rate (a). Here, the transfer rate may be a constant value.

Referring to FIG. 12, the variation sequence of the data voltage Vdata is the pilot voltage Vp(n−1) supplied to the pre-driven sub-pixel SP, and the image data supplied to the pre-driven sub-pixel SP. Voltage (Vd(n-1)), pilot voltage (Vp(n)) supplied to the sub-pixel (SP) during current driving, image data voltage (Vd(n)) supplied to the sub-pixel (SP) during current driving can be

FIG. 13 is a graph showing the pilot voltage Vp according to the image data voltage Vd in the display device 100 according to example embodiments.

Referring to FIG. 13, during the third period S30, which is the pilot voltage application period, the pilot voltage Vp applied to the gate node G of the driving transistor DRT may vary according to the image data voltage Vd. there is.

For example, during the third period S30 , the pilot voltage Vp applied to the gate node G of the driving transistor DRT may be varied in real time according to the image data voltage Vd.

The pilot voltage Vp may be expressed as a function expression of the image data voltage Vd, for example, as c1×ln(c2×Vd+c3). In the mathematical expression, c1, c2, and c3 are constants, and ln is a symbol of the natural logarithm whose base is the real number e (Euler's number).

Meanwhile, the display device 100 according to embodiments of the present disclosure may store a graph of the pilot voltage Vp with respect to the image data voltage Vd as shown in FIG. 13 or information corresponding thereto as a look-up table. .

Accordingly, the controller 140 or the data driving circuit 120 checks the pilot voltage (Vp) corresponding to the current image data voltage (Vd) with reference to the look-up table, and determines the pilot voltage (Vp) may be supplied to the corresponding sub-pixel SP through the data line DL.

14 is an experimental measurement graph showing current according to the S factor in the display device 100 according to example embodiments.

Referring to FIG. 14 , according to the driving method of the display device 100 according to the exemplary embodiments of the present disclosure, the S factor (sub threshold swing value SS) of the driving transistors DRT has three values S1 and S2 , S3), the current supplied by the driving transistors DRT may be the same.

The fact that the S factor (sub threshold swing value SS) of the driving transistors DRT is different in three values (S1, S2, S3) means that the mobility, which is a unique characteristic value of the driving transistors DRT, has three values. can mean different.

Even if there is a mobility deviation of the driving transistors DRT, when the driving method of the display device 100 according to the exemplary embodiments of the present disclosure is applied, the mobility deviation of the driving transistors DRT is compensated and the driving transistor ( DRT) can be almost identical.

15 is an experimental measurement graph illustrating a current deviation before and after applying compensation driving of the display device 100 according to example embodiments.

Referring to FIG. 15, before mobility compensation is applied by compensation driving according to embodiments of the present disclosure, for the first case in which the current deviation increases in a positive direction as the current of the driving transistors DRT increases. Comparing (before compensation 1) and after mobility compensation is applied (after compensation 1), after mobility compensation is applied by compensation driving according to embodiments of the present disclosure (after compensation 1), the current deviation is significantly reduced can confirm that

Referring to FIG. 15, before mobility compensation is applied by compensation driving according to embodiments of the present disclosure, for the second case in which the current deviation increases in the negative direction as the current of the driving transistors DRT increases. Comparing (before compensation 2) and after mobility compensation is applied (after compensation 2), after mobility compensation is applied by compensation driving according to embodiments of the present disclosure (after compensation 2), the current deviation is significantly reduced can confirm that

A brief description of the embodiments of the present disclosure described above is as follows.

A display device according to embodiments of the present disclosure includes a plurality of subpixels, and each of the plurality of subpixels has a light emitting element, a driving transistor for driving the light emitting element, and an ON/OFF control of the driving transistor by a scan signal. A scan transistor for switching the connection between the gate node and the data line, a sensing transistor for switching the connection between the source node of the driving transistor and the initialization voltage line whose on-off control is controlled by a sensing signal, and the gate node and driving of the driving transistor A storage capacitor may be included between source nodes of the transistors.

The driving period of each of the plurality of subpixels may include a first period, a second period, a third period, a fourth period, and a fifth period.

During the first period, a reference voltage may be applied to a gate node of the driving transistor, and an initialization voltage may be applied to a source node of the driving transistor.

During the second period after the first period, the reference voltage is continuously applied to the gate node of the driving transistor, the source node of the driving transistor is electrically floated, and the voltage of the source node of the driving transistor may increase.

During the third period after the second period, the source node of the driving transistor is maintained in a floating state, and a pilot voltage different from the reference voltage may be applied to the gate node of the driving transistor.

During the fourth period after the third period, the source node of the driving transistor and the gate node of the driving transistor may be electrically floated, and the voltage of the gate node of the driving transistor and the voltage of the source node of the driving transistor may rise together.

During the fifth period after the fourth period, the image data voltage may be applied to the gate node of the driving transistor.

In the display device according to example embodiments of the present disclosure, during the second period, the voltage of the source node of the driving transistor may increase in a first rising pattern, and during the fourth period, the voltage of the source node of the driving transistor may increase with the first rising pattern. It can rise in a second rising pattern different from the pattern.

In the display device according to example embodiments of the present disclosure, during the second period, the speed of voltage increase of the source node of the driving transistor may decrease, and during the fourth period, the speed of voltage increase of the source node of the driving transistor may be constant.

In the display device according to example embodiments of the present disclosure, at the end of the second period, the voltage of the source node of the driving transistor may differ from the reference voltage by a first voltage value, and the first voltage value may be different from the threshold voltage of the driving transistor. can be matched.

In the display device according to the exemplary embodiments of the present disclosure, the pilot voltage may vary according to the image data voltage.

In the display device according to the exemplary embodiments of the present disclosure, the pilot voltage may be varied in real time according to the image data voltage.

The display device according to example embodiments of the present disclosure may further include a look-up table storing a correspondence between image data voltages and pilot voltages, and the pilot voltage may be determined based on the look-up table.

In the display device according to example embodiments of the present disclosure, the third period may be included in one horizontal time period or may span two adjacent horizontal times.

In the display device according to example embodiments of the present disclosure, during the fourth period, the voltage of the gate node of the driving transistor may increase by an offset voltage from the pilot voltage, and the voltage of the source node of the driving transistor may increase from the voltage of the third period to It can rise by the offset voltage.

In the display device according to example embodiments of the present disclosure, a value obtained by dividing the offset voltage by the temporal length of the fourth period may correspond to the mobility of the driving transistor.

In the display device according to example embodiments of the present disclosure, the temporal length of the fourth period may be shorter than one horizontal time period.

In the display device according to example embodiments of the present disclosure, each of a plurality of subpixels is turned on and off by a light emission control signal to switch a connection between a drain node of a driving transistor and a driving voltage line; and A sampling transistor for switching a connection between a drain node of the driving transistor and a body node of the driving transistor by being turned on and off controlled by the sampling signal may be further included.

In this case, each of the plurality of subpixels may further include at least one of a first control capacitor between the source node of the driving transistor and the first control node, and a second control capacitor between the body node of the driving transistor and the source node of the driving transistor. can

The first control node may be electrically connected to the driving voltage line.

The second control capacitor may be a built-in capacitor of the driving transistor or an external capacitor of the driving transistor.

During the first period, the light emitting control transistor, scan transistor, sampling transistor, and sensing transistor may be turned on.

When the second period comes after the first period, the light emitting control transistor is turned off, and a voltage difference between both ends of the second control capacitor may change. The sampling transistor may be turned off to end the second period.

During the third period, the emission control transistor and the sampling transistor may be turned off, the sensing transistor may be turned on or off, and the scan transistor may be turned on.

In the fourth period after the third period, the scan transistor, the sensing transistor, and the sampling transistor may be turned off, and the emission control transistor may be turned on.

In the display device according to example embodiments of the present disclosure, each of a plurality of subpixels is controlled to be turned on or off by a light emission control signal, and further includes a light emission control transistor for switching a connection between a drain node of a driving transistor and a driving voltage line. can include

In this case, the second period and the third period may overlap.

During the first period, the scan transistor and the sensing transistor may be turned on. During the second period, the scan transistor and the light emission control transistor may be turned on, and the sensing transistor may be turned off.

During the third period, the scan transistor and the light emission control transistor may be turned on, and the sensing transistor may be turned off.

During the fourth period, the scan transistor and the sensing transistor may be turned off, and the emission control transistor may be turned on. The light emission control transistor may be turned off to end the fourth period.

In the display device according to example embodiments of the present disclosure, each of a plurality of subpixels is turned on and off by a light emission control signal to switch a connection between a drain node of a driving transistor and a driving voltage line; and A reference control transistor for switching a connection between the gate node of the driving transistor and the reference voltage line by being turned on and off controlled by the reference control signal may be further included.

In this case, each of the plurality of subpixels may further include a first control capacitor between the source node of the driving transistor and the first control node.

During the first period, the reference control transistor and the sensing transistor may be turned on. During the second period, the reference control transistor and the emission control transistor may be turned on, and the sensing transistor may be turned off. During the third period, the emission control transistor, the reference control transistor, and the sensing transistor may be turned off, and the scan transistor may be turned on. During the fourth period, the emission control transistor may be turned on, and the scan transistor, sensing transistor, and reference control transistor may be turned off.

A method of driving a display device according to embodiments of the present disclosure includes applying a reference voltage to a gate node of a driving transistor in a subpixel and applying an initialization voltage to a source node of a driving transistor in a subpixel during a first period; During a second period thereafter, continuously applying a reference voltage to the gate node of the driving transistor and electrically floating the source node of the driving transistor to increase the voltage of the source node of the driving transistor; maintaining the source node of the driving transistor in a floating state during the period, and applying a pilot voltage different from the reference voltage to the gate node of the driving transistor, during a fourth period after the third period, together with the source node of the driving transistor, The step of electrically floating the gate node of the driving transistor to increase the voltage of the gate node of the driving transistor and the voltage of the source node of the driving transistor together, and during a fifth period after the fourth period, the image data voltage of the driving transistor It may include applying to the gate node.

A pixel circuit according to embodiments of the present disclosure includes a light emitting device, a driving transistor for driving the light emitting device, a scan transistor for switching a connection between a gate node of the driving transistor and a data line by being turned on/off controlled by a scan signal, A sensing transistor for switching the connection between the source node of the driving transistor and the initialization voltage line by controlling on-off by a sensing signal, and switching the connection between the drain node of the driving transistor and the driving voltage line by controlling on-off by a light emitting control signal. A light emitting control transistor for switching the connection, a reference control transistor for switching the connection between the gate node of the driving transistor and the reference voltage line, the gate node of the driving transistor and the source of the driving transistor having ON-OFF controlled by a reference control signal. It may include a storage capacitor between nodes, and a first control capacitor between a source node of a driving transistor and a first control node.

The first control node may be electrically connected to the driving voltage line.

According to the embodiments of the present disclosure described above, a pixel circuit, a display device, and a driving method thereof capable of compensating for deviations in characteristic values of driving transistors using an internal compensation method may be provided.

According to the exemplary embodiments of the present disclosure, a pixel circuit capable of compensating for a current deviation supplied through driving transistors, a display device, and a driving method thereof may be provided.

According to the exemplary embodiments of the present disclosure, a pixel circuit, a display device, and a driving method thereof capable of reducing a current deviation due to a difference in mobility of driving transistors by inducing a voltage programmed for each sub-pixel may be provided.

The above description is merely an example of the technical idea of the present disclosure, and various modifications and variations may be made to those skilled in the art without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not intended to limit the technical idea of the present disclosure but to explain the scope of the technical idea of the present disclosure by these embodiments. The scope of protection of the present disclosure should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of rights of the present disclosure.

100: display device
110: display panel
120: data driving circuit
130: gate driving circuit
140: controller
150: host system

Claims (25)

In a display device including a plurality of subpixels,
Each of the plurality of subpixels may include a light emitting element; A driving transistor for driving the light emitting element, a scan transistor for switching a connection between a gate node of the driving transistor and a data line by controlling on-off by a scan signal, and controlling on-off by a sensing signal to drive the driving transistor a sensing transistor for switching a connection between a source node of a transistor and an initialization voltage line, and a storage capacitor between a gate node of the driving transistor and a source node of the driving transistor;
The driving period of each of the plurality of subpixels includes a first period, a second period, a third period, a fourth period, and a fifth period;
During the first period, a reference voltage is applied to a gate node of the driving transistor and an initialization voltage is applied to a source node of the driving transistor;
During the second period after the first period, the reference voltage is continuously applied to the gate node of the driving transistor, the source node of the driving transistor is electrically floated and the voltage of the source node of the driving transistor rises, ,
During the third period after the second period, the source node of the driving transistor is maintained in a floating state, and a pilot voltage different from the reference voltage is applied to the gate node of the driving transistor;
During the fourth period after the third period, the gate node of the driving transistor is electrically floated together with the source node of the driving transistor, and the voltage of the gate node of the driving transistor and the voltage of the source node of the driving transistor are rise together,
During the fifth period after the fourth period, an image data voltage is applied to a gate node of the driving transistor.
According to claim 1,
During the second period, the voltage of the source node of the driving transistor rises in a first rising pattern;
During the fourth period, the voltage of the source node of the driving transistor rises in a second rising pattern different from the first rising pattern.
According to claim 1,
During the second period, a voltage rising rate of a source node of the driving transistor decreases;
During the fourth period, a voltage rising rate of the source node of the driving transistor is constant.
According to claim 1,
At the end of the second period, the voltage of the source node of the driving transistor is different from the reference voltage by a first voltage value.
According to claim 4,
The first voltage value corresponds to the threshold voltage of the driving transistor.
According to claim 1,
The pilot voltage is variable according to the image data voltage.
According to claim 6,
The pilot voltage is variable in real time according to the image data voltage.
According to claim 6,
The display device further comprises a look-up table storing a correspondence between image data voltages and pilot voltages, wherein the pilot voltage is determined based on the look-up table.
According to claim 1,
The third period is included in one horizontal time period or spans two adjacent horizontal times.
According to claim 1,
During the fourth period,
The voltage of the gate node of the driving transistor increases by the offset voltage from the pilot voltage, and the voltage of the source node of the driving transistor increases by the offset voltage from the voltage in the third period.
According to claim 10,
A value obtained by dividing the offset voltage by the temporal length of the fourth period corresponds to the mobility of the driving transistor.
According to claim 1,
The temporal length of the fourth period is shorter than one horizontal time.
According to claim 1,
Each of the plurality of subpixels,
a light emission control transistor configured to switch a connection between a drain node of the driving transistor and a driving voltage line by being turned on and off by a light emission control signal; and
The display device further includes a sampling transistor configured to switch a connection between a drain node of the driving transistor and a body node of the driving transistor by being turned on and off controlled by a sampling signal.
According to claim 13,
Each of the plurality of subpixels further includes at least one of a first control capacitor between a source node of the driving transistor and a first control node, and a second control capacitor between a body node of the driving transistor and a source node of the driving transistor. display device.
According to claim 14,
The first control node is electrically connected to the driving voltage line.
According to claim 14,
The second control capacitor is a built-in capacitor of the driving transistor or an external capacitor of the driving transistor.
According to claim 14,
During the first period, the emission control transistor, the scan transistor, the sampling transistor, and the sensing transistor are turned on;
When the second period comes after the first period, the light emitting control transistor is turned off and the voltage difference between the ends of the second control capacitor is changed,
The sampling transistor is turned off to end the second period,
During the third period,
the emission control transistor and the sampling transistor are turned off, the sensing transistor is turned on or off, and the scan transistor is turned on;
In the fourth period after the third period, the scan transistor, the sensing transistor, and the sampling transistor are turned off, and the emission control transistor is turned on.
According to claim 1,
Each of the plurality of subpixels,
The display device further includes a light emitting control transistor configured to switch a connection between a drain node of the driving transistor and a driving voltage line by being turned on and off by a light emitting control signal.
According to claim 18,
The second period and the third period overlap.
According to claim 18,
During the first period, the scan transistor and the sensing transistor are turned on;
During the second period, the scan transistor and the light emission control transistor are turned on, and the sensing transistor is turned off;
During the third period, the scan transistor and the light emission control transistor are turned on, and the sensing transistor is turned off;
During the fourth period, the scan transistor and the sensing transistor are in a turn-off state, and the light emission control transistor is in a turn-on state;
The display device wherein the fourth period ends when the emission control transistor is turned off.
According to claim 1,
Each of the plurality of subpixels,
a light emission control transistor configured to switch a connection between a drain node of the driving transistor and a driving voltage line by being turned on and off by a light emission control signal; and
The display device further includes a reference control transistor configured to switch a connection between a gate node of the driving transistor and a reference voltage line by being turned on and off by a reference control signal.
According to claim 21,
Each of the plurality of subpixels further includes a first control capacitor between a source node of the driving transistor and a first control node.
According to claim 21,
During the first period, the reference control transistor and the sensing transistor are turned on;
During the second period, the reference control transistor and the emission control transistor are turned on, and the sensing transistor is turned off;
During the third period, the emission control transistor, the reference control transistor, and the sensing transistor are turned off, and the scan transistor is turned on;
During the fourth period, the emission control transistor is turned on, and the scan transistor, the sensing transistor, and the reference control transistor are turned off.
A method of driving a display device including a plurality of subpixels,
during a first period, applying a reference voltage to a gate node of a driving transistor in a subpixel and applying an initialization voltage to a source node of the driving transistor;
During a second period after the first period, continuously applying the reference voltage to the gate node of the driving transistor and electrically floating the source node of the driving transistor to increase the voltage of the source node of the driving transistor. ;
maintaining a source node of the driving transistor in a floating state and applying a pilot voltage different from the reference voltage to a gate node of the driving transistor during a third period after the second period;
During a fourth period after the third period, by electrically floating the gate node of the driving transistor together with the source node of the driving transistor, the voltage of the gate node of the driving transistor and the voltage of the source node of the driving transistor elevating together; and
and applying an image data voltage to a gate node of the driving transistor during a fifth period after the fourth period.
light emitting device;
a driving transistor for driving the light emitting element;
a scan transistor for switching a connection between a gate node of the driving transistor and a data line by being turned on and off controlled by a scan signal;
a sensing transistor configured to switch a connection between a source node of the driving transistor and an initialization voltage line by being turned on and off by a sensing signal;
a light emission control transistor configured to switch a connection between a drain node of the driving transistor and a driving voltage line by being turned on and off by a light emission control signal;
a reference control transistor configured to switch a connection between a gate node of the driving transistor and a reference voltage line by being turned on and off by a reference control signal;
a storage capacitor between a gate node of the driving transistor and a source node of the driving transistor; and
and a first control capacitor between a source node of the driving transistor and a first control node.

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