KR20230102601A - Display device - Google Patents

Abstract

According to an embodiment of the present invention, a display device comprises: a display panel having a plurality of sub-pixels defined including a driving transistor and a first transistor containing an oxide semiconductor; a plurality of scan wires connected to the plurality of sub-pixels to output a high-level first scan signal and a low-level second scan signal; a plurality of data wires connected to the plurality of sub-pixels to output a data voltage; and a deterioration compensation portion compensating for luminance fluctuations of the plurality of sub-pixels due to a threshold voltage shift of the first transistor. The deterioration compensation portion gradually varies at least one of the first scan signal, the second scan signal, and the data voltage according to a driving time of the display panel. Accordingly, the present invention can compensate for luminance decrease due to the threshold voltage shift of the first transistor by varying the scan signal and the data voltage without changing a design of a thickness and length of an active layer of the first transistor, the amount of impurity doping, etc.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device in which a decrease in luminance due to deterioration of a transistor of a sub-pixel is compensated for.

Display devices used in computer monitors, TVs, mobile phones, etc. include Organic Light Emitting Displays (OLEDs) that emit light by themselves, and Liquid Crystal Displays (LCDs) that require a separate light source. there is.

The range of applications of display devices is diversifying from computer monitors and TVs to personal portable devices, and research into display devices having a reduced volume and weight while having a large display area is being conducted.

Meanwhile, a plurality of sub-pixels of the display device may drive light emitting elements using a plurality of transistors. However, when the plurality of transistors are driven, stress is accumulated over time, which may cause deterioration in which a threshold voltage is shifted. Also, such a threshold voltage shift may degrade luminance of the display device.

An object to be solved by the present invention is to provide a display device in which luminance degradation due to a threshold voltage shift of an oxide semiconductor transistor is improved.

Another object to be solved by the present invention is to provide a display device capable of compensating luminance by varying only a driving voltage without changing the design of a transistor.

Another object to be solved by the present invention is to provide a display device capable of maintaining the same voltage of a gate electrode of a driving transistor even when a shift in the threshold voltage of a transistor occurs.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an exemplary embodiment of the present invention includes a display panel in which a plurality of sub-pixels including a driving transistor and a first transistor including an oxide semiconductor are defined, a plurality of sub-pixels and A plurality of scan lines connected to output a high-level first scan signal and a low-level second scan signal, a plurality of data lines connected to a plurality of sub-pixels to output data voltages, and a threshold voltage shift of a first transistor. and a deterioration compensator compensating for luminance fluctuations of a plurality of sub-pixels according to , wherein the deterioration compensator gradually varies at least one of the first scan signal, the second scan signal, and the data voltage according to the driving time of the display panel. . Therefore, according to the present invention, the decrease in luminance due to the shift in the threshold voltage of the first transistor can be compensated for only by varying the scan signal and the data voltage without changing the design of the thickness and length of the active layer of the first transistor, the amount of impurity doping, and the like. .

Other embodiment specifics are included in the detailed description and drawings.

The present invention can compensate for a decrease in luminance due to a shift in the threshold voltage of an oxide semiconductor transistor.

According to the present invention, a threshold voltage shift of a transistor and a corresponding decrease in luminance can be compensated for without changing the design of the transistor.

According to the present invention, the voltage of the gate electrode of the driving transistor is kept the same even if the transistor is deteriorated, thereby minimizing the luminance change.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present invention.
3 is a timing diagram illustrating a change in voltage of a second node of a sub-pixel of a display device according to an exemplary embodiment of the present invention.
4 is a graph showing the amount of change in the threshold voltage of the first transistor over time.
5 is a graph illustrating a drain current according to a gate-source voltage of a first transistor of a display device according to an exemplary embodiment of the present invention.
6 is a graph showing changes in luminance and current over time of a display device according to an exemplary embodiment of the present invention.
7 is a graph for explaining a method of compensating luminance of a sub-pixel in a deterioration compensator of a display device according to an exemplary embodiment of the present invention.
8 is a timing diagram illustrating a voltage change of a second node of a sub-pixel of a display device according to an exemplary embodiment of the present invention.
9 is a graph illustrating a drain current according to a gate-source voltage of a first transistor of a display device according to an exemplary embodiment of the present invention.
10 is a graph illustrating a drain current according to a gate-source voltage of a second transistor of a display device according to an exemplary embodiment of the present invention.

The advantages and features of the present invention, and how to achieve them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited thereto. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists', etc. mentioned in the present invention is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween.

In addition, although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The area and thickness of each component shown in the drawings is shown for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention. 1 illustrates a display panel 110, a gate driving unit 120, a data driving unit 130, a timing controller 140, and a degradation compensation unit 150 among various components of the display device 100 for convenience of description. did

The display device 100 includes a display panel 110 including a plurality of sub-pixels SP, a gate driver 120 supplying various signals to the display panel 110, a data driver 130, and a gate driver 120. and a timing controller 140 that controls the data driver 130 and a deterioration compensation unit 150 that compensates for deterioration of the transistors of the plurality of sub-pixels SP.

The display panel 110 is a component for displaying an image to a user. The display panel 110 includes a display area AA in which a plurality of sub-pixels SP are disposed and a non-display area NA outside the display area AA. In the display panel 110, the plurality of scan lines SL and the plurality of data lines DL cross each other, and each of the plurality of sub-pixels SP is connected to the scan lines SL and the data lines DL.

The display area AA is an area where a plurality of sub-pixels SP are disposed to display an image. A plurality of sub-pixels SP is a minimum unit constituting a screen, and a light-emitting element EL and a driving circuit for driving the light-emitting element EL may be disposed in each of the plurality of sub-pixels SP. The light emitting element EL may vary according to the type of display device 100 . For example, when the display device 100 is an organic light emitting display device, the light emitting element EL may be an organic light emitting element EL including an anode, an organic layer, and a cathode. In addition to this, a micro LED (light-emitting diode), a quantum dot light-emitting diode (QLED) including a quantum dot (QD), and the like may be further used as the light emitting element EL.

The non-display area NA is an area in which an image is not displayed, and is an area where various wires, driving ICs, etc. for driving the sub-pixels SP disposed in the display area AA are disposed. For example, various ICs such as a gate driver IC and a data driver IC and driving circuits may be disposed in the non-display area NA. Meanwhile, the non-display area NA may be located on the rear surface of the substrate, that is, the surface without the sub-pixel SP, or may be omitted, and is not limited to what is shown in the drawings.

The gate driver 120 supplies a plurality of scan signals to the plurality of scan lines SL according to the plurality of gate control signals GCS provided from the timing controller 140 . Although FIG. 1 illustrates that one gate driver 120 is spaced apart from one side of the display panel 110 , the number and arrangement of the gate driver 120 are not limited thereto.

The data driver 130 converts the image data RGB input from the timing controller 140 into data voltages using the reference gamma voltage according to the plurality of data control signals DCS provided from the timing controller 140 . Also, the data driver 130 may supply the converted data voltage to the plurality of data lines DL.

The timing controller 140 aligns image data RGB input from the outside and supplies it to the data driver 130 . The timing controller 140 may generate a gate control signal (GCS) and a data control signal (DCS) using a synchronization signal input from the outside, for example, a dot clock signal, a data enable signal, and a horizontal/vertical synchronization signal. there is. The timing controller 140 supplies the generated gate control signal GCS and data control signal DCS to the gate driver 120 and the data driver 130, respectively, to operate the gate driver 120 and the data driver 130. You can control it.

The deterioration compensator 150 compensates for a decrease in luminance due to deterioration of transistors included in each of the plurality of sub-pixels SP. The deterioration compensator 150 may compensate for a luminance change due to a shift in the threshold voltage of the transistors of the plurality of sub-pixels SP. The deterioration compensator 150 gradually varies the data voltage output from the data driver 130 or the scan signal output from the gate driver 120 according to the driving time of the display device 100 to form a plurality of sub-pixels (SP). It is possible to compensate for the luminance variation according to the threshold voltage shift of the transistor.

Meanwhile, although the degradation compensation unit 150 is illustrated as being disposed in the timing controller 140 in FIG. 1 , the degradation compensation unit 150 may be disposed independently of other components, and the data driver 130 and the gate driver (120) may be placed on each, but is not limited thereto.

Hereinafter, the plurality of sub-pixels SP will be described in more detail with reference to FIGS. 2 and 3 .

2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present invention. 3 is a timing diagram illustrating a change in voltage of a second node of a sub-pixel of a display device according to an exemplary embodiment of the present invention. 2 is a circuit diagram of a sub-pixel SP disposed in an n-th row among a plurality of sub-pixels SP.

Referring to FIG. 2 , each of the plurality of sub-pixels SP includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , It includes a sixth transistor T6, a driving transistor DT, a storage capacitor Cst, and a light emitting element EL. Each of the plurality of sub-pixels SP is connected to a plurality of scan lines SL, data lines DL, emission control signal lines, initialization lines, anode reset lines, high-potential power lines, and low-potential power lines.

The plurality of transistors of the plurality of sub-pixels SP may be formed of different types of transistors. For example, one of the plurality of transistors may be a transistor using an oxide semiconductor as an active layer. Oxide semiconductor materials have a low off-current, so they are suitable for switching transistors that maintain a short turn-on time and a long turn-off time.

For another example, another one of the plurality of transistors may be a transistor having low temperature poly-silicon (LTPS) as an active layer. Since the polysilicon material has high mobility, low power consumption, and excellent reliability, it may be suitable for the driving transistor DT.

Meanwhile, the plurality of transistors may be N-type transistors or P-type transistors. Since electrons are carriers in the N-type transistor, electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. Since holes are carriers in the P-type transistor, holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. For example, one transistor among the plurality of transistors may be an N-type transistor, and another transistor among the plurality of transistors may be a P-type transistor.

For example, the first transistor T1 may be an N-type transistor and include an oxide semiconductor as an active layer. The driving transistor DT, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type transistors and low-temperature polysilicon. It may be a transistor serving as an active layer. However, the material constituting the active layer of the plurality of transistors and the type of the plurality of transistors are examples, and are not limited thereto.

The first transistor T1 includes a gate electrode, a drain electrode and a source electrode. The gate electrode is connected to the first scan wire in the n-th row, the drain electrode is connected to the second node N2, and the source electrode is connected to the third node N3. The first transistor T1 is turned on by the first scan signal SCAN1(n) to electrically connect the second node N2 and the third node N3. In this case, the first transistor T1 is implemented as an oxide semiconductor transistor having a low off-state current, so that leakage of current from the gate electrode of the driving transistor DT can be minimized.

The second transistor T2 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the second scan line in the n-th row, the source electrode is connected to the data line DL, and the drain electrode is connected to the first node N1. The second transistor T2 is turned on by the second scan signal SCAN2(n) to transfer the data voltage Vdata from the data line DL to the first node N1.

The third transistor T3 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the emission control signal line in the nth row, and the source and drain electrodes are connected between the high potential power line and the first node N1. The third transistor T3 may be turned on by the emission control signal EM(n) to transfer the high-potential power supply voltage VDD to the first node N1.

The fourth transistor T4 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the emission control signal line in the n-th row, and the source and drain electrodes are connected between the third node N3 and the fourth node N4. The fourth transistor T4 may be turned on by the emission control signal EM(n) to transfer the driving current from the driving transistor DT to the light emitting element EL.

The fifth transistor T5 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the third scan line in the nth row, and the source and drain electrodes are connected between the initialization line and the third node N3. The fifth transistor T5 may be turned on by the third scan signal SCAN3(n) to transfer the initialization voltage Vini(n) to the third node N3.

The sixth transistor T6 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the third scan line in the n+1th row, and the source and drain electrodes are connected between the anode reset line and the fourth node N4. The sixth transistor T6 may be turned on by the third scan signal SCAN3(n+1) to transfer the anode reset voltage VAR to the fourth node N4.

The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the second node N2, the source electrode is connected to the first node N1, and the drain electrode is connected to the third node N3. The driving transistor DT may supply a driving current to the light emitting element EL.

The storage capacitor Cst includes a plurality of capacitor electrodes. Some of the plurality of capacitor electrodes are connected to the high-potential power line, and others are connected to the second node N2. The voltage of the gate electrode of the driving transistor DT may be stored in the storage capacitor Cst.

The light emitting element EL includes an anode and a cathode. The anode of the light emitting element EL is connected to the fourth node N4, and the cathode is connected to the low potential power line to which the low potential power supply voltage VSS is supplied. The light emitting element EL may emit light by a driving current from the driving transistor DT.

Meanwhile, the driving current flowing from the driving transistor DT to the light emitting element EL may be determined based on the voltage of the gate electrode of the driving transistor DT, that is, the voltage of the second node N2. The magnitude of the driving current may be determined according to the magnitude of the voltage applied to the second node N2. Further, the voltage of the second node N2 varies according to the operation of the first transistor T1 connected to the second node N2 and the second transistor T2 that transfers the data voltage Vdata to the driving transistor DT. can

In this regard, referring to FIG. 3 , in a process in which the first transistor T1 and the second transistor T2 are turned on or off by the scan signal transmitted to the first scan wire and the second scan wire, respectively. The voltage of the second node N2 may vary.

First, a high level first scan signal SCAN1(n) is output to the first scan wire at an initial time point t0. The first transistor T1 is turned on by the high-level first scan signal SCAN1(n) to connect the second node N2 and the third node N3. The first transistor T1 is turned on so that the gate electrode and drain electrode of the driving transistor DT can be connected, and the driving transistor DT can be in a diode connection state functioning like a diode.

Subsequently, the low-level second scan signal SCAN2(n) is output to the second scan wire at the first time point t1. The second transistor T2 is turned on by the low-level second scan signal SCAN2(n) to transfer the data voltage Vdata from the data line DL to the first node N1. In this case, current may flow from the source electrode to the drain electrode of the diode-connected driving transistor DT, and the voltage of the second node N2 may increase. Accordingly, the voltage of the second node N2 may increase until the value obtained by subtracting the threshold voltage of the driving transistor DT from the data voltage Vdata. Accordingly, the period from the first point in time t1 to the second point in time t2 when the low-level second scan signal SCAN2(n) is output and the data voltage Vdata is input may also be referred to as a sampling period. there is.

Next, since the low-level second scan signal SCAN2(n) is not output from the second scan wire at the second time point t2, the second transistor T2 may be turned off. At this time, a kick-back phenomenon in which the voltage of the second node N2 is varied due to the turned-off second transistor T2 may occur. For example, when the second transistor T2 is turned off, the voltage of the second node N2 may vary in an increasing direction due to a kickback phenomenon.

During the kickback phenomenon, the amount of change in the voltage of the second node N2 may vary according to the amount of current and charge flowing through the second transistor T2. For example, since the amount of current and charge flowing through the second transistor T2 does not substantially exist immediately after the second transistor T2 is turned on from the turn-off state, the amount of voltage change due to the kickback phenomenon It can be few or zero. Conversely, when the second transistor T2 is turned off from the turn-on state, a voltage change amount may be relatively large due to the current flowing through the second transistor T2 and the amount of charge thereof. Accordingly, the voltage of the second node N2 may increase due to the kickback phenomenon at the second time point t2 when the second transistor T2 is turned off.

However, although the second transistor T2 is not directly connected to the second node N2, the voltage of the second node N2 may be affected by kickback due to parasitic capacitance. Specifically, since the second node N2 is a node connected to the storage capacitor Cst, it may include one of the electrodes forming the storage capacitor Cst. An electrode forming the storage capacitor Cst may have a relatively large area among components disposed in the sub-pixel SP, and it may be easy to form parasitic capacitance with other components of the sub-pixel SP. Therefore, when the second transistor T2 is turned off, the voltage of the second node N2 may vary due to the parasitic capacitance.

Subsequently, since the high level first scan signal SCAN1(n) is not output from the first scan wire at the third time point t3, the first transistor T1 may be turned off. In this case, the voltage of the second node N2 may vary according to the kickback phenomenon. For example, when the first transistor T1 is turned off, a kickback phenomenon may occur in a direction in which the voltage of the second node N2 decreases.

Specifically, when the second transistor T2, which is a P-type transistor, is turned off, a kickback phenomenon occurs in the direction in which the voltage of the second node N2 increases, but the first transistor T1, which is an N-type transistor, is turned off. - When turned off, a kickback phenomenon may occur in a direction in which the voltage of the second node N2 decreases. Accordingly, the voltage of the second node N2 is obtained by subtracting the threshold voltage of the driving transistor DT from the data voltage Vdata through the second time point t2 and the third time point t3. and a voltage in which the kickback phenomenon by the second transistor T2 is reflected.

Therefore, from the fourth time point t4 after the third time point t3 when the first transistor T1 is turned off, the driving current based on the voltage of the gate electrode of the driving transistor DT and the voltage of the second node N2 may be transferred to the light emitting element EL.

Meanwhile, the first transistor T1 including an oxide semiconductor may receive stress due to positive bias temperature stress (PBTS) during driving. The first transistor T1 may be deteriorated in that the threshold voltage of the first transistor T1 increases with time due to the PBTS phenomenon that applies stress. If the threshold voltage of the first transistor T1 is shifted, the kickback effect of the first transistor T1 is reduced, so that the amount of decrease in the voltage of the second node N2 at the third point in time t3 is less than before. For example, a target driving current can be generated only when the voltage of the second node N2 is reduced to the first voltage V1 according to the kickback effect of the first transistor T1 at the third point in time t3. The threshold voltage of the first transistor T1 is shifted and the voltage of the second node N2 may decrease only up to the second voltage V2. Therefore, the voltage of the gate electrode of the driving transistor DT may vary and the luminance may also vary according to the shift in the threshold voltage of the first transistor T1 .

Hereinafter, a process in which the luminance of the sub-pixel SP varies due to the shift in the threshold voltage of the first transistor T1 will be described in more detail with reference to FIGS. 4 to 6 .

4 is a graph showing a change in threshold voltage of a first transistor over time of a display device according to an exemplary embodiment of the present invention. 5 is a graph illustrating a drain current according to a gate-source voltage of a first transistor of a display device according to an exemplary embodiment of the present invention. 6 is a graph showing changes in luminance and current with time.

Referring to FIG. 4 , the first transistor T1 is an N-type oxide semiconductor transistor unlike other transistors of the plurality of sub-pixels SP. During the driving process, the first transistor T1 may be degraded by receiving stress due to positive bias temperature stress (PBTS) and may be shifted in a direction in which the threshold voltage increases.

Referring to FIG. 5 together, when the threshold voltage of the first transistor T1 is shifted, the kickback effect may be reduced when the first transistor T1 is turned off.

Specifically, the threshold voltage of the first transistor T1 before being stressed may be, for example, 0V. And when the gate-source voltage (Vgs) of the first transistor T1, that is, the voltage applied to the gate electrode of the first transistor T1 becomes a voltage of 0V or more, between the source electrode and the drain electrode of the first transistor T1 The amount of drain current Id flowing through may increase. Accordingly, the drain current Id may increase until the voltage of the gate electrode of the first transistor T1 becomes equal to the gate high voltage VGH, which is the high level first scan signal SCAN1(n). , after that, the drain current (Id) may become a constant level in a saturation region.

After receiving the stress, the threshold voltage of the first transistor T1 is shifted in a positive direction, and it can be seen that the drain current Id is generated at a voltage higher than 0V. The first transistor T1 after being stressed is turned on only when a higher voltage is applied to the gate electrode than that of the first transistor T1 before being stressed so that the drain current Id can flow.

At this time, the drain current (Id), which is the vertical axis of the graph, can also be seen as the capacitance of the first transistor (T1). In this case, the area under the drain current Id curve between the threshold voltage at which the drain current Id is generated and the gate high voltage VGH may be the amount of charge. In addition, as the charge amount decreases, the amount of voltage decrease due to the kickback phenomenon may also decrease. For example, the area under the curve between the voltage of 0V, the threshold voltage before stress, and the gate high voltage (VGH) can be larger than the area under the curve between the threshold voltage and the gate high voltage (VGH) after stress. there is. Therefore, the charge amount of the drain current Id flowing through the first transistor T1 after the stress may be reduced compared to before the stress. Therefore, as shown in FIG. 3, the voltage of the second node N2 is reduced to the first voltage V1 by the kickback effect of the first transistor T1 before being stressed, but after being stressed, the amount of charge As a result of this decrease, the voltage of the second node N2 may be reduced only up to the second voltage V2.

In summary, when the threshold voltage of the first transistor T1 increases due to stress, even if the same voltage is applied to the gate electrode of the first transistor T1, the current flowing through the first transistor T1 and the amount of charge thereof decrease. And, the amount of voltage change due to the kickback phenomenon can be reduced. Therefore, since the kickback effect of the first transistor T1 is reduced, the amount of voltage reduction at the second node N2 may be less than before, and the voltage at the second node N2 cannot be set to a desired voltage. For example, the voltage at the second node N2 should be reduced to the first voltage V1 according to the kickback effect of the first transistor T1 at the third point in time, but the threshold voltage of the first transistor T1 shifts. and the voltage of the second node N2 may decrease only up to the second voltage V2. Therefore, the voltage of the gate electrode of the driving transistor DT may vary and the luminance may also vary according to the shift in the threshold voltage of the first transistor T1 .

Referring to FIG. 6 , as the driving time of the display panel 110 increases, the threshold voltage of the first transistor T1 shifts, so that the voltage of the gate electrode of the driving transistor DT may increase and the driving current may decrease. can confirm that The driving transistor DT is a P-type transistor, and more driving current can flow as the voltage of the gate electrode decreases in the negative direction. However, when the threshold voltage of the first transistor T1 increases, the voltage of the gate electrode decreases relatively , the driving current may also decrease.

In addition, it can be seen that the luminance of the display device 100 also decreases as the driving current from the driving transistor DT decreases over time. Accordingly, the threshold voltage of the first transistor T1 is gradually shifted, and thus the driving current and luminance may decrease.

Conventionally, in order to solve the threshold voltage shift phenomenon of the first transistor, an initial threshold voltage has been lowered by changing design conditions of the first transistor. As the initial threshold voltage is lowered, the amount of change in the threshold voltage due to the PBTS phenomenon can be further reduced. For example, the thickness of the oxide semiconductor layer of the first transistor may be increased, the length of the oxide semiconductor layer may be reduced, or the doping amount of an impurity such as boron may be decreased to determine the initial threshold of the first transistor. voltage could be controlled. However, when the device characteristics of the first transistor are changed as described above, the leakage current increases due to the short channel effect, and even if a voltage higher than the threshold voltage is not applied to the gate electrode, the gap between the source electrode and the drain electrode current can flow through it. That is, when the characteristics of the oxide semiconductor layer of the first transistor are changed, the first transistor may become a conductor due to the short channel effect, leading to defective bright points in the sub-pixels. In addition, the initial threshold voltage characteristic of the first transistor is changed and current consumption may increase.

Therefore, in the display device 100 according to an exemplary embodiment of the present invention, instead of changing the design conditions of the first transistor T1, the voltage applied from the degradation driver 150 to the sub-pixel SP is gradually changed to A threshold voltage shift of one transistor T1 and a voltage variation of the second node N2 may be compensated for, and reduction of luminance and driving current may be minimized.

Hereinafter, a method of compensating for a decrease in driving current and luminance due to a shift in the threshold voltage of the first transistor T1 will be described with reference to FIGS. 7 to 10 .

7 is a graph for explaining a method of compensating for luminance of a sub-pixel in a deterioration compensator of a display device according to an exemplary embodiment of the present invention. 8 is a timing diagram illustrating a voltage change of a second node of a sub-pixel of a display device according to an exemplary embodiment of the present invention. 9 is a graph illustrating a drain current according to a gate-source voltage of a first transistor of a display device according to an exemplary embodiment of the present invention. 10 is a graph illustrating a drain current according to a gate-source voltage of a second transistor of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 7 , the deterioration compensator 150 of the display device 100 according to an exemplary embodiment of the present invention increases the data voltage Vdata and the gate low voltage VGL as the driving time of the display panel 110 increases. In addition, the gate high voltage VGH may be gradually varied to compensate for a driving current and luminance deterioration caused by a shift in the threshold voltage of the first transistor T1 .

At this time, the gate high voltage VGH is the voltage of the first scan signal SCAN1(n) applied to the gate electrode of the N-type first transistor T1 as described above with reference to FIG. 5, and the gate low voltage VGL ) is the voltage of the second scan signal SCAN2(n) applied to the gate electrode of the P-type second transistor T2.

Data about changes in the data voltage Vdata, the gate high voltage VGH, and the gate low voltage VGL according to the driving time of the display panel 110 may be previously stored in the degradation compensator 150 . Threshold voltage shift information of the first transistor T1 may be detected through a preliminary test of the display device 100, and the deterioration compensator 150 includes a data voltage Vdata based on the threshold voltage shift information and a gate high voltage ( VGH) and change amount information of the gate low voltage VGL may be stored.

First, referring to FIGS. 7 and 8 together, the deterioration compensator 150 gradually increases the data voltage Vdata according to the driving time of the display device 100 to determine the threshold voltage shift of the first transistor T1. Driving current and luminance deterioration can be compensated for.

The voltage of the second node N2 is increased by the data voltage Vdata applied to the first node N1 from the first time point t1 when the second transistor T2 is turned on to the second time point t2. The voltage may be increased to a voltage obtained by subtracting the threshold voltage of the driving transistor DT from the data voltage Vdata. Further, as shown in FIG. 7 , when the data voltage Vdata is gradually decreased, the amount of voltage increase at the second node N2 between the first time point t1 and the second time point t2 may also decrease.

Assuming that the same image is displayed on the display device 100, the voltage of the second node N2 may increase as indicated by a solid line at the beginning of product use, when the threshold voltage shift of the first transistor T1 is almost zero. When the threshold voltage shift of the first transistor T1 occurs after a certain period of time, the data voltage Vdata output to the sub-pixel SP is reduced to reduce the voltage of the second node N2 with a waveform like a dotted line. can elevate

Subsequently, when the second transistor T2 is turned off at the second time point t2, the voltage at the second node N2 may increase by a certain amount due to a kickback phenomenon. At the beginning of product use, the voltage of the second node N2 rises by a certain amount from a relatively high point, for example, the solid line at the second time point t2, but after the threshold voltage shift of the first transistor T1 occurs, The voltage of the second node N2 may rise by a certain amount from a relatively low point, for example, the dotted line at the second time point t2. That is, after the threshold voltage of the first transistor T1 is shifted, the voltage of the second node N2 may be set to a relatively low voltage during the sampling period by the low data voltage Vdata, and the second transistor ( Even under the kickback effect of T2), the voltage finally raised between the second time point t2 and the third time point t3 may decrease overall.

Also, the voltage of the second node N2 may decrease due to a kickback phenomenon that occurs when the first transistor T1 is turned off at the third point in time t3. The voltage of the second node N2 may decrease from a relatively high voltage at the beginning of product use, but after deterioration, the voltage of the second node N2 may decrease from a relatively low voltage. When the first transistor T1 is turned off at the initial stage of product use, the voltage may decrease relatively greatly, and after deterioration, the voltage may decrease relatively small. At the beginning of product use, the voltage of the second node N2 is relatively high at the third point in time t3, and the amount of voltage drop due to the kickback phenomenon of the first transistor T1 may be relatively large. After deterioration, the voltage of the second node N2 is relatively low at the third point in time t3, and the amount of voltage drop due to the kickback phenomenon of the first transistor T1 may be relatively small. Accordingly, the decrease in the voltage change due to the shift in the threshold voltage of the first transistor T1 may be compensated for by lowering the initial voltage at which the voltage starts to decrease at the third time point t3 .

For example, the threshold voltage of the driving transistor DT is 0V, the data voltage Vdata initially applied is 10V, the data voltage Vdata after stress is 8V, and the turn-off of the second transistor T2 is Assuming that the voltage increase according to the voltage is 2V, the voltage of the second node N2 becomes 10V at the second time point t2 before the stress, and the second node N2 during the second time point t2 and the third time point t3 The voltage of (N2) can be set to 12V. After receiving the stress, the voltage of the second node N2 is set to 8V at the second time point t2, and the voltage of the second node N2 is set to 10V during the second time point t2 and the third time point t3. can Accordingly, from the third point in time t3 when the first transistor T1 is turned off before receiving the stress, the voltage at the second node N2 may decrease from 12V due to the kickback effect, and after receiving the stress, the voltage may decrease to 10V. voltage may decrease. If the 3V voltage decreases due to the kickback of the first transistor T1 before being stressed and the 1V voltage decreases after being stressed, the voltage of the second node N2 is finally set to be the same as 9V. can Accordingly, as the driving time of the display panel 110 increases, the threshold voltage of the first transistor T1 shifts due to the stress, so that the amount of change in the voltage of the second node N2 decreases at the third point in time t3, but the third At the time point t3, the voltage change amount difference according to the threshold voltage shift may be compensated for by lowering the initial voltage itself at which the voltage starts to decrease.

Next, referring to FIGS. 7 and 8 , the degradation compensator 150 gradually increases the gate high voltage VGH according to the driving time of the display device 100 to correspond to the shift of the threshold voltage of the first transistor T1. It is possible to compensate for driving current and luminance deterioration according to the present invention. The amount of voltage drop affected by kickback when the first transistor T1 is turned off may be increased by increasing the gate high voltage VGH.

In this regard, referring to FIG. 9 together, stress is accumulated over time, so that the drain current Id curve of the first transistor T1 may shift in a positive direction. As described above with reference to FIGS. 4 and 5 , the area under the curve between the gate high voltage VGH and the threshold voltage may correspond to the amount of voltage drop caused by the kickback effect. As the area under the curve increases, the amount of voltage change and voltage decrease at the second node N2 at the third time point t3 increases, and as the area under the curve decreases, the amount of voltage decrease at the second node N2 decreases. can do. For example, as the area of the area under the curve increases, the voltage of the second node N2 may decrease a lot at the third time point t3, and as the area of the area under the curve increases, the voltage of the second node N2 may decrease at the third time point t3. The voltage of the second node N2 may decrease slightly.

Therefore, if the gate high voltage (VGH) is gradually increased to correspond to the drain current (Id) curve shifted to the right, the area under the curve in the region between the threshold voltage and the gate high voltage (VGH) will be maintained at a similar level. can

For example, if the gate high voltage VGH before being stressed is referred to as a first gate high voltage VGH1 and the gate high voltage VGH after being stressed is referred to as a second gate high voltage VGH2, The area under the curve between the first gate high voltage VGH1 and the threshold voltage before being stressed may correspond to the area under the curve between the second gate high voltage VGH2 and the threshold voltage. Accordingly, when the first transistor T1 is turned off by increasing the gate high voltage VGH over time, the amount of voltage change at the second node N2 due to the kickback effect may be maintained at a similar level.

Next, referring to FIGS. 7 and 8 , the degradation compensation unit 150 reduces the absolute value of the gate low voltage VGL according to the driving time of the display device 100 to shift the threshold voltage of the first transistor T1. It is possible to compensate for the driving current and luminance deterioration according to . By reducing the absolute value of the gate low voltage VGL, the amount of change in the voltage of the second node N2 due to the kickback phenomenon when the second transistor T2 is turned off may be reduced. The gate low voltage VGL is a negative voltage, and the gate low voltage VGL is increased to approach 0V, that is, the absolute value of the gate low voltage VGL is reduced to control when the second transistor T2 is turned off. A voltage increase amount of the second node N2 may be reduced.

Specifically, referring to FIG. 10 , the second transistor T2 is a P-type transistor and may have a waveform opposite to that of the first N-type transistor T1. A gate low voltage VGL having a negative value may be applied to the gate electrode of the second transistor T2 , and the drain current Id of the second transistor T2 may also have a negative value. However, in FIG. 10, for convenience of explanation, the drain current (Id) value on the vertical axis is expressed as an absolute value.

When a voltage of 0 V or less is applied to the second transistor T2 , the amount of drain current Id flowing between the source electrode and the drain electrode may increase. Accordingly, the current amount of the drain current Id increases until the voltage of the gate electrode of the second transistor T2 becomes equal to the gate low voltage VGL, which is the low-level second scan signal SCAN2(n). After that, the drain current Id may become a constant level in a saturation region.

Similarly to the first transistor T1 , the area under the curve between the gate low voltage VGL and the threshold voltage of the second transistor T2 may correspond to the amount of voltage change due to the kickback. As the area under the curve between the gate low voltage VGL and the threshold voltage increases, the voltage increase and voltage change at the second node N2 between the second time point t2 and the third time point t3 may increase. As the area under the curve between the gate low voltage VGL and the threshold voltage decreases, the amount of change in the voltage at the second node N2 may decrease. For example, as the area under the curve between the gate low voltage VGL and the threshold voltage increases, the voltage at the second node N2 may increase a lot, and as the area under the curve decreases, the second node ( The voltage of N2) may rise slightly.

Therefore, if the gate low voltage VGL is gradually increased toward 0 as the driving time of the display panel 110 increases, the area under the curve between the gate low voltage VGL and the threshold voltage may decrease. For example, if the gate low voltage VGL before the stress is the first gate low voltage VGL1 and the gate low voltage VGL after the stress is the second gate low voltage VGL2, the first gate low voltage An area under the curve between the voltage VGL1 and the threshold voltage may be larger than an area under the curve between the second gate low voltage VGL2 and the threshold voltage. Therefore, after receiving the stress, the voltage increase amount of the second node N2 when the second gate low voltage VGL2 is applied to the sub-pixel SP is the first gate low voltage VGL1 as the second scan signal ( As SCAN2(n), it may be smaller than the voltage increase amount of the second node N2 when applied to the sub-pixel SP. Accordingly, by reducing the absolute value of the gate low voltage VGL in consideration of the shift in the threshold voltage of the first transistor T1 over time, the voltage of the second node N2 at the third point in time t3 is reduced to a lower voltage. , and it is possible to compensate for a decrease in the amount of voltage decrease due to the kickback effect of the first transistor T1 after the third point in time t3.

Meanwhile, the deterioration compensator 150 gradually decreases the data voltage Vdata according to the driving time, gradually increases the gate high voltage VGH, and gradually increases the gate low voltage VGL. Although the threshold voltage shift of the first transistor T1 may be compensated for using all of them, only one of the three methods may be selected and used, but is not limited thereto.

Therefore, in the deterioration compensation unit 150 of the display device 100 according to an exemplary embodiment of the present invention, at least one of the data voltage Vdata, the gate low voltage VGL, and the gate high voltage VGH is applied to the display device ( 100) may be gradually varied according to the driving time, thereby compensating for a luminance change due to a shift in the threshold voltage of the first transistor T1. The first transistor T1 is an N-type transistor including an oxide semiconductor, and may be shifted in a direction in which a threshold voltage increases as stress accumulates over time. When the first transistor T1 is turned off, the voltage of the gate electrode of the driving transistor DT and the voltage of the second node N2 may decrease due to the kickback phenomenon, but the threshold voltage of the first transistor T1 When this is shifted, the amount of voltage reduction of the gate electrode decreases, and thus luminance may vary. Accordingly, the voltage of the second node N2 may not be charged high from the beginning by gradually decreasing the data voltage Vdata according to the driving time. The threshold voltage shift of the first transistor T1 may be compensated for by reducing the voltage of the second node N2 in advance before being affected by the kickback of the first transistor T1 .

Next, the voltage decrease due to the kickback effect of the first transistor T1 may be compensated for by gradually increasing the gate high voltage VGH. As much as the threshold voltage of the first transistor T1 is shifted, the gate high voltage VGH, which is the voltage of the first scan signal SCAN1(n) applied to the gate electrode of the first transistor T1, may be increased. When the gate high voltage VGH is raised to the same level as the threshold voltage, the current and charge amount flowing through the first transistor T1 can be maintained at the same level, and the second transistor T1 generated when the first transistor T1 is turned off can be maintained. The voltage reduction amount of the node N2 may be maintained the same. Accordingly, the threshold voltage of the first transistor T1 is shifted by gradually increasing the gate high voltage VGH, which is the first scan signal SCAN1(n) applied to the gate electrode of the first transistor T1 according to the driving time. can compensate for

Finally, the absolute value of the gate low voltage VGL may be gradually decreased to reduce the amount of voltage increase at the second node N2 due to the kickback phenomenon when the second transistor T2 is turned off. When the second transistor T2 is turned off, the voltage of the second node N2 may also vary due to the parasitic capacitance. For example, when the second transistor T2 is turned off, the voltage of the second node N2 may vary in an increasing direction. However, when the voltage of the second scan signal SCAN2(n) applied to the gate electrode of the second transistor T2 lowers the absolute value of the gate low voltage VGL, the amount of current and charge flowing through the second transistor T2 is reduced. and the amount of change in the voltage of the second node N2 can be reduced. If the absolute value of the gate low voltage VGL is decreased, the voltage at the second node N2 may increase slightly. Accordingly, the absolute value of the gate low voltage VGL may be decreased so that the voltage at the second node N2 increases slightly when the second transistor T2 is turned off. Therefore, the voltage of the second node N2 may be reduced in advance by gradually decreasing the absolute value of the gate low voltage VGL according to driving time, and the threshold voltage shift of the first transistor T1 may be compensated for.

A display device according to embodiments of the present invention can be described as follows.

A display device according to an exemplary embodiment of the present invention includes a display panel in which a plurality of sub-pixels including a driving transistor and a first transistor including an oxide semiconductor are defined, and a high-level first scan signal connected to the plurality of sub-pixels. and a plurality of scan lines outputting a low-level second scan signal, a plurality of data lines connected to the plurality of sub-pixels and outputting data voltages, and luminance variation of the plurality of sub-pixels according to the threshold voltage shift of the first transistor. and a deterioration compensator that compensates for the deterioration compensator, wherein the deterioration compensator gradually varies at least one of the first scan signal, the second scan signal, and the data voltage according to a driving time of the display panel.

According to another feature of the present invention, the driving transistor has a source electrode, a gate electrode, and a drain electrode connected to the first node, the second node, and the third node, respectively, and the source electrode and the drain electrode of the first transistor are connected to the second node. It is connected between the third nodes, the first transistor is turned on based on the first scan signal, and when the first transistor is turned off from the turned on state, the voltage of the second node may decrease. there is.

According to another feature of the present invention, the first transistor may be shifted in a direction in which the threshold voltage increases according to the driving time of the display panel.

According to another feature of the present invention, the degradation compensator may gradually increase the gate high voltage, which is the first scan signal, according to the driving time of the display panel.

According to another feature of the present invention, when the first transistor is turned off, the voltage reduction amount of the second node may be the same.

According to another feature of the present invention, each of the plurality of sub-pixels further includes a second transistor connected between the second node and the plurality of data lines and turned on based on the second scan signal, When the transistor is turned off from the turn-on state, the voltage of the second node may increase.

According to another feature of the present invention, the deterioration compensator may gradually decrease an absolute value of the gate low voltage, which is the second scan signal, according to the driving time of the display panel.

According to another feature of the present invention, when the first transistor is turned off from a turn-on state according to the driving time of the display panel, the voltage reduction amount of the second node decreases, and the second node decreases according to the driving time of the display panel. When the two transistors are turned off from the turn-on state, the amount of voltage increase at the second node may decrease.

According to another feature of the present invention, the degradation compensator may gradually decrease the data voltage according to the driving time of the display panel.

According to another feature of the present invention, when the second transistor is in a turn-on state, the voltage of the second node may rise to a voltage obtained by subtracting the threshold voltage of the driving transistor from the data voltage.

According to another feature of the present invention, when the first transistor is turned off from a turn-on state according to the driving time of the display panel, the amount of voltage reduction of the second node decreases, and the data according to the driving time of the display panel. A voltage increase amount of the second node due to the voltage may decrease.

According to another feature of the present invention, the voltage of the second node rises by the data voltage from the first time point to the second time point, and increases because the second transistor is turned off from the second time point to the third time point. , the first transistor is turned off from the third point in time and may decrease.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: gate driver
130: data driving unit
140: timing controller
150: deterioration compensation unit
SP: sub pixel
AA: display area
NA: non-display area
T1: first transistor
T2: second transistor
T3: third transistor
T4: fourth transistor
T5: fifth transistor
T6: sixth transistor
DT: drive transistor
Cst: storage capacitor
EL: light emitting element
N1: first node
N2: second node
N3: third node
N4: fourth node
SCAN1(n): first scan signal
SCAN2(n): second scan signal
SCAN3(n), SCAN3(n+1): 3rd scan signal
Vdata: data voltage
EM(n): emission control signal
Vini(n): initialization voltage
VAR: anode reset voltage
VDD: high potential supply voltage
VSS: Low Potential Supply Voltage
V1: first voltage
V2: second voltage
VGH: gate high voltage
VGL: Gate Low Voltage

Claims (12)

a display panel in which a plurality of sub-pixels including a driving transistor and a first transistor including an oxide semiconductor are defined;
a plurality of scan lines connected to the plurality of sub-pixels to output a first scan signal of a high level and a second scan signal of a low level;
a plurality of data wires connected to the plurality of sub-pixels to output data voltages; and
a deterioration compensator compensating for a luminance change of the plurality of sub-pixels according to a threshold voltage shift of the first transistor;
The degradation compensator gradually varies at least one of the first scan signal, the second scan signal, and the data voltage according to a driving time of the display panel. According to claim 1,
In the driving transistor, a source electrode, a gate electrode, and a drain electrode are respectively connected to a first node, a second node, and a third node;
The first transistor has a source electrode and a drain electrode connected between the second node and the third node,
The first transistor is turned on based on the first scan signal,
The display device of claim 1 , wherein the voltage of the second node decreases when the first transistor is turned off from a turn-on state. According to claim 2,
The first transistor is shifted in a direction in which the threshold voltage increases according to a driving time of the display panel. According to claim 3,
The degradation compensator gradually increases the gate high voltage, which is the first scan signal, according to a driving time of the display panel. According to claim 4,
When the first transistor is turned off, the voltage reduction amount of the second node is the same. According to claim 2,
Each of the plurality of sub-pixels,
A second transistor connected between the second node and the plurality of data lines and turned on based on the second scan signal;
When the second transistor is turned off from a turn-on state, a voltage of the second node increases. According to claim 6,
The degradation compensator gradually reduces an absolute value of a gate low voltage of the second scan signal according to a driving time of the display panel. According to claim 7,
a voltage reduction amount of the second node decreases when the first transistor is turned off from a turn-on state according to a driving time of the display panel;
The display device of claim 1 , wherein an amount of a voltage rise of the second node decreases when the second transistor is turned off from a turn-on state according to a driving time of the display panel. According to claim 6,
The degradation compensator gradually reduces the data voltage according to a driving time of the display panel. According to claim 9,
When the second transistor is in a turn-on state, the voltage of the second node rises to a voltage obtained by subtracting a threshold voltage of the driving transistor from the data voltage. According to claim 10,
a voltage reduction amount of the second node decreases when the first transistor is turned off from a turn-on state according to a driving time of the display panel;
The display device of claim 1 , wherein a voltage increase amount of the second node by the data voltage decreases according to a driving time of the display panel. According to claim 6,
The voltage of the second node increases due to the data voltage from the first time point to the second time point, rises when the second transistor is turned off between the second time point and the third time point, and rises at the third time point. From then on, the first transistor is turned off and decreases.

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