KR101980763B1 - Organic light emitting diode display device and method for driving the same - Google Patents

Abstract

The present invention amplifies and compensates for the threshold voltage of a driving transistor provided in a pixel circuit of an organic light emitting diode display panel, minimizes loss due to parasitic components, thereby improving image display quality and further increasing the lifetime and reliability of the display panel The present invention relates to an organic light emitting diode (OLED) display device and a method of driving the same, and includes a plurality of sub-pixels for displaying an image; Each sub-pixel having a first switching element for charging a storage capacitor by supplying a data voltage from a data line to a first node in response to a gate-on signal from a gate line, A second switching element which forms a current path between the first node and the second node and a current path between the third node and the supply line of the first power supply signal according to the voltage level of the second node, A third switching element for supplying an initialization voltage to the third node in response to an initialization signal from the initialization line, a third switching element for supplying a compensation voltage from the compensation power supply line to the second node in response to the initialization signal, A fourth switching element for supplying the first node and the second node, And a first stabilization capacitor formed between the second node and the third node to which a gate electrode of the drive switching element is connected, the storage capacitor being connected between the first node and the third node, 1 and the second node, and when the first switching device is turned off, the ON state of the driving switching device is maintained for at least one frame period by using the stored voltage.

Description

Technical Field [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention amplifies and compensates for the threshold voltage of a driving transistor provided in a pixel circuit of an organic light emitting diode display panel, minimizes loss due to parasitic components, thereby improving image display quality and further increasing the lifetime and reliability of the display panel And a method of driving the organic light emitting diode display device.

BACKGROUND ART [0002] Recently, flat panel displays that are emerging include liquid crystal displays (LCDs), field emission displays, plasma display panels, and organic light emitting diodes Emitting Display). Among them, organic light emitting diode display devices are self-luminous devices that emit organic light emitting layers by recombination of electrons and holes, and are expected to be a next generation display device because they have a high brightness, a low driving voltage and an ultra thin film.

Each of the plurality of unit pixels constituting the organic light emitting diode display device includes an organic light emitting diode composed of an organic light emitting layer between an anode and a cathode, and a pixel circuit for independently driving each organic light emitting diode.

The pixel circuit mainly includes a switching transistor, a capacitor, and a driving transistor. The switching transistor charges a data signal in a capacitor in response to a scan pulse, and the driving transistor adjusts the gradation of each pixel by adjusting a magnitude of a current supplied to each organic light emitting diode according to a magnitude of a data voltage charged in the capacitor.

However, the current driving capability of such pixel circuits is greatly affected by the threshold voltages of the driving transistors. Techniques for compensating or compensating for the deviation of the current driving capability of the driving transistor and the switching transistor, for example, techniques for minimizing the capacitance of the parasitic capacitors present in the pixel circuit and minimizing the loss due to the coupling of the nodes Is required. Recently, efforts to minimize the threshold voltage loss of the driving transistor have continued, but since the structure of the pixel circuit becomes more complicated and the capacitance and the coupling phenomenon of the parasitic capacitor have to be always considered, more efforts are needed to solve the technical problem And the like.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to improve the image display quality by minimizing the loss due to parasitic components by amplifying and compensating the threshold voltage of the driving transistors provided in the pixel circuits of the organic light emitting diode display panel. And an organic light emitting diode (OLED) display device and a method of driving the organic light emitting diode display device, which can improve lifetime and reliability of a display panel.

According to an aspect of the present invention, there is provided an organic light emitting diode (OLED) display device including a plurality of sub-pixels for displaying an image, Each sub-pixel having a first switching element for charging a storage capacitor by supplying a data voltage from a data line to a first node in response to a gate-on signal from a gate line, A second switching element which forms a current path between the first node and the second node and a current path between the third node and the supply line of the first power signal according to the voltage level of the second node, A third switching element for supplying an initialization voltage to the third node in response to an initialization signal from the initialization line, a third switching element for supplying a compensation voltage from the compensation power supply line to the second node in response to the initialization signal, A fourth switching element for supplying the first node and the second node, And a first stabilization capacitor formed between the second node and the third node to which a gate electrode of the drive switching element is connected, the storage capacitor being connected between the first node and the third node, 1 and the second node, and when the first switching device is turned off, the ON state of the driving switching device is maintained for at least one frame period by using the stored voltage.

And each of the sub-pixels further includes a second stabilization capacitor formed between a first power source signal input terminal of the driving switching element and a second node connected to a gate electrode of the driving switching element.

Wherein the initialization voltage is smaller than the compensation voltage, the compensation voltage is smaller than the second power supply signal, the second power supply signal is smaller than the first power supply signal, and the maximum current (peak current) The display current of the lowest gradation is held at a certain amount of current of 40 kV or less.

A first period during which the initialization signal and the emission control signal are output as a gate-on voltage, a second period during which the initialization signal, the emission control signal and the gate-on signal are both output as a gate- A third period in which a gate-on signal is output as the gate-on voltage, and a fourth period in which the emission control signal is output as the gate-on voltage.

The first to fifth switching elements and the driving switching element are PNOS or NMOS switching elements.

According to another aspect of the present invention, there is provided a method of driving an organic light emitting diode (OLED) display device including driving a plurality of sub-pixels to display an image, Charging the storage capacitor by supplying a data voltage from the data line to the first node in accordance with a gate-on signal from the gate line using the first switching element, controlling the light emission control from the light emission control line using the second switching element Forming a current path between the first node and the second node according to a signal, forming a current path between the supply line and the third node of the first power supply signal according to the voltage level of the second node using the drive switching element Thereby controlling the amount of current flowing in the light emitting cells, Supplying a reset voltage from the compensating power supply line to the second node in accordance with the initialization signal using the fourth switching element, A storage capacitor configured between a first node and a second node, and a storage capacitor configured between the first node and a third node, and storing the difference voltage between the first node and the second node, And maintaining the on state of the drive switching element for at least one frame period by using a stored voltage when the off state is off.

Wherein the initialization voltage is smaller than the compensation voltage, the compensation voltage is smaller than the second power supply signal, the second power supply signal is smaller than the first power supply signal, and the maximum current (peak current) The display current of the lowest gradation is held at a certain amount of current of 40 kV or less.

The driving of each of the sub-pixels includes a first period during which the initialization signal and the emission control signal are output as a gate-on voltage, a second period during which the initialization signal, the emission control signal, and the gate- A third period during which the gate-on signal is output as the gate-on voltage, and a fourth period during which the emission control signal is output as the gate-on voltage.

The organic light emitting diode display device and the driving method thereof according to embodiments of the present invention having various technical features as described above amplify and compensate the threshold voltage of the driving transistors provided in the pixel circuits of the display panel, By minimizing the loss, the current driving capability can be improved.

Accordingly, the pixel circuits of the display panel according to the present invention can display a brighter image by increasing the current driving capability, improve the initial image quality and prevent the afterimage, and further improve the display quality of the image. In addition, the lifetime and reliability of the display panel can be further improved by stable driving of the driving transistors.

1 is a block diagram illustrating an organic light emitting diode display device according to an embodiment of the present invention.
2 is an equivalent circuit diagram showing one sub-pixel of the display panel shown in Fig.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting diode (OLED) display device.
FIG. 4 is a graph showing the threshold voltage compensation value for each gradation according to the threshold voltage change of the drive switching element shown in FIG. 2;
5 is a graph showing the change in the amount of current according to the data voltage level of each pixel area.

Hereinafter, an organic light emitting diode display device and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an organic light emitting diode display according to an embodiment of the present invention. 2 is an equivalent circuit diagram showing one sub-pixel of the display panel shown in Fig.

The organic light emitting diode display device shown in FIG. 1 includes a display panel 1 formed with a plurality of pixel regions; A gate driver 2 for driving the gate lines GL1 to GLn and the emission control lines EL1 to ELn of the display panel 1; A data driver 3 for driving the data lines DL1 to DLm of the display panel 1; The first and second power supply signals VDD and VSS are supplied to the power supply lines PL1 to PLm of the display panel 1 and the compensation voltage Vref is supplied to the compensation power supply line CPL, (Not shown), a power supply unit 4 for supplying an initialization signal; And a timing controller 5 for controlling the gates and the data drivers 2 and 3 so that the display panel 1 is displayed with the compensation voltage Vref compensated for by the data voltage.

The display panel 1 displays a plurality of subpixels P arranged in a matrix form in each pixel region so that each subpixel P independently emits the light emitting cells OLED and the light emitting cells OLED And a cell driving circuit which drives the cell driving circuit. More specifically, each sub-pixel P as shown in FIG. 2 has a gate line GL, a data line DL, a compensation power line CPL, a light emission control line EL and a power line PL1 And PLn), and a light emitting cell (OLED) connected between the cell driving circuit and the second power supply signal (VSS) and equivalently represented by a diode.

The cell drive circuit is composed of a source follower type compensation circuit structure and includes first to fourth switching devices T1 to T4, a drive switching device DT, a storage capacitor Cst, a compensation capacitor Cem And at least one stabilization capacitor Cgss, Cgds. At least one stabilization capacitor Cgss and Cgds may be formed between the gate electrode and the source electrode of the driving switching device DT and between the drain electrode and the gate electrode of the driving switching device DT. Here, the first to fourth switching elements T1 to T4 and the driving switching element DT may be constituted of an NMOS transistor or a PMOS transistor. Hereinafter, the first to fourth switching elements T1 to T4 and the driving An example in which the switching element DT is an NMOS transistor will be described.

The light emitting cell OLED is composed of an anode electrode connected to the cell driving circuit, a cathode electrode connected to the second power supply signal VSS having a low potential voltage, and an organic layer formed between the anode electrode and the cathode electrode. This light emitting cell OLED emits light by the current from the driving switching element DT through the second switching element T2 of the cell driving circuit. The structure of the subpixel P of the present invention having such a structure will be described in detail with reference to the accompanying drawings.

The gate driver 2 receives the gate control signal GVS from the timing controller 5 in response to a Gate Start Pulse (GSP) and a Gate Shift Clock (GSC) (For example, the gate voltage of high logic, Scan) sequentially and controls the pulse width of the gate-on signal Scan in accordance with a gate output enable (GOE) signal. Then, the gate-on signals Scan are sequentially supplied to the gate lines GL1 to GLn. Here, a gate-off voltage (for example, a gate voltage of low logic) is supplied during a period in which no gate-on voltage is supplied to the gate lines GL1 to GLn. The gate driver 2 generates the initialization signal INT and the emission control signals EM using the gate control signals GVS from the timing controller 5, (EL), respectively. The initialization signal INT and the emission control signals EM are also supplied to the gate-off voltage level during periods when they are not supplied at the gate-on voltage level.

In addition, the gate driver 2 sequentially generates the emission control voltages EM at the gate-on or off-voltage level and sequentially supplies the emission control voltages EM to the emission control lines EL1 to ELn. Here, the emission control voltage EM sequentially outputted is a period for minimizing the threshold voltage loss of the driving switching device DT, that is, a period during which a current flows in the light emitting cell OLED, that is, a period during which an image is displayed .

The data driver 3 is connected to the timing controller 5 using a source start pulse SSP and a source shift clock SSC among data control signals DVS from the timing controller 5. [ That is, the analog data voltage. At this time, the data driver 3 converts the digital image data Data into the analog data voltage using the subdivided gamma voltage set corresponding to the gray level values of the digital image data Data. In response to a source output enable (SOE) signal, a data voltage is supplied to each data line DL1 to DLm.

The power supply unit 4 supplies the first and second power supply signals VDD and VSS to the power supply lines PL1 to PLm of the display panel 1 and supplies the compensation voltage Vref to the compensation power supply line CPL The initialization voltage (INT) is supplied to the initialization lines along with the supply box. At this time, the initialization voltage INT is smaller than the compensation voltage Vref, the compensation voltage Vref is smaller than the second power supply signal VSS, and the second power supply signal VSS is the first power supply signal VDD . For example, the first power supply signal VDD may be a constant voltage of about 10 [V] or more, and the second power supply signal VSS may be a constant voltage of 0 [V]. The compensation voltage Vref may be a constant voltage having a magnitude of about -2 [V] to 0 [V], and the initialization voltage INT may have a magnitude of from -7 [V] to -6 [V] It can be a constant voltage. Since the first power supply signal VDD is determined in consideration of the threshold voltage Vth of the light emitting cell OLED, the first power supply signal VDD can be changed according to the threshold voltage of the light emitting cell OLED used in the circuit.

The timing controller 5 aligns RGB data (RGB) input from the outside in accordance with the size and resolution of the display panel 1 and supplies the aligned digital image data Data to the data driver 3. The timing control unit 5 uses the sync signals input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, Gate and data control signals GVS and DVS and supplies them to the gate driver 2 and the data driver 3, respectively.

Hereinafter, the circuit configuration of the sub-pixel P according to the embodiment of the present invention will be described in detail.

The sub-pixel P shown in FIG. 2 includes first to fourth switching elements T1 to T4, a driving switching element DT, a storage capacitor Cst, a compensation capacitor Cem, and at least one stabilization capacitor Cgss , And Cgds) and a light emitting cell (OLED).

First, the first switching element T1 of the cell driving circuit applies a data voltage Vdata provided from the data line DL to the first node N1 in response to the gate-on signal Scan from the gate line GL Thereby charging the storage capacitor Cst.

The second switching element T2 forms a current path between the first node N1 and the second node N2 in response to the emission control signal EM from the emission control line EL.

The third switching element T3 supplies the initialization voltage INT to the storage capacitor Cst and the third node N3 in response to the initialization signal INT supplied from the initialization line.

The fourth switching element T4 supplies the compensation voltage Vref from the compensation power supply line CPL to the second node N2 in response to the initialization signal INT supplied from the initialization line.

The driving switching element DT forms a current path between the supply line of the first power supply signal VDD and the third node N3 in accordance with the voltage level of the second node N2, .

The storage capacitor Cst is connected between the first node N1 and the third node N3 to store the difference voltage between the first and second nodes N1 and N2, - When OFF, the ON state of the driving switching device DT is maintained for a predetermined period of time, for example, for one frame period by using the stored voltage.

The compensation capacitor Cem is configured between the first node N1 and the second node N2 to charge / discharge the compensation voltage Vref.

The first stabilization capacitor Cgss is configured between the second node N2 and the third node N2 to which the gate electrode of the drive switching element DT is connected. A second stabilization capacitor Cgds may be further provided between the first power supply signal input terminal of the driving switching element DT and the second node N2 connected to the gate electrode of the driving switching element DT.

Thus, the light emitting cell OLED is connected between the third node N3 and the supply line of the second driving power supply VSS. That is, the anode electrode of the light emitting cell OLED is connected to the third node N3, and the cathode electrode thereof is connected to the second driving power supply VSS supply line. Here, it is preferable that the threshold voltage of the light emitting cell OLED is formed to be higher than the threshold voltage of the driving switching device DT.

When the maximum current (peak current) during driving of each of the subpixels P configured as described above is maintained at 20 mu A or more, the display current of the lowest gradation (e.g., a black image display current) . At this time, the threshold voltage compensation width of the drive switching device DT may be -0.5V to 3.5V.

3 is a waveform diagram for explaining a driving method of the organic light emitting diode display according to the present invention.

3, the gate-on signal Scan, the initialization signal INT, and the emission control signal EM supplied to each sub-pixel P are the gate-on voltage VGH or the gate-off voltage VGL ) ≪ / RTI > level. These signals are driven in the first to fourth periods A, B, C, and D, which will be described in detail as follows.

The initialization signal INT is output as the gate-on voltage VGH in the first period A and is output as the gate-off voltage VGL in the second to fourth periods B, C,

The gate-on signal Scan is output as the gate-on voltage VGH in the third period C and is supplied to the gate-off voltage VGL in the first and second periods A and B and the fourth period D .

The emission control signal EM is output as the gate-on voltage VGH in the first and fourth periods A and D and the gate-off voltage VGL in the second and third periods B and C .

Referring to FIGS. 2 and 3, the operation of the subpixel P will be described in detail for each period.

In the first period A,

In the first period A, the initialization signal INT and the emission control signal EM are output as the gate-on voltage VGH and the gate-on signal Scan is output as the gate-off voltage VGL. Thus, during the first period A, the second to fourth switching elements T2 to T4 are turned on, and the first switching element T1 is turned off.

The compensating voltage Vref is supplied to the second node N2 through the fourth switching element T4 turned on so that the second node N2 is turned on again through the second switching element T2, N1. Thus, the first and second nodes N1 and N2 are initialized to the compensation voltage Vref.

On the other hand, the initializing voltage INT is supplied to the third node N3 through the third switching element T3 turned on. At this time, the level of the initialization voltage INT applied to the third node N3 is determined by the ratio of the internal resistance of the drive switching device DT and the internal resistance of the third switching device T3. That is, since the voltage of the third node N3 varies according to the threshold voltage Vth of the driving switching element DT, the voltage of the third node N3 during the first period A becomes equal to the threshold voltage Vth, And saturates in a direction that will help compensate. Further, since the initialization voltage INT is smaller than the second power supply signal VSS and smaller than the threshold voltage of the light emitting cell OLED, the light emitting cell OLED is biased in the opposite direction to maintain the off state.

In the first period A, the second node N2 to which the gate electrode of the drive switching element DT is connected is maintained at the level of the compensation voltage Vref, and the third node N3 to which the source electrode is connected, Is maintained at the level of the initializing voltage INT. As the drain electrode is maintained at the level of the first power supply signal VDD, the drive switching element DT is initialized. At this time, the voltage difference between the gate electrode and the source electrode of the drive switching device DT exceeds the threshold voltage (Vth), and the initialization current flows through the turn-on drive switching device DT. However, as described above, since the light emitting cells OLED form a reverse bias, the initializing current can not flow into the light emitting cells OLED and is synchronized with the initializing line supplying the initializing voltage INT.

Thus, in the first period A, the initialization current flows from the first power supply signal (VDD) supply line to the initialization line through the drive switching element DT. Thus, the drive switching element DT is initialized regardless of the polarity of the threshold voltage Vth. That is, even if the threshold voltage Vth of the N-type drive switching device DT is smaller than 0 or the threshold voltage Vth of the drive switching device DT configured as P type is larger than 0, Since the drive switching element DT is initialized, the threshold voltage (Vth) detection performance of the drive switching element DT is improved after the first period (A).

In summary, in the first period (A), the light emitting cell OLED is kept turned off, and the first and second nodes N1 and N2 are initialized to the compensation voltage Vref. Then, the drive switching element DT is initialized regardless of the polarity thereof. Particularly, by discharging the third node N3 to the initializing voltage INT having a low value during the first period A, the voltage of the third node N3 rises even during the turn-on of the driving switch DT Therefore, the threshold voltage (Vth) detection compensation range of the drive switching device DT is widened.

The second period (B)

In the second period B, the initialization signal INT, the gate-on signal Scan, and the emission control signal EM are both output as the gate-off voltage VGL. Accordingly, during the second period B, all of the first to fourth switching elements T1 to T4 except for the driving switching element DT are turned off.

Then, the voltage of the third node N3 changes in accordance with the difference between the second node N2 and the third node N3, and the source follower method The threshold voltage Vth of the driving switching element DT is detected.

At this time, the voltage of the second node N2 is higher than the capacitance of the compensation capacitor Cem, the capacitance ratio of the gate-source overlap cap of the drive switching device DT, and the capacitance of the first stabilization capacitor Cgss ) Capacitance and is determined according to the threshold voltage Vth of the drive switching element DT. That is, if the threshold voltages Vth of the respective driving switching elements DT provided in the two different sub-pixels P are different from each other, the voltage change amount of the second node N2 provided in the two sub- Is also different.

On the other hand, the voltage of the third node N3 rises from the initializing voltage INT to [(Vref-Vth) +?]. That is, it can be seen that the threshold voltage Vth of the driving switching device DT is amplified and stored in the third node N3 during the second period B. Here, '?' Is an amplification compensation value and has a larger value as the threshold voltage Vth of the drive switching device DT is larger.

The current flowing in the drive switching device DT during the second period B stops when the charge accumulates in the storage capacitor Cst by the threshold voltage Vth of the drive switching device DT and the threshold voltage Vth is detected And is terminated. The reason why the threshold voltage Vth of the drive switching device DT is amplified and stored in the second period B is as follows. In the fourth period B after the second period B, the compensated data voltage of the threshold voltage Vth of the driving switching element DT is transferred from the first node N1 to the second node N2. At this time, the compensated data voltage may be lost due to a parasitic cap between the first and second nodes N1 and N2 in the course of transmission. In order to compensate this loss, the threshold voltage Vth of the driving switching device DT is amplified and stored in the second period B.

During the third period (C)

In the third period C, the gate-on signal Scan is output as the gate-on voltage VGH, and the initialization signal INT and the emission control signal EM are output as the gate-off voltage VGH. Accordingly, during the third period (C), the first switching device (T1) is turned on and the second to fourth switching devices (T2 to T4) are turned off. Then, the data voltage Vdata is supplied to the first node N1 through the first switching element T1 turned on, and is stored in the storage capacitor Cst.

During the fourth period (D)

In the fourth period D, the emission control signal EM is output as the gate-on voltage VGH, and the initialization signal INT and the gate-on signal Scan are output as the gate-off voltage VGL. Accordingly, during the fourth period D, the second switching element T2 is turned on and the first, third, and fourth switching elements T1, T3, and T4 are turned off.

Then, the data voltage (Vdata) of the first node (N1) is supplied to the second node (N2) through the second switching element (T2) turned on. Accordingly, the drive switching device DT is turned on by the voltage difference between the Vgs (voltage difference between the gate electrode and the source electrode) of the drive switching device DT, that is, the voltage between the second node N2 and the third node N3, Is turned on. The driving switching element DT is turned on according to the data voltage Vdata applied to the second node N2 to supply the driving current to the light emitting cell OLED so that the light emitting cell OLED emits light . When the data voltage Vdata is supplied to the second node N2 and then the second switching element T2 is turned off, the voltage of the second node N2 by the storage capacitor Cst and the compensation capacitor Cem And the light emission of the light emitting cell OLED is continued.

On the other hand, since the voltage of the second node N2 rises rapidly in the fourth period D, the parasitic capacitance between the second node N2 and the third node N3 and the parasitic capacitance The voltage of the third node N3 can be raised. In this case, a compensation loss of the threshold voltage Vth of the driving switching device DT may be generated. That is, when the voltage of the third node N3 rises due to the coupling phenomenon, the threshold voltage Vth of the driving switching device DT also increases, so that the amount of current flowing in the driving switching device DT can be reduced. In order to prevent this, the first stabilization capacitor (Cgss) and the second stabilization capacitor (Cgds) are separately formed in the present invention. The third node N3 is connected to the first stabilization capacitor Cgss and the second stabilization capacitor Cgds which can be separately formed even if the voltage of the second node N2 changes abruptly in the fourth period D Can be stabilized.

FIG. 4 is a graph showing the threshold voltage compensation value for each gradation according to the threshold voltage change of the driving switching element shown in FIG. 5 is a graph showing the change in the amount of current according to the data voltage level of each pixel circuit.

Referring to FIGS. 4 and 5, the threshold voltage Vth compensation rate can be confirmed as a simulation result for each gradation according to a threshold voltage change (Vth shift) of the driving switching element DT. The threshold voltage Vth of 5.0 V is compensated from -1 V to 4.0 V when the threshold voltage Vth of the switching device DT moves together with the rate of change of the current amount of the light emitting cell OLED from 95% to 105% (± 5% And a high threshold voltage (Vth) compensation effect can be seen in FIG. In particular, a wide compensation width and a high compensation ratio can be confirmed over all gradations, and it is confirmed that the current amount flow is increased as compared with the other pixels, as shown in FIG.

As described above, the organic light emitting diode display device and the driving method thereof according to the present invention amplify and compensate the threshold voltage of the driving switching device DT provided in the pixel circuits of the display panel, The current driving capability can be improved. Therefore, the cell driving circuits of the display panel according to the present invention can display a brighter image by increasing the current driving capability, improve the initial image quality and prevent the afterimage, and further improve the display quality of the image. In addition, the lifetime and reliability of the display panel can be further improved by stable driving of the driving switching elements DT.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1: display panel 2: gate driver
3: Data driver 4: Power supply
5: timing control section P: sub-pixel
DT: Driving switching element Vref: Compensating voltage
T1 to T4: First to fourth switching elements

Claims (9)

A plurality of sub-pixels for displaying an image;
Each of the sub-pixels
A first switching element for charging the storage capacitor by supplying a data voltage from the data line to the first node in response to a gate-on signal from the gate line,
A second switching element which forms a current path between the first node and the second node in response to the light emission control signal from the light emission control line,
A driving switching element for controlling the amount of current flowing in the light emitting cells by forming a current path between the third node and the supply line of the first power supply signal in accordance with the voltage level of the second node,
A third switching element for supplying an initialization voltage to the third node in response to an initialization signal from the initialization line,
A fourth switching element for supplying a compensation voltage from the compensation power supply line to the second node in response to the initialization signal,
A compensation capacitor configured between the first node and the second node, and
And a first stabilization capacitor formed between the second node and the third node to which the gate electrode of the drive switching element is connected,
Wherein the storage capacitor is connected between the first node and the third node to store a difference voltage between the first and second nodes, and when the first switching device is turned off, On state is maintained for at least one frame period. The method according to claim 1,
In each of the sub-pixels,
And a second stabilization capacitor formed between a first power supply signal input terminal of the driving switching element and a second node connected to a gate electrode of the driving switching element. 3. The method of claim 2,
The initialization voltage is smaller than the compensation voltage,
Wherein the compensation voltage is smaller than a second power supply signal provided at one end of the light emitting cell,
Wherein the second power supply signal is less than the first power supply signal,
Wherein a peak current during driving of each of the sub-pixels is maintained at a current amount of at least 20 mu A while a lowest current display current is maintained at a current of at most 40 volts. . The method according to claim 1,
Each of the sub-
A first period during which the initialization signal and the emission control signal are output as a gate-
A second period during which the initialization signal, the emission control signal, and the gate-on signal are both output as a gate-
A third period during which the gate-on signal is output as the gate-on voltage, and
And a fourth period during which the emission control signal is output as the gate-on voltage. The method according to claim 1,
Wherein the first to fourth switching elements and the driving switching element are PMOS or NMOS switching elements. Driving a plurality of sub-pixels for displaying an image,
The driving step of each sub-pixel
Charging the storage capacitor by supplying a data voltage from the data line to the first node in accordance with a gate-on signal from the gate line using the first switching element,
Forming a current path between the first node and the second node in accordance with a light emission control signal from the light emission control line using a second switching element,
Controlling the amount of current flowing in the light emitting cells by forming a current path between the third node and the supply line of the first power supply signal according to the voltage level of the second node using the drive switching element,
Supplying an initialization voltage to the third node in accordance with an initialization signal from an initialization line using a third switching element,
Supplying a compensation voltage from the compensation power supply line to the second node in accordance with the initialization signal using a fourth switching element,
Storing a difference voltage between the first and second nodes using a compensation capacitor configured between the first node and the second node and the storage capacitor configured between the first node and the third node, The method comprising: maintaining the on state of the driving switching device for at least one frame period using a stored voltage when the driving current is turned off. The method according to claim 6,
The initialization voltage is smaller than the compensation voltage,
Wherein the compensation voltage is smaller than a second power supply signal provided at one end of the light emitting cell,
Wherein the second power supply signal is less than the first power supply signal,
Wherein a peak current during driving of each of the sub-pixels is maintained at a current amount of at least 20 mu A while a lowest current display current is maintained at a current of at most 40 volts. . The method according to claim 6,
The driving step of each sub-pixel
A first period during which the initialization signal and the emission control signal are output as a gate-
A second period during which the initialization signal, the emission control signal, and the gate-on signal are both output as a gate-
A third period during which the gate-on signal is output as the gate-on voltage, and
And a fourth period during which the emission control signal is output as the gate-on voltage. The method according to claim 6,
Wherein the first to fourth switching elements and the driving switching element are PMOS or NMOS switching elements.

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