KR20230092712A - Image-based semiconductor device patterning method using DNN(Deep Neural Network) - Google Patents

Abstract

The technical idea of the present invention is to provide a semiconductor device patterning method capable of accurately predicting and patterning pattern information after a specific semiconductor process. The semiconductor device patterning method includes the steps of imaging information on a pattern of a sample to generate an input image; obtaining an output image of a pattern of the sample after a predetermined semiconductor process on the sample; generating a predictive model through learning using a deep neural network (DNN) with the input image and the output image; and predicting a pattern image of a pattern of a semiconductor device after the semiconductor process using the prediction model.

Description

Image-based semiconductor device patterning method using DNN (Deep Neural Network)}

The technical idea of the present invention relates to a method for patterning a semiconductor device, and more particularly, to an image-based method for patterning a semiconductor device.

In a semiconductor process, a photolithography process using a mask may be performed to form a pattern on a semiconductor substrate such as a wafer. A mask can be said to be a pattern transfer body in which a pattern shape of an opaque material is formed on a transparent base layer material. In order to manufacture such a mask, first, after designing a layout for a required pattern, OPC layout data obtained through OPC (Optical Proximity Correction) is transferred as MTO (Mask Tape-Out) design data. Thereafter, mask data preparation (MDP) may be performed based on the MTO design data, and an exposure process or the like may be performed on the mask substrate. Meanwhile, a pattern may be formed on the semiconductor substrate by performing a process of forming a PR pattern on the semiconductor substrate using a mask and an etching process using the PR pattern.

An object to be solved by the technical spirit of the present invention is to provide a method for patterning a semiconductor device capable of accurately predicting and patterning pattern information after a specific semiconductor process.

In addition, the problem to be solved by the technical spirit of the present invention is not limited to the above-mentioned problems, and other problems can be clearly understood by those skilled in the art from the description below.

In order to solve the above problems, the technical idea of the present invention is to generate an input image by imaging information on the pattern of the sample; obtaining an output image of a pattern of the sample after a predetermined semiconductor process on the sample; generating a predictive model through learning using a deep neural network (DNN) with the input image and the output image; and predicting a pattern image of a pattern of a semiconductor device after the semiconductor process using the prediction model.

In addition, the technical idea of the present invention, in order to solve the above problems, generating an input image by rasterizing the layout of the mask pattern corresponding to the pattern of the sample; obtaining an OPC layout image for the mask pattern as an output image; generating a predictive model through learning using a DNN with the input image and the output image; predicting an OPC layout image of a pattern of a semiconductor device using the prediction model; determining whether the predicted image of the OPC layout satisfies a set condition; manufacturing a mask based on the image of the OPC layout when the condition is satisfied; and forming a pattern on the semiconductor device using the mask.

Furthermore, the technical spirit of the present invention, in order to solve the above problems, obtaining an ADI image for the pattern of the sample; extracting a contour image from the ADI image; generating an input image by rasterizing the contour image; Acquiring an ACI image of a pattern of the sample after an etching process on the sample as an output image; generating a predictive model through learning using a DNN with the input image and the output image; predicting a pattern image of a semiconductor device after the etching process using the prediction model; Determining whether the predicted pattern image after the etching process satisfies a set condition; and forming a pattern on the semiconductor device through the etching process when the above condition is satisfied.

An image-based semiconductor device patterning method using a DNN according to the technical idea of the present invention may generate an input image through imaging and generate an image-based predictive model through learning using the DNN. The image-based prediction model can accurately predict an image of a pattern after a corresponding semiconductor process. In addition, based on the accurate prediction of the pattern image, it is possible to accurately form a pattern required for the semiconductor device.

In addition, in the image-based semiconductor device patterning method using DNN according to the technical idea of the present invention, the DNN effectively reflects the influence of distant patterns and outputs a high-precision image that guarantees sub-pixel level accuracy. It can be created as an image, includes a model that is lightweight enough to perform full-chip simulation, and can be modeled by changing the architecture according to the pattern complexity of each layer of the semiconductor device.

1 is a flowchart schematically illustrating a process of a method of patterning an image-based semiconductor device using a DNN according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram illustrating a portion to which the semiconductor device patterning method of FIG. 1 is applied in eight major semiconductor processes.
3A to 3C are conceptual diagrams for explaining the difference between a CD-based model, a content-based model, and an image-based model.
4A and 4B are flowcharts schematically illustrating a process of a method of patterning an image-based semiconductor device using a DNN according to embodiments of the present invention.
5A and 5B are conceptual diagrams illustrating a method of generating an image to secure sub-pixel level accuracy in the step of generating an input image of the method of patterning a semiconductor device of FIG. 1 .
6A to 7B are conceptual diagrams illustrating methods of removing a defective image in the step of generating an input image of the method of patterning a semiconductor device of FIG. 1 .
FIG. 8 is a conceptual diagram illustrating a process of generating a prediction model through learning using a DNN in the method of patterning the semiconductor device of FIG. 1 .
FIG. 9 is graphs of various activation functions used in the DNN in the method of patterning the semiconductor device of FIG. 1 .
FIG. 10 is a graph showing a comparison between the effects of the semiconductor device patterning method of FIG. 1 and the conventional semiconductor device patterning method.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

1 is a flowchart schematically illustrating a process of a method of patterning an image-based semiconductor device using a DNN according to an embodiment of the present invention, and FIG. 2 shows a part to which the semiconductor device patterning method of FIG. 1 is applied in eight major semiconductor processes. It is a concept diagram to explain. Also, FIGS. 3A to 3C are conceptual diagrams for explaining the difference between a CD-based model, a content-based model, and an image-based model.

Referring to FIGS. 1 to 3C , the image-based semiconductor device patterning method using the DNN of the present embodiment (hereinafter, simply referred to as 'semiconductor device patterning method') first images information about a pattern of a sample and inputs it. An image is created (S110). Here, the sample may be a semiconductor device used for deep neural network (DNN) learning, for example, generative adversarial network (GAN) learning. However, in the semiconductor device patterning method of this embodiment, DNN learning is not limited to GAN learning. Hereinafter, DNNs that are not specifically mentioned may mainly mean GANs. In addition, the pattern of the sample may be formed by transferring the pattern on the mask onto the sample through an exposure process. Accordingly, first, a layout for a pattern on a mask corresponding to a pattern of a sample, that is, a mask layout may be designed. For reference, in general, the shape of the pattern of the sample may differ from the shape of the pattern on the mask due to the nature of the exposure process. In addition, since the pattern on the mask is reduced-projected and transferred onto the substrate, the pattern on the mask may have a larger size than the pattern of the sample.

Information on the pattern of the sample may be a layout of patterns on a mask corresponding to the pattern of the sample. A more detailed description thereof will be given in the description of FIG. 4A. Also, in another embodiment, the information on the pattern of the sample may be an After Develop Inspection (ADI) image of the pattern of the sample. A more detailed description thereof will be given in the description of FIG. 4A. In the semiconductor device patterning method of this embodiment, the information on the pattern of the sample is not limited to the above two, and may be determined in various ways. For example, the information on the pattern of the sample may be a near-field image of the pattern on the mask.

Meanwhile, imaging of information may mean rasterization of the corresponding information. That is, rasterization may mean a process of converting vector or contour data into bitmap or pixel data. For example, a layout for a pattern on a mask corresponds to a contour image, and such a contour image may be converted into a bitmap image through rasterization to generate an input image. In addition, the ADI image of the pattern of the sample is acquired through a scanning electron microscope (SEM). After extracting the convolutional image from the ADI image, rasterization is performed on the convolutional image to generate an input image of a bitmap image. .

In the semiconductor device patterning method of this embodiment, since the input data to the DNN is image data through rasterization, that is, pixel data, it is possible to learn by using tens of thousands of times more data than existing CD-based or content-based data. and thus relatively avoiding model overfitting.

For reference, as patterns have recently been miniaturized, a new technology is needed because it is not enough to manufacture an accurate mask only with the existing OPC and RET (Resolution Enhancement Technology) technology. In the case of miniaturized patterns, the proportion of 2D patterns gradually increases, so a model that accurately predicts even 2D patterns is needed for accurate patterning, and 2D patterns are differentiated from 1D pattern (line & space pattern) defects during wafer verification. Defects must be detected. In the case of an existing lithography simulation model, for example, an OPC model, a CD-based model that predicts a CD of a pattern based on information of a given layout is generally used, as shown in FIG. 3A.

However, recently, as shown in FIG. 3B, a convolution-based model capable of better predicting the 2D profile of a pattern has been used. The CD-based model is a method of modeling by extracting 1 or 2 CDs from one pattern, and the contour-based model extracts pattern information by adding EP (Edge Placement) or EPE (Edge Placement Error) at regular intervals of the contour. This is a method of modeling using dozens of EP information per pattern. This contuo-based model method can extract more 2D information, but depending on the EP extraction method, some information may be omitted.

In contrast, in the semiconductor device patterning method of the present embodiment, an image-based prediction model may be generated through learning using a DNN. As shown in FIG. 3C , since the image-based model uses all pixels (tens of thousands) corresponding to a pattern for modeling, modeling can be performed using much more 2D information than the contour-based model.

In addition, it may be difficult to efficiently and sufficiently utilize a large amount of pixel data in a model generated by linearly combining predefined kernels as in the existing lithography model. However, the semiconductor device patterning method of the present embodiment can find an optimized kernel during learning in order to perform more accurate modeling by utilizing data that is hundreds of thousands of times larger, and DCGAN (Deep Convolutional GAN) specialized for simulating lithography is used. can be utilized In addition, the semiconductor device patterning method of the present embodiment can minimize the time required for data pre-processing by using an algorithm that automates the data pre-processing process. Meanwhile, in the semiconductor device patterning method of the present embodiment, various algorithms may be used when converting an image in order to secure sub-pixel level accuracy of an image-based model generated through learning using a DNN. . This will be described in more detail in the description of FIGS. 5A to 7B .

After generating an input image through imaging, an output image of a pattern of the sample after a predetermined semiconductor process on the sample is obtained (S120). Here, the semiconductor process may include various processes. For example, in the semiconductor device patterning method of the present embodiment, the semiconductor process may include a photo process and an etching process. As can be seen from FIG. 2 , a photo process may generally refer to a process of forming a PR pattern on a semiconductor device through an exposure process and a development process using a mask. Also, the etching process may refer to a process of forming a pattern on a semiconductor device using a PR pattern.

Meanwhile, optical proximity correction (OPC) may be performed in a photo process. OPC may refer to a method of correcting the layout of a mask pattern in order to suppress the occurrence of Optical Proximity Effect (OPE) due to the influence between neighboring patterns in the exposure process as the pattern is miniaturized. there is. OPC may generally include a process of obtaining an image or data of a layout of a mask pattern, that is, an OPC layout, through optical image generation of the mask pattern, OPC model generation, and simulation using the OPC model. Accordingly, the photo process includes a process of generating an OPCed layout through OPC, manufacturing a mask with the OPC layout, and forming a PR pattern on the semiconductor device through an exposure process using the mask. can do. Meanwhile, in order to compensate for an etch bias, a Process Proximity Correction (PPC) process may be performed in an etch process.

As a result, an input image and an output image corresponding to the input image may vary depending on the semiconductor process. For example, if the input image is an image related to the layout of a pattern on a mask and the semiconductor process is an OPC process of a photo process, the output image may be an image of an OPC layout. In addition, if the input image is an image related to the ADI image of the sample pattern and the corresponding semiconductor process is an etching process using a PR pattern, the output image may be an ACI (After Cleaning Inspection) image of the sample pattern. Meanwhile, if the input image is an image related to a near-field image of a pattern on a mask and the corresponding semiconductor process is an exposure process using a mask, the output image may be an ADI image of the pattern of the sample.

After acquiring the output image, a predictive model is generated through learning using DNN with the input image and the output image (S130). Here, the DNN may be a paired GAN (paired GAN) or a conditioned GAN (conditioned GAN) using a paired image of an input image and an output image. In general, GAN has a problem that learning is not stable, but it is possible to learn stably by using paired image information as a condition of GAN. In addition, by using paired images, additional data preprocessing such as data labeling may not be required. The process of generating a predictive model through learning using GAN and the GAN will be described in more detail in the description of FIG. 8 .

After generating the predictive model, a pattern image after a semiconductor process for a pattern of a semiconductor device is predicted using the predictive model (S140). For example, when a semiconductor process is an OPC process, an OPC layout image of a pattern of a semiconductor device may be predicted. In addition, when the semiconductor process is an etching process, an ACI image of a pattern of a semiconductor device may be predicted. Meanwhile, when the semiconductor process is an exposure process, an ADI image of a pattern of a semiconductor device may be predicted.

Thereafter, it is determined whether the predicted pattern image satisfies the set condition, and if it is satisfied, a pattern is formed on the semiconductor device, and if not satisfied, it returns to the step of generating a predictive model through learning using DNN (S130). A predictive model can be created. This will be described in more detail in the description of FIGS. 4A and 4B in relation to a specific semiconductor process.

The semiconductor device patterning method of the present embodiment may generate an input image through imaging and generate an image-based prediction model through learning using DNN. The image-based prediction model can accurately predict an image of a pattern after a corresponding semiconductor process. In addition, based on the accurate prediction of the pattern image, it is possible to accurately form a pattern required for the semiconductor device.

4A and 4B are flowcharts schematically illustrating a process of a method of patterning an image-based semiconductor device using a DNN according to embodiments of the present invention. The contents already described in the description of FIGS. 1 to 3C are briefly described or omitted.

Referring to FIG. 4A , in the semiconductor device patterning method of the present embodiment, first, an input image is generated by rasterizing a layout of a mask pattern corresponding to a pattern of a sample (S110a). Here, the layout of the mask pattern may correspond to the contour image. Accordingly, the input image may be generated by converting the contour image of the layout into a bitmap image through rasterization.

After generating an input image through rasterization, an OPC-operated layout image for a mask pattern is acquired as an output image (S120a). The OPC layout image may correspond to an image of a layout in which the layout of the mask pattern is changed through OPC. As described above, a process of generating an OPC layout through OPC may correspond to a part of a photo process.

After obtaining the output image, a predictive model is generated through learning using DNN with the input image and the output image (S130). The step of generating the predictive model ( S130 ) is the same as described in the description of the semiconductor device patterning method of FIG. 1 .

After generating the predictive model, an OPC layout image corresponding to the pattern of the semiconductor device is predicted using the predictive model (S140a). More specifically, an initial layout of a mask pattern corresponding to a desired pattern of a semiconductor device may be input to a predictive model to generate an OPC layout image. The generated OPC layout image may correspond to a layout image of a mask pattern. Accordingly, an OPC-operated layout image corresponding to a pattern of a required semiconductor device may be predicted.

In addition, in the semiconductor device patterning method of the present embodiment, a predictive model is generated between the layout of the mask pattern and the OPC layout image, but depending on the embodiment, a predictive model may be generated between the pattern of the sample and the OPC layout image. . In the case of such a predictive model, an input image may be generated through a process of obtaining an SEM image of a pattern of a sample, extracting a contour image from the SEM image, and rasterizing the contour image.

Subsequently, it is determined whether the OPC layout image satisfies a set condition (S150). In other words, it is determined whether the OPC layout image generated through the predictive model satisfies a set condition. For example, whether or not the condition is satisfied may be determined by comparing an error amount (errRMS) represented by RMS with a set value or comparing a loss rate with a set value. Here, the error amount or loss rate may be calculated based on the contour image of the target pattern. Meanwhile, depending on the embodiment, both the error amount and the loss rate may be used as conditions.

If the condition is satisfied, a mask may be manufactured based on the OPC layout image (S160). Briefly explaining the mask manufacturing process, first, the OPC layout image is transmitted to the mask manufacturing team as MTO (Mask Task Out) design data. In general, MTO may refer to handing over the final mask data acquired through the OPC method to a mask manufacturing team and requesting mask manufacturing. Such MTO design data may have a graphic data format used in electronic design automation (EDA) software or the like. For example, MTO design data may have data formats such as Graphic Data System II (GDS2) and Open Artwork System Interchange Standard (OASIS).

Then, mask data preparation (MDP) is performed based on the MTO design data. Mask data preparation includes, for example, i) format conversion called fracturing, barcodes for machine reading, standard mask patterns for inspection, job decks, etc. ii) augmentation, and automatic and manual methods. iii) Verification of Here, the job-deck may mean creating a text file related to a series of commands such as arrangement information of multiple mask files, a standard dose, and an exposure speed or method.

After preparing the mask data, the mask substrate is exposed using the mask data, that is, the E-beam data (S295). Here, exposure may mean, for example, E-beam writing. Here, E-beam writing may be performed in a gray writing method using, for example, a multi-beam mask writer (MBMW). Also, E-beam writing may be performed using a variable shape beam (VSB) exposure machine.

After the exposure process, a series of processes may be performed to complete the mask. A series of processes may include, for example, developing, etching, and cleaning processes. In addition, a series of processes for mask manufacturing may include a measurement process, a defect inspection or defect repair process. In addition, a pellicle application process may be included. Here, the pellicle application process refers to the process of attaching a pellicle to the mask surface to protect the mask from subsequent contamination during the delivery and service life of the mask when it is confirmed that there are no contaminant particles or chemical stains through final cleaning and inspection. can do.

If the condition is not satisfied, a new predictive model is generated by returning to the step of generating a predictive model (S130). Depending on the embodiment, returning to the step of generating the input images (S110a), the input images are newly generated, and a predictive model through DNN learning may be regenerated using the new input images.

After manufacturing the mask, a pattern is formed on the semiconductor device using the mask (S170). In other words, a PR pattern may be formed on the semiconductor device through an exposure process using a mask, and then a pattern may be formed on the semiconductor device through an etching process using the PR pattern.

Referring to FIG. 4B , in the method for patterning a semiconductor device according to the present embodiment, first, an ADI image of a pattern of a sample is acquired (S101). For example, the ADI image may be an SEM image obtained by taking a PR pattern on a sample with an SEM.

Continuing, a contun image is extracted from the ADI image (S105), and an input image is generated by rasterizing the contun image (S110b). A process of generating an input image through rasterization may be substantially the same as a process of generating an input image by rasterizing a layout.

Thereafter, an ACI image of the pattern of the sample after the etching process for the sample is obtained as an output image (S120b). The ACI image may be an SEM image obtained by taking a pattern of a semiconductor device after an etching process using a PR pattern by SEM.

After obtaining the output image, a predictive model is generated through learning using DNN with the input image and the output image (S130). The step of generating the predictive model ( S130 ) is the same as described in the description of the semiconductor device patterning method of FIG. 1 .

After generating the predictive model, a pattern image after the etching process for the pattern of the semiconductor device is predicted using the predictive model (S140a). Here, the pattern image may be an ACI image of a pattern of a semiconductor device after an etching process. More specifically, with respect to a desired pattern of a semiconductor device, an ADI image of a semiconductor device corresponding to the pattern may first be obtained, and an ACI image of the semiconductor device may be generated by inputting the ADI image to a prediction model. Accordingly, an ACI image of a desired pattern of a semiconductor device may be predicted.

Subsequently, it is determined whether the pattern image after the etching process, that is, the ACI image satisfies the set condition (S150). In other words, it is determined whether the ACI image generated through the predictive model satisfies a set condition. For example, whether or not the condition is satisfied may be determined by comparing an error amount represented by RMS with a set value or comparing a loss rate with a set value. Here, the error amount or loss rate may be calculated based on the contour image of the target pattern. Meanwhile, depending on the embodiment, both the error amount and the loss rate may be used as conditions.

If the condition is satisfied, an etching process is performed to form a pattern on the semiconductor device (S170a). If the condition is not satisfied, a new predictive model is generated by returning to the step of generating a predictive model (S130). Depending on the embodiment, returning to the step of acquiring ADI images (S101), input images are newly generated from the beginning, and a predictive model through DNN learning may be regenerated using the new input images.

5A and 5B are conceptual diagrams illustrating a method of generating an image to secure sub-pixel level accuracy in the step of generating an input image of the method of patterning a semiconductor device of FIG. 1 . The contents already described in the description of FIGS. 1 to 4B are briefly described or omitted.

Referring to FIGS. 5A and 5B , in the step of generating an input image of the semiconductor device patterning method of FIG. 1 (S110), when the layout is rasterized and converted into an input image, one pixel usually has a size of several nm. However, the accuracy to be predicted should be less than 1 nm. Accordingly, when converting into an input image, information must be preserved at a level smaller than a pixel, that is, at a sub-pixel level. As shown in FIG. 5A, it may be difficult to secure an accurate CD value depending on the filter used when converting an input image. For reference, in FIG. 5A, the leftmost image is the original image, and the second image from the left is the downsampled image. Staircase effects (aliasing) may appear in the original image or in the downsampled image. In order to remove this, anti-aliasing can be performed as in the middle image, or the image can be resized using a Lanczos filter or bi-cubic filter as in the two images on the right.

In the semiconductor device patterning method of the present embodiment, a layout may be converted into an input image using a windowed bi-cubic filter smaller than the size of a minimum pattern during rasterization to maintain accuracy at the sub-pixel level. there is. In addition, in the input image, Shannon-sampling algorithm and bi-linear or bi-cubic algorithm are used to interpolate sub-pixel values, and Newton-Raphson The algorithm can extract the CD value at the threshold. Through this method, since the entire image is not up-sampled, the CD extraction time from the input image can be reduced, and accuracy at the sub-pixel level can be secured.

For example, in FIG. 5B, after converting a 0.1 nm level database unit (DBU) layout into a 1.75 nm pixel image using a windowed bi-cubic filter, the CD value extracted from the input image and the CD measured from the layout When calculating the difference with the value by errRMS, it can be confirmed that it has a very small value of about 0.034 nm. In FIG. 5B , 'bi-cubic: 3' may mean that 3*3 neighboring pixels are used, and 'bi-cubic: 9' may mean that 9*9 neighboring pixels are used.

6A to 7B are conceptual diagrams illustrating methods of removing a defective image in the step of generating an input image of the method of patterning a semiconductor device of FIG. 1 . The contents already described in the description of FIGS. 1 to 5B are briefly described or omitted.

Referring to FIGS. 6A and 6B , in the method for patterning a semiconductor device according to the present embodiment, in order to generate a training image from a wafer measurement image such as an ADI image or wafer measurement data, N convolutional images are extracted from the wafer measurement image, and N convolutional images are extracted from the wafer measurement image. After rasterizing the contour image, the average value can be used. In this way, noise of the wafer metrology image can be minimized by using an average value after extracting and rasterizing a plurality of contour images.

Meanwhile, since wafer measurement images may include defective images, the method for patterning a semiconductor device according to the present embodiment may include a method of automatically capturing defective images and removing them from a training image. For example, when extracting a convolutional image from a total of N images, if an erroneously measured image is included, n*n clip images (n is an integer greater than or equal to 2) of the extracted convolutional images, e.g., 3*3 An average of pixel values of the clip image (∑ _k ∑ _l I _kl /9) may have a value of 255/j (j: 2 to N, 8-bit image). Here, I _kl means the intensity of (k,l) pixels, and 9 is a number reflecting a 3*3 clip image. If all contour images are normal (when j = 1), the average of pixel values may be 255. However, if there is a defect in even one of the N convolution images (j = 2 to N), the average of the pixel values may be less than 255. In FIG. 6A , the defective image portion is indicated as the first defect De1, and the average of pixel values in the first defect De1 portion may be less than 255.

In addition, even when the standard deviation of pixel values is smaller than the set value, it can be captured as a bad image and removed from the training image. In FIG. 6B , portions marked as second depths De2 may correspond to portions in which the standard deviation of pixel values is smaller than a set value.

Referring to FIGS. 7A and 7B , in the semiconductor device patterning method according to the present embodiment, a control band is generated from a control image, and when the value of the band is greater than a set value, it is determined that the control image is abnormal, and a control band is generated from a training image. can be removed Here, the control band may be a concept corresponding to a variation width of control lines in the control image. In FIG. 7A , it is shown that each of the three contuo images among the four contuo images includes a third depex (De3) portion whose contuo band is greater than the set value. In addition, in FIG. 7B, since the control band of the upper and lower control lines is smaller than the set value, it may be normal. On the other hand, the control band (CB) of middle control lines may be greater than the set value. Accordingly, the middle contiguous lines may correspond to the fourth depeck De4 part.

In addition, the method for patterning a semiconductor device according to the present embodiment includes a method of excluding a training image having a set threshold value or more by obtaining a difference and variance from a target image using an output image generated by a predictive model after initial learning using a DNN. can do. Meanwhile, when the target image is T and the generated image is S, the difference and variance may be obtained by normalizing the pattern density in consideration of the pattern density of the target image. For example, the difference value may be expressed as |∑ _i,j T _ij -S _ij |/∑ _i,j T _ij . Here, T _ij and S _ij may mean intensities of (i, j) pixels in the target image and the generated image, respectively. Meanwhile, the variance may be expressed as an RMS value, that is, a standard deviation.

The semiconductor device patterning method of the present embodiment may include a method of reflecting the influence of pattern density received from a farther distance (several hundred micrometers or more) than the image being used during learning using the DNN. That is, in the semiconductor device patterning method of the present embodiment, in order to reflect the pattern density from a long distance, a density map for a full-chip is additionally created as an input image, so that the DNN training image Can be added as a channel. On the other hand, when generating the density map, for example, by applying Gaussian convolution, the pattern density value of the density map reflects the effect coming from a region (several hundred um) larger than the pixel size (usually several um) can make it The density map may be generated using an RGB channel, and for example, the density may be reflected in a red channel. Accordingly, it can be seen that the larger the red region, the larger the pattern density value.

FIG. 8 is a conceptual diagram illustrating a process of generating a prediction model through learning using a DNN in the method of patterning the semiconductor device of FIG. 1 . The contents already described in the description of FIGS. 1 to 8 are briefly described or omitted.

Referring to FIG. 8 , in the semiconductor device patterning method of the present embodiment, an input image and an output image may be used as training images of a DNN, eg, a GAN. Briefly about GAN,

GAN is a deep learning-based generative algorithm and can include two sub-models. That is, GAN may include a generator model and a discriminator model. The generator model may correspond to a predictive model in the semiconductor device patterning method of the present embodiment. The generator model generates new examples, and the discriminator model determines whether the generated example is real data or fake data generated by the generator model.

For example, in relation to the semiconductor device patterning method of the present embodiment, the generator model may convert an input image to generate an output image after a predetermined semiconductor process. As described above, the input image may be generated by rasterizing the layout or rasterizing the layout after extracting the contour image from the ADI image. Meanwhile, the output image may be an OPC layout image or an ACI image. Meanwhile, the discriminator model may receive an output image and a reference image generated by the generator model. Here, the reference image may correspond to a target image to which an output image should reach. For example, if the output image is an OPC layout image, the reference image may be a final OPC layout image used for actual mask manufacturing. Also, when the output image is an ACI image, the reference image may be a target pattern image of the semiconductor device. The discriminator model compares the output image with the reference image to determine whether the output image is real or fake generated by the generator model. In other words, the discriminator model may determine that the output image is genuine if the output image and the reference image are substantially the same, and may determine the output image to be fake if there is a difference between the output image and the reference image.

Specifically, in FIG. 8 , when the input image IPI for the layout of the mask pattern is input to the generator model, the generator model generates the output image OPI. In addition, the output image OPI and the reference image RI are input to the discriminator model. The discriminator model determines whether the output image OPI is the same as the reference image RI. For example, if the output image is an OPC layout image, the reference image RI may be the required final OPC layout image, and the discriminator model determines whether the OPC layout image is really the final OPC layout image or the final OPC layout image. Determine whether it is a fake different from the layout image. After that, the generator model and the discriminator model are continuously updated according to the judgment result. When this process is repeated repeatedly until the discriminator model reaches a level where it can no longer discriminate between the output image (OPI) and the reference image (RI), learning ends, and the generator model at this time is adopted as the final prediction model. can On the other hand, the discriminator model can be discarded when learning is over.

In the semiconductor device patterning method of this embodiment, learning using a DNN may be image-based. In other words, input images generated through the aforementioned rasterization may be used as training images. In the semiconductor device patterning method of this embodiment, the DNN may include the following four features in order to accurately simulate the patterning process. Here, the patterning process may include, for example, a photo process and an etching process. However, the patterning process is not limited to the above processes.

1. It must reflect the influence of distantly located patterns.

2. The output image must generate a high-precision image that can guarantee sub-pixel level accuracy.

3. Include a model that is lightweight enough to perform full-chip simulation.

4. Since the pattern complexity is different for each layer of the semiconductor device, modeling should be possible by changing the architecture.

In the semiconductor device patterning method of the present embodiment, the DNN may be structured as follows to reflect the above characteristics. That is, the DNN may have a structure capable of pixel correlation to a long distance by including a plurality of down sample layers. For each pass through the down sample layer, the input image can be halved in the output layer. However, since the reduced image still contains pattern information corresponding to the same area as the input image, the information represented by one pixel may correspond to twice (or four times as much in terms of area) the input image. As a result, even if a kernel of the same size is used, a kernel acting on an image that has passed more down-sample layers can express pixel correlation for a wider area. For example, when the first input image and the image of the second down-sample layer are substantially the same image, and the image of the second down-sample layer is about 1/4 (1/16 in terms of area) of the input image, the second A kernel corresponding to the down sample layer may cover a very small area in the input image, but may cover most of the area in the image of the second down sample layer.

In the semiconductor device patterning method of the present embodiment, the DNN controls the intra-image correlation through the size of the kernel, the number of residual-layers, the number of down-sample layers, etc., so that the pattern proximity range (pattern proximity range) can be adjusted. In addition, the kernels applied to the image that has passed through the deepest down-sample layer can simulate the effect of a pattern several μm away. For example, denoting the regions in the input image IN as S1, S2, S3, and S4 in the form of concentric circles with radii increasing by a factor of 2, and also, correspondingly, the residual blocks of the four down-sample layers in the DNN. Considering the range of the kernels in RB1, RB2, RB3, and RB4, the kernel of the residual block RB4 of the 4th down-sample layer has a pattern over almost the entire input image IN, for example, S4. effect can be simulated.

In the semiconductor device patterning method of the present embodiment, since the proximity effect is not effectively considered for pixels outside the image, a mask-layer or a weight-layer is used, and DNN is used. Information of outer pixels may be excluded so as not to affect learning. However, since the pattern information in this area affects the learning of the inner area, it is used for forward-propagation in learning using DNN and not used for backward-propagation. can have a structure. Specifically, when an input image is output through a DNN as an image in a crop region, that is, an image of a back-propagation region, the crop region outside the back-propagation region is a masking-layer, Since it affects the inner back-propagation area, it can be used during forward-propagation. However, since the masking-layer is affected in the outer region, it may be excluded without considering it during backward-propagation. For reference, an inspection region may be acquired through measurement, and during learning, a cropped region may be cut and used instead of the entire inspection region.

Meanwhile, the masking-layer may be used to additionally consider dummy pattern information and apply different weights to the main pattern and the dummy pattern so as to be learned. In addition, the masking-layer may be used for weighted learning by adjusting pixel values corresponding to the backpropagation region and applying different weights for each training image.

FIG. 9 is graphs of various activation functions used in the DNN in the method of patterning the semiconductor device of FIG. 1 . The contents already described in the description of FIGS. 1 to 8 are briefly described or omitted.

Referring to FIG. 9 , in the semiconductor device patterning method of this embodiment, in order to generate an output image as a high-resolution image, the DNN upsamples the image using a nearest neighbor up sampling method or simply a nearest neighbor up sampling method. -Can be scaled. Nearest sampling method is a method of sampling using the nearest neighboring pixels. The near list sampling method may not generate a checker board artifact phenomenon. That is, in the case of a method using a de-convolution layer, a checker board structure may occur because the kernel overlap area is not the same in the output image. Meanwhile, the DNN may use a bi-linear or bi-cubic algorithm described above in the description of FIGS. 5A and 5B to generate a high-resolution image.

In addition, in the semiconductor device patterning method of the present embodiment, the DNN may use a swish function as an activation function to generate a negative contribution during backpropagation. 9 shows graphs for various activation functions. In general, the ReLU function is widely used in DNN, but as can be seen from the graph, negative contribution cannot occur in the case of the ReLU function. Meanwhile, in the DNN, the size of the input kernel can be adjusted so that the size of the convolution kernel of the input layer has a size similar to that of the filter used for rasterization.

In the semiconductor device patterning method of the present embodiment, to generate a lightweight model, the DNN uses a layer fusion structure, a structure in which a residual block is applied before the down sample layer, and a dual residual block structures can be used. The layer fusion structure is also referred to as a sum-fusion layer.

A structure in which the residual block is applied before the down sample layer is also referred to as a residual block first structure, and down sampling may be performed after passing through the residual block. In this way, when the residual block is applied before the down sample layer, the complexity of the residual block can be transferred to the down sample layer, and thus more complex phenomena can be simulated without increasing model parameters. For reference, since the model parameters are determined by the kernel function, the DNN structure may include substantially the same model parameters regardless of whether the residual block first structure is employed.

The structure of the residual block can be divided into a single residual block and a dual-residual block. A single residual block may include two 2D-convolution kernel functions and one activation function. In contrast, a dual-residual block may include two 2D-convolution kernel functions and two activation functions. As described above, since the model parameters are determined by the kernel function, the model parameters of the single residual block and the dual-residual block may be substantially the same. Therefore, in the case of a dual-residual block, more diverse data paths can be generated using substantially the same model parameters, and as a result, it is possible to contribute to improving model accuracy.

In the semiconductor device patterning method of the present embodiment, a sum-fusion layer and a concatenation layer may be used as layer functions for up-scaling of the DNN. In the case of the contiguous layer, since it has a structure that is twice as large in the channel direction, the concatenation kernel also becomes large and has many parameters. On the other hand, if a sum-fusion layer is created directly through an elementwise sum without concatenating the layers, a similar output result can be obtained while maintaining a small size of the kernel. there is. Therefore, the sum-fusion layer can contribute to model weight reduction.

In addition, in the semiconductor device patterning method of the present embodiment, the DNN may be designed to adjust and use a model layer and a loss function according to pattern complexity and a pattern proximity region. For example, in DNN, control the kernel size of the input/output layer, control the number of input/output channels of the input layer, control the kernel size of the up-scale/down-scale layer, control the number and kernel size of the residual layer, and control the number of down-sample layers , DNN loss/gradient loss control, and pixel loss weight control can be designed to be possible.

FIG. 10 is a graph showing a comparison between the effects of the semiconductor device patterning method of FIG. 1 and the conventional semiconductor device patterning method. The contents already described in the description of FIGS. 1 to 9 are briefly described or omitted.

Referring to FIG. 16 , the method for patterning a semiconductor device according to the present embodiment can secure model accuracy that exceeds the limit of accuracy of an existing model through learning using a DNN. In addition, in the semiconductor device patterning method of the present embodiment, image conversion and prediction model generation using GAN can be applied to both the PR model and the etching model through adjustment of an architecture control parameter. Furthermore, iterationless correction may be possible according to the modeling directionality. This can reduce the number of times of model application by 10 times or more compared to the existing method of performing correction through iterative model application, and thus can contribute to significantly reducing the total correction time.

As can be seen from FIG. 10 , as a result of comparing the accuracy of the existing model (POR) with respect to the etching process and the DNN of the semiconductor device patterning method of the present embodiment, for example, the model (DNN) generated through learning using GAN, the present The accuracy of the model (DNN) according to the embodiment is 0.64 nm (errRMS), and the accuracy of the existing model (POR) is 1.04 nm (errRMS). Therefore, it can be confirmed that the performance of the model (DNN) according to this embodiment is improved by about 40% compared to the existing model (POR).

So far, the present invention has been described with reference to the embodiments shown in the drawings, but this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. will be. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims (20)

generating an input image by imaging information about a pattern of a sample;
obtaining an output image of a pattern of the sample after a predetermined semiconductor process on the sample;
generating a predictive model through learning using a deep neural network (DNN) with the input image and the output image; and
and predicting a pattern image of a pattern of a semiconductor device after the semiconductor process using the prediction model. According to claim 1,
The information on the pattern of the sample is a layout of the pattern of the sample,
The output image is an OPC (Optical Proximity Correction) layout image,
In the generating of the input image, the semiconductor device patterning method characterized in that the layout is rasterized. According to claim 2,
In the rasterization, a windowed bi-cubic filter is used. According to claim 3,
In the input image, a value of a level smaller than a pixel is interpolated using a Shannon-sampling algorithm and a bi-linear or bi-cubic algorithm, and Newton- A semiconductor device patterning method characterized in that a CD value at a threshold value is extracted by a Newton-Raphson algorithm. According to claim 2,
The information on the pattern of the sample is an ADI (After Develop Inspection) image (measurement data or image) of the pattern of the sample,
The output image is an ACI (After Cleaning Inspection) image of the pattern of the sample,
Generating the input image,
extracting a contour image from the ADI image; and
A semiconductor device patterning method comprising the step of rasterizing the contour image. According to claim 5,
In the step of extracting the contour image,
Among the N concatenation images, the average of pixel values of n*n clip images (n is an integer greater than or equal to 2) is 255/j (j: 2 to N, 8-bit image) and the standard deviation of pixel values is set. Excluding the ADI image if it is less than the value,
In the rasterizing step, after rasterizing the N number of convolutional images, an average value is used. According to claim 5,
The semiconductor device patterning method of claim 1 , further comprising generating a contour band from the contour image and excluding the contour image when the value of the contour band is greater than a set value. According to claim 5,
A method for patterning a semiconductor device, characterized in that a density map for a full-chip of the sample is generated, and the density map is added to a channel by making the density map into the input image. According to claim 1,
The method of patterning a semiconductor device, characterized in that the DNN includes a plurality of down-sample layers. generating an input image by rasterizing a layout of a mask pattern corresponding to a pattern of a sample;
obtaining an OPC layout image for the mask pattern as an output image;
generating a predictive model through learning using a DNN with the input image and the output image;
predicting an OPC layout image of a pattern of a semiconductor device using the prediction model;
determining whether the predicted image of the OPC layout satisfies a set condition;
manufacturing a mask based on the image of the OPC layout when the condition is satisfied; and
A semiconductor device patterning method comprising: forming a pattern on a semiconductor device using the mask. According to claim 10,
In the rasterization, a windowed bi-cubic filter is used,
In the input image, a value of a level smaller than a pixel is interpolated using a Shannon-sampling algorithm and a bi-linear or bi-cubic algorithm, and a CD value at a threshold value is extracted using a Newton-Raphson algorithm. patterning method. According to claim 10,
The method of patterning a semiconductor device, characterized in that the DNN comprises a masking-layer for distinguishing or limiting regions. According to claim 10,
The DNN includes multiple down-sample layers,
The DNN has a residual block structure, a dual residual block structure, a fusion-fusion layer, a residual block first structure, a near list neighbor, a bi-linear or bi-cubic sampling scheme up-scale, and a swish activation function A semiconductor device patterning method, characterized in that using at least one of. According to claim 10,
The DNN uses a different structure according to the semiconductor process to be modeled through hierarchical parameter adjustment,
Adjusting the measurement parameter,
At least one of adjusting the number of down-sample layers, adjusting the number of residual blocks, adjusting the size of a kernel in a residual block, adjusting the size of an input kernel according to the size of a rasterization filter, and adjusting the number of model parameters according to layout complexity. A semiconductor device patterning method comprising a. Acquiring an ADI image of the pattern of the sample;
extracting a contour image from the ADI image;
generating an input image by rasterizing the contour image;
Acquiring an ACI image of a pattern of the sample after an etching process on the sample as an output image;
generating a predictive model through learning using a DNN with the input image and the output image;
predicting a pattern image of a semiconductor device after the etching process using the prediction model;
Determining whether the predicted pattern image after the etching process satisfies a set condition; and
and forming a pattern on the semiconductor device through the etching process when the condition is satisfied. According to claim 15,
The method of patterning a semiconductor device, characterized in that in the steps of acquiring the ADI image and generating the input image, automatically filtering and removing defective images. According to claim 15,
A method of patterning a semiconductor device, characterized in that generating a density map for the full-chip of the sample, and adding the density map to a channel by making the input image. According to claim 15,
The method of patterning a semiconductor device, characterized in that the DNN comprises a masking-layer for distinguishing or limiting regions. According to claim 15,
The DNN includes multiple down-sample layers,
The DNN has a residual block structure, a dual residual block structure, a fusion-fusion layer, a residual block first structure, a near list neighbor, a bi-linear or bi-cubic sampling scheme up-scale, and a swish activation function A semiconductor device patterning method, characterized in that using at least one of. According to claim 15,
The DNN uses a different structure according to the semiconductor process to be modeled through layer parameter adjustment according to the semiconductor process to be modeled,
Adjusting the measurement parameter,
At least one of adjusting the number of down-sample layers, adjusting the number of residual blocks, adjusting the size of a kernel in a residual block, adjusting the size of an input kernel according to the size of a rasterization filter, and adjusting the number of model parameters according to layout complexity. A semiconductor device patterning method comprising a.

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