KR20230079248A - Ferroelectric memory device containing word lines and pass gates and method of forming the same - Google Patents

Abstract

The memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric positioned between the semiconductor channel and the plurality of pass gate electrodes, and a semiconductor channel and a plurality of word lines. It includes portions of ferroelectric material positioned between the word lines.

Description

Ferroelectric memory device containing word lines and pass gates and method of forming the same

related application

This application claims the benefit of priority to U.S. Provisional Application Serial No. 16/457,687, filed on June 28, 2019, and U.S. Provisional Application Serial No. 16/457,721, filed on June 28, 2019, the entire contents of which is incorporated herein by reference for all purposes.

technology field

The present disclosure relates generally to the field of semiconductor memory devices, and more particularly to ferroelectric memory devices including word lines and pass gates and methods of making the same.

A ferroelectric material refers to a material that exhibits spontaneous polarization of an electric charge in the absence of an applied electric field. The net polarization (P) of charge in a ferroelectric material is non-zero at the minimum energy state. Thus, spontaneous ferroelectric polarization of the material occurs, and the ferroelectric material accumulates surface charges of opposite polarity types on two opposing surfaces. The polarization (P) of a ferroelectric material as a function of the voltage (V) applied across the ferroelectric material exhibits hysteresis. The product of the remanent polarization and the coercive field of a ferroelectric material is a measure that characterizes the effect of the ferroelectric material.

A ferroelectric memory device is a memory device containing ferroelectric material used to store information. The ferroelectric material serves as the memory material of the memory device. The dipole moment of a ferroelectric material has two different orientations (e.g. relative to atomic positions such as oxygen and/or metal atomic positions in the crystal lattice) depending on the polarity of the electric field applied to the ferroelectric material to store information in the ferroelectric material. one "up" or "down" polarization position). Different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment of the ferroelectric material. For example, the orientation of the dipole moment can be detected by measuring the current through a semiconductor channel provided adjacent to ferroelectric material in a field effect transistor ferroelectric memory device.

According to one embodiment of the present disclosure, a memory device is disposed between a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, and a semiconductor channel and a plurality of pass gate electrodes. a gate dielectric, and portions of ferroelectric material positioned between the semiconductor channel and the plurality of word lines.

According to another embodiment of the present disclosure, a method of forming a three-dimensional memory device is provided, the method comprising: forming a vertically alternating sequence of insulating layers and electrically conductive layers over a substrate; forming line trenches extending laterally along the first horizontal direction through a vertically alternating sequence, wherein remaining portions of the vertically alternating sequence include alternating stacks of insulating strips and electrically conductive strips; forming a row of in-process memory pillar structures within each of the line trenches, each of the in-process memory pillar structures comprising, in a direction from one side to another, a layer of ferroelectric material; including an interlayer dielectric layer, a sacrificial pillar portion, and a gate dielectric layer; forming channel cavities by removing sacrificial pillar portions; and forming a semiconductor channel within each channel cavity on each pair of the interlevel dielectric layer and the gate dielectric layer.

According to another aspect of the present disclosure, a method of forming a memory device is formed, the method comprising: forming pass gate electrodes embedded in a dielectric material layer over a substrate; forming a gate dielectric layer over the pass gate electrodes; forming a semiconductor channel, source region, and drain region over the gate dielectric layer; and forming interlayer dielectric portions, ferroelectric material portions, and word lines over the semiconductor channel.

According to yet another aspect of the present disclosure, a three dimensional memory device comprises a word line type stack of alternating first insulating strips and word lines positioned over a substrate, alternating second insulating strips and pass positioned over a substrate. A pass gate type stack of gate electrodes, a vertical semiconductor channel located between the pass gate type stack and the word line type stack, a gate dielectric located between the vertical semiconductor channel and the pass gate type stack, and between the vertical semiconductor channel and the word line type stack. It includes portions of ferroelectric material located on.

1A is a vertical cross-sectional view of a first exemplary structure for forming a first ferroelectric memory device after formation of pass gate electrodes and a gate dielectric layer, in accordance with a first embodiment of the present disclosure.
FIG. 1B is a plan view of the first exemplary structure of FIG. 1A.
2A is a vertical cross-sectional view of a first exemplary structure after formation of semiconductor channels, source regions, and drain regions, according to a first embodiment of the present disclosure.
FIG. 2B is a plan view of the first exemplary structure of FIG. 2A.
3A is a vertical cross-sectional view of a first exemplary structure after formation of an interlayer dielectric layer, a ferroelectric material layer and word lines, according to a first embodiment of the present disclosure.
FIG. 3B is a plan view of the first exemplary structure of FIG. 3A.
4A is a vertical cross-sectional view of an alternative configuration of a first exemplary structure, in accordance with a first embodiment of the present disclosure.
4B is a plan view of the first exemplary structure of FIG. 4A.
5A is a vertical cross-sectional view of a second exemplary structure after formation of a vertically alternating sequence of insulating layers and electrically conductive layers, according to a second embodiment of the present disclosure.
FIG. 5B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 5A. The vertical plane A - A' is the plane of the vertical section in Fig. 5a.
6A is a vertical cross-sectional view of a second exemplary structure after formation of vertically alternating stacks of line trenches and insulating strips and electrically conductive strips, in accordance with a second embodiment of the present disclosure.
6B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 6A. The vertical plane A - A' is the plane of the vertical section in Fig. 6A.
7A is a vertical cross-sectional view of a second exemplary structure after formation of a ferroelectric material layer, according to a second embodiment of the present disclosure.
FIG. 7B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 7A. The vertical plane A - A' is the plane of the vertical section in Fig. 7a.
8A is a vertical cross-sectional view of a second exemplary structure after patterning a layer of ferroelectric material into multiple portions, in accordance with a second embodiment of the present disclosure.
FIG. 8B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 8A. The vertical plane A-A' is the plane of the vertical cross-section of FIG. 8A.
9A is a vertical cross-sectional view of a second exemplary structure after deposition of a continuous dielectric material layer, in accordance with a second embodiment of the present disclosure.
FIG. 9B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 9A. The vertical plane A - A' is the plane of the vertical section in Fig. 9A.
10A is a vertical cross-sectional view of a second exemplary structure after formation of a combination of a ferroelectric material layer, an interlevel dielectric layer, a sacrificial pillar rail, and a gate dielectric layer within each line trench, according to a second embodiment of the present disclosure.
FIG. 10B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 10A. The vertical plane A - A' is the plane of the vertical section in Fig. 10A.
11A is a vertical cross-sectional view of a second exemplary structure after formation of a laterally alternating sequence of in-process memory pillar structures and dielectric pillar structures within each line trench, in accordance with a second embodiment of the present disclosure.
11B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 11A. The vertical plane A - A' is the plane of the vertical section in Fig. 11A.
12A is a vertical cross-sectional view of a second exemplary structure after formation of channel cavities within each line trench, in accordance with a second embodiment of the present disclosure.
FIG. 12B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 12A. The vertical plane A - A' is the plane of the vertical section in Fig. 12A.
13A is a vertical cross-sectional view of a second exemplary structure after formation of semiconductor channels, dielectric cores and drain regions within pillar cavities, in accordance with a second embodiment of the present disclosure.
FIG. 13B is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane B-B′ of FIG. 13A. The vertical plane A - A' is the plane of the vertical section in Fig. 13A.
13C is a vertical cross-sectional view of a second exemplary structure after formation of word lines, pass gates, and bit lines, in accordance with a second embodiment of the present disclosure.
13D is a horizontal cross-sectional view of a second exemplary structure along the horizontal plane D-D′ of FIG. 13C. The vertical plane C - C' is the plane of the vertical section in Fig. 13c.
14A is a vertical cross-sectional view of a first configuration of a third exemplary structure including a three-dimensional array of ferroelectric memory elements, in accordance with a third embodiment of the present disclosure.
14B is a horizontal cross-sectional view of a first configuration of a third exemplary structure along horizontal plane B-B′ of FIG. 14A. The vertical plane A - A' is the plane of the vertical section in Fig. 14A.
14C is a vertical cross-sectional view of a first configuration of a third exemplary structure along the vertical plane C-C′ of FIG. 14B. The horizontal plane B-B' is the plane of the horizontal cross-section in Fig. 14B.
14D is a horizontal cross-sectional view of a first configuration of a third exemplary structure along the horizontal plane D-D′ of FIGS. 14A and 14C. The vertical plane A - A' is the plane of the vertical section in Fig. 14A. The vertical plane C-C' is the plane of the vertical section in Fig. 14c.
15A is a vertical cross-sectional view of a second configuration of a third exemplary structure including a three-dimensional array of ferroelectric memory elements, in accordance with a third embodiment of the present disclosure.
15B is a horizontal cross-sectional view of a second configuration of the third exemplary structure along the horizontal plane B-B′ of FIG. 15A. The vertical plane A - A' is the plane of the vertical section in Fig. 15A.
16A is a vertical cross-sectional view of a third configuration of a third exemplary structure including a three-dimensional array of ferroelectric memory elements, in accordance with a third embodiment of the present disclosure.
16B is a horizontal cross-sectional view of a third configuration of the third exemplary structure along the horizontal plane B-B′ of FIG. 16A. The vertical plane A - A' is the plane of the vertical section in Fig. 16A.
16C is a vertical cross-sectional view of a third configuration of the third exemplary structure along the vertical plane C-C′ of FIG. 16B. The horizontal plane B-B' is the plane of the horizontal cross-section in Fig. 16B.
17A is a vertical cross-sectional view of a first configuration of a fourth exemplary structure comprising a three-dimensional array of ferroelectric memory elements, in accordance with a fourth embodiment of the present disclosure.
17B is a horizontal cross-sectional view of a first configuration of a fourth exemplary structure along horizontal plane B-B′ of FIG. 17A. The vertical plane A - A' is the plane of the vertical section in Fig. 17A.
17C is a horizontal cross-sectional view of a first configuration of a fourth exemplary structure along horizontal plane C-C′ of FIG. 17A. The vertical plane A - A' is the plane of the vertical section in Fig. 17A.
18A is a vertical cross-sectional view of a second configuration of a fourth exemplary structure comprising a three-dimensional array of ferroelectric memory elements, in accordance with a fourth embodiment of the present disclosure.
18B is a horizontal cross-sectional view of a second configuration of the fourth exemplary structure along the horizontal plane B-B′ of FIG. 18A. The vertical plane A - A' is the plane of the vertical section of FIG. 18A.
18C is a vertical cross-sectional view of a third configuration of a fourth exemplary structure including a three-dimensional array of ferroelectric memory elements, in accordance with a fourth embodiment of the present disclosure.
19A is a vertical cross-sectional view of a fourth configuration of a fourth exemplary structure including a three-dimensional array of ferroelectric memory elements, in accordance with a fourth embodiment of the present disclosure.
19B is a horizontal cross-sectional view of a fourth configuration of a fourth exemplary structure along horizontal plane B-B′ of FIG. 19A. Vertical plane A - A' is the plane of the vertical cross-section of FIG. 19A.
20 is a vertical cross-sectional view of a fifth configuration of a fourth exemplary structure including a three-dimensional array of ferroelectric memory elements, in accordance with a fourth embodiment of the present disclosure.
21A is a schematic circuit diagram of second, third, and fourth exemplary structures of the present disclosure. 21B and 21C are tables showing exemplary voltages that may be used to operate the circuit of FIG. 21A.

As discussed above, embodiments of the present disclosure relate to ferroelectric memory devices including both word lines and pass gate electrodes and methods of fabrication thereof, various aspects of which are described in detail herein. Pass gate electrodes reduce or eliminate disturbances between adjacent ferroelectric memory cells within the same memory string.

The drawings are not drawn to scale. Multiple instances of an element may be redundant where a single instance of an element is shown unless the absence of overlapping of elements is explicitly stated or clearly indicated otherwise. Ordinal numbers such as “first,” “second,” and “third” are only used to identify like elements, and different ordinal numbers may be used throughout the specification and claims of this disclosure. Like reference numerals designate the same or similar elements. Unless otherwise indicated, elements having the same reference numbers are assumed to have the same composition and the same function. Unless indicated otherwise, “contact” between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element positioned “on” a second element may be positioned on an outer face of a surface of the second element or on an inner face of the second element. As used herein, a first element is positioned “directly on” a second element when there is physical contact between the surface of the first element and the surface of the second element. As used herein, a first element is “electrically connected” to a second element when there is a conductive path between the first element and the second element made of at least one conductive material. As used herein, a “prototype” structure or “in-process” structure refers to a temporary structure that is subsequently modified in shape or composition of at least one component therein.

As used herein, “layer” refers to a portion of material that includes a region having a thickness. A layer may extend throughout the entirety of the underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. A layer can also be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between any pair of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and/or along a tapered surface. The substrate may be one layer, may include one or more layers therein, or may have one or more layers on, above, and/or below it.

As used herein, when a second surface overlies or underlies a first surface, and there is a vertical plane or substantially vertical plane comprising the first surface and the second surface, the first surface and the second surface "coincident" with each other. A substantially vertical plane is a plane that extends straight along a direction that departs from the vertical by an angle of less than 5 degrees. The vertical plane or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along the vertical or substantially perpendicular direction.

A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate, such as a semiconductor wafer, without intervening substrates. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each underlying level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167 entitled "Three-dimensional Structure Memory," forming memory levels on separate substrates and stacking the memory levels vertically to achieve a non-monolithic Stacked memories were constructed. Substrates may be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed on separate substrates, such memories are not truly monolithic three-dimensional memory arrays. Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices, and may be fabricated using various embodiments described herein.

Referring to FIGS. 1A and 1B , a first exemplary structure for forming a first ferroelectric memory device according to a first embodiment of the present disclosure is shown. The first example structure includes a substrate 109 that can be a semiconductor substrate, an insulating substrate, or a conductive substrate. For example, substrate 109 may include a commercially available silicon wafer. Where substrate 109 includes a semiconductor material or a conductive material, an insulating spacer layer 10 may be formed over substrate 109 to provide electrical isolation from substrate 109 for devices to be formed thereon. . The insulating spacer layer 10 includes a dielectric material such as silicon oxide, silicon nitride or dielectric metal oxide. For example, insulating spacer layer 10 may comprise undoped silicate glass or doped silicate glass and may have a thickness ranging from 10 nm to 500 nm, although smaller and larger thicknesses may also be used. can

A pass-gate-isolation dielectric layer 132 is deposited over the insulating spacer layer 10 and patterned to form line trenches extending laterally along a horizontal direction referred to herein as the gate direction gd. Pass-gate-isolation dielectric layer 132 is a layer of insulating material having a horizontal upper surface. At least one conductive material may be deposited within the line trenches. The at least one conductive material may include at least one metallic material and/or at least one heavily doped semiconductor material. For example, a combination of a conductive metal nitride (eg, TiN, TaN, or WN) and a conductive fill material (eg, W, Co, Mo, Ru, Cu, etc.) may be deposited in the line trenches. Excess portions of at least one conductive material may be removed from above a horizontal plane that includes upper surfaces of remaining portions of pass-gate-isolation dielectric layer 132 . Remaining portions of at least one conductive material in the line trenches include pass gate electrodes 36 . As used herein, a "pass gate electrode" is an electrode, such as a back gate electrode, used to control the flow of current through a semiconductor channel regardless of the voltage applied to a word line located adjacent to the semiconductor channel. refers to Select gate electrodes 26 and 66 may be formed in addition to pass gate electrodes 36 . As used herein, “selection gate electrode” refers to an electrode capable of enabling or disabling current through a semiconductor channel. The select gate electrodes 26 and 66 include a source-side select gate electrode 26 formed on one side of the pass gate electrodes 36 and a drain-side formed on the other side of the pass gate electrodes 66. A side selection gate electrode 66 may be included.

Alternatively, prior to forming pass-gate-isolation dielectric layer 132, select gate electrodes 26, 66 and pass gate electrodes 36 may be formed. An electrically conductive layer may be formed and patterned to form rail-shaped select gate electrodes 26, 66 and pass gate electrodes 36. Dielectric material is then formed over and between the electrodes, and planarized to remove the dielectric material from over the electrodes to form a pass-gate-isolation dielectric layer 132 located between electrodes 26, 66, 36. form

A gate dielectric layer 52 may be deposited on top surfaces of pass gate electrodes 36 , select gate electrodes 26 and 66 , and pass-gate-isolation dielectric layer 132 . Gate dielectric layer 52 includes a gate dielectric layer material such as silicon oxide and/or dielectric metal oxide.

Referring to FIGS. 2A and 2B , a semiconductor material may be deposited over the gate dielectric layer 52 and patterned into strips extending laterally along the channel direction cd, which may be perpendicular to the gate direction gd. can get angry The semiconductor material may include, for example, silicon (eg, amorphous silicon or polysilicon), a silicon-germanium alloy, or a compound semiconductor material. The semiconductor material may have doping of a first conductivity type, which may be p-type or n-type. The atomic concentration of electrical dopants of the first conductivity type in the semiconductor material may range from 1.0×10 ¹⁵ /cm 3 to 1.0×10 ¹⁸ /cm 3 , although smaller and larger atomic concentrations may be used. The thickness of the patterned strips of semiconductor material may range from 3 nm to 60 nm, such as from 6 nm to 30 nm, although smaller and larger thicknesses may also be used. The patterned strips of semiconductor material are laterally spaced by line trenches extending laterally along the channel direction cd.

A source region 28 and a drain region 68 may be formed on or within opposite ends of the strips of semiconductor material. The source and drain regions may include respective source and drain lines, or separate doped semiconductor regions electrically connected to respective source and drain lines. For example, dopants of the second conductivity may be implanted into end portions of the strips of semiconductor material using a masked ion implantation process. Implanted portions of the patterned strips of semiconductor material may be located outside the regions containing pass gate electrodes 36 and select gate electrodes 26, 66. A source region 28 may be formed in an implanted portion of each of the strips of semiconductor material adjacent to the source-side select gate electrode 26, and a drain region 68 of semiconductor material adjacent to the drain-side select gate electrode 66. It can be formed within the injection portion of each of the strips. Each continuous portion of the strip of semiconductor material extending between source region 28 and drain region 68 constitutes a semiconductor channel 160 . The atomic concentration of dopants of the second conductivity type in source regions 28 and drain regions 68 may range from 5.0×10 ¹⁸ /cm 3 to 2.0×10 ²¹ /cm 3 , although smaller atomic concentrations and larger Atomic concentrations may also be used.

A dielectric material such as silicon oxide is deposited in the line trenches. Excess portions of the dielectric material overlying the horizontal plane including the upper surfaces of the semiconductor channels 160 are removed by a planarization process. The planarization process may use recess etching and/or chemical mechanical planarization. The remainder of the deposited dielectric material constitutes the channel-isolation dielectric layer 162, which includes semiconductor channels 160, source regions 28 and a plurality of strips extending laterally along the channel direction cd. ), and a matrix portion that laterally surrounds the entire region including the drain regions 68 .

Alternatively, channel-isolation dielectric layer 162 may be formed by first depositing a dielectric material and patterning the dielectric material into rail-shaped portions of channel-isolation dielectric layer 162 . Semiconductor channels 160 are then formed by depositing semiconductor material between and over the rail-shaped portions of channel-isolation dielectric layer 162, and rail-shaped portions between rail-shaped portions of channel-isolation dielectric layer 162. It is formed by planarizing the semiconductor material to leave semiconductor channels 160 of .

Referring to FIGS. 3A and 3B , interlevel (eg, barrier) dielectric layer 156 , ferroelectric material layer 154L, and at least one electrically conductive material layer form semiconductor channels 160 and a channel-isolation dielectric layer ( 162) can be sequentially deposited on top. Interlevel dielectric layer 156 includes a dielectric material such as silicon oxide, silicon nitride or dielectric metal oxide. The thickness of the interlevel dielectric layer 156 may range from 0.5 nm to 6 nm, such as from 1 nm to 3 nm, although smaller and larger thicknesses may also be used.

The ferroelectric material layer 154L includes a ferroelectric material. As used herein, “ferroelectric material” refers to a crystalline material that exhibits spontaneous electrical polarization in the absence of an external electric field. The ferroelectric material in ferroelectric material layer 154L may be an insulating ferroelectric material. In one embodiment, the ferroelectric material layer 154L includes an orthorhombic phase hafnium oxide layer including at least one dopant selected from Al, Zr, and/or Si. Other suitable ferroelectric materials such as titanate ferroelectric materials (eg, barium titanate, lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate (“PLZT”), etc.) may also be used. The ferroelectric material layer 154L may have a thickness ranging from 3 nm to 60 nm, such as from 6 nm to 30 nm, although smaller and larger thicknesses may also be used. In one embodiment, the ferroelectric material layer 154L may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The at least one conductive material may include at least one metallic material and/or at least one heavily doped semiconductor material. In one embodiment, the at least one conductive material is a conductive metal nitride barrier layer comprising a conductive metal nitride material (eg, TiN, TaN, and/or WN) and a metal (eg, W, Mo, Cu, Co, Ru, etc.) ) may include a layer stack of metal layers comprising. At least one conductive material may be patterned into strip shapes extending in direction gd and overlying semiconductor channels 160 . Each patterned strip of at least one conductive material constitutes a word line 46 that is a control gate electrode for each of the underlying semiconductor channels 160 . In one embodiment, each word line 46 overlies a respective one of the pass gate electrodes 36 . In another embodiment, the word lines and pass gate electrodes may be laterally offset from each other.

Dielectric material may be deposited around word lines 46 and planarized to provide word-line-isolation dielectric layer 142 . Alternatively, word-line-isolation dielectric layer 142 can be formed and patterned prior to forming word lines 46, which word-line-isolation dielectric layer 142 formed by a damascene process at openings in A stack of an interlayer dielectric portion and a ferroelectric material portion may be formed between each word line 46 and each semiconductor channel 160 . Each interlevel dielectric portion includes a portion of interlevel dielectric layer 156 . Each ferroelectric material portion is a portion of ferroelectric material layer 154L. Accordingly, interlevel dielectric portions are formed as portions of interlevel dielectric layer 156 and lie underneath a respective one of word lines 46 . Portions of ferroelectric material are formed as portions of ferroelectric material layer 154L and underlie a respective one of word lines 46 .

Referring to FIGS. 4A and 4B , an alternative configuration of a first example structure according to a first embodiment of the present disclosure is shown. In such a configuration, in the processing steps of FIGS. 3A and 3B used to pattern the at least one conductive material, an anisotropic etching process may be used to etch through the at least one conductive material and the ferroelectric material layer 154L. .

In other words, ferroelectric material layer 154L is patterned using the same etch mask used to pattern at least one electrically conductive material into word lines 46 . The ferroelectric material layer 154L is patterned into ferroelectric material portions 154 having the same horizontal cross-sectional shape as overlying one of the word lines 46 .

In general, a layer stack of ferroelectric material layer 154L and at least one conductive material layer may be formed over interlevel dielectric layer 156 . The layer stack can be patterned into individual material stacks using an anisotropic etch process. Each of the individual material stacks includes a patterned portion of a ferroelectric material layer 154L, which constitutes one of the ferroelectric material portions 154, and a pattern of at least one conductive material layer, which constitutes one of the word lines 46. may contain fragments.

Referring to FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B , adjacent portions of the semiconductor channel 160 and word lines 46, pass gate electrodes ( 36), the select gate electrodes 26, 66, the gate dielectric layer 52, and the interlayer dielectric layer 156 constitute a ferroelectric memory string, and data is connected to the semiconductor channel 160 and the word lines ( 46) in the form of the direction of the ferroelectric polarization in the ferroelectric material portions located between them. The ferroelectric polarization of each ferroelectric material portion may be directed toward or away from the semiconductor channel 160 .

A memory device comprising at least one ferroelectric memory string is provided. Each of the at least one ferroelectric memory string includes a semiconductor channel 160 extending between a source region 28 and a drain region 68; A gate dielectric located on a first longitudinal surface (eg, bottom surface) of the semiconductor channel 160 between the source region 28 and the drain region 68, for example, extending along the channel direction cd. layer 52; pass gate electrodes 36 located on the gate dielectric layer 52 and extending between the source region 28 and the drain region 68; and word lines (46) located over a second longitudinal surface (eg, upper surface) of the semiconductor channel (160) between the source region (28) and the drain region (68), the second longitudinal surface being the second longitudinal surface. Located on opposite sides of one longitudinal surface, each of the word lines 46 is bounded by a respective ferroelectric material portion 154L or 154 and a respective interlayer dielectric portion, i.e., portions of the interlayer dielectric layer 156. 2 spaced apart from the longitudinal surface.

In one embodiment, the interlayer dielectric portions within each of the at least one ferroelectric memory string include portions of an interlayer dielectric layer 156 extending across each of the word lines 46 .

In one embodiment, the ferroelectric material portions within each of the at least one ferroelectric memory string include portions of the ferroelectric material layer 154L extending from a region overlying the source region 28 to a region overlying the drain region 68.

In one embodiment, the ferroelectric material portions within each of the at least one ferroelectric memory string are individual ferroelectric material portions that are spaced apart from each other by interposing dielectric material portions (e.g., portions of word-line-isolation dielectric layer 142). (154).

In one embodiment, each of the at least one ferroelectric memory string is positioned over an insulating material layer 10 having a horizontal upper surface. The first longitudinal surface and the second longitudinal surface are parallel to the horizontal upper surface of the insulating material layer 10 .

Referring to FIGS. 5A and 5B , an exemplary second structure for forming a second ferroelectric memory device according to a second embodiment of the present disclosure is illustrated. A vertically alternating sequence 32L, 42L of insulating layers 32L and sacrificial layers 42L may be formed over a substrate including a substrate semiconductor layer 9 . The substrate semiconductor layer 9 may include single crystal silicon with a doping of a first conductivity type (eg p-type). Dopants may include a well in a single crystal silicon wafer (ie a well in the substrate semiconductor layer 9), or a wafer background doping. The atomic concentration of dopants of the first conductivity type in the substrate semiconductor layer 9 may range from 1.0×10 ¹⁵ /cm 3 to 3.0×10 ¹⁸ /cm 3 , although smaller and larger atomic concentrations may also be used. . Source regions 28 (eg, portions of a doped source line or a doped region located in electrical contact with a source line) may be formed in an upper portion of the substrate semiconductor layer 9 . Source regions 28 have a doping of a second conductivity type opposite to the first conductivity type (eg, n-type). The atomic concentration of dopants of the second conductivity type in the source region in the substrate semiconductor layer 9 may range from 5.0×10 ¹⁹ /cm 3 to 2.0×10 ²¹ /cm 3 , although smaller and larger atomic concentrations are also used. It can be.

Insulating materials that may be used for insulating layers 32L include silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, high dielectric dielectric metal oxides and silicates thereof, commonly known as constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.), dielectric metal oxynitrides and silicates thereof, and organic insulating materials. . In one embodiment, the insulating layers 32L may include silicon oxide. The sacrificial layers 42L may be formed of any suitable sacrificial material that is removed selectively with respect to the first material of the insulating layers 32L. The sacrificial layers 42L may include an insulating material such as silicon nitride or, when the insulating layers 32L include silicon oxide, a semiconductor material such as amorphous silicon or polysilicon.

Each of insulating layers 32L and sacrificial layers 42L may be deposited by, for example, chemical vapor deposition (CVD). Each of insulating layers 32L and sacrificial layers 42L may have a thickness ranging from 20 nm to 50 nm, although smaller and larger thicknesses may also be used. In one embodiment, each of the insulating layers 32L may have a first thickness, and each of the sacrificial layers 42L may have a second thickness. In one embodiment, the uppermost one of the insulating layers 32L may have a greater thickness than the underlying insulating layers 32L. The combination of the insulating layer 32L and the sacrificial layer 42L constitutes a repeating unit that is repeated multiple times along the vertical direction. The total number of repetitions of a repeating unit may range from 8 to 1,024, such as from 32 to 256, although fewer and more repetitions may be used.

6A and 6B, a photoresist layer may be applied over top insulating layer 32L and lithographically patterned to form a line and space pattern extending laterally along a first horizontal direction hd1. It can be. The line and space patterns are transferred through vertically alternating sequences 32L and 42L to form line trenches 49 extending laterally along the first horizontal direction hd1. It can be divided into a plurality of separate parts that are laterally spaced from each other and laterally spaced apart along the second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The anisotropic etching process can stop on the upper surface of the substrate semiconductor layer 9 . The photoresist layer may be subsequently removed, for example by ashing.

The patterned portions of insulating layers 32L include insulating strips 32 . The patterned portions of sacrificial layers 42L include sacrificial strips 42 . The remaining portions of the vertically alternating sequence 32L, 42L include word line type stacks 31 and pass gate type stacks 33 of insulating strips 32 and sacrificial strips 42 . Word line type stacks 31 and pass gate type stacks 33 may alternate laterally along the second horizontal direction hd2. Each neighboring pair of word line type stack 31 and pass gate type stack 33 may be laterally spaced by a respective line trench 49 .

The width of each word line type stack 31 along the second horizontal direction hd2 may range from 20 nm to 200 nm, although smaller and larger widths may also be used. The width of each pass gate type stack 33 of insulating strips 32 and the pass gate electrodes 36 along the second horizontal direction hd2 may range from 20 nm to 200 nm, but with a smaller width. and larger widths may also be used. The width of each line trench 49 may range from 20 nm to 200 nm, although smaller and larger widths may also be used.

7A and 7B, a continuous ferroelectric material layer 54L is physically formed on the substrate semiconductor layer 9 and the alternating stacks 31, 33 by conformal deposition such as chemical vapor deposition or atomic layer deposition. It can be formed on exposed surfaces. Continuous ferroelectric material layer 54L may include an insulating ferroelectric material. In one embodiment, the continuous ferroelectric material layer 54L includes an orthorhombic phase hafnium oxide layer including at least one dopant selected from Al, Zr, and/or Si. Other suitable ferroelectric materials such as titanate ferroelectric materials (eg, barium titanate, lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate (“PLZT”), etc.) may also be used. Continuous ferroelectric material layer 54L may have a thickness ranging from 3 nm to 60 nm, such as from 6 nm to 30 nm, although smaller and larger thicknesses may also be used.

8A and 8B, the volumes of the line trenches 49 are partially filled with a masking material layer 53 covering the continuous ferroelectric material layer 54L. Masking material layer 53 may include a material that can function as an etch mask. For example, masking material layer 53 may include a hard mask material such as borosilicate glass, carbon, or amorphous silicon.

Masking material layer 53 may be patterned such that patterned portions of masking material layer 53 cover each word line type stack 31 but do not cover pass gate type stacks 33 . Thus, the masking material layer 53 covers the first longitudinal sidewall of each line trench 49 (ie the sidewalls of each word line type stack 31), but the It does not cover the second longitudinal sidewall (ie the sidewalls of each pass gate type stack 33). In other words, the patterned masking material layer 53 covers one of the pair of longitudinal sidewalls of each line trench 49 and does not cover the other of the pair of longitudinal sidewalls of each line trench 49 . . As used herein, “longitudinal sidewall” refers to a sidewall that extends laterally along the length of the line trench 49 .

For example, a photoresist layer (not shown) can be applied over the masking material layer and can be lithographically patterned. The pattern of the photoresist layer may subsequently be transferred through the masking material layer 53 by anisotropic etching. The photoresist layer may be subsequently removed, for example by ashing. Unmasked portions of the continuous ferroelectric material layer 54L may be removed by an etching process. The continuous ferroelectric material layer 54L is divided into a plurality of ferroelectric material layers 54 spaced laterally along the second horizontal direction hd2. Each layer of ferroelectric material 54 covers each word line type stack 31 but does not cover each pass gate type stack 33 . The first longitudinal sidewall of each line trench 49 is in contact with a respective one of the ferroelectric material layers 54L, and the second longitudinal sidewall of each line trench 49 is any one of the ferroelectric material layers 54L. do not come into contact with A line cavity 49 ′ extending laterally along the first horizontal direction hd1 is present in each line trench 49 . A respective second longitudinal sidewall of the line trenches 49 is physically exposed to a respective one of the line cavities 49'.

Referring to FIGS. 9A and 9B , portions of the masking material layer 53 and the ferroelectric material layers 54 lying on a horizontal plane including the upper surfaces of the uppermost insulating strips 32 are subjected to, for example, chemical mechanical planarization and can be removed by the same planarization process. The ferroelectric material layer 54 may be divided into pairs of ferroelectric material layers 54 located on the sidewalls of each word line type stack 31 . Subsequently, remaining portions of the masking material layer 53 may be selectively removed relative to the ferroelectric material layers 54 , the alternating stacks 31 , 33 , and the substrate semiconductor layer 9 . As used herein, removal of a first material is “selective” relative to a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

A continuous dielectric material layer 56L may be deposited on the physically exposed surfaces of the ferroelectric material layers 54 , the substrate semiconductor layer 9 , and the alternating stacks 31 , 33 . Continuous dielectric material layer 56L includes a dielectric material such as silicon oxide, silicon nitride, or dielectric metal oxide. The thickness of the continuous dielectric material layer 56L may range from 0.5 nm to 6 nm, such as from 1 nm to 3 nm, although smaller and larger thicknesses may also be used. A line cavity 49' exists within each line trench 49.

Referring to FIGS. 10A and 10B , an anisotropic etching process may be performed to remove horizontal portions of the continuous dielectric material layer 56L. Each remaining vertical portion of continuous dielectric material layer 56L in contact with ferroelectric material layer 54 constitutes interlevel dielectric layer 56 . Each remaining vertical portion of continuous dielectric material layer 56L in contact with the sidewalls of alternating stacks 31 and 33 constitutes gate dielectric layer 52 .

Subsequently, a sacrificial fill material may be deposited into each of the line cavities 49'. The sacrificial fill material includes a material that can be removed selectively to the materials of the gate dielectric layers 52, the interlevel dielectric layers 56, the insulating strips 32 and the substrate semiconductor layer 9. For example, the sacrificial filler material may include amorphous carbon, diamond-like carbon (DLC), a silicon-germanium alloy, amorphous silicon, or a polymeric material. Portions of the sacrificial fill material lying on a horizontal plane including the top surfaces of the alternating stacks 31 and 33 may be removed by a planarization process such as chemical mechanical planarization and/or recess etching. Each remaining portion of the sacrificial filling material constitutes a sacrificial pillar rail 67R.

The contiguous set of material portions that fill line trench 49 constitute line trench filling assemblies 67R, 52, 56, and 54. Each line trench filling assembly 67R, 52, 56, 54 includes a sacrificial pillar rail 67R, gate dielectric layers 52, interlevel dielectric layers 56, and ferroelectric material layer 54.

11A and 11B, a first photoresist layer may optionally be applied over the alternating stacks 31, 33 and line trench filling assemblies 67R, 52, 56, 54, in a first horizontal direction. It can be lithographically patterned to form linear apertures extending along and overlying each one of the alternating stacks 31,33. A respective linear opening in the photoresist layer may overlie a middle portion of a respective one of the word line type stacks 31 . An anisotropic etching process may be performed to transfer the pattern of linear openings in the first photoresist layer through the top insulating strips 32 and the sacrificial strips 42 . The first photoresist layer may be subsequently removed, for example by ashing.

A second photoresist layer may be applied over top insulating strips 32 and line trench fill assemblies 67R, 52, 56, 54 and may be lithographically patterned to form a two-dimensional array of individual apertures. . The two-dimensional array of individual apertures may include multiple rows of individual apertures. Each row of discrete openings extends laterally along the first horizontal direction hd1 and overlies a respective one of the line trench filling assemblies 67R, 52, 56, 54. In one embodiment, each individual opening in the second photoresist layer has a line trench fill assembly 67R, 52, 56 parallel to and underlying a respective one along the second horizontal direction hd2. , 54) may include a pair of straight edges extending across the entire width. In one embodiment, each individual opening in the second photoresist layer may have a rectangular shape.

An anisotropic etching process is performed to transfer the pattern of individual openings in the second photoresist layer through the line trench fill assemblies 67R, 52, 56, 54. A two-dimensional array of rectangular pillar cavities may be formed in the volumes from which the etched portions 67R, 52, 56, 54 of the line trench filling assemblies were removed. Each rectangular pillar cavity may extend vertically through the entire height of the line trench filling assemblies 67R, 52, 56, 54, and the top surface of the substrate semiconductor layer 9 is at the bottom of each rectangular pillar cavity. may be physically exposed. Each line trench filling assembly 67R, 52, 56, 54 may be divided into a number of separate parts spaced laterally along the first horizontal direction hd1. Each of the plurality of discrete parts constitutes an in-process memory pillar structure 67, 52, 56, 54. The second photoresist layer may be removed, for example by ashing.

Each of the in-process memory pillar structures 67, 52, 56, 54 includes, from one side to the other, a ferroelectric material layer 54, an interlayer dielectric layer 56, a sacrificial pillar portion 67, and a gate. dielectric layer 52 . The respective ferroelectric material layer 54 in the in-process memory pillar structures 67, 52, 56, 54 is the pattern of the ferroelectric material layer 54 in the respective line trench filling assembly 67R, 52, 56, 54. the burned part. Each interlayer dielectric layer 56 in the in-process memory pillar structures 67, 52, 56, 54 is the pattern of the interlayer dielectric layer 56 in the respective line trench filling assembly 67R, 52, 56, 54. the burned part.

Each sacrificial pillar portion 67 in the in-process memory pillar structures 67, 52, 56, 54 is a pattern of the sacrificial pillar rail 67R in the respective line trench filling assembly 67R, 52, 56, 54. the burned part. Each gate dielectric layer 52 in the in-process memory pillar structures 67, 52, 56, 54 is the pattern of the gate dielectric layer 52 in the respective line trench filling assembly 67R, 52, 56, 54. the burned part. Each in-process memory pillar structure 67, 52, 56, 54 may have a pair of straight sidewalls extending along the second horizontal direction. Each component of the in-process memory pillar structure 67, 52, 56, 54 is uniform in width along the first horizontal direction hd1, the width of the respective in-process memory pillar structure 67, 52, 56, 54. can have one width.

A dielectric material, such as silicon oxide, is located between each laterally neighboring pair of in-process memory pillar structures 67, 52, 56, 54, and separates the alternating stacks 31, 33. can be conformally deposited in rectangular pillar cavities located in line trenches. Excess portions of dielectric material may be removed from above the horizontal plane containing the top surfaces of the top insulating strips 32 . Each remaining portion of the dielectric material filling a respective rectangular pillar cavity constitutes a dielectric pillar structure 64 . Each remaining portion of the dielectric material filling the respective line trench constitutes a drain-select-level dielectric isolation structure 72 .

In one embodiment, a respective dielectric pillar structure 64 is interposed between each laterally neighboring pair of in-process memory pillar structures 67, 52, 56, 54 in respective line trenches 49. is formed in A row of dielectric pillar structures 64 is formed within each line trench 49 . A row of dielectric pillar structures 64 is interlaced with a row of in-process memory pillar structures 67, 52, 56, 54 in each line trench 49. Accordingly, a laterally alternating sequence of in-process memory pillar structures 67 , 52 , 56 , 54 and dielectric pillar structures 64 are formed within each line trench 49 .

Referring to FIGS. 12A and 12B , the sacrificial pillar portions 67 are applied to the materials of the gate dielectric layers 52, the interlevel dielectric layers 56, the substrate semiconductor layer 9, and the dielectric pillar structures 64. can be selectively removed. A channel cavity 69 is formed in each volume from which the sacrificial pillar portion 67 is removed. An upper surface of the substrate semiconductor layer 9 may be physically exposed at the bottom of each channel cavity 69 . Gate dielectric layer 52 is physically exposed on one side of each channel cavity 69 and interlevel dielectric layer 56 is physically exposed on the opposite side of each channel cavity 69 . The sidewalls of the pair of dielectric pillar structures 64 may be physically exposed to the channel cavity 69 .

Referring to FIGS. 13A and 13B , a semiconductor material having doping of a first conductivity type may be deposited into channel cavities 69 by a conformal deposition process. The semiconductor material may be selected from at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. there is. In one embodiment, the conformally deposited semiconductor material includes amorphous silicon or polysilicon. The atomic concentration of electrical dopants of the first conductivity type in the semiconductor material may range from 1.0×10 ¹⁵ /cm 3 to 1.0×10 ¹⁸ /cm 3 , although smaller and larger atomic concentrations may be used. Semiconductor materials may be deposited by conformal deposition methods such as low pressure chemical vapor deposition (LPCVD). The thickness of the deposited semiconductor material may range from 2 nm to 20 nm, although smaller and larger thicknesses may also be used. After deposition of the semiconductor material, an optional unfilled volume may exist within each channel cavity 69 .

A dielectric fill material, such as silicon oxide, may be deposited in the unfilled volumes of channel cavities 69 . Excess portions of the deposited semiconductor material and dielectric fill material overlying the horizontal plane including the upper surfaces of the top insulating strips 32 may be removed by a planarization process. For example, the first recess etch process may vertically recess the dielectric fill material to a height below a horizontal plane that includes the top surfaces of the top insulating strips 32 . The first recess etch process may etch the dielectric fill material selectively relative to the underlying semiconductor material. Each remaining portion of the dielectric fill material in the channel cavities 69 constitutes the dielectric core 62 . Horizontal portions of the semiconductor material lying above the horizontal plane including the top surfaces of the top insulating strips 32 may be removed by a second recess etch process. The second recess etch process may etch the semiconductor material selectively to the materials of the insulating strips 32 and the dielectric cores 62 . Each remaining portion of the semiconductor material within the channel cavities 69 constitutes a vertical semiconductor channel 60 . Each vertical semiconductor channel 60 is formed in a respective channel cavity 69 on a respective pair of interlevel dielectric layer 56 and gate dielectric layer 52 .

Drain regions 68 may be formed by depositing a doped semiconductor material in each recessed region over dielectric core 62 . Drain regions 68 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in drain regions 68 may range from 5.0×10 ¹⁸ /cm 3 to 2.0×10 ²¹ /cm 3 , although lower and higher dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from over the top surface of the top insulating strips 32 by, for example, chemical mechanical planarization (CMP) or recess etching to form drain regions 68. . In one embodiment, surface portions of the substrate semiconductor layer 9 extending between the source regions 28 and the bottom ends of the vertical semiconductor channels 60 constitute the horizontal semiconductor channels 59 . In this case, each of the semiconductor channels 59 and 60 may include a vertical semiconductor channel 60 and a horizontal semiconductor channel 59 . Alternatively, the source regions 28 may be configured such that the bottom end of each vertical semiconductor channel 60 contacts a respective one of the source regions 28 . In this case, each semiconductor channel 60 may be configured as a vertical semiconductor channel 60 .

A memory pillar structure 54 , 56 , 60 , 62 , 68 , 52 may be formed between each laterally neighboring pair of dielectric pillar structures 64 in each line trench 49 . Each memory pillar structure 54, 56, 60, 62, 68, 52 includes a ferroelectric material layer 54, an interlevel dielectric layer 56, a vertical semiconductor channel 60, a dielectric core 62, and a gate dielectric layer. (52) may be included.

Subsequently, openings such as trenches or vias are formed through the structure to expose the sacrificial strips 42 . Sacrificial strips 42 are removed through the openings by selective etching to form horizontal recesses between the insulating strips 32 . Electrically conductive material is deposited through the openings into the recesses. The electrically conductive material may include an electrically conductive metal nitride barrier material such as TiN, WN or TN, and/or a metal fill material such as W, Al, Cu, Ru, Ti, Mo and/or alloys thereof. The electrically conductive material is then removed from the openings by anisotropic etching, leaving various electrodes and lines in the recesses.

13c and 13d, the electrodes and lines include word lines 46, pass gate electrodes 36, and two types of drain-side select gate electrodes 44, 66. do. Word lines 46 and first type drain side select gate electrodes 44 are located in word line type stacks 31 . Pass gate electrodes 36 and drain-side select gate electrodes 66 of the second type are located in pass gate type stacks 33 . Respective drain-side select gate electrodes 44, 66 overlie respective word lines 46 and pass gate electrodes 36 in their respective alternating stacks 31, 33. Each of the drain-side select gate electrodes 44 and 66 functions as a select gate electrode that selects or deselects the vertical semiconductor channel 60 for programming, erasing, or reading operations.

A bit line level insulating layer 82 is formed over the drain regions 68 and the alternating stacks 31 and 33 . Openings are formed in bit line level insulating layer 82 to expose drain regions 68 . Bit lines 98 and optional drain contact via structures 88 are formed in the openings that electrically contact drain regions 68 .

With reference to all figures from FIGS. 5A-13D , a memory device comprising at least one ferroelectric memory string is provided. Each of the at least one ferroelectric memory string includes a semiconductor channel (59, 60) extending between a source region (28) and a drain region (68); a gate dielectric layer 52 located on the first longitudinal surface (which is the first vertical surface) of the semiconductor channel 60; pass gate electrodes 36 positioned on the gate dielectric layer 52 and extending between the source and drain regions 68; and word lines (46) located over a second longitudinal surface of the semiconductor channel (59, 60) between the source region (28) and the drain region (68), the second longitudinal surface being the first longitudinal surface. Located on opposite sides of the surface, each of the word lines 46 has a respective ferroelectric material portion (which is a portion of the ferroelectric material layer 54) and a respective interlayer dielectric portion (which is a portion of a respective interlayer dielectric layer 56). is spaced from the second longitudinal surface by

In one embodiment, the interlayer dielectric portions within each of the at least one ferroelectric memory string include portions of an interlayer dielectric layer 56 extending across each of the word lines 46 .

In one embodiment, the source region 28 is located in an upper portion of the substrate semiconductor layer 9 underlying the word lines 46, the first longitudinal surface and the second longitudinal surface having the substrate semiconductor layer 9 ) is perpendicular to the upper surface of

In one embodiment, each of the word lines 46 is located at the same vertical distance from the top surface of the substrate semiconductor layer 9 as a respective one of the pass gate electrodes 36 in each ferroelectric memory string. In one embodiment, each of the word lines 46 has the same material composition and the same thickness as a respective one of the pass gate electrodes 36 .

In one embodiment, the gate dielectric layer 52, semiconductor channel 60, ferroelectric material portions 54, and interlayer dielectric portions 56 in each ferroelectric memory string are arranged along the length of the semiconductor channel 60. (ie vertical direction) and parallel to the first longitudinal surface and the second longitudinal surface (eg first horizontal direction hd1).

In one embodiment, the semiconductor channel 60 within each ferroelectric memory string has a hollow rectangular horizontal cross-sectional shape with an outer rectangular perimeter and an inner rectangular perimeter (eg, as shown in FIG. 13B).

In one embodiment, the at least one ferroelectric memory string comprises at least one row of ferroelectric memory strings spaced laterally along a first horizontal direction hd1; each of the word lines 46 extends laterally along the first horizontal direction hd1 and is shared between each row of ferroelectric memory strings; Each of the pass gate electrodes 36 extends laterally along the first horizontal direction hd1 and is shared between each row of ferroelectric memory strings.

In one embodiment, a memory device comprises a two-dimensional array of ferroelectric memory strings comprising a plurality of rows of ferroelectric memory strings spaced laterally along a second horizontal direction (hd2) perpendicular to a first horizontal direction (hd1). include

Third exemplary structures of various configurations of the third embodiment may be derived from the second exemplary structure of the second embodiment. 14A-14D, 15A-15B, and 16A-16C show various configurations of a third exemplary structure of a third embodiment that may be derived from a second exemplary structure of the second embodiment.

Referring to FIGS. 14A-14D , a first configuration of a third exemplary structure according to a third embodiment of the present disclosure is shown, which is instead of separate ferroelectric material layers 54 illustrated in the second embodiment. It includes a three-dimensional array of ferroelectric memory portions (154). The individual ferroelectric memory portions 154 include the same ferroelectric material as the ferroelectric material layers 54 . Individual ferroelectric memory portions 154 are located in lateral recesses between adjacent insulating strips 32 adjacent to word lines 46 . Individual ferroelectric memory portions 154 located adjacent to the same vertical semiconductor channel 60 are vertically separated from each other by a respective one of the insulating strips 32 .

Optionally, a blocking dielectric portion 157 is positioned between each word line 46 and the adjacent individual ferroelectric memory portion 154. The blocking dielectric portion 157 may be located in the same lateral recesses as the adjacent discrete ferroelectric memory portion 154 . Blocking dielectric portion 157 may include any suitable electrically insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or dielectric metal oxide, such as aluminum oxide.

The first configuration of the third exemplary structure also includes dielectric pillar structures 364 that may be wider in the first horizontal direction hd1 than the dielectric pillar structures 64 of the second exemplary structure. In one embodiment, each of the dielectric pillar structures 364 may have a respective rectangular horizontal cross-sectional shape. The vertical semiconductor channels 60 of the first configuration of the third exemplary structure, rather than the hollow rectangular shape of the second exemplary structure shown in FIG. 13D , as shown in FIGS. hd1) and has a strip shape extending in length.

The laterally alternating sequence of memory pillar structures 52, 60, 62, 68, 56, 154, 157 and dielectric pillar structures 364 are within each line trench extending in the first horizontal direction hd1. can be located A two-dimensional array of memory pillar structures 52, 60, 62, 68, 56, 154, 157 comprising a three-dimensional array of individual ferroelectric memory portions 154 may be provided.

Referring to FIGS. 15A and 15B , a second configuration of a third exemplary structure is shown, which may be derived from the first configuration of the third exemplary structure. In the second configuration, the insulating strips 32 of the first configuration are replaced with cavity-containing insulating strips 332 . The cavity-containing insulating strips 332 may include a cavity 333 (ie, an air gap) surrounded by a dielectric material of the cavity-containing insulating strips 332, such as silicon oxide.

Cavity-containing insulating strips 332 may be formed by selectively removing insulating strips 32 before or after forming word lines 46 to form lateral recesses. A layer of dielectric material may be deposited by a non-conformal deposition process (eg, plasma enhanced chemical vapor deposition) in the lateral recesses to form the cavity-containing insulating strips 332 . The dielectric material may include, for example, porous or non-porous organosilicate glass or silicate glass. Each of the cavity-containing insulating strips 332 may include a respective sealed cavity 333 (eg, an air gap) free of any solid-state material and portions of the encapsulating insulating material. Each sealed cavity may be filled with an inert gas or air. Each portion of encapsulating insulating material includes a closed inner surface defining a cavity encapsulated therein.

In general, the layout of dielectric pillar structures 364 may be selected to facilitate electrical wiring of various metal interconnect structures to be formed subsequently. For example, each of the drain regions 68 may be contacted by a respective drain contact via structure 88 (shown in FIG. 13C). Bit lines 98 (shown in FIG. 13C ) extending laterally along the second horizontal direction hd2 may be formed on respective subsets of the drain contact via structures 88 . The dielectric pillar structures 364 in the neighboring line trenches 49 are aligned in rows in the second horizontal direction hd2, as shown in FIGS. 13B and 13D, 14B and 14D, and 15B. It can be.

Referring to FIGS. 16A and 16B , a third configuration of a third exemplary structure may be derived from the second configuration by staggering dielectric pillar structures 364 along a second horizontal direction hd2. can In this case, neighboring rows of dielectric pillar structures 364 may be laterally offset along the first horizontal direction by p/N, where p is the dielectric pillar structure located within the respective line trench 49. is the pitch (ie, center-to-center distance between neighboring pairs) of the dielectric pillar structures 364 of each row of fields 364, where N is an integer greater than one. N can be, for example, 2, 3, 4, 5, etc. The lateral offset of drain regions 68 facilitates wiring of drain contact via structures to the bit lines.

Referring to FIGS. 14A-16B , and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided, comprising insulating strips 32 or 332 positioned over a substrate 9 . ) and vertically alternating stacks 31, 33 of electrically conductive strips 46, 36, 44, 66 - the vertically alternating stacks laterally extending along a first horizontal direction hd1, line laterally spaced from one another along the second horizontal direction hd2 by trenches 49; and laterally alternating sequences of memory pillar structures 157, 154, 56, 60, 62, 68, 52 and dielectric pillar structures 364, located within line trenches 49 - the memory pillar structure. Each of the s 157, 154, 56, 60, 62, 68, 52 contacts the substrate 9, 28 and extends in a horizontal plane that includes the top surfaces of the vertically alternating stacks 31, 33. including a vertical semiconductor channel 60; A gate dielectric layer ( 52); an interlayer dielectric layer 56 in contact with the second sidewall of the vertical semiconductor channel 60 and the electrically conductive strips 46, 44 in the second vertically alternating stack 31, and an interlayer dielectric layer 56; It comprises a vertical stack of individual ferroelectric material portions 154 positioned between electrically conductive strips 46, 44 of two vertically alternating stacks 31. Electrically conductive strips 46 , 36 , 44 , 66 may or may not include drain-side control gate electrodes 44 and/or drain-side select gate electrodes 66 .

In one embodiment, the vertical semiconductor channel 60 includes a first vertically extending portion including a first sidewall; a second vertically extending portion including a second sidewall; and a horizontal portion adjacent to the bottom end of the first vertically extending portion and the bottom end of the second vertically extending portion.

In one embodiment, a rectangular dielectric core 62 is located between the first and second vertically extending portions and overlies the horizontal portion of the vertical semiconductor channel 60 and each of the dielectric pillar structures 364 comes into contact with a pair of

In one embodiment, the vertical semiconductor channel 60 includes a semiconductor material having a doping of a first conductivity type and the drain region 68 including a semiconductor material having a doping of a second conductivity type is a vertical semiconductor channel 60 ) in contact with the upper end of In one embodiment, substrate 9 includes a source region 28 electrically connected to vertical semiconductor channel 60 .

In one embodiment, the three-dimensional memory device comprises blocking dielectric portions positioned between a vertical stack of individual ferroelectric material portions 154 and electrically conductive strips 46, 44 of a second vertically alternating stack 31. (157).

In one embodiment, each of the blocking dielectric portions 157 is flush with and in contact with a respective one of the electrically conductive strips 46, 44 of the second vertically alternating stack 31. In one embodiment, each of the blocking dielectric portions 157 is in contact with and has the same height and the same width as a respective one of the individual ferroelectric material portions 154 in the vertical stack of individual ferroelectric material portions 154. .

In one embodiment, vertical semiconductor channel 60, gate dielectric layer 52, interlayer dielectric layer 56, and individual ferroelectric The vertical stack of material portions 154 has a uniform width along the first horizontal direction hd1.

In one embodiment, a subset of insulating strips 332 includes a respective cavity 333 therein, and each cavity is free of any solid phase material.

The fourth exemplary structures in various configurations of the fourth embodiment may be derived from the second and third exemplary structures of the second and third embodiments. 17A to 17C, 18A to 18C, 19A and 19B, and 20 are exemplary examples of a fourth embodiment that can be derived from second and third exemplary structures of the second and third embodiments. Various configurations of the fourth structure are shown.

Referring to FIGS. 17A-17C , a first configuration of a fourth exemplary structure according to a fourth embodiment of the present disclosure is shown, comprising ferroelectric material layers 54 of the second embodiment, and ferroelectric material layers 54 of the third embodiment. Instead of individual ferroelectric memory portions 154, it includes dummy individual ferroelectric memory portions 254. The dummy discrete ferroelectric memory portions 254 of the fourth embodiment are located at a vertical level adjacent to the insulating strips 32 between the vertical levels of the pass gate electrodes 36 . In other words, the dummy individual ferroelectric memory portion 254 is formed in a first horizontal plane corresponding to the top surface of the underlying nearest pass gate electrode 36 and the bottom surface of the overlying nearest pass gate electrode 36. It is located between corresponding second horizontal planes. Thus, the pass gate electrodes 36 are located at different distances from the substrate 9 than the dummy discrete ferroelectric memory portions 254 . In other words, the dummy discrete ferroelectric memory portions 254 are located adjacent to the pass gate type stacks 33 and are not intended to store data (eg, 1 or 0). In contrast, ferroelectric material layers 54 are positioned adjacent word line type stacks 31, and portions of ferroelectric material layers 54 positioned adjacent word lines 46 are data (e.g., 1 or 0) function as memory cells used to store.

The dummy individual ferroelectric memory portions 254 of the fourth embodiment are positioned at the same vertical level as the respective insulating strips 32 and the dummy spacer dielectric layers 51 and laterally therebetween. The dummy spacer dielectric layers 51 are positioned at the same vertical level as the respective dummy discrete ferroelectric memory portions 254 and the vertical semiconductor channel 60 and laterally therebetween. In other words, the dummy individual ferroelectric memory portion 254, its laterally adjacent insulating strip 32 and its laterally adjacent dummy dielectric 51 are formed on the upper surface of the underlying nearest pass gate electrode 36. It is located between a corresponding first horizontal plane and a second horizontal plane corresponding to the bottom surface of the overlying nearest pass gate electrode 36 .

Also, in the fourth embodiment, the dielectric pillar structures 64 and 364 of the second and third embodiments may be omitted if desired. Instead, a dielectric trench filling structure 76 may be formed in the trenches extending through the pass gate type stacks 33 . The dielectric trench filling structures 76 continuously extend in the first horizontal direction hd1 and laterally separate the pass gate electrodes 36 .

Referring to FIGS. 18A and 18B , the second configuration of the exemplary fourth structure has each dummy individual ferroelectric memory portion 254 further from the overlying and underlying pass gate electrodes 36 than in the first configuration. A fourth exemplary structure can be derived from the first configuration by reducing the vertical height of the dummy individual ferroelectric memory portions 254 to be vertically spaced apart. For example, each dummy individual ferroelectric memory portion 254 is provided with overlying and underlying pass gate electrodes by respective overlying and underlying protruding portions 32P of insulating strips 32 . (36) further vertically spaced. The protruding portions 32P protrude horizontally (ie, in a lateral direction) from each insulating strip 31 . The respective overlying and underlying protruding portions 32P of the insulating strips 32 overlie and underlie the respective dummy individual ferroelectric memory portion 254 in a vertical direction perpendicular to the substrate 9.

Referring to FIG. 18C , a third configuration of the fourth exemplary structure is obtained by increasing the vertical height of the pass gate electrodes 36 in regions overlying and underlying the reduced height dummy individual ferroelectric memory portions 254 . It can be derived from the second configuration of the fourth exemplary structure. For example, each pass gate electrode 36 includes upper and lower protruding portions 36P. The respective upper and lower protruding portions 36P of the pass gate electrodes overlie and underlie their respective adjacent dummy individual ferroelectric memory portions 254 in a vertical direction perpendicular to the substrate 9 . The protruding portions 36P protrude vertically from the pass gate electrode 36 . Accordingly, each dummy individual ferroelectric memory portion 254 has, in a vertical direction perpendicular to the substrate 9, an overlying protruding portion 36P of an underlying pass gate electrode 36 and an overlying pass gate The electrodes 36 are positioned between the respective underlying projecting portions 36P.

Referring to FIGS. 19A and 19B , a fourth configuration of a fourth exemplary structure may include first insulating strips 32 in a word line type stack 31 of a first, second, or third configuration. The first, second or second configuration of the fourth exemplary structure by replacing with insulating strips 332 containing cavities including cavities (i.e., air gaps) 333 between word lines 46 in (31). 3 configuration can be derived.

Referring to FIG. 20 , the fifth configuration of the exemplary fourth structure, in addition to forming cavities 333 within the word line type stack 31 , the second configuration within the pass gate type stack 33 of the fourth configuration The insulating strips 32 are also replaced by insulating strips 332 containing a cavity 333 (i.e., an air gap) between the pass gate electrodes 36 of the pass gate type stack 33. 4 can be derived from the configuration.

17A-20, and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided, which is a word positioned over first insulating strips 32 or 332 and a substrate 9. a first vertically alternating stack 31 of first electrically conductive strips comprising lines 46, the first vertically alternating stack 31 extending laterally along a first horizontal direction hd1; ; a second vertically alternating stack 33 of second electrically conductive strips comprising second insulating strips 32 or 332 and pass gate electrodes 36 located above the substrate 9 - the second vertically alternating a stack (33) extending laterally along a first horizontal direction (hd1) and spaced laterally from the first alternating stack (31) along a second horizontal direction (hd2); and line trench filling structures (254, 51, 60, 62, 68, 56, 54) positioned between the first vertically alternating stack (31) and the second vertically alternating stack (33), and adjacent pass gates. and a memory structure assembly comprising a combination of portions of a gate dielectric layer (52) positioned between electrodes (36) and line trench filling structures (254, 51, 60, 62, 68, 56, 54). The memory structure assembly 254, 51, 60, 62, 68, 56, 54, 52 includes first insulating strips 32 or 332, respectively, and first electrically conductive strips (i.e., word lines 46). a first layer of ferroelectric material (54) in contact with the sidewalls of; dummy second ferroelectric material portions 254 positioned over the sidewalls of the second vertically alternating stack 33; and a vertical semiconductor channel 60 positioned between the first layer of ferroelectric material (ie, layer 54 of ferroelectric material) and the dummy ferroelectric material portions 254 . The semiconductor channel 60 extends vertically from the substrate 9 to a horizontal plane comprising the top surfaces of the first vertically alternating stack 31 and the second vertically alternating stack 33 .

In one embodiment, the three-dimensional memory device includes a first ferroelectric material layer (ie, ferroelectric material layer 54) and an interlayer dielectric layer 56 in contact with the first outer sidewall of the vertical semiconductor channel 60.

In one embodiment, the spacer dielectric layer 51 contacts the second outer sidewall of the vertical semiconductor channel 60 . In one embodiment, spacer dielectric layer 51 may have the same composition and same thickness as interlevel dielectric layer 56 . In one embodiment, the vertical semiconductor channel 60 comprises a first vertically extending portion comprising a first outer sidewall, a second vertically extending portion comprising a second outer sidewall, and a bottom end and second vertically extending portion of the first vertically extending portion. It includes a horizontal part connecting the bottom end of the vertically extending part and contacting the upper surface of the substrate 9 .

In one embodiment, a subset of the first insulating strips 32 or 332 and the second insulating strips 32 or 332 include a respective cavity 333 therein. Each cavity is free of any solid phase material.

21A is a schematic circuit diagram of first, second, third, and fourth exemplary structures of the present disclosure. Each pass gate electrode PL (corresponding to the pass gate electrode 36 of the aforementioned devices) of the pass gate field effect transistor (represented by NFET in FIG. 21A) is connected to the word line WL (word line 46 of the aforementioned devices). (corresponding to )) provides a parallel gated conductive path to each vertical ferroelectric-memory element-controlled transistor (FeFET) controlled by The respective NFETs and FeFETs share a common semiconductor channel 60, 160 and are electrically connected in parallel between a common source line SL (eg 28) and a common bit line BL (eg 98). In one embodiment, a plurality of FeFETs electrically connected in series between a source line (SL) (eg, 28) and a bit line (eg, 98), a common semiconductor channel (60, 160) and a common drain side and source-side select gate transistors SGD, SGS (including respective drain-side and source select gate electrodes 26, 66), which also have the same source line SL as a plurality of FeFETs. It is shared with a plurality of pass gate transistors (NFETs) connected in series between the bit lines (BL). Although pass gate transistors are shown as NFETs, these transistors may alternatively include PFETs, if desired.

A plurality of series connected FeFETs form a NAND string comprising a series connection of field effect transistors with variable threshold voltages controlled by the polarization of a respective portion of ferroelectric material adjacent to a respective word line (WL). A first end of each NAND string (eg, the bottom end of each vertical NAND string) is connected to a source line SL, which may include a source region 28 in the devices described above. The second end of each NAND string (eg, the upper end of each vertical NAND string) is connected to bit line BL (eg, 98). Optionally, source-side select gate electrodes 26 and drain-side select gate electrodes 66 may be provided.

21B and 21C are tables showing example voltages that may be used to operate the circuit of FIG. 21A. 21B shows example voltages that can be used to operate a single level cell in a channel boosting scheme (columns 2, 3 and 4) and in a direct channel potential control scheme (columns 5, 6 and 7). 21C shows example voltages used to operate a multi-level cell in a channel boosting scheme (columns 2, 3 and 4) and in a direct channel potential control scheme (columns 5, 6 and 7). The voltages shown are exemplary and other suitable voltages may be used for different device dimensions and materials.

As shown in these tables, the selected word line 46 (i.e., the word line of the selected memory cell) is at a high negative voltage for write/inhibit, at a high positive voltage for erase/inhibit, and at a high positive voltage for read/inhibit. is set to 0V or a lower positive/negative voltage. Unselected word lines are floating for write and erase and set to 0V for read/inhibit. The selected pass gate electrode 36 (i.e., the pass gate electrode adjacent to the selected memory cell) is set to a pass voltage for write and erase, and set to 0V for read/inhibit. Unselected pass gate electrodes are set to pass voltage for write and erase, and set to read voltage for read/inhibit. The bit lines are set to 0V/positive voltage for write/inhibit and erase/inhibit for channel boosting scheme, Vdd for read/inhibit, and Vdd for write/inhibit for direct channel potential control scheme. Set to 0V/negative voltage, set to 0V/positive voltage for erase/inhibit, and set to Vdd for read/inhibit. The source lines are set to a positive voltage for write/inhibit and erase/inhibit and to 0V for read/inhibit. The SGD and SGS select transistors are set up as shown in the tables. Action units are per page of the device.

Various configurations of the illustrative structure provide memory devices that include at least one ferroelectric memory string that includes word lines and pass gate electrodes. In other words, word lines 46 and ferroelectric memory elements (i.e. ferroelectric material portions 54, 154) are located on at least one side of semiconductor channel 60, pass gate electrodes 36 and Gate dielectric 52 is located on at least one other side of semiconductor channel 60 .

Pass gate transistors that include pass gate electrodes 36 but do not have ferroelectric memory elements (i.e., ferroelectric material portions 54, 154) can be used between adjacent memory cells (i.e., between adjacent FeFETs) in the same memory string. ) reduce or eliminate the disturbance.

Referring to all drawings and embodiments of the present disclosure, a memory device includes semiconductor channels 60 and 160 extending between a source region 28 and a drain region 68, a plurality of pass gate electrodes 36 , the plurality of word lines 46, the gate dielectric 52 located between the semiconductor channels 60 and 160 and the plurality of pass gate electrodes 36, and between the semiconductor channel and the plurality of word lines 46 ferroelectric material portions (54, 154) located on the

In one embodiment, the gate dielectric 52 includes a gate dielectric layer located on the first longitudinal surface of the semiconductor channel 60, 160, and the pass gate electrodes 36 are interposed between the source and drain regions. located on the gate dielectric layer of the first row, the word lines 46 being located over a second longitudinal surface of the semiconductor channel of the second row between the source region 28 and the drain region 68, the second The longitudinal surface is located on the opposite side of the first longitudinal surface of the semiconductor channel 60, 160, each of the word lines 46 having a respective ferroelectric material portion 54, 154 and a respective interlayer dielectric portion It is spaced from the second longitudinal surface by one of (56).

In one embodiment, interlevel dielectric portions 56 include portions of an interlevel dielectric layer positioned between ferroelectric material portions 54 and 154 and the second longitudinal surface of the semiconductor channel. In one embodiment, ferroelectric material portions 54, 154 are located over the second longitudinal surface of the semiconductor channel 60, 160 extending from the region overlying the source region 28 to the region overlying the drain region 68. parts of the ferroelectric material layer 54 In another embodiment, ferroelectric material portions 54 and 154 include individual ferroelectric material portions 154 spaced apart by interposing dielectric material portions 32 and 142 . In one embodiment, the ferroelectric material portions 54, 154 comprise orthorhombic phase hafnium oxide comprising at least one dopant selected from at least one of Al, Zr or Si.

In the first embodiment shown in Figures 1 to 4b, the semiconductor channel 160 extends horizontally over the layer of insulating material 10 having a horizontal top surface, the first longitudinal surface of the semiconductor channel and the second longitudinal surface thereof. The surface is parallel to the horizontal upper surface of the insulating material layer 10 .

In the second embodiment shown in FIGS. 5A to 13D , the semiconductor channel 60 extends vertically above the substrate 9 with a horizontal upper surface, the first longitudinal surface of the semiconductor channel 60 and the second length. The directional surface is perpendicular to the horizontal upper surface of the substrate 9 .

In one embodiment, source region 28 is located in the upper portion of substrate 9 underlying word lines 46, each of which word lines 46 pass a gate electrode from the upper surface of substrate 9. Located at the same vertical distance as a respective one of the s 36 , each of the word lines 46 has the same material composition and the same thickness as a respective one of the pass gate electrodes 36 .

In one embodiment, word lines 46 are separated from each other by respective first insulating strips 32, 332 in word line type stack 31, and pass gate electrodes 36 are pass gate type stack They are separated from each other by respective second insulating strips 32, 332 in 33.

In one embodiment, the semiconductor channel 60 has a hollow rectangular horizontal cross-sectional shape with an outer rectangular perimeter and an inner rectangular perimeter. Ferroelectric material portions (54, 154) are located in a plurality of rows of ferroelectric memory strings spaced laterally along a first horizontal direction (hd1) and extending in a second horizontal direction (hd2) perpendicular to the first horizontal direction. Each of the word lines 46 extends laterally along the first horizontal direction and is shared among a plurality of rows of ferroelectric memory strings, and each of the pass gate electrodes 36 extends laterally along the first horizontal direction. and is shared among a plurality of rows of ferroelectric memory strings.

In the second, third and fourth embodiments, the three-dimensional memory device is a word line type stack of alternating first insulating strips 32, 332 and word lines 46 positioned over a substrate 9. 31, pass gate type stack 33 of alternating second insulating strips 32, 332 and pass gate electrodes 36, pass gate type stack 33 and word A vertical semiconductor channel 60 located between the line type stack 31, a gate dielectric 52 located between the vertical semiconductor channel 60 and the pass gate type stack 33, and a vertical semiconductor channel 60 and word and ferroelectric material portions (54, 154) positioned between the line type stack (31).

In the third embodiment shown in FIGS. 14A-16B , ferroelectric material portions 54 and 154 are provided within lateral recesses adjacent to word lines 46 and between adjacent first insulating strips 32 . The individual ferroelectric memory parts 154 are vertically separated from each other by a respective one of the first insulating strips 32 .

In one embodiment, the device further includes an interlevel dielectric layer 56 in contact with the second sidewall of the vertical semiconductor channel 60 and in contact with the individual ferroelectric memory portions 154, wherein the gate dielectric layer 52 is in the vertical It contacts the first sidewall of the semiconductor channel 60 and contacts the pass gate type stack 33 .

In one embodiment, the vertical semiconductor channel 60 comprises a first vertically extending portion comprising a first sidewall, a second vertically extending portion comprising a second sidewall, and a bottom end and second vertically extending portion of the first vertically extending portion. It includes a horizontal portion adjacent to the bottom end of the portion.

In one embodiment, the device is positioned between the pair of dielectric pillar structures 364 and the first and second vertically extending portions of the vertical semiconductor channel 60 and over the horizontal portion of the vertical semiconductor channel 60. and a rectangular dielectric core 62 overlying and in contact with the pair of dielectric pillar structures 364 .

In one embodiment, the vertical semiconductor channel 60 includes a semiconductor material having a doping of a first conductivity type and the drain region 68 comprising a semiconductor material having a doping of a second conductivity type is at the top of the vertical semiconductor channel. make contact with the end Substrate 9 includes a source region 28 electrically connected to a vertical semiconductor channel 60 .

In one embodiment, blocking dielectric portions 157 are located in the lateral recesses between the individual ferroelectric material portions 154 and the word lines 46 . Each of the blocking dielectric portions 157 is in contact with and has the same height as a respective one of the word lines 46 . Each of the blocking dielectric portions 157 is in contact with and has the same height and the same width as a respective one of the individual ferroelectric material portions 154 . In one embodiment shown in FIG. 15A, the first and second insulating strips 332 include a respective cavity 333 therein, and each cavity is free of any solid-state material.

In the fourth embodiment shown in FIGS. 17A-20, ferroelectric material portions 54 and 154 are portions of ferroelectric material layer 54 located between vertical semiconductor channel 60 and word line type stack 31. include them Dummy individual ferroelectric memory portions 254 are formed between the vertical semiconductor channel 60 and the pass gate electrodes 36, between the vertical levels of the pass gate electrodes 36, the second insulating strips 32, 332 It is located on a vertical level adjacent to. The pass gate electrodes 36 are located at different distances from the substrate 9 than the dummy discrete ferroelectric memory portions 254 .

In one embodiment shown in FIGS. 18A and 18B , each dummy individual ferroelectric memory portion 254 is formed by respective overlying and underlying protruding portions 32P of second insulating strips 32 . , spaced vertically from the overlying and underlying pass gate electrodes 36 .

In another embodiment shown in FIG. 18C, each pass gate electrode 36 includes upper and lower protruding portions 36P. The upper and lower protruding portions 36P of the pass gate electrodes 36 overlie and underlie their respective adjacent dummy individual ferroelectric memory portions 254 in a vertical direction perpendicular to the substrate 9 . Each dummy individual ferroelectric memory portion 254 is formed between its respective overlying protruding portion of an underlying pass gate electrode and its underlying protruding portion of an overlying pass gate electrode, in a vertical direction perpendicular to the substrate 9. is located in

In one embodiment shown in FIG. 20 , the first insulating strips and the second insulating strips 332 include a respective cavity 333 therein, and each cavity is free of any solid-state material.

While the foregoing refers to certain preferred embodiments, it will be understood that the present disclosure is not so limited. It will occur to those skilled in the art that various modifications can be made to the disclosed embodiments and that such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed between all embodiments, not alternatives to each other. The word “comprise” or “include” means, unless expressly stated otherwise, that the word “consist essentially of” or the word “consist of” replaces the word “comprise”. All embodiments are considered. Where an embodiment using a particular structure and/or configuration is shown in this disclosure, this disclosure does not cover any other compatible structures that are functionally equivalent, unless such substitution is expressly prohibited or otherwise known to those skilled in the art to be impossible. and/or configurations. All publications, patent applications and patents cited herein are hereby incorporated by reference in their entirety.

Claims (20)

As a three-dimensional memory device,
a word line type stack of alternating first insulating strips and word lines positioned over a substrate;
a pass gate type stack of alternating second insulating strips and pass gate electrodes positioned over the substrate;
a vertical semiconductor channel positioned between the pass gate type stack and the word line type stack;
a gate dielectric positioned between the vertical semiconductor channel and the pass gate type stack; and
and portions of ferroelectric material positioned between the vertical semiconductor channel and the word line type stack. According to claim 1,
said ferroelectric material portions comprising individual ferroelectric material portions positioned within lateral recesses adjacent to said word lines and between adjacent first insulating strips;
wherein the individual ferroelectric memory portions are vertically separated from each other by a respective one of the first insulating strips. According to claim 2,
and an interlayer dielectric layer in contact with the second sidewall of the vertical semiconductor channel and in contact with the individual ferroelectric memory portions, wherein the gate dielectric layer contacts the first sidewall in the vertical semiconductor channel and in contact with the pass gate type stack. Contact, three-dimensional memory device. According to claim 3,
The vertical semiconductor channel,
a first vertically extending portion including the first sidewall;
a second vertically extending portion including the second sidewall; and
and a horizontal portion adjacent to a bottom end of the first vertically extending portion and a bottom end of the second vertically extending portion. According to claim 4,
a pair of dielectric pillar structures; and
a rectangular dielectric core positioned between the first vertically extending portion and the second vertically extending portion of the vertical semiconductor channel, overlying the horizontal portion of the vertical semiconductor channel, and in contact with the pair of dielectric pillar structures; , a three-dimensional memory device. According to claim 4,
said vertical semiconductor channel comprising a semiconductor material having a doping of a first conductivity type;
wherein a drain region comprising a semiconductor material having a doping of a second conductivity type contacts an upper end of the vertical semiconductor channel. 7. The device of claim 6, wherein the substrate includes a source region electrically connected to the vertical semiconductor channel. 3. The device of claim 2, further comprising blocking dielectric portions positioned within the lateral recesses between the individual ferroelectric material portions and the word lines. 9. The three-dimensional memory device of claim 8, wherein each of the blocking dielectric portions is in contact with and has the same height as a respective one of the word lines. 9. The device of claim 8, wherein each of the blocking dielectric portions is in contact with and has the same height and the same width as a respective one of the individual ferroelectric material portions. 3. The device of claim 2, wherein the first insulating strips and the second insulating strips include a respective cavity therein, each cavity being free of any solid-state material. 3. The device of claim 1, wherein portions of ferroelectric material include portions of a layer of ferroelectric material positioned between the vertical semiconductor channel and the word line type stack. 13. The method of claim 12, further comprising dummy discrete ferroelectric memory portions positioned between the vertical semiconductor channel and the pass gate electrodes at a vertical level adjacent to the second insulating strips between the vertical levels of the pass gate electrodes. , a three-dimensional memory device. 14. The device of claim 13, wherein the pass gate electrodes are located at different distances from the substrate than the dummy individual ferroelectric memory portions. 14. The method of claim 13, wherein each dummy individual ferroelectric memory portion is vertically spaced from the overlying and underlying pass gate electrodes by overlying and underlying protruding portions of each of the second insulating strips. , a three-dimensional memory device. 14. The three-dimensional memory device of claim 13, wherein each pass gate electrode includes upper and lower protruding portions. 17. The device of claim 16, wherein the upper and lower protruding portions of the pass gate electrodes overlie and underlie respective adjacent dummy individual ferroelectric memory portions in the vertical direction perpendicular to the substrate. 18. The method of claim 17, wherein each dummy individual ferroelectric memory portion comprises, in a vertical direction perpendicular to the substrate, a protruding portion overlying each of an underlying pass gate electrode and a protruding portion underlying an overlying pass gate electrode. A three-dimensional memory device, located between. 13. The device of claim 12, wherein the first insulating strips and the second insulating strips include a respective cavity therein, each cavity being free of any solid-state material. 2. The three-dimensional memory device of claim 1, wherein the ferroelectric material portions comprise orthorhombic phase hafnium oxide comprising at least one dopant selected from at least one of Al, Zr or Si.

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