KR20230072320A - Display devece and the method of manufacturing of the same - Google Patents

Abstract

According to an embodiment of the present invention, a display device comprises: a substrate; a buffer layer positioned on the substrate; an active layer positioned on the buffer layer and including a channel region, a source region positioned between the channel regions, and a drain region; a gate electrode positioned on the active layer; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region. The source region includes a source contact hole penetrating the source region and a first source conductive region and a second source conductive region surrounding the source contact hole. The drain region includes a drain contact hole penetrating the drain region and a first drain conductive region and a second drain conductive region surrounding the drain contact hole. The present invention can improve an aperture ratio.

Description

Display device and its manufacturing method {DISPLAY DEVECE AND THE METHOD OF MANUFACTURING OF THE SAME}

The present specification relates to a display device capable of improving an aperture ratio and a manufacturing method thereof.

Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. To this end, research to develop thinning, lightening, and low power consumption of display devices is being continued.

The display device includes a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an electro-wetting display device. : EWD) or an organic light emitting display device (OLED).

Among them, the organic light emitting display device OLED includes a plurality of pixel areas arranged in a display area where images are displayed and a plurality of organic light emitting elements corresponding to the plurality of pixel areas. Since the organic light emitting device is a self-emitting device that emits light by itself, the organic light emitting display device has advantages in that it has a fast response speed, high luminous efficiency, luminance and viewing angle, and excellent contrast ratio and color gamut compared to liquid crystal display devices.

An organic light emitting display device includes a light emitting unit and a circuit unit for driving the light emitting unit. The circuit unit includes a thin film transistor and a storage capacitor. When such an organic light emitting display device is a bottom emission method in which light generated from the light emitting layer is emitted in the opposite direction of the substrate, that is, toward the back surface of the substrate, the area where the circuit unit is disposed does not emit light to the outside. . Accordingly, there is a problem in that the aperture ratio decreases by the area where the circuit unit is disposed.

An object to be solved according to embodiments of the present specification is to provide a display device capable of improving an aperture ratio by increasing an area of a light emitting region in a bottom emission type organic light emitting display device.

To this end, the invention according to the embodiments of the present specification is to provide an organic light emitting display device capable of increasing the total capacitance of the storage capacitor while increasing the area of the light emitting region by reducing the area occupied by the storage capacitor.

Another object of the present invention is to increase the capacitance of the storage capacitor by improving the structure of a dielectric constituting the storage capacitor.

In addition, an object of the invention according to the embodiments of the present specification is to increase the lifespan of an organic light emitting device by reducing the current consumption for implementing the same luminance in individual pixels by increasing the area of the light emitting region.

In addition, an object of the invention according to an embodiment of the present specification is to promote contact connection stability by introducing a ring-shaped contact structure to connect a source electrode and a drain electrode and an active layer with a plane.

In addition, an object of the invention according to an embodiment of the present specification is to reduce the amount of loss in the active layer by introducing a photoresist pattern using a halftone mask.

Solving problems according to an embodiment of the present specification are not limited to the above-mentioned purposes, and other objects and advantages of the present invention not mentioned above can be understood by the following description, and can be more easily understood by the embodiments of the present specification. will be clearly understood. Further, it will be readily apparent that the objects and advantages of this specification may be realized by means of the instrumentalities and combinations indicated in the claims.

According to one embodiment of the present specification, a display device includes a substrate; a buffer layer positioned on the substrate; an active layer disposed on the buffer layer and including a channel region, a source region disposed with the channel region interposed therebetween, and a drain region; a gate electrode positioned on the active layer; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region. wherein the source region includes a source contact hole penetrating the source region, a first source conductor region and a second source conductor region surrounding the source contact hole, and the drain region comprises the drain region It is characterized in that it includes a drain contact hole penetrating, and a first drain conductor region and a second drain conductor region surrounding the drain contact hole.

Another example of the present invention is forming a buffer layer on a substrate; forming an active layer and a gate insulating film on the buffer layer; etching to form a source contact hole and a drain contact hole in the buffer layer through the gate insulating layer and the active layer; A source region and a drain region are formed on the active layer with a channel region interposed therebetween, the source region including a first source conductor region and a second source conductor region surrounding the source contact hole; , forming the drain region to include a first drain conductor region and a second drain conductor region surrounding the drain contact hole; and forming a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, and a gate electrode positioned on the active layer. do.

According to the exemplary embodiments of the present specification, an area occupied by a storage capacitor may be reduced to increase an area of a light emitting region, thereby improving an aperture ratio.

In addition, it is advantageous to increase capacitance of the storage capacitor by improving the structure of a dielectric constituting the storage capacitor while reducing the area occupied by the storage capacitor.

In addition, the reliability of the display device can be improved by increasing the lifetime of the organic light emitting device by reducing the current consumption for implementing the same luminance in individual pixels by increasing the area of the light emitting region.

In addition, by introducing a ring-shaped contact structure into the active layer and connecting the source electrode or drain electrode and the active layer face to face, there is an effect of stably connecting the active layer.

Effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1A is a plan view of a display device according to a first embodiment of the present specification.
FIG. 1B is a cross-sectional view cut along II', II-II', III-III', IV-IV', VV', and VI-VI' directions of FIG. 1A.
FIG. 2 is an enlarged view of a portion 'X' of FIG. 1A.
3A is a plan view of a display device according to a second exemplary embodiment of the present specification.
FIG. 3B is cross-sectional views cut along II', II-II', III-III', IV-IV', VV', and VI-VI' directions of FIG. 3A.
FIG. 3C is a plan view showing part X of FIG. 3A.
4 to 18 are cross-sectional views illustrating a method of manufacturing a display device according to a second exemplary embodiment of the present specification.

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments make the disclosure of this specification complete, and common knowledge in the art to which this specification belongs. It is provided to fully inform the owner of the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, so this specification is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, when a temporal precedence relationship is described as 'after', 'continue to', 'after ~', 'before', etc., 'immediately' or 'directly' As long as ' is not used, non-continuous cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Each feature of the various embodiments of the present specification can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in an association relationship. may be

Hereinafter, an organic light emitting display device according to each exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1A is a plan view of a display device according to a first embodiment of the present specification. FIG. 1B is a cross-sectional view taken along directions II', II-II', III-III', IV-IV', V-V', and VI-VI' of FIG. 1A. And FIG. 2 is a view showing part 'X' of FIG. 1A in a plan view.

Referring to FIGS. 1A, 1B, and 2 , the display device 10 according to the first embodiment of the present specification is a bottom emission type display device that emits light in a downward direction where a substrate 100 is disposed. . Such a display device 10 includes a light emitting region 194 in which an organic light emitting element emitting light is disposed, and a circuit unit provided with driving circuit elements for supplying driving current to the organic light emitting element. The light emitting area 194 and the driving circuit elements are arranged in a display area where a plurality of sub-pixels are arranged in a matrix form and an image is displayed. Each of the sub-pixels disposed in the display area includes a driving circuit element and an organic light emitting element disposed in the circuit unit.

The driving circuit element includes a thin film transistor T and a storage capacitor Cst. The driving circuit elements constituting the circuit unit are disposed in the area other than the light emitting area 194 .

The thin film transistor T includes a gate electrode 164 , a source electrode 166 , a drain electrode 168 and an active layer 125 .

The gate electrode 164 overlaps the channel region CH of the active layer 125 . A gate insulating layer 130 is disposed between the gate electrode 164 and the channel region CH of the active layer 125 . The gate electrode 164 is any one from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu). It may be a single layer or multiple layers made of one or an alloy thereof. The gate electrode 164, the source electrode 166, and the drain electrode 168 may have a structure in which a first gate metal 161 and a second gate metal 163 are stacked.

The active layer 125 includes a source region SA and a drain region DA facing each other with the channel region CH interposed therebetween. The channel region CH is disposed to overlap the gate electrode 164 with the gate insulating layer 130 interposed therebetween.

The source electrode 166 is electrically connected to the source region SA of the active layer 125 , and the drain electrode 168 is electrically connected to the drain region DA of the active layer 125 . The drain electrode 168 contacts and is electrically connected to the first electrode 186 through the pixel contact hole 184 formed through the planarization layer 182 and the interlayer insulating layer 176 . In addition, the drain electrode 168 may be electrically connected to the light blocking layer 105 through the light blocking contact hole 154 penetrating the first buffer layer 120 and the second buffer layer 122 . The source electrode 166 and the drain electrode 168 are made of the same material as the gate electrode 164 and are positioned on the same plane (layer) as the gate electrode 164 through an etching process using the same mask.

The active layer 125 includes at least one of amorphous silicon, polycrystalline silicon, and an oxide semiconductor. For example, the active layer 125 may include at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO).

Each of the source region SA and the drain region DA provided in the active layer 125 includes a first source conductor region 127 and a first drain conductor region 129 . The first source/drain conductor regions 127 and 129 are formed on exposed portions of the active layer 125 during dry etching to pattern the gate insulating layer 130 , respectively. Second source/drain conductor regions 126 and 128 are disposed between the first source/drain conductor regions 127 and 129 and the channel region CH of the active layer 125 . The second source/drain conductor regions 126 and 128 include the gate electrode 164, the source electrode 166, and the drain electrode 168 in a state where the first source/drain conductor regions 127 and 129 are formed, respectively. In the process of dry etching for patterning, it is formed on exposed portions of the first source/drain conductor regions 127 and 129 . In the second source/drain conductor regions 126 and 128, as thickness loss occurs in the active layer during the dry etching process, the initially formed active layer 125 and the first source/drain conductor regions 127 and 129 has a thickness lower than the surface of

Each of the source electrode 166 and the drain electrode 168 overlaps the first source/drain conductor regions 127 and 129 . Referring to FIG. 2 showing the X portion of FIG. 1A on a plan view, the source electrode 168 is disposed to overlap the first source conductor region 127 . Specifically, referring to an enlarged portion of the X1 region where the source electrode 168 overlaps the first source conducting region 127, the first source conducting region 127 and the second source conducting region 126 As a contact point (CP) occurs at the corner where the silver is in contact with each other, point contact rather than surface contact is made. And the current path (C _i ) is also made through this contact point (CP). In this case, since point contact is made instead of surface contact, connection with the source electrode 166 may be unstable. This may also occur in the drain electrode 168 in the same way.

A light blocking layer 105 is formed between the active layer 125 and the substrate 100 . The light blocking layer 105 is formed at a position overlapping the active layer 125 and overlaps at least the channel region CH of the active layer 125 . A surface of the light blocking layer 105 may be partially exposed through the light blocking contact hole 154 and electrically connected to the active layer 125 through the drain electrode 168 .

The light blocking layer 105 may be formed of the same material on the same plane as the storage lower electrode 110 and the wiring electrode 115 . Here, the wire electrode 115 includes a power supply line VDL, a data line DL, and a reference power supply line Vref, and is arranged in a first direction X, for example, a horizontal line. In one example, the light blocking layer 105 may have a structure in which a first metal layer 102 and a second metal layer 104 are stacked. In addition, the light blocking layer 105 may be formed of any one selected from the group of opaque metal materials such as molybdenum (Mo), aluminum (Al), titanium (Ti), or copper (Cu), or an alloy thereof.

The first buffer layer 120 and the second buffer layer 122 are disposed on the light blocking layer 105 , the storage lower electrode 110 , and the wiring electrode 115 . The first buffer layer 120 and the second buffer layer 122 block penetration of moisture or oxygen toward the organic light emitting device and protect the thin film transistor from impurities such as hydrogen.

The storage capacitor Cst is formed by overlapping the lower storage electrode 110 and the upper storage electrode 172 with the first buffer layer 120 and the second buffer layer 122 interposed therebetween. That is, between the lower storage electrode 110 and the upper storage electrode 172, the first buffer layer 120 and the second buffer layer 122 are stacked to form a multi-layer dielectric structure. In this case, the storage lower electrode 110 is made of the same material as the light blocking layer 105 , and the storage upper electrode 172 is made of the same material as the active layer 125 . When viewed cross-section on the second buffer layer 122, the storage upper electrode 172 has a plate shape.

As one of the methods for increasing the capacitance of the storage capacitor Cst, there is a method of shortening the distance between the storage lower electrode 110 and the storage upper electrode 172 . That is, as the thickness of the dielectric increases, the capacitance decreases in inverse proportion, and as the thickness of the dielectric decreases, the capacitance increases.

In the first embodiment of the present specification, a structure in which the first buffer layer 120 and the second buffer layer 122 are stacked as dielectrics is introduced. Here, the first buffer layer 120 is formed of silicon nitride (SiNx) having a first thickness, and the second buffer layer 122 is formed of silicon oxide (SiOx) having a second thickness thicker than the first buffer layer 120 . For example, the first buffer layer 120 is formed to a first thickness of 1000 Å to 1500 Å, and the second buffer layer 122 is formed to a second thickness of 2700 Å to 3300 Å.

Accordingly, since the dielectric constant of the first buffer layer 120 is about 6.9 and the dielectric constant of the second buffer layer 122 is about 3.9, the capacitance value of the storage capacitor Cst has a value that is 0.0011 * constant. When the area occupied by the storage capacitor Cst is increased to improve capacitance, there is a problem in that the aperture ratio decreases as the area of the light emitting region 194 decreases.

The pad electrode 174 is disposed on the same plane as the gate electrode 164 , the source electrode 166 , and the drain electrode 168 . The pad electrode 174 serves to supply driving signals to each of the gate electrode 164, the data line DL, the power supply line VDL, and the reference power supply line Vref. In the embodiment of the present specification, a configuration in which the pad electrode 174 is connected to the power supply line VDL has been presented as an example, but is not limited thereto. For example, a plurality of pad electrodes 174 may be configured to be connected to each of the data line DL and the reference power supply line Vref.

The pad electrode 174 is made of the same material as the gate electrode 164, the source electrode 166, and the drain electrode 168. A pad cover electrode 188 preventing corrosion of the pad electrode 174 is disposed on the pad electrode 174 .

In response to the power supply line (VDL), data line (DL), and reference power supply line (Vref) arranged in the first direction (X), which is a horizontal line, scan lines (SCAN1) in a second direction (Y), which is a vertical line, SCAN2) is placed. While the scan lines SCAN1 and SCAN2 supply data signals to the sub-pixels, the first scan line SCAN1 supplies scan signals for selecting each horizontal line and data signals supplied to the sub-pixels during initialization. and a second scan line (SCAN2) supplying a signal for selecting each horizontal line.

An interlayer insulating film 176 and a planarization film 182 are disposed on the substrate 100 on which the gate electrode 164 , the source electrode 166 , the drain electrode 168 , and the upper storage electrode 172 are formed. The interlayer insulating film 176 and the planarization film 182 are formed by selecting an inorganic insulating material or an organic insulating material.

A color filter 180 is disposed on the interlayer insulating layer 176 . The color filter 180 is disposed at a position overlapping the light emitting region 194 . The color filter 180 may represent a color assigned to each sub-pixel. For example, the color filter 180 may be one of red (R), green (G), and blue (B).

The planarization film 182 is formed to form a flat surface on the substrate 100, and may be made of acrylic resin or the like. The planarization layer 182 further includes a pixel contact hole 184 exposing a portion of the surface of the drain electrode 168 .

A first electrode 186 is disposed on the planarization layer 182 and the pixel contact hole 184 and electrically connected to the drain electrode 168 . The first electrode 186 is formed on the planarization layer 182 so as to overlap the driving circuit element including the light emitting region 194 formed by the bank hole 192 provided in the bank 190, the thin film transistor, and the storage capacitor Cst. is placed on The width EAW1 of the light emitting region 194 may be defined by the size of the bank hole 192 .

The first electrode 186 includes a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first electrode 186 may also be referred to as an anode electrode or a pixel electrode.

The organic light emitting layer 198 extends to the upper surface of the bank 190 while being connected to the first electrode 186 exposed by the bank hole 192 . The organic emission layer 198 has a stacked structure of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). The organic emission layer may further include a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL), and an electron injection layer (EIL). The organic light emitting layer 198 is made of an organic material that emits white light, and a color may be displayed by the color filter 180 .

A second electrode 199 is disposed on the organic light emitting layer 198 . Accordingly, an organic light emitting diode (OLED) composed of the first electrode 186 , the organic light emitting layer 198 and the second electrode 199 is formed. The second electrode 199 serves to apply a voltage by commonly contacting adjacent pixels on the display area, and may also be referred to as a common electrode or a cathode electrode.

As described above, in the first embodiment of the present specification, the first source/drain conductor regions 127 and 129 and the second source/drain conductors overlap each of the source electrode 166 and the drain electrode 168. Connection instability between the image regions 126 and 128 may occur. In addition, as a structure in which a double layer of the first buffer layer 120 and the second buffer layer 122 is introduced as a dielectric is introduced, there is a limit to improving the capacitance.

Accordingly, in another embodiment of the present specification, the contact area between the first source/drain conductor regions 127 and 129 and the second source/drain conductor regions 126 and 128 is increased so that the source electrode or the drain electrode A display device structure capable of securing connection stability between active layers and increasing capacitance while improving an aperture ratio by increasing an area of a light emitting region and a manufacturing method thereof will be described. It will be described with reference to the drawings below.

3A is a plan view of a display device according to a second exemplary embodiment of the present specification. FIG. 3B is cross-sectional views cut along II', II-II', III-III', IV-IV', V-V', and VI-VI' directions of FIG. 3A. And Figure 3c is a view showing the X portion of Figure 3a in a plane.

Referring to FIGS. 3A to 3C , the display device 20 according to the second exemplary embodiment of the present specification is a bottom emission type display device in which a light source emitted from the organic light emitting layer is emitted in a downward direction where the substrate 200 is disposed. . Such a display device 20 includes a light emitting region 294 in which an organic light emitting element emitting light is disposed, and a circuit unit provided with driving circuit elements for supplying driving current to the organic light emitting element. The light emitting area 294 and the driving circuit elements are arranged in a display area where a plurality of sub-pixels are arranged in a matrix form and an image is displayed. Each of the sub-pixels disposed in the display area includes a driving circuit element and an organic light emitting element disposed in the circuit unit.

The driving circuit element includes a thin film transistor T and a storage capacitor Cst. The driving circuit elements constituting the circuit unit are disposed in the area other than the light emitting area 294 .

The thin film transistor T may control light emission of the organic light emitting device by supplying and controlling driving current from the power supply line VDL to the light emitting device through a data signal supplied to the gate electrode 264 . Here, since the gate electrode 264 of the thin film transistor T is connected to the storage capacitor Cst, the thin film transistor T is turned on based on the charging voltage of the storage capacitor Cst. That is, by the voltage charged in the storage capacitor Cst, a constant current is supplied to the thin film transistor T until the next data signal is supplied, so that the organic light emitting diode can maintain light emission.

The thin film transistor T includes a gate electrode 264 , a source electrode 266 , a drain electrode 268 and an active layer 225 .

The gate electrode 264 may overlap the channel region CH of the active layer 225 . A gate insulating layer 230 may be disposed between the gate electrode 264 and the channel region CH of the active layer 225 . The gate insulating layer 230 may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The gate electrode 264 is any one from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu). It may be a single layer or multiple layers made of one or an alloy thereof.

The source electrode 266 is electrically connected to the source region SA of the active layer 225 through a source contact hole 262 formed in the second buffer layer 222 . The drain electrode 268 is connected to the drain region DA of the active layer 225 through the drain contact hole 260 formed in the second buffer layer 222 . In addition, the drain electrode 268 of the thin film transistor T is in contact with and electrically connected to the first electrode 286 through the pixel contact hole 284 formed to penetrate the planarization layer 282 and the interlayer insulating layer 280. . In addition, the drain electrode 268 may be electrically connected to the light blocking layer 205 through the light blocking contact hole 254 penetrating the first buffer layer 220 and the second buffer layer 222 . The source electrode 266 and the drain electrode 268 are made of the same material as the gate electrode 264 and are positioned on the same plane (layer) as the gate electrode 264 .

The active layer 225 includes a source region SA and a drain region DA positioned to face each other with the channel region CH interposed therebetween. The channel region CH is disposed to overlap the gate electrode 264 with the gate insulating layer 230 interposed therebetween.

In one example, the active layer 225 may include at least one of amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the active layer 225 may include at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO). In addition, the active layer 225 may be formed of another oxide semiconductor material known in the art.

The source region SA provided in the active layer 225 includes a source contact hole 262 passing through the source region SA, a first source conductor region 226 surrounding the source contact hole 262, and a second It includes a source conductor region 227, and the drain region DA includes a drain contact hole 260 penetrating the drain region DA and a first drain conductor region 228 surrounding the drain contact hole 260. and a second drain conductorization region 229 .

Each of the first source conductor region 226 and the first drain conductor region 228 is formed to surround an upper corner of the source contact hole 262 or the drain contact hole 260 . Also, the second source conductor region 227 and the second drain conductor region 229 surround the outer circumferences of the first source conductor region 226 and the first drain conductor region 228 , respectively.

In one example, the first source conductor region 226 and the first drain conductor region 228 have a ring shape. Referring to FIG. 3C showing the X portion of FIG. 3A on a plane, the source electrode 266 is positioned in surface contact with an exposed surface of one side of the first source conductor region 226 . Specifically, referring to an enlarged portion of the X1 region where the source electrode 266 is in surface contact with the first source conducting region 226, the first source conducting region 226 surrounding the source contact hole 262 A contact point CP is generated by surface contact with the second source conductor region 227 . And the current path (C _i ) is also made through this contact point (CP). That is, the first source conductor region 226 is in surface contact with the second source conductor region 227, and the source electrode 266 is also exposed on one side of the first source conductor region 226. As it comes into surface contact with the surface, it can be stably connected to the source electrode 266 . This may also occur in the drain electrode 268 in the same way.

A light blocking layer 205 is formed between the active layer 225 and the substrate 200 . The light blocking layer 205 is formed at a position overlapping the active layer 225 and is disposed to overlap at least the channel region CH of the active layer 225 . The light blocking layer 205 may protect the thin film transistor T from light incident from the outside. A surface of the light blocking layer 205 may be partially exposed through the light blocking contact hole 254 and electrically connected to the active layer 225 through the drain electrode 268 .

The light blocking layer 205 may be formed of the same material on the same plane as the storage lower electrode 210 and the wiring electrode 215 . Here, the wiring electrode 215 includes a power supply line VDL, a data line DL, and a reference power supply line Vref, and is arranged in a first direction X, for example, a horizontal line. In one example, the light blocking layer 205 may have a structure in which a first metal layer 202 and a second metal layer 204 are stacked. In addition, the light blocking layer 205 may be formed of any one selected from the group of opaque metal materials such as molybdenum (Mo), aluminum (Al), titanium (Ti), or copper (Cu), or an alloy thereof.

The first buffer layer 220 and the second buffer layer 222 are disposed on the light blocking layer 205 , the lower storage electrode 210 , and the wiring electrode 215 . The first buffer layer 220 and the second buffer layer 222 block moisture or oxygen from penetrating from the substrate 200 toward the organic light emitting device to be formed thereon, and prevent impurities such as hydrogen from flowing out of the substrate 200. It serves to protect the thin film transistor formed in the subsequent process.

The first buffer layer 220 is formed of silicon nitride (SiNx) having a first thickness, and the second buffer layer 222 is formed of silicon oxide (SiOx) having a second thickness thicker than the first buffer layer 220 . For example, the first buffer layer 220 is formed to a thickness greater than 500 Å.

In the thin film transistor region III-III', a light blocking contact hole 254 penetrating the first buffer layer 220 and the second buffer layer 222 is disposed, and the drain electrode 268 fills the light blocking contact hole 254. It may be connected to the light blocking layer 205 .

The storage capacitor Cst has a structure in which a storage lower electrode 210 and a storage upper electrode 272 are disposed with the first buffer layer 220 interposed therebetween. The storage upper electrode 272 may fill the storage contact hole 257 penetrating the second buffer layer 222 and extend to partially cover the upper surface of the second buffer layer 222 .

The storage contact hole 257 becomes narrower toward the bottom and has an inclined side surface. As the storage upper electrode 272 is formed to fill the storage contact hole 257, the bottom portion of the storage upper electrode 272 contacts the first buffer layer 220 and the side portion contacts the second buffer layer 222. Accordingly, a main capacitor is formed between the storage lower electrode 210, the first buffer layer 220, and the storage upper electrode 272, and the storage lower electrode 210, the second buffer layer 222, and the storage upper electrode 272 ), an auxiliary capacitor may be formed between the capacitance of the auxiliary capacitor and the capacitance of the main capacitor, so that the capacitance of the total capacitor may increase.

The pad electrode 274 is disposed on the same plane as the gate electrode 264, the source electrode 266, the drain electrode 268, and the storage capacitor Cst.

The pad electrode 274 serves to supply driving signals to each of the gate electrode 264, the data line DL, the power supply line VDL, and the reference power supply line Vref. In the embodiments of the present specification, a configuration in which the pad electrode 274 is connected to the power supply line VDL has been presented as an example, but is not limited thereto. For example, a plurality of pad electrodes 274 may be connected to each of the data line DL and the reference power supply line Vref.

The pad electrode 274 is made of the same material as the gate electrode 264, the source electrode 266, the drain electrode 268, and the storage capacitor Cst. A pad cover electrode 288 preventing corrosion of the pad electrode 274 is disposed on the pad electrode 274 . The pad cover electrode 288 is formed of the same material as the first electrode 286 .

In response to the power supply line (VDL), data line (DL), and reference power supply line (Vref) arranged in the first direction (X), which is a horizontal line, scan lines (SCAN1) in a second direction (Y), which is a vertical line, SCAN2) is placed. While the scan lines SCAN1 and SCAN2 supply data signals to the sub-pixels, the first scan line SCAN1 supplies scan signals for selecting each horizontal line and data signals supplied to the sub-pixels during initialization. A second scan line SCAN2 supplying a signal for selecting each horizontal line may be included. Here, each of the power supply line VDL and the reference power supply line Vref may correspond to two or more vertical lines, that is, scan lines SCAN1 and SCAN2.

An interlayer insulating film 276 and a planarization film 282 are disposed on the substrate 200 on which the gate electrode 264 , the source electrode 266 , the drain electrode 268 , and the upper storage electrode 272 are formed. The interlayer insulating film 276 and the planarization film 282 are formed by selecting an inorganic insulating material or an organic insulating material.

A color filter 280 is disposed on the interlayer insulating layer 276 . The color filter 280 is disposed at a position overlapping the light emitting region 294 . The color filter 280 may represent a color assigned to each sub-pixel. For example, the color filter 280 may be one of red (R), green (G), and blue (B).

The planarization film 282 is formed to form a flat surface and may be made of acrylic resin or the like. The planarization layer 282 further includes a pixel contact hole 284 exposing a portion of the surface of the drain electrode 268 .

A first electrode 286 is disposed on the planarization layer 282 and the pixel contact hole 284 and electrically connected to the drain electrode 268 . The first electrode 286 is a planarization film (which overlaps with the driving circuit element including the light emitting region 294 formed by the bank hole 292 provided in the bank 290, the thin film transistor T, and the storage capacitor Cst). 282) is placed on it.

The first electrode 286 includes a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first electrode 286 may also be referred to as an anode electrode or a pixel electrode.

Meanwhile, the width EAW2 of the light emitting region 294 may be defined by the size of the bank hole 292 . In the storage capacitor Cst according to the second embodiment of the present specification, the storage upper electrode 272 formed together in the process of forming the gate electrode 264 through the storage contact hole 257 disposed through the second buffer layer 222. ) is formed to fill, it may be disposed overlapping with the gate electrode 264 .

Accordingly, since the area occupied by the storage capacitor Cst partially overlaps the area occupied by the gate electrode 264 , the area occupied by the storage capacitor Cst in the circuit unit may be reduced. In addition, the width EAW3 of the light emitting region 294 may increase by at least the reduced area of the storage capacitor Cst, so that the area may increase. That is, the width EAW1 of the light emitting region 294 according to the second embodiment of the present specification is increased by at least the width EAW and the increased width EAW3 of the light emitting region 194 according to the first embodiment, so that the entire The area of the light emitting region 294 increases.

When the area of the light emitting region 294 is increased, current consumption for implementing the same luminance in each pixel is reduced, and thus the lifetime of the organic light emitting device is increased, thereby improving reliability of the organic light emitting display device. Also, as the area of the light emitting region 294 increases, the aperture ratio can be improved.

The organic light emitting layer 298 extends to the upper surface of the bank 290 while being connected to the first electrode 286 exposed by the bank hole 292 . The organic emission layer 298 has a stacked structure of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). The organic emission layer may further include a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL), and an electron injection layer (EIL).

The organic light emitting layer 298 is made of an organic material that emits white light, and can display colors by the color filter 280 .

The bank 290 is a boundary region defining the light emitting region 294 of the region where pixels are to be formed, and serves to divide each sub-pixel. In addition, the bank 290 serves as a barrier to prevent light of different colors from adjacent pixels from being mixed and output.

A second electrode 300 is disposed on the organic emission layer 298 . Accordingly, an organic light emitting diode (OLED) including the first electrode 286 , the organic light emitting layer 298 and the second electrode 300 is formed.

The second electrode 300 serves to apply a voltage by commonly contacting adjacent pixels on the display area. The second electrode 300 may also be referred to as a common electrode or a cathode electrode. In one example, the second electrode 300 may include a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, the second electrode 300 may include a translucent metal material composed of molybdenum (Mo), tungsten (W), silver (Ag), or aluminum (Al) and an alloy including at least one of them.

As described above, according to the second exemplary embodiment of the present specification, an aperture ratio may be improved by increasing an area of a light emitting region in a bottom emission type display device. To this end, the area occupied by the storage capacitor may be reduced to increase the area of the light emitting region and increase the total capacitance value. In addition, by introducing a ring-shaped contact structure, it is possible to stably connect the source electrode or drain electrode and the active layer by contacting each other with a surface.

Hereinafter, a method of manufacturing a display device according to a second embodiment will be described with reference to the accompanying drawings.

4 to 18 are cross-sectional views illustrating a method of manufacturing a display device according to a second exemplary embodiment of the present specification. 4 to 18 are cross-sectional views cut along II', II-II', III-III', IV-IV', V-V', and VI-VI' directions in FIG. 3A. In addition, components identical or similar to those of FIGS. 3A to 3C will be described using the same reference numerals.

Referring to FIG. 4 , a light blocking layer 205 , a storage lower electrode 210 , and a wiring electrode 215 are formed on a substrate 200 . Specifically, a first metal layer 202 and a second metal layer 204 are formed on the substrate 200 . Next, a photolithography process and an etching process using a mask are performed on the first metal layer 202 and the second metal layer 204 to form the light blocking layer 205, the storage lower electrode 210, and the wiring electrode 215. . Here, the light blocking layer 205 is preferably formed at a position overlapping with the active layer of the thin film transistor to be formed later. The light blocking layer 205 serves to protect the thin film transistor from light incident from the outside. In one example, the wiring electrode 215 may be any one of a power supply line (VDD), a data line (DL), or a reference power supply line (Vref).

The substrate 200 may be made of a flat insulating material. For example, the substrate 200 may be a light-transmitting substrate. The substrate 200 may be made of a hard material such as glass or tempered glass or a flexible material such as plastic, but is not limited thereto.

The light blocking layer 205, the storage lower electrode 210, and the wiring electrode 215 may be formed using the same material. In one example, the first metal layer 202 and the second metal layer 204 are any one selected from the group of opaque metal materials such as molybdenum (Mo), aluminum (Al), titanium (Ti) or copper (Cu), or It may be made of an alloy of these.

Referring to FIG. 5 , a first buffer layer 220 and a second buffer layer 222 are formed on a substrate 200 . The first buffer layer 220 and the second buffer layer 222 are formed to cover the light blocking layer 205 , the storage lower electrode 210 and the wiring electrode 215 . The first buffer layer 220 and the second buffer layer 222 block moisture or oxygen from penetrating from the substrate 200 toward the organic light emitting device to be formed thereon, and prevent impurities such as hydrogen from flowing out of the substrate 200. It serves to protect the thin film transistor formed in the subsequent process. In addition, the first and second buffer layers 220 and 222 serve to insulate the light blocking layer 205 , the storage lower electrode 210 and the wiring electrode 215 .

The first buffer layer 220 and the second buffer layer 222 may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). In one example, the first buffer layer 220 is formed of silicon nitride (SiNx) having a first thickness, and the second buffer layer 222 is formed of silicon oxide (SiOx) having a second thickness thicker than the first buffer layer 220 . can do. For example, the first buffer layer 220 may be formed to a first thickness of 1000 Å to 1500 Å, and the second buffer layer 222 may be formed to a second thickness of 2700 Å to 3300 Å.

Here, the first buffer layer 220 is formed to a thickness greater than 500 Å. For example, if the first buffer layer 220 positioned above the lower electrode 210 of the storage node is formed to a thickness less than 500 Å, the first buffer layer 220 is removed in the course of subsequent processing steps to form the lower portion of the storage node. A surface of the electrode 210 may be exposed. Then, since a short may occur between the upper electrode of the storage node and the lower electrode 210 of the storage node to be formed later, the thickness of the storage node is preferably greater than 500 Å.

An active layer 225 is positioned on the second buffer layer 222 . The active layer 225 may include at least one of amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the active layer 225 may include at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO). In addition, the active layer 225 may be formed of another oxide semiconductor material known in the art.

Referring to FIG. 6 , a gate insulating layer 230 is formed on the entire surface of the substrate 200 on which the active layer 225 is formed. The gate insulating layer 230 may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

Next, a photoresist film is applied on the gate insulating film 230 . Subsequently, an exposure process of selectively irradiating light onto the photoresist film through a halftone mask and a development process of removing the photoresist film modified by the exposure process are performed. Then, the plurality of open regions 234 , 236 , 238 , and 240 from which the photoresist layer is completely removed to expose the surface of the gate insulating layer 230 and the halftone region 242 where the photoresist layer remains on the gate insulating layer 230 are formed. The provided first photoresist pattern 232 is formed. In one example, the portion where the halftone region 242 is disposed is a capacitor region V−V′ where the storage lower electrode 210 is formed.

Referring to FIG. 7 , a first patterning process is performed using the first photoresist pattern 232 . The first patterning process may be performed by a wet etching method. Then, the gate insulating film 230 whose surface is exposed by the plurality of open regions 234, 236, 238, and 240 of the first photoresist pattern 232 is etched to form a plurality of GI holes 244, 246, 248, and 250. is formed In one example, the plurality of GI holes 244, 246, 248, and 250 formed in the first patterning process serve to align positions of regions where light blocking contact holes, source contact holes, drain contact holes, and data contact holes are to be formed. do Here, the halftone region 242 is formed to have a depth greater than the initial depth, but the lower gate insulating layer 230 is not exposed and the first photoresist pattern 232 remains.

The first GI hole 244 may be formed by etching the entire exposed surface of the gate insulating layer 230 and having a predetermined depth from the surface of the second buffer layer 222 . In the second GI hole 246, the third GI hole 248, and the fourth GI hole 250, all exposed surfaces of the gate insulating film 230 are etched and the active layer 225 is exposed. , e3) occurs.

Referring to FIG. 8 , a first ashing process of removing a part of the thickness of the first photoresist pattern 232 is performed. The primary ashing process may be performed using oxygen (O ₂ ) plasma. When the primary ashing process is performed, the first photoresist pattern 232 remaining in the halftone region 242 of the capacitor region V-V′ is removed to expose the surface of the gate insulating layer 230. The upper surface i2 of the first photoresist pattern 232a remaining after the first ashing process is lowered from the position of the upper surface i1 formed by the initial application.

Referring to FIGS. 9A and 9B , a secondary patterning process is performed using the remaining first photoresist pattern 232a as an etch mask. Here, FIG. 9B is a view showing part A of FIG. 9A on a plan view. Hereinafter, a description thereof will be omitted. In FIG. 9B , for ease of explanation, the gate insulating layer 230 disposed on the active layer 225 and the remaining first photoresist pattern 232a are omitted.

The secondary patterning process may be performed by a dry etching method such as plasma treatment. In one example, the plasma treatment may proceed by generating a plasma discharge in helium (He), hydrogen (H2), or argon (Ar) gas. When the secondary patterning process is performed, the second buffer layer 222 on the bottom surface of the first GI hole 244 (see FIG. 8) is removed and etched to the exposed first buffer layer 220 so that the surface of the light blocking layer 205 is formed. An exposed light blocking contact hole 254 may be formed.

In addition, in the exposure regions e1, e2, and e3 where the active layer 225 is exposed by the second GI hole 246, the third GI hole 248, and the fourth GI hole 250, a dry etching process is performed. The first conductor region 225a may be formed by primary conductorization. For example, when the active layer 225 is formed of an oxide semiconductor, conduction characteristics vary depending on the content of oxygen, and when the plasma treatment is performed, the oxygen content in the oxide semiconductor is reduced and the resistance of the oxide semiconductor is lowered, leading to a decrease in the resistance of the oxide semiconductor. can get angry

Referring to FIG. 9B , the first conductive region 225a formed in the secondary patterning process has a first horizontal width W1 and a first vertical width L1, and is surrounded by an active layer 225 to be isolated. It may have an island shape.

On the other hand, a loss from the surface of the first conductive region 225a of the active layer 225 formed in the process of making the primary conductor may occur by a predetermined thickness h1. A part of the side surface S of the active layer 225 that is not conductive by the loss of thickness h1 is exposed. However, since the remaining portion of the active layer 225 except for the first conductive region 225a is covered with the gate insulating layer 230 and the remaining first photoresist pattern 232a, no loss of the active layer 225 occurs. don't

In addition, in the capacitor region (V-V′) region, the gate insulating film 230, the surface of which was exposed by the primary ashing process, is all etched during the dry etching process, and the second buffer layer 222 is removed from the surface. Etched by a predetermined depth, a trench 256 is formed in the second buffer layer 222, the width of which becomes narrower toward the bottom. Here, all of the second buffer layer 222 in the capacitor region V-V′ is not removed, and a portion of the second buffer layer 222 remains on the storage lower electrode 210.

Referring to FIGS. 10A and 10B , a third patterning process is performed using the residual first photoresist pattern 232a as an etch mask. The tertiary patterning process may be performed using a wet etching method. In one example, the wet etching method may be performed using a buffered oxide etchant (BOE) solution in which an ammonium fluoride (NH ₄ F) solution and a hydrogen fluoride (HF) solution are mixed. The BOE solution can selectively etch silicon oxide.

When the tertiary patterning process is performed, the second buffer layer 222 (see FIG. 9A) partially remaining on the upper portion of the storage lower electrode 210 is removed in the capacitor region V-V′, and the first buffer layer 220 is exposed. A storage contact hole 257 is formed. In the tertiary patterning process, as the first buffer layer 220 made of silicon nitride serves as an etch stop film for the BOE solution, etching can proceed uniformly. Here, the storage contact hole 257 is tapered and inclined towards the bottom where the first buffer layer 220 is exposed.

Here, since the first buffer layer 220 is formed by including a material having a relatively slower etching rate than the second buffer layer 222 made of silicon oxide (SiOx), for example, silicon nitride (SiNx), wet etching using a BOE solution In the process, the lower electrode 210 of the storage node may be prevented from being exposed.

In the exposure regions e1, e2, and e3 where the active layer 225 is exposed by the second GI hole 246, the third GI hole 248, and the fourth GI hole 250 of FIG. 9A, in FIG. 10A As shown, the first conductive area 225a is completely removed by the BOE solution. In addition, as the first conductive region 225a is removed and the exposed second buffer layer 222 is also etched from the surface, a plurality of contact holes 260 , 262 , and 264 are formed in the second buffer layer 222 . The contact holes 260 , 262 , and 264 include source/drain contact holes 260 and 262 and data contact holes 264 .

In the tertiary patterning process, the gate insulating layer 230 and the active layer 225 exposed to the BOE solution may be recessed by a predetermined thickness r1 in an inward direction from the side surface. Specifically, a portion (S) of the side surface of the active layer 225 is exposed by the primary conductorization process, and the BOE solution penetrates through this portion (S) to cause loss of the active layer 225. , the active layer 225 may be recessed inward from the side surface.

Referring back to FIG. 10B , each of the contact holes 260 , 262 , and 264 formed by removing the first conductive region 225a may have an isolated island shape surrounded by the active layer 225 . Here, each of the contact holes 260, 262, and 264 is recessed by a predetermined thickness r1 in an inward direction from the first conductive region 225a, so that the first horizontal width W1 and the first vertical width L1 are smaller than each other. It may be formed to have a wide second horizontal width W2 and a wide second vertical width L2. In addition, the residual first photoresist pattern 232a may have an undercut shape as it is not removed by the BOE solution or remains without loss.

Referring to FIGS. 11A and 11B , a secondary ashing process is performed on the substrate 200 . The secondary ashing process may be performed using an etching gas including oxygen (O2) gas, sulfur hexafluoride (SF ₆ ) gas, and carbon tetrafluoride (CF ₄ ) gas.

The width of the remaining first photoresist pattern 232a is reduced by the secondary ashing process, and at the same time, the end of the gate insulating layer 230 under the remaining first photoresist pattern 232a has a predetermined width r2 in the inward direction. Recessed as much as Then, the surface of the tip 225t of the active layer may be exposed by a width r2 in which the end of the gate insulating layer 230 is recessed inward. In addition, the end portion 225t of the active layer exposed in the secondary ashing process may also be ashed to have a thickness about 20% lower than the thickness of the first active layer.

Referring back to FIG. 11B , the gate insulating layer 230 and the remaining first photoresist pattern 232a cover the active layer 225 except for the exposed end portion 225t of the active layer. Accordingly, it can be confirmed that the distal end 225t of the active layer appears in a shape in which the contact holes 260, 262, and 264 are disposed. That is, the distal end of the active layer 225 may be formed to surround upper corners of each of the contact holes 260 , 262 , and 264 in a ring shape when viewed from a plane.

12A and 12B, a second conductorization process is performed on the end portion 225t of the active layer exposed to the outside to form a first source conductor region 226 and a first drain conductor region 228. form The secondary conductorization process may be performed using an ion implantation process method for supplying impurity ions or plasma treatment.

For example, in an ion implantation process for supplying impurity ions, boron ions or phosphorus ions are implanted onto the exposed end portion 225t of the active layer to make the portion conductive. In another example, the plasma treatment may be performed by converting impurity ions into plasma and supplying the plasma-generated ions to the end portion 225t of the active layer. The secondary conductorization process may selectively proceed only to the end portion 225t of the active layer exposed to the outside. Here, other non-exposed portions of the active layer 225 are not conductive because they are covered with the gate insulating layer 230 and the remaining first photoresist pattern 232a during the secondary conductorization process.

Referring back to FIG. 12B , the first source conductor region 226 has contact holes 260 , 262 , and 264 disposed in the inner direction of the first source conductor region 226 . (260, 262, 264) It can be seen that it has a ring shape surrounding the upper part of each corner. In addition, the outside of the first conductive region 225b is surrounded by a structure in which the gate insulating layer 230 and the remaining first photoresist pattern 232a are stacked.

Referring to FIG. 13 , a strip process is performed to remove the remaining first photoresist pattern 232a. Subsequently, a gate metal layer 265 is formed on the upper surface of the substrate 200 including the gate insulating layer 230 whose surface is exposed through the strip process. The gate metal layer 265 may have a structure in which a first gate metal layer 261 and a second gate metal layer 263 are stacked. The gate metal layer 265 may be formed on the entire surface of the substrate 200 to extend to the pad region I-I', the capacitor region V-V', and the wiring region VI-VI'.

In one example, the first gate metal layer 261 and the second gate metal layer 263 may be made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be composed of a single layer or multiple layers made of any one from the group consisting of neodymium (Nd) or copper (Cu) or an alloy thereof, but is not limited thereto.

14A and 14B, the gate electrode 264, the source electrode 266, and the drain electrode 268 are patterned by patterning the gate metal layer 265 (see FIG. 13A) through a photolithography process and an etching process using a photo mask. ), the storage upper electrode 272 and the pad electrode 274 may be formed. Here, the etching process may proceed with dry etching. The gate electrode 264, the source electrode 266, the drain electrode 268, the upper storage electrode 272, and the pad electrode 274 are formed by patterning the same gate metal layer 265, and are made of the same material, can be formed on the same layer.

In one example, tertiary conductorization may be performed during dry etching to form the gate electrode 264 . For example, in the process of forming the gate electrode 264, the gate insulating film 230 remains at a portion overlapping the gate electrode 264, and the region of the active layer 225 that is not covered by the gate electrode 264 is the gate. The insulating layer 230 is also removed to expose the surface of the active layer 225 . In dry etching, the etching gas applied comes into contact with the exposed surface of the active layer 225 . Then, selective conduction is performed on the surface portion of the active layer 225 that is in contact with the etching gas, so that the second source conductor region 227 and the second drain conductor region 229 may be formed.

In the portion of the first source conductor region 226 not covered by the source electrode 266, loss of the exposed active layer may occur during the conduction process. Also, a portion of the first drain conductor region 228 that is not covered with the drain electrode 268 may lose an active layer exposed during the conduction process.

Accordingly, the first source conductor region 226 may include a first portion in surface contact with the source electrode 266 and a second portion not covered by the source electrode 266 . Also, the first drain conductor region 229 may include a first portion in surface contact with the drain electrode 268 and a second portion not covered by the drain electrode 268 .

Here, the upper surface of the second portion of each of the first source conductor region 226 and the first drain conductor region 229 is located at a position lower than that of the first region. In one example, the second portion of each of the first source conductor region 226 and the first drain conductor region 229 has a thickness that is about 40% lower than the thickness remaining in the secondary ashing process. Accordingly, the second portion of each of the first source conductor region 226 and the first drain conductor region 229 has a thickness about 40% lower than that of the first active layer.

In another example, after forming the gate electrode 264, doping by ion implantation is performed on the exposed surface of the active layer 225 to form the second source conductor region 227 and the second drain conductor region 227. (229) can be formed.

A channel region CH is disposed in the active layer 225 under the gate electrode 264 on which the second source conductor region 227 and the second drain conductor region 229 are not formed by this conducting process. can

Therefore, in the thin film transistor region III-III', the active layer 225, the gate electrode 264, the source electrode 266, the drain electrode 268, and the source electrode 266 and the drain electrode 268 are disposed. A thin film transistor (TFT) including a channel region (CH) is formed.

Here, the source electrode 266 is formed in surface contact with the first source conductor region 226 and partially fills the source contact hole 262 . In addition, the drain electrode 268 is formed in surface contact with the first drain conductor region 229 and partially fills the drain contact hole 260 . Then, when part A is viewed from a plane, as shown in FIG. 3C, the first source conductor region 226 surrounding the source contact hole 262 is in surface contact with the second source conductor region 2257. A contact point (CP) occurs. And the current path (C _i ) is also made through this contact point (CP). That is, since the first source conductor region 226 is in surface contact with the second source conductor region 2257, it can be stably connected to the source electrode 266. In addition, the source electrode 266 is positioned while covering an exposed surface of one side of the first source conductor region 226 . This can also be applied to the drain electrode 268 in the same way.

As the storage node upper electrode 272 filling the storage contact hole 257 is formed in the capacitor region V-V′, the storage capacitor Cst is formed. The storage capacitor Cst may be formed by overlapping the storage lower electrode 210 and the upper storage electrode 272 on and under the first buffer layer 220 using the first buffer layer 220 as a dielectric layer. The storage node upper electrode 272 may be formed by extending to partially cover the upper surface of the second buffer layer 222 after fully filling the storage contact hole 257 . Accordingly, the bottom portion of the storage node upper electrode 272 is in contact with the first buffer layer 220 and the side portion is in contact with the second buffer layer 220 .

The storage capacitor Cst serves to maintain light emission of the organic light emitting device by charging a voltage and supplying a current to the thin film transistor TFT.

At this time, the storage capacitor Cst according to the second embodiment of the present specification uses a single layer of the first buffer layer 220 as a dielectric. The first buffer layer 220 is made of silicon nitride (SiNx) and has a first thickness of 1000 Å to 1500 Å. Since the permittivity of silicon nitride (SiNx) is about 6.9, the capacitance value of the storage capacitor Cst has a constant value of 0.0069*.

Also, referring to FIG. 14B showing an enlarged portion B of the storage capacitor Cst, the storage capacitor Cs according to the second embodiment of the present specification has a first buffer layer ( 220), the main capacitor c1 is formed between the storage lower electrode 210 and the storage upper electrode 272 with the first buffer layer 220 as a medium. In addition, both side surfaces of the storage node upper electrode 272 contact the second buffer layer 220 so that an auxiliary capacitor ( c2, c3) are formed. Accordingly, as the auxiliary capacitors c2 and c3 are formed in addition to the main capacitor c1 having a flat plate shape, the auxiliary capacitor capacitance is added to the main capacitor capacitance, so that the total capacitor capacitance may increase.

In the storage capacitor Cst according to the first embodiment of the present specification, a double layer of the first buffer layer 120 and the second buffer layer 122 is introduced as a dielectric. Here, the first buffer layer 120 is made of silicon nitride and the second buffer layer 122 is made of silicon oxide. Here, the dielectric constant of silicon nitride is about 6.9, whereas the dielectric constant of silicon oxide is about 3.9. In addition, the first buffer layer 120 is formed to have a first thickness of 1000 Å to 1500 Å, and the second buffer layer 12 is formed to have a second thickness of 2700 Å to 3300 Å. Accordingly, the capacitor capacity of the storage capacitor Cst according to the first embodiment has a constant value of 0.0011*.

That is, the capacitor capacity of the storage capacitor Cst according to the second embodiment of the present specification introduced as a single layer of the first buffer layer 220 as a dielectric is about 6 times or more than that of the storage capacitor Cst according to the first embodiment. An increased capacitor capacity can be secured. Accordingly, when the dielectric is introduced as a single layer of the first buffer layer 220, the light emission of the light emitting device can be maintained for a relatively longer time than when the dielectric is introduced as a double layer of the first buffer layer and the second buffer layer.

Referring to FIG. 15 , an interlayer insulating film 276 and a planarization film 282 are formed on the substrate 200 on which the gate electrode 264, the source electrode 266, the drain electrode 268, and the upper storage electrode 272 are formed. form The interlayer insulating layer 276 is formed to a thickness sufficient to cover all surfaces of the gate electrode 264, the source electrode 266, the drain electrode 268, the active layer 225, and the storage upper electrode 272. Here, the interlayer insulating film 276 and the planarization film 282 are not formed in the pad region II' where the pad electrode 274 is formed. The interlayer insulating layer 276 may be formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).

Next, a color filter 280 is formed on the interlayer insulating film 276 . To this end, red (R), green (G), and blue (B) pigments are applied on the interlayer insulating film 280, and a mask process is performed to form a color filter 280 corresponding to the light emitting area. When the color filter 280 is made of red (R), green (G), and blue (B) colors, the mask process may require three mask processes.

A planarization layer 282 may be disposed on the interlayer insulating layer 276 on which the color filter 280 is disposed. The planarization layer 282 may be formed to have a sufficient thickness to planarize the surface of the substrate 200 while serving to protect underlying devices. The planarization layer 282 may be formed by coating an organic insulating material such as acrylic resin. Next, a pixel contact hole 284 exposing a portion of the surface of the drain electrode 268 is formed by patterning the planarization layer 282 and the interlayer insulating layer 280 .

Referring to FIG. 16 , a first electrode 286 is formed on the planarization layer 282 . The first electrode 286 may be electrically connected to the gate electrode 264 through the drain electrode 268 exposed through the pixel contact hole 284 . The first electrode 286 may be formed of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first electrode 286 may also be referred to as an anode electrode or a pixel electrode. Here, the first electrode 286 may be formed as a pad cover electrode 288 that extends to the pad region II′ and covers the exposed surface of the pad electrode 274 to prevent corrosion of the pad electrode 274. .

Referring to FIG. 17 , a bank 290 having a bank hole 292 is formed on the planarization layer 282 on which the first electrode 286 is formed. The bank 290 may be formed to cover a remaining portion while exposing a portion of the first electrode 286 through the bank hole 292 .

To this end, an insulating layer is formed on the planarization layer 282 and a patterning process is performed on the insulating layer to form the bank hole 292 . The bank 290 is a boundary region defining the light emitting region 294 of the region where pixels are to be formed, and serves to divide each sub-pixel. In addition, the bank 290 serves as a barrier to prevent light of different colors from adjacent pixels from being mixed and output. The bank 290 may be formed using an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or an organic insulating material such as polyimide.

The bank 290 may be formed in an area other than the pad area II′ to expose the pad electrode 274 covered by the pad cover electrode 288 .

Referring to FIG. 18 , an organic light emitting layer 298 and a second electrode 300 are formed on the light emitting region 294 defined by the bank 290 . Accordingly, an organic light emitting diode (OLED) including the first electrode 286 , the organic light emitting layer 298 and the second electrode 300 may be configured. The organic light emitting layer 298 and the second electrode 300 may be formed in the remaining area except for the pad area I-I'.

The organic emission layer 298 is directly connected to the first electrode 286 exposed through the bank hole 292 . In one example, the organic emission layer 298 may be formed to extend to the upper surface of the bank 290 along the exposed surface of the first electrode 286 . In one example, the organic light emitting layer 298 is made of an organic material that emits white light, and can display colors by the color filter 280 .

Although not shown in the drawings, the organic emission layer 298 may include a stacked structure of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). The organic light emitting layer includes a hole transport layer (HTL), a light emitting layer (EML) and an electron transport layer (ETL) together with a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL) and an electron injection layer (EIL). It may be configured to include more.

The second electrode 300 may be connected to the organic light emitting layer 298 to cover the entire exposed surface of the organic light emitting layer 298 . The second electrode 300 may be formed as a common electrode that commonly contacts adjacent pixels on the display area and applies a voltage thereto. The second electrode 300 may also be referred to as a cathode electrode.

In one example, the second electrode 300 may be formed of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the second electrode 300 may be formed of a translucent metal material composed of molybdenum (Mo), tungsten (W), silver (Ag) or aluminum (Al) and an alloy containing at least one of them.

As described above, according to the embodiments of the present specification, the area occupied by the storage capacitor may be reduced to increase the area of the light emitting region and the total capacitance of the storage capacitor. In addition, capacitance of the storage capacitor may be increased by improving the structure of a dielectric constituting the storage capacitor. In addition, the lifetime of the organic light emitting diode can be increased by reducing the current consumption required to realize the same luminance in individual pixels by increasing the area of the light emitting region. In addition, by introducing a ring-shaped contact structure into the active layer, there is an effect of stably connecting the source electrode or drain electrode and the active layer by plane-to-plane connection.

10, 20: display device 100, 200: substrate
105, 205: light blocking layer 110, 210: storage lower electrode
115, 215: wiring electrode 120, 220: first buffer layer
122, 222: second buffer layer 125, 225: active layer
130, 230: active layer 226: first source conductor region
227: second source conductor region 228: first drain conductor region
229: second drain conductor area Cst: storage capacitor
272: storage upper electrode 180, 280: color filter
186, 286: first electrode 190, 290: bank
198, 298: organic light emitting layer 199, 300: second electrode

Claims (22)

Board;
a buffer layer positioned on the substrate;
an active layer disposed on the buffer layer and including a channel region, a source region disposed with the channel region interposed therebetween, and a drain region;
a gate electrode positioned on the active layer;
a source electrode electrically connected to the source region; and
a drain electrode electrically connected to the drain region; including,
The source region includes a source contact hole penetrating the source region and a first source conductor region and a second source conductor region surrounding the source contact hole;
The drain region includes a drain contact hole penetrating the drain region and a first drain conductor region and a second drain conductor region surrounding the drain contact hole. According to claim 1,
The source electrode and the drain electrode are in surface contact with exposed surfaces of the first source conductor region and the first drain conductor region, respectively. According to claim 1,
The source contact hole or the drain contact hole extends to the buffer layer and is located in the display device. According to claim 3,
The source electrode or the drain electrode extends to the source contact hole or the drain contact hole extending to the buffer layer and is positioned to contact a side surface of the source contact hole or the drain contact hole. According to claim 1,
The source electrode is positioned while covering an exposed surface of one side of the first source conductor region, and the drain electrode is positioned while covering the exposed surface of one side of the first drain conductor region. According to claim 1,
The second source conductor region is positioned to surround the periphery of the first source conductor region;
The second drain conductor region is positioned to surround the periphery of the first drain conductor region. According to claim 1,
The first source conductor region includes a first portion in surface contact with the source electrode and a second portion excluding the first portion;
The first drain conductor region includes a first portion in surface contact with the drain electrode and a second portion excluding the first portion.
According to claim 7,
The upper surface of the second portion of the first source conductor region is positioned lower than the first portion of the first source conductor region;
A display device in which an upper surface of the second portion of the first drain conductor region is positioned lower than the first portion of the second drain conductor region. According to claim 1,
the first source conductor region and the second source conductor region surround upper corners of the source contact hole;
The first drain conductor region and the second drain conductor region have a ring shape surrounding upper corners of the drain contact hole. According to claim 1,
The source electrode or the drain electrode fills a portion of the source contact hole or the drain contact hole, respectively. The method of claim 1, wherein the substrate,
a storage lower electrode positioned on the substrate;
a first buffer layer on the storage lower electrode;
a second buffer layer disposed on the storage lower electrode and having a storage contact hole exposing a portion of a surface of the first buffer layer; and
and a storage capacitor formed of a storage upper electrode filling the storage contact hole. According to claim 11,
The storage contact hole has an inclined side portion that becomes narrower toward a bottom portion where the first buffer layer is exposed, and the storage upper electrode fills the storage contact hole and extends to a portion of a surface of the second buffer layer. According to claim 12,
A bottom portion of the storage upper electrode overlaps the storage lower electrode with the first buffer layer interposed therebetween, and a side portion of the storage upper electrode contacts the second buffer layer. According to claim 11,
The storage upper electrode is positioned on the same plane as the gate electrode and made of the same material;
The first buffer layer is formed of a material having a first permittivity of a first thickness, and the second buffer layer has a second thickness thicker than the first buffer layer and a second permittivity lower than the first permittivity. According to claim 11,
The first buffer layer disposed between the storage lower electrode and the storage upper electrode has a thickness greater than 500 Å. Forming a buffer layer on the substrate;
forming an active layer and a gate insulating film on the buffer layer;
etching to form a source contact hole and a drain contact hole in the buffer layer through the gate insulating layer and the active layer;
Forming a source region and a drain region positioned on the active layer with a channel region interposed therebetween,
The source region includes a first source conductor region and a second source conductor region surrounding the source contact hole;
forming the drain region to include a first drain conductor region and a second drain conductor region surrounding the drain contact hole; and
and forming a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, and a gate electrode positioned on the active layer. According to claim 16,
The source electrode and the drain electrode are in surface contact with exposed surfaces of the first source conductor region and the first drain conductor region, respectively. According to claim 16,
The source or drain electrode extends to the source or drain contact hole that extends to the buffer layer, and fills a portion of the source or drain contact hole while contacting a side surface of the source or drain contact hole. Method of manufacturing the device. According to claim 16,
The source electrode is formed to cover an exposed surface of one side of the first source conductor region, and the drain electrode is formed to cover an exposed surface of one side of the first drain conductor region. According to claim 16,
The first source conductor region and the first drain conductor region have a ring shape surrounding upper corners of the source contact hole and the drain contact hole, respectively. According to claim 16,
wherein the second source conductor region surrounds the periphery of the first source conductor region, and the second drain conductor region surrounds the periphery of the first drain conductor region. According to claim 16,
Forming the source region and the drain region,
After forming the source contact hole and the drain contact hole,
etching the gate insulating layer to expose a portion of the surface of the active layer surrounding upper corners of the source contact hole and the drain contact hole; and
and forming the first source conductor region and the first drain region by conducting the exposed active layer.

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