KR20230071755A - Power-on Resetting Device - Google Patents

Abstract

A power-on reset device capable of stably power-on resetting a system subject to power-on reset while having a simple structure and being able to be driven with low power is provided. A power-on reset device according to an exemplary embodiment of the present invention supplies a reset signal to a circuit subject to power-on reset to perform a power-on reset of the circuit subject to power-on reset, and in response to a power supply voltage, a charging current a current source that supplies; a capacitor charged by the charging current and outputting a charging voltage corresponding to the charging amount; a regulated voltage supply that adjusts the level of the power supply voltage to generate a level-adjusted power supply voltage; and a power sensitive comparator that is biased by the level-adjusted power supply voltage, receives the charging voltage, compares it with a predetermined reference voltage, and outputs the reset signal activated during a time period when the charging voltage is smaller than the reference voltage. do.

Description

Power-on resetting device {Power-on Resetting Device}

The present invention relates to a device for resetting an electric circuit or a system composed of electronic circuits, and more particularly, to a power-on reset device for executing a power-on reset when power is newly applied to a system. .

A power-on reset circuit is a circuit that outputs a reset signal for a certain period of time so that circuits inside the system can be started under the same conditions whenever power is newly applied to the system. 1A shows a typical power-on reset circuit. When the input power VDD is applied, current flows through the current source 110 to the capacitor 120, thereby charging the capacitor 120 and increasing the voltage Vc across the capacitor. The signal comparator 130 receives the voltage Vc across the capacitor, compares it with the reference voltage, and outputs a reset signal V _RESET having a different level according to the comparison result. The reset signal (V _RESET ) may be an active-low signal, has a value of 0 volts (V) when the voltage (Vc) across the capacitor is lower than the reference voltage, and has a value of 0 volts (V) when the voltage (Vc) across the capacitor is higher than the reference voltage. have a high level.

In order to reliably power-on reset a system requiring a power-on reset, it needs to be reset for a sufficient amount of time. That is, as shown in FIG. 1B, it is preferable to sufficiently lengthen the period of the reset signal period. To this end, the output current of the current source 110 should be reduced to lower the rising slope of the voltage Vc across the capacitor. If the output current of the current source 110 is small, the charging of the capacitor 120 is delayed and the time required for the voltage across the capacitor (Vc) to become higher than the reference voltage increases, resulting in a longer reset time.

However, as semiconductor processes become increasingly miniaturized and device sizes decrease, the power-on reset circuit may not operate stably. As the leakage current generated from individual elements in the integrated circuit increases, the output current of the current source 110 may leak or the charge of the capacitor 120 may leak, so that the voltage Vc across the capacitor corresponds to the reference voltage. This is because failure to reach may occur intermittently. In this case, the power-on reset circuit continuously outputs a low-level reset signal (V _RESET ) so that the system is continuously reset and may not operate normally.

SUMMARY OF THE INVENTION The present invention provides a power-on reset device capable of stably power-on resetting a system subject to power-on reset while having a simple structure and being able to be driven with low power.

A power-on reset device according to an exemplary embodiment of the present invention supplies a reset signal to a circuit subject to power-on reset to perform a power-on reset of the circuit subject to power-on reset, and in response to a power supply voltage, a charging current a current source that supplies; a capacitor charged by the charging current and outputting a charging voltage corresponding to the charging amount; a regulated voltage supply that adjusts the level of the power supply voltage to generate a level-adjusted power supply voltage; and a power sensitive comparator that is biased by the level-adjusted power supply voltage, receives the charging voltage, compares it with a predetermined reference voltage, and outputs the reset signal activated during a time period when the charging voltage is smaller than the reference voltage. do.

A magnitude of the level-adjusted power voltage may be smaller than that of the power voltage.

The regulated voltage supply may include a voltage divider. The voltage divider may be implemented as a circuit including a plurality of resistors.

The power sensitive comparator may include an inverter circuit that changes a switching point voltage according to the level-adjusted bias voltage.

The power sensitive comparator may include a Schmitt-trigger circuit in which first and second switching point voltages are changed according to the level-adjusted bias voltage.

According to the power-on reset device according to an embodiment of the present invention, the regulated voltage supply supplies a power supply voltage adjusted to a small size to the power sensitive comparator, and the power sensitive comparator operates based on the scaled power supply voltage. to generate a reset signal. Even when the power-on reset device is driven with low power and the current flowing therein is weak and the proportion of the leakage current increases, a system subject to power-on reset can be stably powered-on reset.

A power-on reset device according to an embodiment has additional advantages in that it has a simple structure and occupies a very small area on a semiconductor chip.

1A is a block diagram of a typical power-on reset circuit.
FIG. 1B is a waveform diagram for explaining the operation and problems of the power-on reset circuit shown in FIG. 1A.
2 is a block diagram showing an example of a use environment of a power-on reset device according to an exemplary embodiment of the present invention.
Fig. 3 is a block diagram of a power-on reset device according to an exemplary embodiment of the present invention.
FIG. 4 is a waveform diagram for explaining the operation of the power-on reset device of FIG. 3 .
FIG. 5 is a circuit diagram of an embodiment of the power sensitive comparator shown in FIG. 3 .
FIG. 6 is a circuit diagram of another embodiment of the power sensitive comparator shown in FIG. 3 .

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Ordinal numbers such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. The term “and/or” includes any combination of a plurality of related listed items or any of a plurality of related listed items.

In embodiments of the present application, “at least one of A and B” may mean “at least one of A or B” or “at least one of combinations of one or more of A and B”. Also, in the embodiments of the present application, “one or more of A and B” may mean “one or more of A or B” or “one or more of combinations of one or more of A and B”.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "include" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that the presence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present application, they should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate overall understanding in the description of the present invention, the same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

2 shows an example of a use environment of a power-on reset circuit according to an exemplary embodiment of the present invention. The system 200 shown in FIG. 2 may include a power switch 210 , a power-on reset circuit 220 , and a power-on reset target circuit 290 . Power switch 210 may allow power to be selectively supplied to system 200 . That is, when the power switch 210 is turned on, power is supplied to the power-on reset circuit 220 and the power-on reset target circuit 290 . In a state in which the power switch 210 is turned off, power may not be supplied to the power-on reset circuit 220 and the power-on reset target circuit 290 . The system 200 may be implemented on a semiconductor integrated circuit (IC).

The power-on reset circuit 220 may be connected to the power-on reset target circuit 290 and supply the reset signal V _RESET to the power-on reset target circuit 290 . The reset signal V _RESET includes a power-on reset signal. In this specification, the power-on reset signal is a circuit inside the power-on reset target circuit 290 whenever the power switch 210 is switched from a turn-off state to a turn-on state and power is supplied to the system 200. It refers to a signal that resets the power-on reset target circuit 290 so that they can be started under the same condition. In the following description, “reset signal (V _RESET )” is used to refer to a power-on reset signal. In one embodiment, the reset signal (V _RESET ) is an active-low signal, and is activated to a low level immediately after power-on to reset the power-on reset target circuit 290, and a normal operating state after power-on is deactivated at a high level and does not affect the operation of the circuit 290 subject to power-on reset.

3 is a block diagram of a power-on reset circuit 220 according to an exemplary embodiment of the present invention. A power-on reset circuit 220 according to an exemplary embodiment may include a current source 230 , a capacitor 240 , a regulated voltage supply 250 , and a power sensitive comparator 260 .

Current source 230 outputs a constant current to capacitor 240 through node 235 while power is supplied to power-on reset circuit 220 through input power supply VDD. In one embodiment, the current output by the current source 230 is a constant current, and it is preferable that the size of the current is sufficiently small. Accordingly, the charging rate of the capacitor 240 is reduced to reduce the power-on reset target circuit ( In 290), the power-on reset can be performed for a sufficient period of time.

Capacitor 240 has one terminal connected to the output terminal of current source 230 at node 235 and the other terminal to ground. The capacitor 240 may be charged by the current supplied by the current source 230 . Accordingly, the voltage Vc across the capacitor, that is, the potential of the node 235 gradually increases immediately after power is applied to the power-on reset circuit 220 .

The regulated voltage supply 250 generates a level-adjusted power voltage VDD1 from the input power voltage VDD and supplies it to the power sensitive comparator 260 . The adjusted power supply voltage VDD1 is used to change the decision criterion of the power sensitive comparator 260, and the level of the level adjusted power supply voltage VDD1 has a smaller value than the input power voltage VDD. The specific magnitude of the level-adjusted power supply voltage VDD1 may vary depending on the system 200 or the power-on reset target circuit 290 . In one embodiment, the regulated voltage supply 250 may be implemented by a voltage divider circuit comprising a plurality of resistors.

The power sensitive comparator 260 receives the voltage Vc across the capacitor as an input, compares the voltage across the capacitor Vc with a constant reference voltage, and outputs a reset signal V _RESET whose level varies according to the comparison result. The reset signal (V _RESET ) may be an active-low signal, has a value of 0 volts (V) when the voltage (Vc) across the capacitor is lower than the reference voltage, and has a value of 0 volts (V) when the voltage (Vc) across the capacitor is higher than the reference voltage. You can have a high level.

FIG. 4 is a waveform diagram for explaining the operation of the power-on reset device of FIG. 3 .

Referring to FIG. 4 , a current source 230 supplies a constant current to the capacitor 240 while power is supplied to the power-on reset circuit 220 through the input power source VDD. The capacitor 240 is charged by the current supplied by the current source 230, and accordingly, the voltage Vc across the capacitor gradually increases immediately after power is applied to the power-on reset circuit 220. At this time, the voltage across the capacitor (Vc) can be expressed by Equation 1.

Here, C represents the capacitance value of the capacitor 240, i represents the current value input to the capacitor 240, and t represents time.

In general, a comparator circuit has a feature in which a comparison reference voltage changes according to a power supply voltage level. According to an exemplary embodiment of the present invention, since the power-sensitive signal comparator 260 is biased by the level-adjusted power supply voltage VDD1 supplied from the regulated voltage supply 250, the level-unregulated power supply voltage ( Compared to the case of being biased with VDD), the comparison reference voltage is reduced. Accordingly, when the power-on reset circuit 220 is biased by the high-level supply voltage VDD, the comparison operation is performed using a relatively large comparison reference voltage, and the power-on reset circuit 220 performs a comparison operation when the power-on reset circuit 220 has a low level. When biased by the level-adjusted power supply voltage VDD1, a comparison operation is performed using a relatively small comparison reference voltage.

According to an exemplary embodiment of the present invention, the power-sensitive signal comparator 260 compares the voltage Vc across the capacitor using a reference signal that varies according to the applied bias voltage VDD1. As mentioned above, when the output current of the current source 230 is reduced for stable power-on reset, the power-on reset period can be set sufficiently based on the slowly or unstablely increasing voltage Vc across the capacitor, The bias voltage VDD1 applied to the power sensitive signal comparator 260 may be set lower than the ideal voltage VDD. The regulated voltage supply 250 supplies a bias voltage VDD1 for enabling the comparison reference voltage of the power sensitive signal comparator 260 to have an appropriate value to a bias terminal of the power sensitive signal comparator 260 .

Accordingly, as shown in FIG. 4 , when the output current of the current source 230 is small so that the voltage across the capacitor (Vc) increases slowly or the level after the increase is small, the comparison criterion used by the power sensitive signal comparator 260 Since the voltage is also reduced, the power-on reset period can be reliably ended while the time length of the power-on reset period is sufficiently secured. Through this operation, the power-on reset circuit 220 according to the present invention can provide a more stable power-on reset function for the power-on reset target circuit 290 even if there is leakage current due to miniaturization of the semiconductor process. there will be

In addition, according to an exemplary embodiment, a separate complicated circuit or a separate control signal is not used to change the comparison reference voltage of the power sensitive comparator 260, but is input by the regulated voltage supply 250 having a simple structure. Since the level-adjusted power supply voltage VDD1 is generated from the power supply voltage VDD, the circuit structure can be simplified. Due to this structural simplification, there are additional advantages of minimizing the semiconductor area and reducing power consumption.

5 is a circuit diagram of one embodiment of a power sensitive comparator 260. In this embodiment, the power sensitive comparator 260 may be implemented to include a CMOS inverter circuit including a pMOS transistor M1 and an nMOS transistor M2.

)은 수학식 2로 표현될 수 있다. 수학식 2에서 보듯이, 스위칭 포인트 전압(

)은 반도체 공정 파라미터와 반도체 소자의 크기뿐만 아니라 CMOS 인버터에 인가되는 전원전압(

크기에 의해서도 달라지게 된다. 따라서, CMOS 인버터에 인가되는 전원전압(

의 크기를 조정함으로서 인버터의 스위칭 포인트 전압(

)을 제어할 수 있고, 이러한 동작을 통하여 누설 전류 등으로 인하여 커패시터(230)의 양단 전압(Vc)이 일정 크기의 전압에 도달하지 못하게 되었을 때에도, 더 낮은 비교 기준 전압을 사용하여 정상적인 파워-온 리셋 기능을 수행할 수 있게 된다. In a CMOS inverter circuit, the switching point voltage (

) can be expressed as Equation 2. As shown in Equation 2, the switching point voltage (

) is the semiconductor process parameter and the size of the semiconductor device as well as the power voltage applied to the CMOS inverter (

It also varies by size. Therefore, the power supply voltage applied to the CMOS inverter (

By sizing the inverter's switching point voltage (

) can be controlled, and even when the voltage (Vc) across the capacitor 230 does not reach a certain voltage due to leakage current through this operation, normal power-on using a lower comparison reference voltage The reset function can be performed.

은 CMOS 인버터 내에 있는 nMOS 트랜지스터(M2)의 공정 파라미터와 크기로 결정되는 변수이고,

는 CMOS 인버터 내에 있는 pMOS 트랜지스터(M1)의 공정 파라미터와 크기로 결정되는 변수이다.

은 CMOS 인버터 내에 있는 nMOS 트랜지스터(M2)의 문턱 전압을 나타내고,

은 CMOS 인버터 내에 있는 pMOS 트랜지스터(M2)의 문턱 전압을 나타내며, VDD1은 레벨조정된 바이어스 전압이다.In Equation 2,

is a variable determined by the process parameters and size of the nMOS transistor M2 in the CMOS inverter,

is a variable determined by the process parameters and size of the pMOS transistor M1 in the CMOS inverter.

represents the threshold voltage of the nMOS transistor M2 in the CMOS inverter,

represents the threshold voltage of the pMOS transistor M2 in the CMOS inverter, and VDD1 is the level-adjusted bias voltage.

6 is a circuit diagram of another embodiment of a power sensitive comparator 260. In this embodiment, power sensitive comparator 260 may be implemented to include a Schmitt-trigger circuit.

) 레벨이 일반적으로 2개(즉,

,

) 존재한다. 일반적인 CMOS 인버터 회로의 경우, 스위칭 포인트 전압(

)이 일반적으로 바이어스 전압의 1/2배 되는 레벨에서 형성되는데 반하여, 슈미트-트리거 회로는 상기 2개의 스위칭 포인트 전압(

,

) 레벨이 각각 바이어스 전압의 1/2배되는 레벨보다 더 크거나 더 낮게 설정될 수 있다는 특징을 가진다.Unlike the CMOS inverter circuit shown in FIG. 5, the Schmitt-trigger circuit shown in FIG. 6 changes the state of the output signal, that is, the reset signal VRESET, at a switching point voltage (

) levels are usually two (i.e.

,

) exist. For a typical CMOS inverter circuit, the switching point voltage (

) is generally formed at a level that is 1/2 times the bias voltage, whereas the Schmitt-trigger circuit is formed at the two switching point voltages (

,

) level can be set higher or lower than the level that is 1/2 times the bias voltage, respectively.

,

)은 수학식 3과 수학식 4로 각각 표현될 수 있다.The switching point voltage of the Schmitt-trigger circuit shown in FIG. 6 (

,

) can be expressed as Equations 3 and 4, respectively.

은 슈미트-트리거 회로 내 pMOS 트랜지스터(M11)의 공정 파라미터와 크기로 결정되는 변수이고,

은 nMOS 트랜지스터(M13)의 공정 파라미터와 크기로 결정되는 변수이며,

는 pMOS 트랜지스터(M15)의 공정 파라미터와 크기로 결정되는 변수이고,

은 nMOS 트랜지스터(M16)의 공정 파라미터와 크기로 결정되는 변수이며,

은 nMOS 트랜지스터들(M13, M14, M16)의 문턱 전압이고,

는 pMOS 트랜지스터들(M11, M12, M15)의 문턱 전압이며,

은 레벨조정된 바이어스 전압을 나타낸다.In Equations 3 and 4,

is a variable determined by the process parameters and size of the pMOS transistor M11 in the Schmitt-trigger circuit,

is a variable determined by the process parameters and size of the nMOS transistor M13,

Is a variable determined by the process parameters and size of the pMOS transistor M15,

is a variable determined by the process parameters and size of the nMOS transistor M16,

Is the threshold voltage of the nMOS transistors M13, M14, and M16,

Is the threshold voltage of the pMOS transistors M11, M12, and M15,

represents the level-adjusted bias voltage.

는 반도체 공정 파라미터와 소자의 크기뿐만 아니라 슈미트-트리거 회로에 인가되는 레벨조정된 바이어스 전압(

) 크기에 의해서도 영향을 받게 됨을 알 수 있다. 따라서, 슈미트-트리거 회로의 바이어스 전압(

)의 크기를 조정함으로서

를 추가적으로 더 제어를 할 수 있게 된다. Looking at Equation 3, the high switching point voltage of the Schmitt-trigger circuit is

is the semiconductor process parameter and device size as well as the level-adjusted bias voltage applied to the Schmitt-trigger circuit (

) is also affected by the size. Therefore, the bias voltage of the Schmitt-trigger circuit (

) by scaling

gives you more control.

역시 비슷한 것을 확인할 수 있으며,

경우와 마찬가지로, 바이어스 전압(

)의 크기를 조정함으로서

를 추가적으로 더 제어할 수 있게 된다.Looking at Equation 4, the low switching point voltage of the Schmitt-trigger circuit is

You can also see something similar

As in the case, the bias voltage (

) by scaling

gives you more control.

In general, a constant power voltage is supplied to a semiconductor integrated circuit (IC), but in a system in which the IC is actually used, an error may occur in the power voltage supplied to the IC. In addition, the power supply voltage inside the IC may vary internally depending on the device temperature, load, etc., and deviation between devices may also have an effect due to process deviation due to miniaturization of the semiconductor process and decrease in device size. Accordingly, even if, for example, the power supply voltage applied to the IC is designed to be 1 volt (V), a significant error, for example, an error of about ±10% may occur in an actual system. A factor that causes the variation of the power supply voltage is also referred to as a PVT (process, voltage, temperature) variation factor.

Due to such an error in the power supply voltage, the power supply voltage of the same level cannot always be applied even to the power-on reset device, and the power supply voltage may fluctuate. According to an exemplary embodiment of the present invention, for example, even if the power distribution ratio is fixed because the regulated voltage supply is a voltage divider composed of a plurality of resistors having fixed resistance values, the input power supply voltage is, for example, 0.9V or 1.0V. When V differs from 1.1V, the switching reference voltage of the comparator circuit changes. As the reference voltage of the power sensitive comparator fluctuates in response to the input power voltage, the possibility that the power-on reset may not properly be performed depending on the input power voltage can be greatly reduced.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. You will understand that you can.

Claims (1)

A power-on reset device supplying a reset signal to a power-on reset target circuit to power-on reset the power-on reset target circuit,
a current source supplying a charging current in response to a power supply voltage;
a capacitor charged by the charging current and outputting a charging voltage corresponding to the charging amount;
a regulated voltage supply that adjusts the level of the power supply voltage to generate a level-adjusted power supply voltage; and
a power sensitive comparator that is biased with the level-adjusted power supply voltage, receives the charging voltage, compares it with a predetermined reference voltage, and outputs the reset signal activated during a time period when the charging voltage is smaller than the reference voltage;
A power-on reset device comprising a.

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