KR20230060736A - A Memory Tester with a BOST Board - Google Patents

Abstract

The test device may include a test head, a BOST board, and a socket board. The test head receives a test command from a server computer and generates a plurality of test control signals based on the test command. A test processor of the BOST board generates test signals for operation of a semiconductor device based on the plurality of test control signals and transmits the test signals to the semiconductor device through first and second terminals connected to the socket board. Therefore, a TS signal line can be shorter than before, thereby reducing manufacturing costs of the test device.

Description

Semiconductor test device including BOST board {A Memory Tester with a BOST Board}

The present invention relates to a test device, and relates to a test device using a BOST capable of testing a memory device.

After a memory semiconductor is manufactured on a wafer, diced, and packaged, it undergoes various tests through a test device.

A conventional test device includes a relay control unit capable of switching between a DC test mode and a function test mode. While the relay control unit can optimize the DC test and function test environment and allows connection to the termination unit, there is a problem in which replacement is impossible. This made it cumbersome to replace the device adjacent to the relay control unit.

KR 10-2195256

Embodiments of the present invention may provide a test apparatus and system capable of generating control signals required for operation of a semiconductor device on a BOST board and accurately transmitting the control signals to a device under test (DUT) to be tested.

An embodiment of the present invention divides the relay control unit into a first relay unit and a second relay unit to enable smooth replacement of the BOST board.

Embodiments of the present invention may provide a test apparatus and system capable of optimizing functional test and DC test environments.

A test apparatus according to an embodiment of the present invention includes a test head receiving a test command from a server computer and generating a plurality of test control signals based on the test command; and a BOST board generating a test signal for operating the semiconductor device based on the plurality of test control signals and providing the test signal to the semiconductor device.

In an embodiment of the present invention, the BOST board for generating the test signal having a variety of patterns based on the test control signal; and a socket board electrically connected to the BOST board, including at least one terminal, and providing the test signal received through the at least one terminal to the semiconductor device.

In an embodiment of the present invention, the test head may include a first relay unit that connects the at least one terminal to the test head in response to the relay control signal TSS during a DC test operation of the semiconductor device.

In an embodiment of the present invention, the socket board may include the second relay unit for terminating one or more terminals in response to at least the relay control signal TSS in a function test operation of the semiconductor device.

The embodiment of the present invention can reduce the manufacturing cost of the test device because the TS signal line is shorter than before.

According to the embodiment of the present invention, the accuracy of the signal is maintained by the termination unit of the second relay unit, thereby increasing the accuracy of the test.

Embodiments of the present invention can increase the degree of freedom of the test because it is easy to replace the BOST board.

In an embodiment of the present invention, when replacing a BOST board, the number of replacement relays may be reduced compared to before.

1 is a view showing the configuration of a test device according to an embodiment of the present invention;
FIG. 2 is a diagram showing configurations of a test communication control unit, a first relay unit, and a second relay unit shown in FIG. 1 .

In FIG. 1 , a test system according to an embodiment of the present invention may include a test head 100 , a BOST board 210 and a socket board 230 . The BOST board 210 may be electrically connected to the test head 100. A semiconductor device to be tested (Device Under Test, DUT) may be electrically connected to the socket board 230 . A plurality of semiconductor devices may be electrically connected to the socket board 230 , and the test system may simultaneously perform tests on a plurality of semiconductor devices.

The test head 100 may include a communication board 110 and a programmable power supply board 120 . The communication board 110 may communicate with the server computer 310 . The communication board 110 may generate a plurality of test control signals according to a test command received from the server computer 310 . The communication board 110 may receive a test command for performing a test of the semiconductor device from the server computer 310, and provide a test control signal generated according to the test command to the BOST board 210. can do.

The programmable power supply board 120 may receive power from the power supply 320 and generate internal power used in the semiconductor device. The programmable power supply board 120 may generate a plurality of internal power sources having different voltage levels. For example, the programmable power supply board 120 may generate various internal power sources such as a high voltage power source, a reference voltage power source, and a low voltage power source used to operate the semiconductor device.

The BOST board 210 may receive the test control signal from the test head 100 and generate the test signal, which is actually a control signal necessary for the operation of the semiconductor device. The BOST board 210 may generate the test signal having various patterns according to the test control signal.

The test head 100 may receive a test command TCOM from the server computer 310 and may feed back a test result of a semiconductor device to be tested to the server computer 310 . Also, the test head 100 may receive power from the power supply 320 .

The test head 100 may include a communication board 110 . The communication board 110 may relay communication between the server computer 310 and the BOST board 210 . The communication board 110 may include a test communication control unit 111 , a DC test unit 112 , and a first relay unit 221 . The test communication controller 111 may receive the test command TCOM and generate the plurality of test control signals TCS. For example, the test communication controller 111 may decode the test command TCOM to generate the test control signal TCS. Also, the test communication control unit 111 may generate a relay control signal (TSS) indicating what type of test is performed on the semiconductor device by the DC test unit 112 . The relay control signal TSS may be a part of the test control signal TCS and may be generated by the test communication controller 111 based on a test command TCOM from the server computer 310 . The test device enables a function test operation and a DC test operation of the semiconductor device to be performed. The function test operation may be for testing a normal operation of the semiconductor device, and the DC test operation may be for testing whether an electrical connection between the semiconductor device and the test device is well established. Accordingly, the DC test operation may be performed prior to the functional test operation.

The test head 100 may include the first relay unit 221 . The first relay unit 221 may receive the relay control signal TSS from the test head 100 .

The test head 100 may include a programmable power supply board 120, and the programmable power supply board 120 may be configured as a programmable power supply. The programmable power supply may receive power from the power supply 320 and generate internal power having various voltage levels from the received power.

The BOST board 210 may include a test processor 211 . The test processor 211 may receive a plurality of test control signals TCS from the test head 100 and generate test signals TS having various patterns according to the plurality of test control signals TCS. there is. Also, the test processor 211 may convert the test signal TS into a signal suitable for use in the semiconductor device. In an embodiment of the present invention, the test command TCOM and the test control signal TCS may be low frequency signals, and the test signal TS may be a higher frequency signal than the test command TCOM and the test control signal TCS. can Therefore, an expensive and sophisticated cable may not be required to transmit the test command TCOM and the test control signal TCS, and an expensive and sophisticated cable may be required to transmit the test signal TS. The test signal TS may be one or more control signals used in the operation of the semiconductor device to be tested. For example, the test signal may include a command signal, an address signal, and data.

The socket board 230 may include at least one terminal and a second relay unit 222 . The at least one terminal may receive the test signal TS from the test processor 211 and may be connected to the semiconductor device to be tested to transmit the test signal TS to the semiconductor device. In FIG. 1 , the at least one terminal may include a first terminal 231 and a second terminal 232 . For example, the first terminal 231 may receive a command signal CMD among the test signals TS generated by the test processor 211, and the second terminal 232 may receive the test processor ( 211), data DQ among the test signals TS generated may be received. The first terminal 231 may be connected to a command terminal of the semiconductor device to provide the command signal CMD to the semiconductor device. Also, the second terminal 232 may be connected to a data terminal included in the semiconductor device to provide the data DQ to the semiconductor device.

The first relay unit 221 and the second relay unit 222 may be connected between the test head 100 and the first and second terminals 231 and 232 . Specifically, the first relay unit 221 and the second relay unit 222 may be connected to the DC test unit 112 of the communication board 110 . The first relay unit 221 and the second relay unit 222 optimize the environment according to the test operation performed by the first and second terminals 231 and 232 in response to the test operation mode signal TSS. can have For example, when the function test operation is performed, the first relay unit 221 turns off the switch and connects the DC test unit 112 to the first and second terminals 231 and 232. and the second relay unit 222 may terminate the first and second terminals 231 and 232 by turning on the switch. The first and second terminals 231 and 232 may be impedance matched to a command terminal and a data terminal of the semiconductor device through termination of the second relay unit 222 . Accordingly, the first relay unit 221 and the second relay unit 222 enable the command signal CMD and data DQ generated by the test processor 211 to be accurately transmitted to the semiconductor device. When the DC test operation is performed, the second relay unit 221 turns off the switch and does not terminate the first and second terminals 231 and 232, and the first relay unit 221 switches is turned on so that the first and second terminals 231 and 232 can be connected to the DC test unit 112 .

The socket board 230 may further include at least one voltage terminal. In FIG. 1 , the at least one voltage terminal may include a first voltage terminal 233 and a second voltage terminal 234 . For example, the first voltage terminal 233 receives a first internal power generated by a programmable power supply of the power supply board 120 and is a first power terminal included in the semiconductor device, and receives the first voltage terminal 233 . Internal power can be supplied. The second voltage terminal 234 may receive the second internal power generated by the programmable power supply and supply the second internal power to a second power terminal included in the semiconductor device. The first internal power supply and the second internal power supply are each selected from a pumping voltage (VPP), a power supply voltage (VDD), a high voltage such as the data power supply voltage (VDDQ), a low voltage such as the bulk bias voltage (VBB), and a reference voltage (VREF). It can be any one.

2 is a diagram showing the configuration of the test communication control unit 111, the first relay unit 221 and the second relay unit 222 shown in FIG. The first relay unit 221 and the second relay unit 222 may receive the relay control signal from the test communication control unit 111 . However, since the first relay unit 221 and the second relay unit 222 cannot simultaneously receive the relay control signal due to their physical locations, the test communication control unit 111 uses the TSS signal timing correction unit 111a separately provided so that the first relay unit 221 and the second relay unit 222 can simultaneously receive the relay control signal. The second relay unit 222 may connect the first and second terminals 231 and 232 to a termination resistance RTT and a termination voltage VTT, respectively, in response to the relay control signal TSS. The first relay unit 221 may connect the first and second terminals 231 and 232 to the DC test unit 112 in response to the relay control signal TSS. The relay control signal TSS may be enabled when the function test operation is performed, and the relay control signal TSS may be disabled when the DC test operation is performed. The second relay unit 222 may connect the first and second terminals 231 and 232 to the termination resistance RTT and termination voltage VTT when the relay control signal TSS is enabled, , The first relay unit 221 may connect the first and second terminals 231 and 232 to the DC test unit 112 when the relay control signal TSS is disabled. When the relay control signal TSS is enabled, the second relay unit 222 connects the first and second terminals 231 and 232 to a termination resistor RTT and a termination voltage VTT to The semiconductor device can accurately receive the test signal TS generated by the BOST board 210 . In addition, when the relay control signal TSS is disabled, the first relay unit 221 does not form any other electrical connection between the first and second terminals 231 and 232 and the DC test unit. 112 to form an electrical connection between them so that an accurate DC test operation can be performed.

When the test device and system are prepared and the semiconductor device to be tested is electrically connected to the socket board 230 of the test device, the first relay unit 221 and the second relay unit 221 are connected according to the relay control signal TSS. The relay unit 222 may connect the first and second terminals 231 and 232 of the socket board 230 to the DC test unit 112 of the test head 100 . The DC test unit 112 measures the current and voltage output through the first and second terminals 231 and 232 while supplying current or voltage, so that the first and second terminals 231 and 232 are It is possible to check whether or not the terminal of the semiconductor device is normally connected, that is, whether or not the semiconductor device is normally connected to the socket board 230 . A measurement result (PMR) of the DC test unit 112 is fed back to the server computer 310 through the test communication control unit 111, and an electrical connection between the semiconductor device and the test device may be confirmed. Thereafter, the test communication controller 111 provides the test control signal TCS to the test processor 211 of the BOST board 210 according to the test command TCOM from the server computer, and the relay control signal (TSS) can be enabled. The second relay unit 222 terminates the first and second terminals 231 and 233 in response to the relay control signal TSS, and the test processor 211 terminates the test control signal TCS. The command signal CMD and the data DQ generated based on ) may be provided to the first and second terminals 231 and 232 . The semiconductor device receives the command signal CMD and data DQ through the first and second terminals 231 and 232, and receives the first and second voltage terminals 233 and 234 through the first and second voltage terminals 233 and 234. 2 It can perform normal operation by receiving internal power. In the embodiment of the present invention, the test communication control unit 111 of the test head 110 communicates with the server computer 310 and transmits the test command TCOM received from the server computer 310 to the test control signal TCS. ) is provided to the test processor 211 of the BOST board 210. The test communication controller 111 and the test processor 211 may be connected by a cable. The test command (TCOM) and the test control signal (TCS) are low-frequency signals and do not require sophisticated cables for signal transmission. The test signal TS generated by the test processor 211, that is, the command signal CMD and the data DQ are actually signals used to communicate with the semiconductor device, and thus have a high frequency. Accordingly, an expensive and sophisticated cable is required to transmit the command signal CMD and the data DQ. However, since the BOST board 210 is directly adjacent to the socket board 230, the length of a cable for transmitting the command signal CMD and data DQ, which are high frequency signals, may be shortened. The test device according to an embodiment of the present invention may change the socket board 230 among the components of the test device to test another semiconductor device using the same or similar interface signal as the semiconductor device being tested. In addition, the test device may change the socket board 230 and the BOST board 210 among the components of the test device to test a semiconductor device currently being tested and a heterogeneous semiconductor device requiring a different interface signal. Therefore, even if the structure of the test head 100 is not changed, the test apparatus can be compatible with tests of various types of semiconductor devices.

The BOST board 210 is located between the ATE and the DUT to increase the number of channels, expand the number of simultaneous paras, and multiply the ATE signal at high speed to improve specifications and performance of existing ATE equipment.

According to an embodiment of the present invention, since the replacement of the BOST device becomes simpler than before, the engineer's management becomes easier. In addition, various types of DUT inspections can be performed with the same device and system only by improving the inside of the BOST device.

Those skilled in the art to which the present invention pertains should understand that the embodiments described above are illustrative in all respects and not limiting, since the present invention can be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. only do The scope of the present invention is indicated by the following claims rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

100: test head / 110: communication board / 111: test communication control unit / 112: DC test unit / 221: 1st relay unit (DC relay unit) / 222: 2nd relay unit (termination relay unit) / 120: programmable power supply
210: BOST board / 211: test processor
230: socket board / 231: first terminal (CMD signal terminal) / 232: second terminal (DQ signal terminal) / 233: first voltage terminal / 234: second voltage terminal
310: server computer / 320: power supply
111: test communication control unit / 111a: TSS signal timing correction unit
221: 1st relay unit (DC relay unit) / 222: 2nd relay unit (termination relay unit)
231: 1st terminal (CMD signal terminal) / 232: 2nd terminal (DQ signal terminal)

Claims (12)

a test head that receives a test command from the server computer and generates a plurality of test control signals based on the test command; and
a BOST board generating test signals for operation of the semiconductor device based on the plurality of test control signals and providing the test signals to the semiconductor device;
and a socket board electrically connected to the BOST board, including at least one terminal, and providing the test signal received through the at least one terminal to the semiconductor device. According to claim 1,
The test head includes a communication board communicating with the server computer and the BOST board;
The communication board includes a test communication control unit configured to receive the test command from the server computer and generate the plurality of test control signals; and
a DC test unit connected to the first relay unit and the second relay unit, measuring current or voltage output from the relay units, and providing a measurement result to the test communication control unit; and
and the first relay unit connecting the at least one terminal to the test head in response to a relay control signal from the test communication control unit. According to claim 2,
wherein the test communication controller feeds back the measurement result to the server computer and generates the relay control signal (TSS) based on the test command. According to claim 3,
The test communication control unit includes a TSS signal timing correction unit capable of transmitting a relay control signal to the first relay unit and the second relay unit,
The TSS signal timing correction unit reduces a timing delay generated when the relay control signal is transmitted to the first relay unit and the second relay unit. According to claim 2,
The first relay unit connects the at least one terminal to the test head in response to the relay control signal TSS during a DC test operation of the semiconductor device. According to claim 1,
The test head includes a programmable power supply supplying a plurality of internal powers having different voltage levels to the socket board. According to claim 1,
wherein the BOST board includes a test processor configured to generate the test signal based on the test control signal. According to claim 7,
The BOST board processes and multiplies signals transmitted for testing and performs a DUT test at the multiplied data rate. According to claim 7,
The test processor may include an algorithm pattern generator generating pattern signals having various patterns based on the test control signal; and
and an output driver configured to generate the test signal by adjusting the pulse width and amplitude of the pattern signal. According to claim 7,
The test processor is a test device that is an application-specific semiconductor chip. The socket board includes a second relay unit connecting the at least one terminal to a termination terminal,
The second relay unit terminates the at least one terminal in response to the relay control signal (TSS) in a function test operation of the semiconductor device. According to claim 1,
The semiconductor device is connected to the socket board and receives the test signal from the at least one terminal.

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