KR20230052434A - Test method and switch ic using logical identification - Google Patents

Abstract

The present invention relates to a test method performed by at least one switch IC including multiple channels, each of which is connected to a device under test (DUT), and multiple cores including the multiple channels, respectively. The test method comprises the steps of: allocating an identical logical ID (LID) to cores connected to the DUT, which are tested together; and outputting an active control signal for each allocated logical identifier. Accordingly, a time required to perform a test can be reduced.

Description

TEST METHOD AND SWITCH IC USING LOGICAL IDENTIFICATION}

The present invention relates to a test method and a switch IC capable of improving the mass productivity of semiconductors, and more particularly, to a test method and a switch IC capable of improving the mass productivity of semiconductors using logical identifiers.

Mass productivity is a very important factor in the production of semiconductor devices, of which test costs account for a large portion. As the degree of integration of semiconductor devices increases, the time required to test one wafer increases, and the increase in test time entails an increase in test cost.

Therefore, it is required to reduce the test time, and for this purpose, the test equipment measures a plurality of semiconductor devices at the same time, thereby reducing the test time per device. On the side of testing semiconductor devices, equipment with as many channels for measurement as possible is required, but the price of the equipment increases as the number of channels increases.

The number of channels required to satisfy an appropriate test time is rapidly increasing due to the rapid increase in the level of integration of semiconductor devices. This trend requires frequent replacement of test equipment. Since replacing equipment is also part of the cost of testing, other solutions are needed to lower the cost of testing. To do this, a probe card is added between the equipment and the wafer to secure the number of channels required for measurement.

The probe card includes a number of analog muxes, and the multiplexers are connected to the measurement channels of the test equipment. During measurement, the device to be tested is connected to the analog multiplexer to test the device.

Analog multiplexers used in probe cards are largely divided into power supply (PMIC) and signal (switch IC), and multiplexers are DUT (device under test) and automatic test equipment (ATE) located on highly integrated wafer Since it performs the function of connecting , the required number per card is large. Usually, one IC includes a plurality of multiplexers, each collectively referred to as a channel. In general, one probe card can have thousands of channels or less.

Since multiple ICs share a line through which commands are transmitted, it is necessary to transmit as many commands as the number of objects to be controlled in order to control each channel of each IC in a desired form.

Each IC has a unique ID to designate the object to be controlled by sending a command. Each IC is connected with a physical pin and its ID is assigned, or written in a non-volatile memory to obtain its own ID whenever each IC is booted. In addition, each channel of the ICs is given a number so that the command can designate the target of control through the ID.

However, as described above, since commands must be transmitted for each target in order to operate numerous ICs as intended, it takes a long time to transmit commands for each control target IC, making it difficult to improve the throughput of semiconductor devices. .

The present invention is to solve the above-mentioned difficulties of the prior art, and to provide a command transmission method and IC for improving the throughput of a semiconductor device.

The present invention is a test method performed in one or more switch ICs including a plurality of channels each connected to a device under test (DUT) and a plurality of cores each including the plurality of channels, The test method includes: assigning the same logical ID (LID) to cores connected to the DUT to be tested together, and outputting an active control signal for each assigned logical ID.

According to one aspect of the present invention, at least some of the plurality of channels are power management ICs (PMICs) connected to power DUTs, and at least some of the plurality of channels are switch ICs connected to signal-related DUTs.

According to one aspect of the present invention, the channel is an analog multiplexer (analog MUX) connected to the DUT.

According to one aspect of the present invention, the test method further performs a step of allocating an identifier (ID) to each of the one or more switch ICs before the step of allocating the logical identifier.

According to one aspect of the present invention, one or more of the channels in the same core in the same switch IC, one or more of the channels in one or more different cores in the same switch IC and one or more different cores in one or more different switch ICs. At least any one or more of the one or more channels within the channel are assigned the same logical identifier.

The present invention is a switch IC, wherein the switch IC includes: a plurality of channels respectively connected to a plurality of DUTs; a plurality of cores each including the plurality of channels; and a command decoder for decoding a given command and controlling the channels according to the decoded command, wherein the switch IC performs a test control method, wherein the test control method: connects cores connected to the DUT with the same logic The method includes receiving and decoding a command allocated as an identifier (LID, logical ID), and controlling activation by outputting an activation control signal for each of the allocated logical identifiers.

According to one aspect of the present invention, at least some of the plurality of channels are power management ICs (PMICs) connected to power DUTs, and at least some of the plurality of channels are connected to signal-related DUTs.

According to one aspect of the present invention, the channel is an analog multiplexer (analog MUX) connected to the DUT.

According to one aspect of the present invention, one or more of the channels in the same core in the same switch IC, one or more of the channels in one or more different cores in the same switch IC and one or more different cores in one or more different switch ICs. At least any one or more of the one or more channels within the channel are assigned the same logical identifier.

According to one aspect of the present invention, the switch IC further includes a channel controller for controlling a channel in the core according to a command decoded by the command decoder.

According to one aspect of the present invention, the decoding step is performed by the command decoder, and the activating step is performed by the channel controller according to the decoded command.

According to the present invention, the number of commands transmitted to perform a test can be reduced. Therefore, it is possible to reduce the time required to perform the test, thereby providing an advantage that productivity of the semiconductor can be improved.

1 is a diagram showing the outline of a test method according to the present invention.
2 is a block diagram schematically showing a probe card 10 including a switch IC 100 according to the present invention.
3 is a diagram explaining the outline of a test method according to the prior art.
4 is a diagram for explaining a process of performing a test using the test method of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1 is a diagram showing the outline of a test method according to the present invention. Referring to FIG. 1, the test method is performed in one or more switch ICs including a plurality of channels connected to a device under test (DUT) and a plurality of cores each including the plurality of channels. and allocating cores connected to the DUT to be tested together with the same logical identifier (LID, logical ID) (S200), and outputting an active control signal for each allocated logical identifier (S300). include As an embodiment, the present invention may further perform the step of allocating an identifier (ID) to each of the one or more switch ICs (S100) before the step of allocating the logical identifier (S200). In one embodiment, the step of allocating the logical identifier may be performed several times according to circumstances.

2 is a block diagram schematically showing a probe card 10 including a switch IC 100 according to the present invention. Referring to FIG. 2, a switch IC 100 according to the present invention includes a plurality of channels (CH) connected to a plurality of DUTs, a plurality of cores (CORE) each including the plurality of channels, and provided commands. and a command decoder 110 that decodes and controls the channels according to the decoded command, wherein the switch IC 100 performs a test method, wherein the test method: cores connected to the DUT The method includes receiving and decoding a command assigned with the same logical ID (LID, logical ID), and controlling activation by outputting an activation control signal for each assigned logical ID.

As an embodiment, the switch IC 100 may further include a channel controller 120 that controls activation of a channel in the core according to a command decoded by the command decoder 110 .

The probe card 10 operates in connection with an automatic test equipment (ATE). The automatic test equipment (ATE) is a device that is electrically connected to the DUT and receives a signal from the DUT to determine whether or not there is a defect.

The control unit 200 receives a signal from the automatic test device (ATE) and forms a digital control command (CMD) corresponding to the signal provided by the automatic test device (ATE) to test a target DUT. Information about the mapping relationship between each channel of the CORE and the DUT is not transmitted to the automatic test equipment (ATE). Therefore, the control unit 200 converts the inspection command provided by the automatic test device (ATE) and forms a digital control command (CMD) so that the device under test (DUT) can be tested.

The command protocol of the automatic test equipment (ATE) is different from the protocol generally used in the probe card 10. Therefore, the control unit 200 interprets the test command provided by the automatic test device (ATE) according to the protocol of the automatic test device (ATE), and generates the control command (CMD) according to the command protocol used in the probe card 10. is formed and output to the switch IC 100. All of these processes are performed in the digital domain.

The control unit 200 receives a test command provided by the automatic test device (ATE) in its own protocol, forms a control command (CMD) corresponding thereto, and provides the control command (CMD) to the switch IC 100 to control the switch IC 100. do. As an example, the control command (CMD) provided by the control unit 200 may be provided to the switch IC 100 through an 8-bit line. For example, the control unit 200 may be implemented as a Field Programmable Gate Array (FPGA).

Each switch IC 100 may include a command decoder 110 and a core/channel controller 120. In the illustrated example, each switch IC 100 may be provided with an identifier (ID) such as 0, 1, 2, 3, etc. (S100), and the identifier (ID) is provided through a physical connection, or the switch IC 100 It can be obtained by reading the identifier written in the non-volatile memory during booting.

The command decoder 110 receives the digital control command (CMD) provided by the controller 200 and decodes it to control a channel (CH) in a target core (CORE) to be activated. In addition, the core/channel control unit 120 controls activation of cores and channels within the core according to commands decoded by the command decoder 110 .

In one embodiment, each channel (CH) in the core (CORE) includes an analog multiplexer. The channel CH is connected to a plurality of devices under test (DUT) through a plurality of channels. Each channel is controlled by the command decoded by the command decoder 110, and driving is controlled. Accordingly, a plurality of devices under test (DUT) may be inspected through the channel (CH).

In addition, the channel (CH) includes an analog circuit that performs a test by providing an analog signal provided by an automatic test device (ATE) to a device under test (DUT), and the analog circuit is an embodiment, It may include any one or more of a low dropout (LDO) regulator, a DC-DC converter, and an analog-to-digital converter.

In one embodiment, an analog signal provided to the DUT through the analog test circuit 300 is used to measure the characteristics of the DUT. For example, when measuring the amount of current consumed by the DUT, the automatic test equipment (ATE) measures the amount of current provided as an analog signal.

As another example, when testing whether the DUT operates properly while fine-tuning the DUT's power voltage, the automatic test equipment (ATE) adjusts and provides the voltage of the analog signal line connected to the automatic test equipment (ATE)'s power supply, detect the motion of

As another example, when measuring the leakage current in the input/output of the DUT, the automatic test equipment (ATE) measures the current leaked through the analog signal line connected to the input/output pin of the DUT.

In addition, in order to reduce the number of commands to be transmitted, power supply ICs and signal switch ICs provide various commands to support control of multiple channels with a small number of commands.

Hereinafter, an overview of a test method according to the prior art will be described with reference to FIG. 3 . This is purely to improve the understanding of the present invention through comparison with the present invention described with reference to FIG. 4 . In addition, the method described with reference to FIG. 3 is described as a prior art, but it was created by the present applicant but not disclosed, and is not easily invented by a person skilled in the art.

FIG. 3 is a diagram showing a test sequence, which illustrates that Test ①, Test ②, and Test ③ are performed in a switch IC having an identifier (ID) 0 and an identifier (ID) 1. Referring to FIG. 3, DUTs 1, 2, 3, ..., 8 are tested in Test ①, DUTs 289, 290, 291, ..., 296 are tested in Test ②, and DUT 577, 296 are tested in Test ③. Illustrates testing 578, 579, ..., 584.

In Test ①, to test DUT 1 and DUT 5, commands to activate CH0, CH1, CH2, CH4, CH5, CH6 of ID 0 switch IC, CORE 0 must be provided. Also, to test DUT 2 and DUT 6 in Test ①, commands to activate CH0, CH1, CH2, CH4, CH5, and CH6 of ID 0 switch IC and CORE 4 must be provided.

Similarly, to test DUT 3 and DUT 7 in Test ①, commands to activate CH0, CH1, CH2, CH4, CH5, and CH6 of ID #1 switch IC, CORE 0 must be provided, and DUT 4 and DUT 8 To test, a command must be provided to activate CH0, CH1, CH2, CH4, CH5, CH6 of ID #1 switch IC, CORE 4.

That is, four commands must be provided in Test ①, and a total of 12 commands must be provided to complete Test ①, Test ②, and Test ③.

Hereinafter, a process of performing a test by the test method of the present invention will be described with reference to FIGS. 1, 2 and 4. Cores connected to the DUT to be tested together are assigned the same logical identifier (LID) (S200).

In one embodiment, the step of allocating the logical identifier may be performed several times according to circumstances.

In the example illustrated by FIG. 4, DUTs 1, 2, 3, ..., 8 are tested together in Test 1, and therefore are assigned the same logical identifier LID 1. Subsequently, since DUTs 289, 290, 291, ..., 296 are tested together in Test ②, they are assigned the same logical identifier LID 2. Similarly, DUTs 577, 578, 579, ..., 584 are assigned the same logical identifier LID 3 as they are tested together in Test ③.

A test may be performed by controlling activation/deactivation of DUTs assigned with the same logical identifier by providing an activation control signal (S300).

According to the illustrated example, the same core (CORE) within the same switch IC and a plurality of channels within the same core may be assigned a single logical identifier, and channels within different cores (CORE) within the same switch IC may be assigned a single logical identifier. , and channels in a plurality of different switch ICs can be assigned with a single logical identifier.

If allocated according to the present invention, it is sufficient to send a command only once to control the activation of channels of a corresponding logical identifier for each test item, and as a result, it is sufficient to send 3 commands for 3 test items. As described above, according to the present invention, it can be seen that as the number of tests increases, fewer CMDs are required compared to the prior art, thereby providing an advantage in that high productivity can be secured.

According to the present invention, it is possible to reduce the time required for testing by using a minimum number of commands by simplifying DUT mapping. That is, even if the number of DUTs increases and the number of switch ICs increases, in the case of a logical identifier, if the same ID is assigned, it can be controlled simultaneously, so the number of commands does not increase significantly, reducing the time required for testing.

There are various constraints such as the number of DUTs, the number of power supplies and shared resources used to configure the map of the prior art probe card, and due to these constraints, the contents to be stored when programming the control unit increase, The problem of the capacity of the included memory is growing.

That is, if the program size is excessively large, a memory capacity problem may occur and additional memory may be required. disadvantageous in terms of cost.

However, according to the present invention, since the contents to be stored are reduced and the size of the program can be reduced by simplifying, the need for an additional memory and an additional control unit is reduced.

Although it has been described with reference to the embodiments shown in the drawings to aid understanding of the present invention, this is an embodiment for implementation and is only exemplary, and those having ordinary knowledge in the field can make various modifications and equivalents therefrom. It will be appreciated that other embodiments are possible. Therefore, the true technical scope of protection of the present invention will be defined by the appended claims.

10: probe card
100: switch IC
110: command decoder
120: core/channel control

Claims (11)

A test method performed in one or more switch ICs including a plurality of channels each connected to a device under test (DUT) and a plurality of cores each including the plurality of channels, the test method silver:
Allocating cores connected to the DUT to be tested together with the same logical identifier (LID, logical ID);
and outputting an active control signal for each of the assigned logical identifiers.
According to claim 1,
At least some of the plurality of channels are power management ICs (PMICs) connected to power DUTs,
At least some of the plurality of channels are switch ICs connected to signal-related DUTs.
According to claim 1,
the channel
A test method that is an analog multiplexer (analog MUX) connected to the DUT.
According to claim 1,
The test method is
Prior to the step of assigning to the logical identifier
The test method further performing the step of allocating an identifier (ID) to each of the one or more switch ICs.
According to claim 1,
one or more of the channels within the same core within the same switch IC;
one or more of the channels in one or more of the different cores in the same switch IC, and
A test method in which at least any one or more of the one or more channels in the core in the one or more different switch ICs are assigned the same logical identifier.
With a switch IC, the switch IC:
a plurality of channels respectively connected to a plurality of DUTs;
a plurality of cores each including the plurality of channels;
a command decoder for decoding a given command and controlling the channels according to the decoded command;
The switch IC performs a test control method, and the test control method:
Receiving and decoding a command assigned to cores connected to the DUT with the same logical identifier (LID, logical ID);
and controlling activation by outputting an activation control signal for each of the assigned logical identifiers.
According to claim 6,
At least some of the plurality of channels are power management ICs (PMICs) connected to power DUTs,
At least some of the plurality of channels are switch ICs connected to signal-related DUTs.
According to claim 6,
the channel
A switch IC that is an analog multiplexer (analog MUX) connected to the DUT.
According to claim 6,
one or more of the channels within the same core within the same switch IC;
one or more of the channels in one or more of the different cores in the same switch IC, and
A switch IC in which at least one or more of the one or more channels in the core in one or more different switch ICs are assigned the same logical identifier.
According to claim 6,
The switch IC,
A switch IC further comprising a channel controller controlling a channel in the core according to a command decoded by the command decoder.
According to claim 10,
The decoding is performed by the command decoder,
The step of controlling the activation is performed by the channel controller according to the decoded command.

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