CN110544505A

CN110544505A - test system and method for screening poor Die in Wafer

Info

Publication number: CN110544505A
Application number: CN201910802816.9A
Authority: CN
Inventors: 杨林英; 陈道华
Original assignee: Shenzhen Union Memory Information System Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2019-08-28
Filing date: 2019-08-28
Publication date: 2019-12-06
Anticipated expiration: 2039-08-28
Also published as: CN110544505B

Abstract

The application relates to a test system, a method, a computer device and a storage medium for screening bad Die in Wafer, wherein the system comprises: the test system comprises a test host, a transmission card, a plurality of test cards and a probe card; the test host is communicated with the transmission card through a serial port and is used for obtaining the test result of each test channel on each test card; the transmission card is used for supplying power to the plurality of test cards, and the plurality of test cards are communicated with the test host through serial ports of the transmission card; the test card can be used to test a plurality of channels, and the signal and power on each channel are connected to the corresponding Wafer to be tested through the probe card. The test system and the test method can be directly applied to an automation platform, can realize automatic test of a plurality of channels, and can effectively improve the test efficiency.

Description

Test system and method for screening poor Die in Wafer

Technical Field

The invention relates to the technical field of solid state disks, in particular to a test system and method for screening bad Die in Wafer, computer equipment and a storage medium.

Background

at present, Wafer is also called Wafer, which refers to a silicon Wafer used for manufacturing silicon semiconductor integrated circuits, and is called Wafer because its shape is circular; various circuit element structures can be processed on a silicon wafer to form an integrated circuit product with specific electrical functions. The Wafer is the most used in the company and has wide application, and if the purchased Wafer can be tested and screened to be bad, the yield of finished products can be improved, the cost can be saved, and the manufacturing and testing period can be shortened.

In the traditional technology, a plurality of tools for manually testing Wafer are available on the market, but the manual testing is very inefficient, and the actual production needs cannot be met.

disclosure of Invention

in view of the above, it is necessary to provide a test system, a method, a computer device and a storage medium for screening bad Die in Wafer, which can improve test efficiency.

a test system for screening Wafer for undesirable Die, the system comprising: the test system comprises a test host, a transmission card, a plurality of test cards and a probe card;

the test host is communicated with the transmission card through a serial port and is used for obtaining the test result of each test channel on each test card;

the transmission card is used for supplying power to the plurality of test cards, and the plurality of test cards are communicated with the test host through serial ports of the transmission card;

The test card can be used to test a plurality of channels, and the signal and power on each channel are connected to the corresponding Wafer to be tested through the probe card.

in one embodiment, the signal and power supply links between the transmission card and the plurality of test cards need to be implemented on the probe card, and the transmission card and the plurality of test cards use the same connector specification.

In one embodiment, the number of test cards is 4.

In one embodiment, a transmission subsystem is arranged in the transmission card;

the GPIO of the singlechip in the transmission subsystem is used for controlling power supplies of 4 switches;

And 1 UART of a singlechip in the transmission subsystem controls 4 test cards through a 1-to-4 chip.

In one embodiment, a test subsystem is arranged in the test card;

The signal switching module in the test subsystem is used for switching a signal switch;

the power switch control module is used for controlling a power switch and measuring current;

The signal switching module and the power switch control module are controlled by a system chip.

a test method for screening Wafer for bad Die applied to the test system according to any one of the preceding claims, the method comprising:

Opening test software on a test computer;

Electrifying the test card and the transmission card, and loading corresponding firmware programs;

downloading the Wafer Map from the server, and installing the Wafer and the Probe after checking the Wafer Map;

reading product information to check a bad block of an original factory, and performing current detection, time detection and error rate detection;

Erasing all data to restore the original state;

determining the last Wafer coordinate, and moving the Probe to the next position to be tested after each time a group of multiple Dies is tested until all Dies on the Wafer are tested;

And powering off the test card and the transmission card, transmitting the test result on the test card to the test software in real time through serial port communication, counting the final test result by the test software, and displaying the test result on a test interface.

In one embodiment, the step of downloading the Wafer Map from the server, and installing the Wafer and the Probe after checking the Wafer Map comprises:

downloading the Wafer Map from the server, and determining Die to be tested; wherein, the Wafer Map displays the position coordinates and the quality classification of all Dies on one Wafer;

For the Die to be tested, the test software sends an instruction to the singlechip program through the serial port, and the GPIO of the singlechip controls the gating chip to perform signal connection on the Die to be tested;

for Dies which do not need to be tested, signal connection is not carried out;

and controlling the Wafer machine to feed a Wafer, and controlling the Probe to press down to a corresponding test position.

in one embodiment, the step of reading the product information to check for a bad block in the original factory, and performing the current detection, the time detection, and the error rate detection includes:

reading basic information such as an identification code of a product and checking whether the basic function is normal;

Checking bad blocks of an original factory, reading the quantity of the bad blocks of a product and calculating the capacity of the bad blocks;

Respectively detecting whether the current exceeds a normal standard or not in the erasing, reading data and writing data operation and standby states of the product;

Selecting a specific block of the product, checking the time for finishing the operation and judging whether the time exceeds a normal standard under the conditions that the product is erased, read and written;

and selecting a specific block of the product, performing data writing and data reading operations, and checking the number of data errors in the unit size by comparing the read data with the written data.

a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.

A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the methods described above.

According to the test system, the test method, the computer equipment and the storage medium for screening the bad Die in the Wafer, the test system and the test method can be directly applied to an automation platform, automatic tests of a plurality of channels can be realized, and the test efficiency can be effectively improved. In addition, the invention can not only carry out open/short test to screen bad Die, but also finish normal read-write and erase operations, and the scheme design supports Wafer of different manufacturers, thereby having wide market application prospect.

drawings

FIG. 1 is a block diagram of a test system for screening for bad Die in a Wafer according to one embodiment;

FIG. 2 is a hardware architecture diagram of a test system for screening for bad Dies in a Wafer, under an embodiment;

FIG. 3 is a block diagram of the connections of a test system for screening for bad Die in a Wafer according to one embodiment;

FIG. 4 is a block diagram of the connections of the Transfer Card subsystem in one embodiment;

FIG. 5 is a block diagram of the connection of the Tester Card subsystem in one embodiment;

FIG. 6 is a schematic flow chart of a test method for screening for undesirable Die in Wafer according to one embodiment;

FIG. 7 is a schematic flow chart of a test method for screening Wafer for undesirable Die in another embodiment;

FIG. 8 is a schematic flow chart of a test method for screening Wafer for undesirable Die in accordance with yet another embodiment;

FIG. 9 is a software architecture diagram of the test method used to screen for bad Die in Wafer in one embodiment;

FIG. 10 is a software flow diagram of a test method for screening for bad Die in Wafer according to one embodiment;

FIG. 11 is a diagram illustrating an internal structure of a computer device in one embodiment.

Detailed Description

in order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In one embodiment, as shown in fig. 1, a test system 100 for screening Wafer for bad Die is provided: a test host 110, a transport card 120, a plurality of test cards 130, and a probe card 140;

The test host 110 communicates with the transport card 120 through a serial port to obtain a test result of each test channel on each test card 130;

the transmission card 120 is used for supplying power to the plurality of test cards 130, and the plurality of test cards 130 communicate with the test host 110 through the serial port of the transmission card 120;

the test card 130 may be used to test a plurality of channels, each of which has a signal and power connection to a corresponding Wafer to be tested through the probe card 140.

the hardware architecture diagram of the test system for screening bad Die in Wafer provided in this embodiment is shown in fig. 2. The system mainly comprises Main PC, cable, 1 Transfer Card, 4 Tester cards, and Probing Card.

Specifically, the Main PC obtains the test result of each channel on each Tester Card through the cable. The Transfer Card is used to power 4 Tester cards, and the 4 Tester cards and the Main PC communicate through the Transfer Card's UART. Each Tester Card is provided with a test system consisting of main devices such as a main control device, a DRAM (dynamic random access memory), a NORFLASH (random access memory) and the like. Each Tester Card can test 4 channels. The signal and power on each channel are connected to the Wafer through the Probing Card.

it will be appreciated that the design of the test scheme is to support 4 Card (16DIE) peers, and how many peers can be supported will also depend on how many valid pins are on the Probing Card. The number of components required for this test scheme is large, and therefore the mechanical contact and mechanical interference of each component need to be strictly controlled. The assembly difficulty is large, and the operation can be carried out by personnel trained by professionals.

in this embodiment, the test system can be directly applied to an automation platform, and can realize automatic testing of multiple channels, thereby effectively improving the test efficiency. In addition, the invention can not only carry out open/short test to screen bad DIE, but also complete normal read-write and erase operations, and the scheme design supports refer of different manufacturers, thereby having wide market application prospect.

In one embodiment, the signal and power links between the transport card 120 and the plurality of test cards 130 need to be implemented on the probe card 140, and the transport card 120 and the plurality of test cards 130 use the same connector specification, and the number of test cards 130 is 4.

specifically, a connection block diagram of the test system for screening bad Die in Wafer provided in this embodiment is shown in fig. 3.

Among them, the signals between Transfer Card and Tester Card, and between Tester Card and Die, the power supply link needs to be implemented on the Probing Card. The connector specifications used by the Transfer Card and the Tester Card are the same. The default number of Tester cards is 4 at present, and the number can be increased according to the actual maximum support number of 512Pin and 1024Pin so as to meet the test requirements of different scenes.

in one embodiment, a transport subsystem is provided within transport card 120; the GPIO of the singlechip in the transmission subsystem is used for controlling the power supplies of the 4 switches; 1 UART of a single chip machine in the transmission subsystem controls 4 test cards through a 1-to-4 chip.

specifically, a block diagram of the Transfer Card subsystem connection provided in this embodiment is shown in fig. 4.

the GPIO of the single chip microcomputer controls 5V power supplies of the 4 SW. 1 UART of the singlechip controls 4 test cards through a chip with 1 to 4 paths.

in one embodiment, a test subsystem is provided within the test card 130; the signal switching module in the test subsystem is used for switching a signal switch; the power switch control module is used for controlling a power switch and measuring current; the signal switching module and the power switch control module are controlled by a system chip.

specifically, a block diagram of the Tester Card subsystem connection provided in the present embodiment is shown in fig. 5.

Wherein, SW is used for signal switch switching. PM is used for VCC, VCCQ power switch control, and VCC current measurement. SW and PM are controlled by SOC.

In one embodiment, as shown in fig. 6, there is provided a test method for screening Wafer for bad Die, comprising:

step 602, opening test software on a test computer;

Step 604, electrifying the test card and the transmission card, and loading corresponding firmware programs;

step 606, downloading the Wafer Map from the server, checking the Wafer Map and installing the Wafer and the Probe;

Step 608, reading product information to check a bad block of an original factory, and performing current detection, time detection and error rate detection;

Step 610, erasing all data to restore the original state;

Step 612, determining the last Wafer coordinate, wherein after each time a group of multiple dice are tested, the Probe needs to move to the next position to be tested until all dice on the Wafer are tested;

And 614, powering down the test card and the transmission card, transmitting the test result on the test card to the test software in real time through serial port communication, counting the final test result by the test software, and displaying the test result on the test interface.

In one embodiment, as shown in fig. 7, a test method for screening bad Die in Wafer is provided, in which a Wafer Map is downloaded from a server, and the step of installing Wafer and Probe after checking the Wafer Map includes:

step 702, downloading the Wafer Map from the server, and determining Die to be tested; wherein, the Wafer Map displays the position coordinates and the quality classification of all Dies on one Wafer;

Step 704, for the Die to be tested, the test software sends an instruction to the single chip microcomputer program through the serial port, and the GPIO of the single chip microcomputer controls the gating chip to carry out signal connection on the Die to be tested;

step 706, for the Die not required to be tested, no signal connection is performed;

And step 708, controlling the Wafer machine to load a Wafer, and controlling the Probe to press to a corresponding test position.

In one embodiment, as shown in fig. 8, a test method for screening bad Die in Wafer is provided, in which the steps of reading product information to check for a bad block in a factory, and performing current detection, time detection and error rate detection include:

step 802, reading basic information such as an identification code of a product, and checking whether basic functions are normal;

Step 804, checking bad blocks of the original factory, reading the quantity of the bad blocks of the product and calculating the capacity of the bad blocks;

step 806, detecting whether the current exceeds the normal standard in the erasing, reading data, writing data operation and standby state of the product;

808, selecting a specific block of the product, checking the time for completing the operation and judging whether the time exceeds a normal standard under the conditions that the product is erased, read and written;

step 810, selecting a product specific block, performing data writing and data reading operations, and checking the number of data errors in a unit size by comparing the read data with the written data.

in the above embodiments, the test method may be applied to the test system according to any of the above embodiments, and for specific limitations of the test system for screening the bad Die in the Wafer, reference may be made to the description in the above embodiments, which is not repeated herein.

Specifically, the software architecture of the testing method for screening bad Die in Wafer provided in this embodiment is shown in fig. 9, and includes: the test host is used for testing software operation, testing interface display, command interaction and data receiving and transmitting. The transmission card is used for switching the adapter plate and the serial port and transmitting data. The test card is used for testing boards, Wafer tests, power supply control and signal control. The test machine is used for Wafer machine, loading and unloading and Prober control. And the MAP server is used for storing the Wafer MAP file. And the database server is used for storing the test result.

Specific software requirements include: firstly, the specification and the model of a singlechip used for power control on a transmission card are confirmed. Next, a signal distribution table for channel isolation, power control, current measurement for 4 channels on the SOC is specified. Then, the speed requirements of each interface at the back end are determined, and the minimum speed is reached on the premise of not influencing the service. Finally, the storage capacity size of the NOR is confirmed.

referring to fig. 10, the test flow of the test method for screening Wafer for bad Die includes the following steps:

1. Beginning: and opening the test software on the test computer, and starting the test.

2. electrifying: the test card and the transport card are powered up.

3. Loading a firmware program: the software downloads the test firmware to a Flash memory (Nor Flash) of the test card for storage, and a Flash controller of the test card can load a firmware program on the Flash memory (Nor Flash) to automatically run.

4. And checking the Wafer MAP, namely downloading the Wafer MAP from the server, determining the Dies to be tested, wherein the Wafer MAP displays the position coordinates and the quality classification of all the Dies on one Wafer, for the Dies to be tested, the software sends an instruction to a single chip microcomputer program through a serial port, a General Purpose Input Output (GPIO) control gating chip of the single chip microcomputer performs signal connection on the Dies to be tested, and for the Dies not to be tested, the signal connection is not performed.

5. Wafer and Probe installation: and controlling the Wafer machine to feed a Wafer, and controlling the Probe to press to a test position.

6. open short circuit test: checking whether the product is open or short-circuit failed.

7. Reading product information: reading basic information such as the identification code of the product and checking whether the basic function is normal.

8. And (3) checking bad blocks of the original factory: a Die product consists of a plurality of blocks, and the number of bad blocks of the product is read to calculate the capacity of the product.

9. current detection: the test item mainly checks the physical characteristics by detecting the current magnitude in the erasing, reading data, writing data operation and standby state of the product respectively and whether the current magnitude exceeds the normal standard.

10. and (3) time detection: selecting a specific block of the product, checking the time for completing the operation of the specific block under the operations of erasing, reading and writing data of the product, and judging whether the specific block exceeds a normal standard, wherein the test item mainly checks the performance of the specific block.

11. and (3) bit error rate detection: selecting a specific block of a product, performing data writing and data reading operations, checking the number of data errors in a unit size through data comparison of writing of read data, usually checking whether the number of data errors exceeds the standard of 120 bit errors or more per 1Kbyte, and mainly checking the performance of the test item.

12. erasing: all data are erased and the original state is restored.

13. final Wafer coordinates: a Wafer has about 700 Die, 1 test card can test 4 Die, 4 test cards support 16Die simultaneous testing, and each time 16Die are tested, a Probe needs to be moved to the next position to be tested until all the Die on the Wafer are tested.

14. powering off: the test card and the transport card are powered down.

15. and (4) ending: the test result on the test card can be transmitted to the test software in real time through serial port communication, the test software counts the final test result, and the test result is displayed on the test interface to complete the test.

In the embodiment, the automatic test of a plurality of channels can be realized, and the test efficiency can be effectively improved. In addition, the invention can not only carry out open/short test to screen bad Die, but also finish normal read-write and erase operations, and the scheme design supports Wafer of different manufacturers, thereby having wide market application prospect.

It should be understood that although the various steps in the flow charts of fig. 6-8 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Also, at least some of the steps in fig. 6-8 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.

in one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 11. The computer apparatus includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation device in the nonvolatile storage medium and the execution of the computer program. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a test method for screening Wafer for bad Die.

those skilled in the art will appreciate that the architecture shown in fig. 11 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

in one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above respective method embodiments.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

the technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. a test system for screening Wafer for undesirable Die, the system comprising: the test system comprises a test host, a transmission card, a plurality of test cards and a probe card;

2. the test system for screening for bad Die in a Wafer according to claim 1, wherein the signal and power links between the transport card and the plurality of test cards need to be implemented on the probe card, and the transport card and the plurality of test cards use the same connector specification.

3. The test system for screening Wafer for bad Die as claimed in claim 2, wherein the number of the test cards is 4.

4. the test system for screening Wafer for bad Die according to claim 3, wherein a transmission subsystem is arranged in the transmission card;

5. The test system for screening Wafer for bad Die according to claim 4, wherein a test subsystem is arranged in the test card;

6. A test method for screening Wafer for bad Die applied to the test system according to any one of claims 1 to 5, wherein the method comprises the following steps:

opening test software on a test computer;

erasing all data to restore the original state;

7. The test method for screening undesired Die in a Wafer according to claim 6, wherein the step of downloading the Wafer Map from the server, and the step of installing the Wafer and the Probe after checking the Wafer Map comprises:

For Dies which do not need to be tested, signal connection is not carried out;

8. The testing method for screening bad Die in Wafer according to claim 6, wherein the step of reading product information to check for factory bad blocks and performing current detection, time detection and error rate detection comprises:

9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to any of claims 6 to 8 are implemented when the computer program is executed by the processor.

10. a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 6 to 8.