KR20020089888A - method for providing burn-in enable signal in order to test semiconductor memory device and signal generating circuit therefore - Google Patents

Abstract

PURPOSE: A method for providing a burn-in enable signal for burn-in test of a semiconductor memory device and a signal generation circuit according to the same are provided to perform the burn-in test and generate a burn-in enable signal by using a JTAG(Joint Test Action Group) circuit. CONSTITUTION: A JTAG controller(60) is used for providing a burn-in enable signal in response to input data in a burn-in test mode. A latch(70) is connected between the JTAG controller(60) and a switch circuit. The latch(70) is used for latching a burn-in enable signal applied from the JTAG controller(60) and outputting the latched burn-in enable signal. The burn-in enable signal is always stored into the latch(70) by using the JTAG controller(60). Accordingly, the burn-in enable signal is outputted continuously even if an operation of a JTAG is stopped.

Description

A method for providing a burn-in enable signal for a burn-in test of a semiconductor memory device and a signal generating circuit according to the present invention {method for providing burn-in enable signal in order to test semiconductor memory device and signal generating circuit therefore}

The present invention relates to a test of a semiconductor memory device, and more particularly, to a method of providing a burn-in enable signal for a burn-in test of a semiconductor memory device and a signal generating circuit accordingly.

In the semiconductor manufacturing process, burn-in tests are performed for the purpose of improving the reliability of semiconductor products, and early defective products are removed early. Burn-in test refers to a test that checks whether a memory cell passes through a stress factor that has a large influence on determining a defect of a semiconductor product such as temperature and voltage higher than normal state and passes such stress. Here, the test equipment which performs a burn-in test is comprised so that all the semiconductor products of the same series may be tested instead of exclusively testing the set semiconductor product. The reason for this is to reduce the problem of increasing production costs by increasing the operational efficiency of the equipment.

For semiconductor products, high integration of products is inevitably pursued for low cost and high quality to secure competitiveness. In order to achieve high integration, scale-down such as thinning and shortening the gate oxide thickness and channel lengths of a transistor device is inevitably required, and thus, power reduction of products has been required to improve product reliability.

However, since the electronic system of the user maintains the existing voltage as it is, in a semiconductor product, an internal power supply voltage generation circuit that receives an external power supply voltage and drops the voltage and outputs it as an internal power supply voltage (hereinafter referred to as an IVC circuit). Is removed in the memory chip.

By adopting the IVC circuit, it is possible to unify various semiconductor products and to easily control the product characteristics, while the constant voltage is output regardless of the external voltage over a certain voltage range. This makes it difficult to apply high voltage stress in burn-in test processes for screening vulnerable memory cells. In addition, burn-in testing is usually performed in a multi-testing manner in which multiple memory products are controlled identically and stressed simultaneously in consideration of productivity. In such a case, there is an advantage in that many semiconductor products can be burned-in at the same time, but when a problem occurs in one chip under the control of multiple memory chips at the same time, it may affect other adjacent chips. For example, when a large current flows in a certain chip, when the power cut-off device is operated to protect the equipment, the power applied to the other chip is also cut off and burn-in is stopped, that is, a lamp-on phenomenon occurs. Therefore, in order to perform burn-in with a large amount, it is necessary to reduce the amount of current for each chip.

1, a block diagram of a typical burn-in voltage generation circuit is shown. The voltage kick-up circuit 20 connected in parallel with the internal power supply voltage generator 10 generates the burn-in voltage through the output node N1 during the burn-in test. The voltage kick-up circuit 20 performs an operation when the level difference voltage Vx shown in FIG. 2 is generated and outputs the voltage level corresponding to the graph G2 as the burn-in voltage at the burn-in test. Here, FIG. 2 is a graph showing the level of the internal power supply voltage output from FIG. 1 compared with the external power supply voltage, in which section T1 is an IVC clamp section, and graph G1 is an increase in the level of the external power supply voltage Ext.Vdd. Shows. The voltage kick up circuit 20 may be formed of a transistor or a diode device. In general, when the voltage kick-up circuit 20 is formed of a MOS transistor, the semiconductor kick may be operated very sensitive to a process and a temperature, and thus different stresses may be applied to each manufactured semiconductor product. In addition, since the characteristics of the voltage output in the case of FIG. 1 are shown in the graph of FIG. 2, there has been a problem in that the burn-in voltage must be raised very high.

In order to solve the problem of the circuit of FIG. 1 described above, the improved conventional technology is configured as shown in FIG. 3. 3 is a block diagram of a burn-in voltage generating circuit according to the conventional technology, the switch 40 connected in parallel with the internal power supply voltage generator 10, and the burn-in enable circuit 30 for controlling the switching operation of the switch. It consists of. Here, the burn-in enable circuit 30 includes a NAND gate NAN1 as shown in FIG. 4.

Referring to FIG. 3, when the switch is driven by the switch-on signal generated by the burn-in enable circuit 30, the level of the internal power supply voltage becomes the same potential as that of the external power supply voltage. In such a voltage application method, since a constant voltage is generated as a burn-in voltage regardless of a process or temperature, burn-in can be performed stably. Operation into the burn-in test mode is as follows. In the synchronous SRAM series semiconductor products of the synchronous pipeline system (SP), the M1 and M2 pins are shown as mode select pins. When the logic level “high” is commonly applied to the burn-in test during the burn-in test, the switch 40 is driven and burned. The quoted voltage is output at the level of the external power supply voltage.

However, when the mode select pin does not protrude outside, such as a synchronous SRAM, it is impossible to perform burn-in using the above-described external voltage. Therefore, in order to enable burn-in, an unused pin must be allocated and specified in the specification of the product. However, if the user uses it incorrectly, the operation characteristic of the product is hindered.

In addition, in view of the recent technical trend of minimizing the number of existing package pins due to the addition of various functional pins, it is necessary to add two pins in the package pins such that the burn-in voltage is applied during the burn-in test as described above. It is not desirable to use dogs. This is because, in the highly integrated semiconductor memory having a relatively fixed package size, the arrangement of the package pins necessary for the operation of the memory is difficult. As a result, the density of semiconductor memories is increasing rapidly, but the package pin assignment problem is very critical because the size of the package is not easily changed. Therefore, it can be seen that test pins that are not related to the direct operation of the semiconductor memory are minimized due to the lack of package pin assignment.

As a result, if the M1 and M2 pins are removed and the pins are installed to perform other functions at the positions of the pins, the operation of the package pins can be facilitated and contribute to the cost reduction of the product.

As described above, in the conventional technology, since burn-in tests were performed using package pins of a chip, there has been a problem that it is difficult to minimize the number of package pins.

Disclosure of Invention An object of the present invention is to provide a burn-in test using a JTAG test circuit and a burn-in enable signal generation circuit when a burn-in test of a semiconductor memory device is performed by applying a burn-in voltage through a switch circuit connected in parallel with an internal voltage generator. In providing.

It is still another object of the present invention to provide a method for providing a burn-in enable signal for burn-in test of a semiconductor memory device while minimizing package pins and a signal generation circuit accordingly.

According to an aspect of the present invention for achieving the above objects, a method of performing a burn-in test of a semiconductor memory device by applying a burn-in voltage through a switch circuit connected in parallel with an internal voltage generator, burn-in for enabling the switch circuit The enable signal may be provided through a JTAG test circuit built in the semiconductor memory device.

According to another aspect of the present invention, a burn-in test signal generation circuit for burn-in test of a semiconductor memory device which performs burn-in test of a semiconductor memory device by applying a burn-in voltage through a switch circuit connected in parallel with an internal voltage generator, has a burn-in test mode. And a latch for latching the applied burn-in enable signal connected between the JTAG controller and the switch circuit and providing a burn-in enable signal in response to data input at the time.

According to the above configuration, there is an advantage that the desired burn-in voltage can be applied to the memory cell for all BGA products employing the JTAG circuit without being assigned to the specific pin without allocating the mode pin for burn-in test.

1 is a block diagram of a conventional burn-in voltage generating circuit

FIG. 2 is a graph illustrating the level of the internal power supply voltage output from FIG. 1 compared to the external power supply voltage. FIG.

3 is a block diagram of a burn-in voltage generation circuit according to convention technology.

4 is a detailed diagram of the burn-in enable generation circuit of FIG.

5 is a block diagram of a signal generation circuit providing a burn-in enable signal according to an exemplary embodiment of the present invention.

Hereinafter, a preferred embodiment of a semiconductor memory according to the present invention will be described with reference to the accompanying drawings. Components that perform the same or similar functions are shown with the same reference numerals even if they are shown in other drawings.

5 is a block diagram of a signal generation circuit providing a burn-in enable signal according to an exemplary embodiment of the present invention. In the figure, a JTAG controller 60 which provides a burn-in enable signal in response to data input in the burn-in test mode, and is connected between the JTAG controller and the switch circuit 40 of FIG. 3 and applied to the burn-in enable. A latch 70 of a flip-flop circuit configuration for latching the signal is shown.

To describe the JTAG controller 60, first, the JTAG will be described. In order to reduce various problems related to the testing of the integrated circuit, a hierarchical system design for gathering integrated circuits to form a functional module and assembling the modules to form a system has been actively conducted in the art. Accordingly, a more systematic design for testability (DFT) method has been required for test at the board or system level. As a solution to that need, the boundary scan design, which was being studied by the Joint Test Action Group (JTAG) in the late 1980s, was standardized by the IEEE in 1990. The JTAG standard widely employed in this field is defined as IEEE 1149.1, IEEE Standard Test Access Port and Boundary Scan Architecture, and IEEE Standard 1149.1 is described in the IEEE computer society press, 1990, which describes Test Access Port and Boundary Scan Architecture. Is disclosed.

Ultimately, system boards consisting of surface mount, tape automated bonding, miniaturized components, multi-chip modules (MCM), and complex ASICs will be tested. In order to solve the problem of code access problem or all node test, IEEE standardizes the standard of device manufacturing and load circuit board testing. This is the Joint Test Action Group (JTAG).

Typically, semiconductor memory chips, such as static random access memories, which typically use a ball grid array (BGA) package, have JTAG logic employed therein for chip testing. In the SRAM, when performing a boundary scan test for testing a device with a shift register between each device pin and internal logic, only a short and open level of each pin is checked. The reason for this is that when the JTAG IEEE 1149.1 standard is implemented in the SRAM, signal delay and chip size overhead problems occur.

The test circuit such as JTAG logic is operated in a specific operation mode, for example, a test mode, in which the semiconductor memory chip is not normally operated. The JTAG logic may include a boundary scan register block composed of a plurality of boundary scan registers, a bypass register, an identification register, and an instruction register. Test data output pin (TDO). A test access port (TAP) controller corresponding to the controller 60 of FIG. 5 receives a test mode selection and a test clock from each input terminal TMS and TCK and outputs timing control signals. Serial data is input to the test data input terminal TDI connected to the inputs of the registers. The serial data is typically sampled at the rising edge of the test clock and applied to the command register or data register depending on the test command mode.

The detailed operation of the TAP controller is disclosed under the title "method of input / output toggle test using JTAG" registered on June 10, 2000 to the applicant of the patent application No. 10-0265138. Incorporated as part of the description of the invention.

In the embodiment of the present invention, the command code IR2, IR1, IR0 is applied to the test data input terminal TDI as 1, 1, 0 so that the command is newly defined. That is, 1,1,0 is applied through the input pin TDI to output the burn-in enable signal to the outside through the enable pin B_I ENABLE so that the JTAG controller is not a boundary scan test mode. Mode, in this embodiment, a transition to the burn-in test mode. Since the command code data 1, 1, 0 is not currently used as an input code in JTAG, it is determined as a user mode for entering the test mode of the semiconductor memory. Similarly, other undefined codes can be used as the enable signal generation mode for burn-in test.

In the embodiment of the present invention, the burn-in enable signal is always stored in the latch 70 by using the controller 60, and the signal 60 may be continuously output even when the operation of the JTAG is stopped. In the case of initial power-on or normal operation, the reset signal is applied to enable the IVC circuit 10 in FIG. 3 to output the internal power supply voltage which is normally lower than the external power supply voltage. It is also possible to control the input termination circuit applied in the ultra-fast DDR3 SRAM using the applied signal. Here, the input termination circuit is a circuit attached to the input pad and is configured to always consume a constant current for impedance matching.

As described above, the external package pin can be removed by providing a burn-in enable signal for enabling the switch circuit through the JTAG test circuit built in the semiconductor memory device.

Although the above description has been given by way of example only with reference to the accompanying drawings, it will be apparent to those skilled in the art that the present invention may be modified or changed within the scope of the technical idea of the present invention. Or change will also belong to the claims of the present invention. For example, the command code data can be changed if the matter is different.

As described above, according to the method of providing a burn-in enable signal for a burn-in test of a semiconductor memory device and a signal generation circuit according thereto, a control signal for test can be generated through the JTAG circuit for all semiconductor products in which the JTAG circuit is embedded. As a result, there is an effect of eliminating the circuit burden and the burden of assigning an arbitrary pin. Therefore, there is an additional advantage that the pin allocation can be relaxed by eliminating the shortage of package pins.

Claims (4)

A method of performing a burn-in test of a semiconductor memory device by applying a burn-in voltage through a switch circuit connected in parallel with an internal voltage generator, And providing a burn-in enable signal for enabling the switch circuit through a JTAG test circuit embedded in the semiconductor memory device. The method of claim 1, wherein the providing of the burn-in enable signal is performed by a latch having a set and a reset terminal connected to the JTAG test circuit. In the burn-in test signal generation circuit for burn-in test of a semiconductor memory device which performs burn-in test of a semiconductor memory device by applying a burn-in voltage through a switch circuit connected in parallel with an internal voltage generator, A JTAG controller that provides a burn-in enable signal in response to data input in the burn-in test mode, And a latch connected between the JTAG controller and the switch circuit for latching the applied burn-in enable signal. 4. The circuit of claim 3 wherein the latch comprises a flip-flop circuit having a set and a reset stage.