KR20230047970A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present disclosure relates to a semiconductor device with improved reliability and productivity and a manufacturing method thereof. According to one embodiment of the present invention, the semiconductor device comprises a substrate and a capacitor structure positioned over the substrate. The capacitor structure includes: a plurality of lower electrodes separated from each other; a supporter positioned between the plurality of lower electrodes; an upper electrode covering the plurality of lower electrodes; and a dielectric layer positioned between the lower electrodes and the upper electrode. The plurality of lower electrodes each include a first lower electrode layer and a second lower electrode layer surrounded by the first lower electrode layer. The first lower electrode layer contains a first material doped with a second material. The second lower electrode layer contains a third material different from the first material and the second material. The doping concentration of the second material becomes higher toward the second lower electrode layer.

Description

Semiconductor device and manufacturing method thereof

The present disclosure relates to a semiconductor device and a manufacturing method thereof.

As the semiconductor device is downscaling, the size of the capacitor structure of the DRAM device is also being reduced. Accordingly, a structure capable of overcoming spatial limitations and design rule limitations in the capacitor structure, reducing leakage current in the capacitor structure even when the dielectric film of the capacitor structure has a relatively small thickness, and maintaining desired electrical characteristics need to develop

Embodiments are intended to provide a semiconductor device with improved reliability and productivity and a manufacturing method thereof.

A semiconductor device according to an embodiment includes a substrate and a capacitor structure disposed on the substrate, wherein the capacitor structure includes a plurality of lower electrodes spaced apart from each other, a supporter disposed between the plurality of lower electrodes, and the plurality of lower electrodes. An upper electrode covering a plurality of lower electrodes, and a dielectric layer positioned between the lower electrodes and the upper electrode, wherein each of the plurality of lower electrodes is surrounded by a first lower electrode layer and the first lower electrode layer. and a second lower electrode layer, wherein the first lower electrode layer includes a second material doped with a first material, and the second lower electrode layer includes a third material different from the first material and the second material. And, the doping concentration of the first material increases as it is closer to the second lower electrode layer.

The third material may have higher rigidity than the second material.

The second material may include at least one of TiN, TaN, NbN, MoN, and WN, and the third material may include Ti-Si-N (TSN).

The first material may include at least one of Nb, V, Cr, Ta, Mo, W, Co, Rh, and Ir.

The supporter may include a first supporter positioned between upper regions of the plurality of lower electrodes and a second supporter positioned between central regions of the plurality of lower electrodes.

The dielectric layer may be further positioned between the supporter and the upper electrode.

A method of manufacturing a semiconductor device according to an embodiment includes stacking a mold layer and a supporter on a substrate, forming an opening penetrating the mold layer and the supporter,

Forming a first lower electrode layer in the opening, forming a source material layer on the first lower electrode layer, and performing a heat treatment process so that the first material included in the source material layer is introduced into the first lower electrode layer. Diffusion step, removing the source material layer, forming a second lower electrode layer on the first surface of the first lower electrode layer, removing the mold layer, on the second surface of the first lower electrode layer Forming a dielectric layer, and forming an upper electrode on the dielectric layer, wherein the source material layer is made of an oxide containing the first material.

The first material may include at least one of Nb, V, Cr, Ta, Mo, W, Co, Rh, and Ir.

The first lower electrode layer may be doped with the first material by diffusing the first material into the first lower electrode layer, and the doping concentration of the first material may increase as it is closer to the second lower electrode layer.

The first lower electrode layer may include at least one of TiN, TaN, NbN, MoN, and WN, and the second lower electrode layer may include Ti-Si-N (TSN).

According to embodiments, since the lower electrode is doped by diffusing metal atoms from the inner surface toward the outer surface of the lower electrode, a process step of etching the metal atoms remaining on the outer surface of the lower electrode and the source material layer may be omitted. . Accordingly, it is possible to prevent the outer surface of the lower electrode from being damaged by the etching process, thereby improving the crystallinity of the dielectric layer deposited on the outer surface of the lower electrode.

Since the lower electrode of the capacitor structure is formed before removing the mold structure, it is possible to prevent the lower electrode from being bent or damaged by the mold structure in a subsequent process step.

Also, the lower electrode may include a first lower electrode layer including a first material and a second lower electrode layer including a second material having a higher rigidity than the first material. Accordingly, it is possible to prevent the lower electrode from being damaged or deformed by the second lower electrode layer having high rigidity during a process step.

Accordingly, reliability and productivity of the semiconductor device including the capacitor may be improved.

1 is a layout diagram illustrating a semiconductor device according to an exemplary embodiment.
FIG. 2 is a cross-sectional view taken along line Ⅰ-Ⅰ′ in FIG. 1 .
FIG. 3 is an enlarged view of area A of FIG. 2 .
4 is a graph schematically showing the concentration of a dopant according to a position in a lower electrode.
5 and 6 are cross-sectional views taken along line II′ of FIG. 1 according to some embodiments.
7 to 19 are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. This invention may be embodied in many different forms and is not limited to the embodiments set forth herein.

In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, the present invention is not necessarily limited to the shown bar. In the drawings, the thickness is shown enlarged to clearly express the various layers and regions. And in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggerated.

In addition, when a part such as a layer, film, region, plate, etc. is said to be "on" or "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where another part is in the middle. . Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. In addition, being "above" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "on" in the opposite direction of gravity. .

In addition, throughout the specification, when a certain component is said to "include", it means that it may further include other components without excluding other components unless otherwise stated.

In addition, throughout the specification, when it is referred to as "planar image", it means when the target part is viewed from above, and when it is referred to as "cross-sectional image", it means when a cross section of the target part cut vertically is viewed from the side.

1 is a layout diagram illustrating a semiconductor device according to an exemplary embodiment. FIG. 2 is a cross-sectional view taken along line Ⅰ-Ⅰ′ in FIG. 1 . FIG. 3 is an enlarged view of region A of FIG. 2 . 4 is a graph schematically showing the concentration of a dopant according to a position in a lower electrode.

Referring to FIGS. 1 to 3 , the substrate 110 may have an active region AC defined by an isolation layer 112 . In some embodiments, substrate 110 may include Si, Ge, or a semiconductor material such as SiGe, SiC, GaAs, InAs, or InP. In some embodiments, the substrate 110 may include a conductive region, for example, a well doped with impurities, or a structure doped with impurities.

The device isolation layer 112 may have a shallow trench isolation (STI) structure. For example, the device isolation layer 112 may include an insulating material filling the device isolation trench 112T formed in the substrate 110 . The insulating material is FSG (Fluoride Silicate Glass), USG (Undoped Silicate Glass), BPSG (Boro-Phospho-Silicate Glass), PSG (Phospho-Silicate Glass), FOX (Flowable Oxide), PE-TEOS (Plasma Enhanced Tetra- Ethyl-Ortho-Silicate), or TOSZ (Tonen Silazene), but is not limited thereto, and may be variously modified.

The active region AC may have a relatively long island shape having a minor axis and a major axis, respectively, on a plane. As shown in FIG. 1 , the long axis of the active region AC may be arranged along a diagonal direction DR1 parallel to the upper surface of the substrate 110 . In some embodiments, P-type or N-type impurities may be doped in the active region AC.

The gate line trench 120T crosses the active region AC and may be formed to a predetermined depth from the top surface of the substrate 110 toward a vertical third direction (Z direction). A portion of the gate line trench 120T may extend into the device isolation layer 112, and a portion of the gate line trench 120T formed in the device isolation layer 112 may be a gate line trench formed in the active region AC ( 120T) may have a bottom surface located at a lower level than a portion of the lower part.

A first source/drain region 114A and a second source/drain region 114B may be disposed in an upper region of the active region AC positioned on both sides of the gate line trench 120T. The first source/drain region 114A and the second source/drain region 114B may be alternately disposed with the gate line trench 120T interposed therebetween. The first source/drain region 114A and the second source/drain region 114B may be impurity regions doped with impurities having a conductivity type different from that of the impurity doped in the active region AC. For example, N-type or P-type impurities may be doped into the first source/drain region 114A and the second source/drain region 114B.

A gate structure 120 may be positioned inside the gate line trench 120T. The gate structure 120 may include a gate insulating layer 122, a gate electrode 124, and a gate capping layer 126 sequentially formed on the inner wall of the gate line trench 120T.

The gate insulating layer 122 may be conformally formed on the inner wall of the gate line trench 120T to a predetermined thickness. The gate insulating layer 122 may be formed of at least one selected from silicon oxide, silicon nitride, silicon nitride, oxide/nitride/oxide (ONO), or a high dielectric material having a higher dielectric constant than silicon oxide. For example, the gate insulating layer 122 may have a dielectric constant of about 10 to about 25. In some embodiments, the gate insulating layer 122 may be made of HfO ₂ , ZrO ₂ , Al ₂ O ₃ , HfAlO ₃ , Ta ₂ O ₃ , TiO ₂ , or a combination thereof, but is not limited to the above examples. , can be variously modified.

The gate electrode 124 may be formed on the gate insulating layer 122 to fill the gate line trench 120T to a predetermined height from the bottom of the gate line trench 120T toward a vertical third direction (Z direction). can In some embodiments, the gate electrode 124 may include a work function control layer (not shown) disposed on the gate insulating layer 122 and a buried metal layer (not shown) filling the bottom of the gate line trench 120T on the work function control layer. city) may be included. For example, the work function control layer may include a metal such as Ti, TiN, TiAlN, TiAlC, TiAlCN, TiSiCN, Ta, TaN, TaAlN, TaAlCN, TaSiCN, metal nitride, or metal carbide, and the buried metal layer is It may include at least one of W, WN, TiN, and TaN.

The gate capping layer 126 may fill the remaining portion of the gate line trench 120T on the gate electrode 124 . For example, the gate capping layer 126 may include at least one of silicon oxide, silicon nitride, and silicon nitride.

A bit line structure 130 extending in a second direction (Y direction) parallel to the upper surface of the substrate 110 and perpendicular to the first direction (X direction) may be formed on the first source/drain region 114A. can The bit line structure 130 may include a bit line contact 132 , a bit line 134 , a bit line capping layer 136 , and a bit line spacer 138 sequentially stacked on the substrate 110 . . The bit line contact 132 may connect between the bit line 134 and the first source/drain region 114A. The bit line contact 132 may be positioned in an overlapping portion of the bit line 134 and the first source/drain region 114A. The bit line contact 132 is shown in a substantially circular shape, but is not limited thereto and the planar shape of the bit line contact 132 may be variously changed. The bit line contact 132 and the bit line 134 may include a conductive material. For example, the bit line contact 132 may include polysilicon, and the bit line 134 may include a metal material.

The bit line capping layer 136 may include an insulating material such as silicon nitride or silicon nitride. The bit line spacer 138 may have a single-layer structure or a multi-layer structure made of an insulating material such as silicon oxide, silicon nitride, or silicon nitride.

In some embodiments, the bit line spacer 138 may further include an air space (not shown). Optionally, a bit line intermediate layer (not shown) may be interposed between the bit line contact 132 and the bit line 134 . The bit line intermediate layer may include a metal silicide such as tungsten silicide or a metal nitride such as tungsten nitride.

In FIG. 2 , the bit line contact 132 is illustrated as having a bottom surface at the same level as the top surface of the substrate 110 , but unlike the above, a recess (not shown) is recessed from the top surface of the substrate 110 to a predetermined depth. ) is formed and the bit line contact 132 extends to the inside of the recess, so that the bottom surface of the bit line contact 132 may be formed at a level lower than the top surface of the substrate 110 .

A first insulating layer 142 and a second insulating layer 144 may be sequentially disposed on the substrate 110 , and the bit line structure 130 may include the first insulating layer 142 and the second insulating layer 144 may be connected to the first source/drain region 114A through the .

A capacitor contact 150 may be positioned on the substrate 110 . The capacitor contact 150 may be disposed on the second source/drain region 114B. Side surfaces of the capacitor contact 150 may be surrounded by the first insulating layer 142 and the second insulating layer 144 . In some embodiments, the capacitor contact 150 includes a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) sequentially stacked on the substrate 110, and the upper contact A barrier layer (not shown) surrounding the side surface and the bottom surface of the pattern may be included.

Also, in some embodiments, the lower contact pattern may include polysilicon, and the upper contact pattern may include a metal material. The barrier layer may include a metal nitride having conductivity.

A third insulating layer 146 may be disposed on the second insulating layer 144 , and a landing pad 152 passing through the third insulating layer 146 and connected to the capacitor contact 150 may be disposed. As shown in FIG. 2 , the landing pad 152 may overlap the entire capacitor contact 150 in the third direction (Z direction) and may have a larger width than the capacitor contact 150 . The landing pad 152 is made of metal such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), titanium nitride (TiN), It may include at least one of conductive metal nitrides such as tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN). Additionally, in some embodiments, landing pad 152 may include titanium nitride (TiN).

An etch stop layer 162 may be positioned on the landing pad 152 and the third insulating layer 146 . The etch stop layer 162 may include an opening 162H overlapping at least a portion of the landing pad 152 . The etch stop layer 162 may include a material having an etch selectivity with respect to an oxide-containing mold layer (refer to 'MD' in FIG. 7 ). The etch stop layer 162 may include, for example, silicon nitride (SiN), silicon carbonide nitride (SiCN), silicon boron nitride (SiBN), silicon carbonate (SiCO), silicon nitride (SiON), silicon oxide (SiO), It may include at least one of silicon carbonate nitride (SiOCN).

A capacitor structure CS may be disposed on the etch stop layer 162 . The capacitor structure CS includes a lower electrode 170 electrically connected to the capacitor contact 150 with a landing pad 152 therebetween, a dielectric layer 180 conformally covering the lower electrode 170, and a dielectric layer ( 180) may include an upper electrode 200.

As shown in FIG. 1 , the lower electrode 170 and the capacitor contact 150 may be repeatedly arranged along a first direction (X direction) and a second direction (Y direction). Although not shown in FIG. 1 , the landing pad 152 overlaps the lower electrode 170 in the third direction (Z direction) and is spaced apart in the first direction (X direction) and the second direction (Y direction) to form a matrix. can be arranged in shape. However, it is not limited thereto, and in some embodiments, the capacitor contacts 150 are repeatedly arranged along the first direction (X direction) and the second direction (Y direction), but the lower electrode 170 has a honeycomb structure and may be arranged in the same hexagonal shape. In this case, the landing pad 152 may be disposed to overlap a portion of the capacitor contact 150 in the third direction (Z direction) and to overlap the entire lower electrode 170 in the third direction (Z direction). .

In addition, as shown in FIG. 1 , the lower electrode 170 is illustrated as having a circular cross section on a plane, but is not limited thereto, and in some embodiments, the horizontal cross section of the lower electrode 170 is an elliptical, or It may be various polygons such as rectangles, rounded rectangles, rhombuses, trapezoids, etc., and various rounded polygons.

The lower electrode 170 may be disposed on the landing pad 152 , and a bottom portion of the lower electrode 170 may be disposed within the opening 162H of the etch stop layer 162 . The width of the bottom of the lower electrode 170 may be smaller than the width of the landing pad 152, so

Accordingly, the entire bottom surface of the lower electrode 170 may contact the landing pad 152 .

The lower electrode 170 may include a first lower electrode layer 171 and a second lower electrode layer 172 .

The first lower electrode layer 171 may be formed on the landing pad 152 in the shape of a closed cylinder or cup, and the bottom surface of the first lower electrode layer 171 may contact the top surface of the landing pad 152. there is.

The second lower electrode layer 172 is disposed on the first lower electrode layer 171 , and side and bottom surfaces of the second lower electrode layer 172 may be surrounded by the first lower electrode layer 171 . That is, the first lower electrode layer 171 may be conformally formed on the side surface and the bottom surface of the second lower electrode layer 172 .

The second lower electrode layer 172 may have a pillar or pillar shape extending in a vertical third direction (Z direction), and may have an inclined side surface that narrows as it approaches the landing pad 152 according to an aspect ratio. there is.

In some embodiments, the first lower electrode layer 171 and the second lower electrode layer 172 may include different materials. For example, the first lower electrode layer 171 includes a second material doped with the first material M, and the second lower electrode layer 172 is different from the first material M and the second material. A third material may be included. However, it is not limited thereto, and the first lower electrode layer 171 may include a second material doped with the first material M, and the second lower electrode layer 172 may include the second material.

Also, the third material may have higher rigidity than the second material. Accordingly, the stiffness of the second lower electrode layer 172 may be higher than that of the first lower electrode layer 171 . Stiffness is a physical quantity that indicates the degree of resistance to deformation that occurs when an external force is applied to an object. The opposite concept is flexibility. For example, when an external force is applied to an object, if the material has high flexibility that easily bends or changes shape or volume, then the material has low stiffness. It has high stiffness and low flexibility.

As the first lower electrode layer 171 is disposed on the side surface and the bottom surface of the second lower electrode layer 172 having high rigidity, even if the lower electrode 170 has a shape with an increased aspect ratio, it is easily bent by an external force, or shape change can be prevented. Accordingly, electrical characteristics or reliability are improved by preventing the lower electrode 170 from being bent and contacting the adjacent lower electrode 170 or from damaging the lower electrode 170 in the forming process and subsequent processes of the lower electrode 170 to be described later. A semiconductor device including an improved capacitor may be provided.

In some embodiments, the first material M may be a dopant. The first material M may be, for example, niobium (Nb), vanadium (V), chromium (Cr), tantalum (Ta), molybdenum (Mo), tungsten (W), cobalt (Co), or rhodium (Rh). ), iridium (Ir), or a metal material in combination thereof, but is not limited thereto, and the first material (M) may be variously changed.

As shown in FIG. 3 , the first lower electrode layer 171 is disposed on one side of the second lower electrode layer 172 and is in contact with the second lower electrode layer 172 and a first surface 171S1, which will be described later. A second surface 171S2 contacting the dielectric layer 180 may be included. In addition, the first lower electrode layer 171 is disposed on the other side opposite to one side of the second lower electrode layer 172, and the third surface 171S3 contacting the second lower electrode layer 172 and the dielectric layer 180 ) and may further include a fourth surface 171S4 in contact with.

That is, each of the first surface 171S1 and the third surface 171S3 of the first lower electrode layer 171 facing each other with the second lower electrode layer 172 interposed therebetween is on the inner surface of the first lower electrode layer 171 in cross section. Correspondingly, each of the second surface 171S2 and the fourth surface 171S4 is opposite to the first surface 171S1 and the third surface 171S3 and may be an outer surface of the first lower electrode layer 171 in cross section. .

Referring further to FIG. 4 together with FIG. 3 , in FIG. 4 , the X-axis means the position within the lower electrode 170, and the Y-axis represents the concentration of the first material M according to the position within the lower electrode 170. means Specifically, it means that the closer to the origin on the graph, the closer to the first lower electrode layer 171 disposed on one side of the second lower electrode layer 172, and the farther from the origin, the closer the second lower electrode layer 172 is. It means getting closer to the first lower electrode layer 171 disposed on the other side. That is, as it approaches the origin on the graph, it means that the center of the second lower electrode layer 172 gets closer to the second surface 171S2 of the first lower electrode layer 171, and as it gets farther from the origin, the second lower electrode layer 172 ) means being closer to the fourth surface 171S4 of the first lower electrode layer 171.

In addition, the first material (M) may be any one of the materials described above. For example, the first material M may be niobium (Nb), and hereinafter, the first material M will be described based on niodium (Nb).

As shown in FIG. 4 , the concentration of niobium (Nb) may increase as the cross-sectional view approaches the outer surface from the inner surface of the first lower electrode layer 171 . That is, the concentration of niobium (Nb) is the highest on the first surface 171S1 and the third surface 171S3, which are the inner surfaces of the first lower electrode layer 171, and the first lower electrode layer 171, which is the inner surface of the first lower electrode layer 171. The concentration of niobium (Nb) decreases from the surface 171S1 and the third surface 171S3 toward the second surface 171S2 and the fourth surface 171S4, which are outer surfaces of the first lower electrode layer 171, and The concentration of niobium (Nb) in the surface 171S2 and the fourth surface 171S4 may be minimal. The above-described concentration gradient of niobium (Nb) doped in the first lower electrode layer 171 may be a concentration gradient by a manufacturing process described later with reference to FIGS. 10 to 13 . A detailed description thereof will be described later with reference to FIGS. 10 to 13 .

Also, the second lower electrode layer 172 may be in an undoped state, and the second lower electrode layer 172 may not include niobium (Nb).

As such, when the lower electrode 170 includes the doped first lower electrode layer 171 , the capacitance of the capacitor structure CS may be increased. That is, when the doped first lower electrode layer 171 is interposed between the undoped second lower electrode layer 172 and the dielectric layer 180, the dielectric layer 180 having an increased dielectric constant is placed on the lower electrode 170. can be formed in This may be because the doped first lower electrode layer 171 directly contacts the dielectric layer 180 and affects the crystal phase of the dielectric layer 180 formed on the first lower electrode layer 171 .

Further, in some embodiments, the second material is a metal such as tungsten (W), ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), Conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), tungsten nitride (WN), and iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium It includes at least one selected from conductive metal oxides such as oxide (SrRuO3), and the third material may include TSN (Ti-Si-N). However, the second material and the third material are not limited to the above materials and may be variously modified. Also, in some embodiments, the second material and the third material may be the same material. For example, the second material and the third material may include titanium nitride (TiN).

Supporters 190 may be disposed on both side surfaces of the lower electrode 170 . That is, the supporter 190 is disposed on both side surfaces of the lower electrode and may contact the first lower electrode layer 171 .

In addition, as the first lower electrode layer 171 is interposed between the supporter 190 and the second lower electrode layer 172, the supporter 190 and the second lower electrode layer 172 are interposed between the first lower electrode layer 171. It can be placed on and spaced apart from each other.

The supporter 190 is disposed between the lower electrode 170 and another lower electrode 170 adjacent thereto, and is a lower electrode in a process of removing a mold layer (refer to 'MD' in FIG. 16) or forming a dielectric layer 180. (170) can function as a support member to prevent it from falling or collapsing. The supporter 190 may include silicon nitride, silicon nitride, silicon boron nitride (SiBN), or silicon carbon nitride (SiCN). However, it is not limited thereto, and the material included in the supporter 190 may be variously modified.

A dielectric layer 180 may be disposed on side surfaces and top surfaces of the lower electrode 170 . The dielectric layer 180 may extend from the side of the lower electrode 170 to the upper and lower surfaces of the supporter 190 and may also be disposed on the etch stop layer 162 . That is, the dielectric layer 180 contacts the first lower electrode layer 171 and is disposed on a side surface of the first lower electrode layer 171, and the dielectric layer 180 has the first lower electrode layer 171 therebetween, and the first lower electrode layer 171 is disposed therebetween. It may be spaced apart from the second lower electrode layer 172 and disposed on a side surface of the second lower electrode layer 172 .

In some embodiments, dielectric layer 180 may include at least one of zirconium oxide, hafnium oxide, titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanides. can

In addition, the dielectric layer 180 may include hafnium oxide formed to predominantly have a tetragonal crystal phase. Also, in some embodiments, the dielectric layer 180 may have a multi-layer structure formed by stacking a first dielectric layer and a second dielectric layer, and at least one of the first dielectric layer and the second dielectric layer has a tetragonal crystal phase predominately. It may include hafnium oxide formed to have a similar shape.

An upper electrode 200 covering the lower electrode 170 may be disposed on the dielectric layer 180 . The upper electrode 200 is, for example, a metal such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), or titanium nitride. Conductive metal nitrides such as (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN), and iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium oxide ( It may include at least one selected from conductive metal oxides such as SrRuO3). However, the material included in the upper electrode 200 is not limited thereto and may be variously modified.

In some embodiments, the upper electrode 200 may be formed of a single material layer or a stacked structure of a plurality of material layers. For example, the upper electrode 200 may be formed of a single layer of titanium nitride (TiN) or a single layer of niobium nitride (NbN).

Also, in some embodiments, the upper electrode 200 may have a stacked structure including a first upper electrode layer including titanium nitride (TiN) and a second upper electrode layer including niobium nitride (NbN).

Hereinafter, other exemplary embodiments of a semiconductor device will be described with reference to FIGS. 5 and 6 . In the following embodiments, the same reference numerals refer to components identical to those of the previously described embodiments, and redundant descriptions will be omitted or simplified, and description will focus on differences.

5 and 6 are cross-sectional views taken along line II′ of FIG. 1 according to some embodiments.

According to the semiconductor device 100_1 including the capacitor structure CS_1 shown in FIG. 5 , unlike the semiconductor device 100 including the capacitor structure CS shown in FIG. 2 , both side surfaces of the lower electrode 170 It may include a first supporter 191 and a second supporter 192 disposed on the top.

Referring to FIG. 5 , a first supporter 191 and a second supporter 192 may be spaced apart from each other in a third direction (Z direction) perpendicular to each other on a side surface of the lower electrode 170 .

Specifically, the first supporter 191 is disposed on both side surfaces of the first lower electrode layer 171 positioned on the uppermost part of the lower electrode 170, and the second supporter 192 is connected to the first supporter 191. They may be spaced apart in three directions (Z direction) and disposed on both side surfaces of the first lower electrode layer 171 positioned at the center of the lower electrode 170 . That is, the first supporter 191 and the second supporter 192 directly contact the first lower electrode layer 171 and are spaced apart from the second lower electrode layer 172 with the first lower electrode layer 171 interposed therebetween. can be placed.

5 shows that one first supporter 191 and one second supporter 192 are disposed on one side of the lower electrode 170, but a second supporter 191 and one second supporter 192 are disposed on one side of the lower electrode 170. The number of each of the first supporter 191 and the second supporter 192 may vary. For example, in some embodiments, a supporter may be additionally disposed on one side of the lower electrode 170 . In this case, the added supporter may be disposed between the first supporter 191 and the second supporter 192 .

Also, in some embodiments, a supporter may be additionally disposed on one side of the lower electrode 170 positioned between the second supporter 192 and the etch stop layer 162 .

The plurality of first supporters 191 and the plurality of second supporters 192 may be spaced apart from each other by substantially the same distance along the third direction (Z direction), which is a vertical direction. However, it is not limited thereto, and the plurality of first supporters 191 and the plurality of second supporters 192 may be spaced apart from each other at different distances along the third direction (Z direction).

When the capacitor structure CS_1 according to the present embodiment includes the first supporter 191 and the second supporter 192 disposed on the side surface of the lower electrode 170, the mold layer ('MD' in FIG. 16 ) It is possible to effectively prevent the lower electrode 170 from collapsing or collapsing in the removal process or a subsequent process of the reference), and thus, a semiconductor device including a capacitor having improved electrical characteristics or reliability can be provided.

According to the semiconductor device 100_2 including the capacitor structure CS_2 shown in FIG. 6 , unlike the semiconductor devices 100 and 100_1 including the capacitor structures CS and CS_1 shown in FIGS. 2 and 5 , , Supporters 190 , 191 , and 192 may not be disposed on both sides of the lower electrode 170 .

Referring to FIG. 6 , since the supporters 190 , 191 , and 192 shown in FIGS. 2 and 5 are not disposed on both side surfaces of the lower electrode 170 , the upper surface of the etch stop layer 162 is higher than that of the supporters 190 , 191 , and 192 . A side surface of the first lower electrode layer 171 positioned at the level may be entirely covered by the dielectric layer 180 .

That is, in the embodiments shown in FIGS. 2 and 5 , a part of the side surface of the first lower electrode layer 171 positioned at a level higher than the upper surface of the etch stop layer 162 contacts the supporters 190 , 191 , and 192 , and the rest of the side surface. Unlike a portion of which is in contact with the dielectric layer 180 , all of the side surfaces of the first lower electrode layer 171 may be in contact with the dielectric layer 180 in the embodiment shown in FIG. 6 .

According to this embodiment, even when the supporters 190, 191, and 192 are not disposed on the side of the lower electrode 170 of the capacitor structure CS_2, the mold layer (see 'MD' in FIG. 16) is removed. Manufacturing process of the lower electrode 170 as the lower electrode 170 is prevented from collapsing or collapsed by the second lower electrode layer 172 having a higher rigidity than the first lower electrode layer 171 in a process or a subsequent process. And it is possible to prevent the shape of the lower electrode 170 from changing in subsequent processes.

Hereinafter, a method of manufacturing a semiconductor device will be described with reference to FIGS. 7 to 19 . Hereinafter, the same reference numerals refer to the same components described previously, and redundant descriptions will be omitted or simplified, and the differences will be mainly described.

7 to 19 are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.

Referring to FIG. 7 , device isolation trenches 112T may be formed in the substrate 110 , and device isolation layers 112 may be formed in the device isolation trenches 112T. An active region AC may be defined on the substrate 110 by the device isolation layer 112 .

Next, a gate line trench 120T may be formed in the substrate 110 using a photo and etching process. The gate line trenches 120T may extend parallel to each other and have a line shape crossing the active region AC.

Subsequently, a gate insulating layer 122 may be formed on an inner wall of the gate line trench 120T. After forming a gate conductive layer (not shown) filling the inside of the gate line trench 120T on the gate insulating layer 122, a portion of the gate conductive layer is removed to a predetermined height by an etch-back process to form a gate electrode 124 can form

Thereafter, an insulating material is formed to fill the remaining portion of the gate line trench 120T, and the insulating material is planarized until the top surface of the substrate 110 is exposed, thereby forming a gate on the inner wall of the gate line trench 120T. A capping layer 126 may be formed.

Subsequently, impurity ions may be implanted into the substrate 110 to form a first source/drain region 114A and a second source/drain region 114B. The first source/drain region 114A and the second source/drain region 114B may be positioned on both sides of the gate structure 120 .

Next, the bit line structure 130 and the first insulating layer 142 and the second insulating layer 144 surrounding the bit line structure 130 may be formed on the substrate 110 . For example, the first insulating layer 142 may be formed first, and then an opening (not shown) exposing the upper surface of the first source/drain region 114A may be formed in the first insulating layer 142 . A bit line contact 132 filling the opening may be formed on the first insulating layer 142 .

Subsequently, a conductive layer (not shown) and an insulating layer (not shown) are sequentially formed on the first insulating layer 142, and the insulating layer and the conductive layer are patterned to be parallel to the upper surface of the substrate 110. An extended bit line 134 and a bit line capping layer 136 may be formed.

Then, bit line contact 132, bit line 134, and bit line capping layer 136

A bit line spacer 138 may be formed on a side surface of the bit line spacer 138 . A second insulating layer 144 covering the bit line structure 130 may be formed on the first insulating layer 142 .

Subsequently, an opening (not shown) exposing the upper surface of the second source/drain region 114B is formed in the first insulating layer 142 and the second insulating layer 144, and a capacitor contact 150 is formed in the opening. can form In some embodiments, the capacitor contact 150 is formed by sequentially forming a lower contact pattern (not shown), a metal silicide layer (not shown), a barrier layer (not shown), and an upper contact pattern (not shown) inside the opening. can be formed.

Subsequently, a third insulating layer 146 is formed on the capacitor contact 150 and the second insulating layer 144, and an opening (not shown) exposing the upper surface of the capacitor contact 150 is formed in the third insulating layer 146. ) may be formed, and a landing pad 152 may be formed in the opening.

Subsequently, an etch stop layer 162 and the mold structure MS may be sequentially formed on the landing pad 152 and the third insulating layer 146 . The mold structure MS may include a mold layer MD and a preliminary supporter layer 190P sequentially stacked on the etch stop layer 162 . However, it is not limited thereto, and in some embodiments, the mold structure MS may include a plurality of first preliminary supporter layers (not shown), a second preliminary supporter layer (not shown), and a mold layer MD. In addition, the first preliminary supporter layer, the second preliminary supporter layer, and the mold layer MD may be alternately disposed.

The mold layer MD and the etch stop layer 162 may include materials having an etch selectivity to each other. For example, when the mold layer MD includes silicon oxide, the etch stop layer 162 may include silicon nitride, silicon nitride, or silicon carbon nitride (SiCN).

Also, the mold layer MD and the preliminary supporter layer 190P may include materials having an etch selectivity to each other. For example, when the mold layer MD includes silicon oxide, the preliminary supporter layer 190P may include silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), or silicon carbonitride (SiCN). .

Subsequently, the preliminary supporter layer 190P, the mold layer MD, and the etch stop layer 162 may be patterned. The preliminary supporter layer 190P, the mold layer MD, and the etch stop layer 162 may be patterned using the same mask. When the preliminary supporter layer 190P is patterned, the supporter 190 may be formed as shown in FIG. 8 . A mold opening MDH may be formed in the mold layer MD, and an opening 162H may be formed in the etch stop layer 162 . The mold opening MDH and the opening 162H may correspond to a portion from which the preliminary supporter layer 190P is removed. The mold opening MDH and the opening 162H may have substantially the same planar shape. As the mold opening MDH and the opening 162H are formed in the mold layer MD and the etch stop layer 162, respectively, the upper surface of the landing pad 152 may be exposed.

Next, referring to FIG. 9 , a first preliminary lower electrode layer 171P may be formed in the mold opening MDH. The first preliminary lower electrode layer 171P may conformally cover the side surface and bottom of the mold opening MDH without completely filling the mold opening MDH. In addition, the first preliminary lower electrode layer 170P may also cover the upper surface of the supporter 190.

For example, the forming process of the first preliminary lower electrode layer 171P is a chemical vapor deposition (CVD) process, a metal organic CVD (MOCVD) process, an atomic layer deposition (ALD) process, or a metal It may be an organic ALD (MOALD) process. However, the process of forming the first preliminary lower electrode layer 171P is not limited thereto and may be variously changed.

Next, referring to FIGS. 10 and 11 , a source material layer SL may be formed on the first preliminary lower electrode layer 171P. The source material layer SL may conformally cover the first preliminary lower electrode layer 171P without completely filling the mold opening MDH.

As shown in FIG. 11 in which region B of FIG. 10 is enlarged, the source material layer SL may include the above-described first material M. The first material M may be uniformly distributed in the source material layer SL. The first material M may be a dopant that moves from the source material layer SL to the first preliminary lower electrode layer 171P in a subsequent process to dope the first preliminary lower electrode layer 171P. The first material M may include, for example, niobium (Nb), vanadium (V), chromium (Cr), tantalum (Ta), molybdenum (Mo), tungsten (W), cobalt (Co), or rhodium (Rh). , iridium (Ir), or a metal material in combination thereof, but is not limited thereto, and the first material (M) may be variously changed.

Next, referring to FIGS. 12 and 13 , the first material M in the source material layer SL may be moved into the first preliminary lower electrode layer 171P. For example, by performing an annealing process on the source material layer SL and the first preliminary lower electrode layer 171P, the first material M in the source material layer SL is formed in the first preliminary lower electrode layer 171P. , and thus, the first preliminary lower electrode layer 171P may be doped.

That is, as shown in FIG. 13 , which is an enlarged region C of FIG. 12 , the first material M in the source material layer SL is the first preliminary lower electrode layer from the inner surface of the first preliminary lower electrode layer 171P in cross section. It can diffuse toward the outer surface of (171P). That is, the first material M is applied from the first side surface 171PS1 of the first preliminary lower electrode layer 171P in contact with the source material layer SL to the first preliminary lower electrode layer 171P in contact with the mold layer MD. may be diffused toward the second side surface 171PS2.

The annealing process for the first preliminary lower electrode layer 171P and the source material layer SL may be performed under, for example, an ammonia (NH ₃ ) atmosphere, a nitrogen (N ₂ ) atmosphere, an argon (Ar) atmosphere, or a combination thereof. can In addition, the annealing process may be performed at a temperature of about 200 ° C to about 800 ° C, for example, about 400 ° C to about 600 ° C. However, the temperature of the annealing process is not limited to the above-described numerical range, and variously can be changed.

Next, referring to FIGS. 13 and 14 , after the first material M in the source material layer SL is moved into the first preliminary lower electrode layer 171P, the source material layer SL may be removed.

As the source material layer SL is removed, the first preliminary lower electrode layer 171P may be exposed, and the first preliminary lower electrode layer 171P may be doped. As described above, as the first material M is diffused from the inner surface of the first preliminary lower electrode layer 171P toward the outer surface of the first preliminary lower electrode layer 171P, the first preliminary lower electrode layer 171P is formed. In a portion close to the inner surface of the first material M may be distributed with a relatively high density. Conversely, the first material M may be distributed with a relatively low density in a portion close to the outer surface of the first preliminary lower electrode layer 171P. Accordingly, the concentration of the first material M diffused into the first preliminary lower electrode layer 171P may decrease from the inner surface to the outer surface of the first preliminary lower electrode layer 171P.

Next, referring to FIGS. 15 and 16 , a second preliminary lower electrode layer 172P filling the inside of the mold opening MDH may be formed on the first preliminary lower electrode layer 171P. In addition, the second preliminary lower electrode layer 172P may also be formed on the upper surface of the supporter 190 .

The first lower electrode layer 171 may include a second material, and the second lower electrode layer 172 may include a third material that is different from the second material and has higher stiffness than the second material. For example, the second material is a metal such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), titanium nitride (TiN ), conductive metal nitrides such as tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN), and iridium oxide (IrO ₂ ), ruthenium oxide (RuO ₂ ), strontium ruthenium oxide ( It includes at least one selected from conductive metal oxides such as SrRuO ₃ ), and the third material may include TSN (Ti-Si-N). However, the second material and the third material are not limited to the above materials and may be variously modified. In some cases, the first lower electrode layer 171 and the second lower electrode layer 172 may include a second material.

In some embodiments, the process of forming the second preliminary lower electrode layer 172P is a chemical vapor deposition (CVD) process, a metal organic CVD (MOCVD) process, an atomic layer deposition (ALD) process, or It may be a metal organic ALD (MOALD) process. However, the process of forming the second preliminary lower electrode layer 172P is not limited thereto and may be variously modified.

Also, in some embodiments, the deposition process of the second preliminary lower electrode layer 172P may be performed by repeating a material layer forming cycle a plurality of times, and the material layer forming cycle includes inputting a first precursor source, a redundant It may include purging the first precursor source, introducing a second precursor source, and purging an extra second precursor source.

Subsequently, the portion covering the supporter 190 among the first preliminary lower electrode layer 171P and the second preliminary lower electrode layer 172P and the portion protruding from the upper surface of the supporter 190 among the second preliminary lower electrode layer 172P are removed. can For example, etch back or polishing may be performed.

As a result, the lower electrode 170 may be completed. That is, the remaining part of the first preliminary lower electrode layer 171P becomes the first lower electrode layer 171 of the lower electrode 170, and the remaining part of the second preliminary lower electrode layer 172P becomes the lower electrode 170. It may become the second lower electrode layer 172 .

Next, referring to FIG. 17 , an empty space OP may be formed between the supporter 190 and the etch stop layer 162 by removing the mold layer MD. That is, by removing the mold layer MD, the upper surface of the etch stop layer 162 , the side surface of the first lower electrode layer 171 , and the lower surface of the supporter 190 may be exposed to the empty space OP.

In the process of removing the mold layer MD, the supporter 190 is not removed, and the lower electrodes 170 adjacent to each other may be connected to and supported by the supporter 190 .

In addition, as described above, since the second lower electrode layer 172 includes a material having high rigidity, it prevents the lower electrode 170 from being bent or deformed in the process of removing the mold layer MD, thereby reducing the aspect ratio. The original shape of the lower electrode 170 may be maintained.

Next, referring to FIG. 18 , a dielectric layer 180 may be conformally formed on the lower electrode 170 and the supporter 190 .

For example, the formation process of the dielectric layer 180 is a chemical vapor deposition (CVD) process, a metal organic CVD (MOCVD) process, an atomic layer deposition (ALD) process, or a metal organic ALD (MOALD) process. ) can be fair. However, the formation process of the dielectric layer 180 is not limited thereto and may be variously modified.

The dielectric layer 180 may be formed using hafnium oxide, and a portion of the dielectric layer 180 contacting the lower electrode 170 may have a tetragonal crystal phase predominately.

As described above with reference to FIGS. 10 to 13 , the first material M in the source material layer SL is spread from the inner surface of the first preliminary lower electrode layer 171P to the outer surface of the first preliminary lower electrode layer 171P in cross-section. Since the diffusion is directed toward the side surface, a process for removing the material remaining on the outer surface of the first preliminary lower electrode layer 171P, the source material layer SL, and the like may be omitted, and the mold layer MD may not be removed. Since the first preliminary lower electrode layer 171P is formed in , an outer surface of the first preliminary lower electrode layer 171P may have a relatively even surface roughness.

In addition, in the process of removing the mold layer MD described with reference to FIG. 16 , a part of the outer surface of the first lower electrode layer 171 that is in contact with the mold layer MD may be removed together. However, as described above, the concentration of the first material (refer to 'M' in FIG. 13) doped in the first lower electrode layer 171 is maximum on the inner surface in contact with the second lower electrode layer 172, Since the outer surface in contact with the mold layer MD is minimal, the first lower electrode layer 171 may maintain a high doping concentration even if a part of the surface of the outer surface is removed together with the mold layer MD.

Accordingly, the crystallinity of the dielectric layer 180 formed on the first lower electrode layer 171 may be improved, and the dielectric layer 180 having a higher dielectric constant may be formed.

Next, referring to FIG. 19 , an upper electrode 200 covering the lower electrode 170 and the supporter 190 may be formed on the dielectric layer 180 . That is, the upper electrode 200 may be formed to cover the side surface and upper surface of the lower electrode 170 . In addition, the upper electrode 200 may be formed to cover the etch stop layer 162 and the top and bottom surfaces of the supporter 190 . Through this process, the semiconductor device 100 including the capacitor structure CS shown in FIG. 19 may be completed.

The manufacturing process of the semiconductor device 100 described with reference to FIGS. 7 to 19 is only one embodiment and is not limited, and in some embodiments, some of the manufacturing process steps described above may be omitted or additional manufacturing process steps may be added. there is.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also included in the scope of the present invention. that fall within the scope of the right.

100: semiconductor device
110: substrate
120: gate structure
130: bit line structure
150: capacitor contact
152: landing pad
170: lower electrode
171: first lower electrode layer
172: second lower electrode layer
180: dielectric layer
190: Supporter
200: upper electrode
CS: capacitor structure
MS: mold structure
MD: mold layer
SL: source material layer

Claims (10)

substrate, and
Including a capacitor structure located on the substrate,
The capacitor structure,
A plurality of lower electrodes spaced apart from each other;
A supporter positioned between the plurality of lower electrodes;
An upper electrode covering the plurality of lower electrodes, and
A dielectric layer positioned between the lower electrodes and the upper electrode,
Each of the plurality of lower electrodes is
a first lower electrode layer, and
A second lower electrode layer surrounded by the first lower electrode layer;
The first lower electrode layer includes a second material doped with a first material,
The second lower electrode layer includes a third material different from the first material and the second material,
The semiconductor device of claim 1 , wherein the doping concentration of the first material increases as it is closer to the second lower electrode layer. In paragraph 1,
The third material has higher rigidity than the second material. In paragraph 2,
The second material includes at least one of TiN, TaN, NbN, MoN, and WN,
The semiconductor device of claim 1 , wherein the third material includes TSN (Ti-Si-N). In paragraph 1,
The semiconductor device of claim 1 , wherein the first material includes at least one of Nb, V, Cr, Ta, Mo, W, Co, Rh, and Ir. In paragraph 1,
The supporter,
A first supporter positioned between upper regions of the plurality of lower electrodes, and
A semiconductor device comprising a second supporter positioned between central regions of the plurality of lower electrodes. In paragraph 1,
The semiconductor device of claim 1 , wherein the dielectric layer is further positioned between the supporter and the upper electrode. Laminating a mold layer and a supporter on a substrate;
Forming an opening penetrating the mold layer and the supporter;
Forming a first lower electrode layer in the opening;
Forming a source material layer on the first lower electrode layer;
Proceeding a heat treatment process to diffuse the first material included in the source material layer into the first lower electrode layer;
removing the source material layer;
Forming a second lower electrode layer on the first surface of the first lower electrode layer;
removing the mold layer;
forming a dielectric layer on the second surface of the first lower electrode layer; and
Forming an upper electrode on the dielectric layer,
The method of claim 1 , wherein the source material layer is made of an oxide containing the first material. In paragraph 7,
The method of claim 1 , wherein the first material includes at least one of Nb, V, Cr, Ta, Mo, W, Co, Rh, and Ir. In paragraph 8,
The first material is diffused into the first lower electrode layer so that the first lower electrode layer is doped with the first material;
A method of manufacturing a semiconductor device in which the doping concentration of the first material increases as it is closer to the second lower electrode layer. In paragraph 7,
The first lower electrode layer includes at least one of TiN, TaN, NbN, MoN, and WN,
The second lower electrode layer is a method of manufacturing a semiconductor device including TSN (Ti-Si-N).

Images