KR20230047969A - Semiconducter device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device according to one embodiment of the present invention comprises: a semiconductor substrate; an active area located in the substrate; a boundary insulating layer that surrounds the active area; a barrier layer located at a circumference of the insulating layer; a first gate structure that crosses the active area; a first contact that contacts a first part of the active area; and a second contact that contacts a second part of the active area and the barrier layer, wherein the first part and the second part of the active area are located on opposite sides centered on the first gate structure. Therefore, the present invention is capable of reducing data loss.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTER DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a semiconductor device and a manufacturing method thereof.

As the degree of integration of semiconductor memory devices increases, circuits become more minute, and accordingly, design rules are reduced, making processes increasingly complex and difficult.

A technical problem to be solved by the present invention is to reduce defects and improve performance of a semiconductor device.

A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, an active region positioned within the substrate, a boundary insulating layer surrounding the active region, a barrier layer positioned around the insulating layer, and a barrier layer extending across the active region. a first gate structure, a first contact in contact with the first portion of the active region, and a second contact in contact with the second portion of the active region and the barrier layer; Part 2 is located on the opposite side of the first gate structure.

The semiconductor device further includes a second gate structure crossing the active region in parallel with the first gate structure, wherein the active region is positioned on an opposite side of the first portion of the active region with the gate structure as a center. The semiconductor device further includes three portions, wherein the barrier layer includes first, second, and third portions positioned around the first, second, and third portions of the active region, respectively, and wherein the semiconductor device comprises: A third contact contacting the third portion and the third portion of the barrier layer may be further included.

The barrier layer may be positioned within a first trench of the substrate, and the gate structure may be positioned within a second trench of the substrate.

The second trench may be deeper than the first trench.

The gate structure includes a gate conductive layer and a capping insulating layer sequentially stacked, and a bottom surface of the barrier layer may not reach a bottom surface of the capping insulating layer.

The second trench may be shallower than the first trench.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first trench in a semiconductor substrate to define an active region, forming a first insulating layer and a barrier layer on sidewalls of the first trench, forming second and third trenches that are parallel to each other across the active region, forming gate structures within the second and third trenches, and forming first, second, and third portions of the active region, respectively. and forming first, second and third contacts, wherein the first portion of the active region is positioned between the second trench and the third trench, and the second and third portions of the active region are positioned between the second trench and the third trench. is positioned opposite to the first portion with the second and third trenches interposed therebetween, and the second contact and the third contact contact the barrier layer.

The barrier layer may be divided into a plurality of portions by the second and third trenches, and the second contact and the third contact may contact different portions of the barrier layer.

The first contact may not contact the barrier layer.

The second and third trenches may be deeper than the first trench.

As such, by disposing the barrier layer around the active region, capacitance of the capacitor can be increased and data loss can be reduced.

1 is a schematic layout view of a semiconductor device according to an exemplary embodiment, and FIG. 2 is an example of a cross-sectional view of the semiconductor device of FIG. 1 taken along line II-II.
FIG. 3 is a graph showing the potential according to the depth in the structure shown in FIGS. 1 and 2 with and without a barrier layer.
4, 7, and 9 are layout views in an intermediate process of manufacturing the semiconductor device of FIG. 2 .
5 and 6 are cross-sectional views of the semiconductor device of FIG. 4 taken along line VV.
FIG. 8 is a cross-sectional view of the semiconductor device of FIG. 7 taken along line VIII-VIII.
FIG. 10 is a cross-sectional view of the semiconductor device of FIG. 9 taken along line XX.
11 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
12 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
13 to 17 are schematic cross-sectional views taken along line XIII-XIII of FIG. 12 in an intermediate stage of manufacturing the semiconductor device shown in FIG. 12 .

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. In order to clearly describe the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

The accompanying drawings relate to dynamic random access memory (DRAM), but the present invention is not limited thereto.

FIG. 1 is a schematic layout view of a semiconductor device according to an exemplary embodiment, and FIG. 2 is an example of a cross-sectional view of the semiconductor device of FIG. 1 taken along line II-II.

Referring to FIG. 1 , a semiconductor device according to an exemplary embodiment of the present invention includes a plurality of active regions (AC), a plurality of direct contacts (DC), a plurality of buried contacts (BC), and a plurality of It includes a word line (WL) of. The semiconductor device may also include a plurality of bit lines (not shown).

A plurality of word lines WL are in the x direction, for example. For example, they may run parallel to each other and may be spaced evenly.

The bit line may cross, for example, be orthogonal to the word line WL. When the word line WL extends in the x direction, for example, the bit line may extend in the y direction. A plurality of bit lines may be arranged parallel to each other at even intervals.

The word line WL and the bit line are electrically insulated, and the word line WL and the bit line may cross each other to define a cell. For example, the word line WL and the bit line may intersect with an insulating layer interposed therebetween, and the bit line may be positioned above the word line WL at the intersection. However, the vertical relationship between the word line WL and the bit line is not limited thereto.

Widths of word lines WL and bit lines, intervals between word lines WL, and intervals between bit lines may be determined according to design rules.

Each active region AC may cross the word line WL with an insulating layer interposed therebetween and may be connected to the bit line. Each active region AC may also be connected to a capacitor (not shown). Through this structure, it is possible to form a transistor having a channel in the active region AC. In this case, the word line WL serves as a gate conductive layer and is formed on both sides of the word line WL in the active region AC. The located portion functions as a source/drain area.

According to one embodiment of the present invention, referring to FIG. 1 , a plurality of active regions AC are regularly arranged in a matrix form. However, the embodiment of the present invention is not limited thereto, and, for example, every two rows have a regular arrangement, and adjacent rows may be staggered from each other.

According to one embodiment of the present invention, the active region AC may have a relatively long island shape having a short axis and a long axis, for example, a long bar shape in a diagonal line or an oblique line direction. can be This shape is only based on the reduction of the design rule of the semiconductor device, and the shape of the active region AC according to the exemplary embodiment is not limited thereto.

According to one embodiment of the present invention, each active region AC may cross two word lines WL and be connected to one bit line. In this case, the active region AC can be divided into three parts with the word line WL as a boundary, the middle part is connected to the bit line through the direct contact DC, and both ends have buried contacts (BC). ) It may be connected to a capacitor (not shown) through.

The direct contact DC may overlap and contact the bit line and the active region AC, and may be located at the center of the active region AC. The buried contact BC may overlap and contact both ends of the active region AC.

However, embodiments of the present invention are not limited thereto and may have various arrangements.

The aforementioned word line (WL), bit line, active region (AC), direct contact (DC), buried contact (BC), and the like can be implemented with various structures.

Referring to FIG. 2 , a semiconductor device according to an exemplary embodiment may include a substrate 10 . The substrate 10 may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate 10 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. .

The active region CA may be defined by the region isolation layer 14 formed in the substrate 10 . That is, a portion of the substrate 10 without the region isolation layer 14 may be the active region AC.

The region isolation layer 14 may occupy a predetermined depth on the surface of the substrate 10 and may have a shallow trench isolation (STI) structure in which a trench is formed on the surface of the substrate 10 to a predetermined depth and then filled with an insulating material.

The region isolation layer 14 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto. Although the region isolation layer 14 is shown as a single layer in FIG. 2 , it is only for convenience of explanation, and is not limited thereto. Each of the region isolation layers 14 may be formed of one insulating layer or a plurality of insulating layers depending on their width.

A barrier layer 15 and a boundary insulating layer 16 are positioned between the region isolation layer 14 and the active region AC. The barrier layer 15 contacts the region isolation layer 14 and the boundary insulating layer 16 contacts the active region AC.

Since the active region AC has an island shape, the barrier layer 15 substantially surrounds the active region AC. However, the barrier layer 15 may be divided into two parts located at the center and two parts located at both ends of the word line WL as a boundary.

The boundary insulating layer 16 may also have a shape similar to that of the barrier layer 15 . However, the boundary insulating layer 16 may extend below the region isolation layer 14 and cover the entire surface of the trench accommodating the region isolation layer 14 .

The barrier layer 15 is a thin film containing metal and may have a thickness of about 3 to 4 nm. The barrier layer 15 may be, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, It may include at least one of IrOx, RuOx, and combinations thereof.

The boundary insulating layer 16 is a thin film containing an insulating material and may have a thickness of about 3 to 5 nm. The boundary insulating layer 16 may include the same material as the region isolation layer 14, but is not limited thereto. The boundary insulating layer 16 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The word line WL according to an embodiment of the present invention may be a buried type. In FIG. 2 , gate structures 22 , 24 , 25 , and 26 formed in the substrate 10 are associated with the word line WL. The gate structures 22, 24, 25, and 26 may cross the region isolation layer 14 and the active region AC, and the closed barrier layer 15 surrounding the active region AC is placed at the center. It can be divided into two parts and both ends. The gate structures 22, 24, 25, and 26 include a gate conductive layer 24, a capping conductive layer 25, and a capping insulating layer 26 sequentially stacked, and a gate insulating layer 22 surrounding them. can do. Here, the gate conductive layer 24 may correspond to the word line WL.

The gate structures 22, 24, 25, and 26 may be formed by digging a trench in the substrate 10, forming a gate insulating layer 22 on the surface of the trench, and then stacking three layers 24, 25, and 26 therein. can The depth of the trench may be greater than that of the region isolation layer 14, and thus the barrier layer 15 may be divided into several parts.

Referring to FIG. 2 , the gate insulating layer 22 may be formed by thinly coating the surface of the trench along the curved surface. However, embodiments of the present invention are not limited thereto.

The gate insulating layer 22 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. The high dielectric constant material is, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium Zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium At least one of strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof can include

The gate conductive layer 24 may be positioned on the gate insulating layer 22 and may fill a lower space of the trench. The gate conductive layer 24 may be formed of a single layer or multiple layers.

The gate conductive layer 24 and the capping conductive layer 25 may be, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal. It may contain at least one of metal oxides. The gate conductive layer 24 may be, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co , Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi , IrOx, RuOx, and combinations thereof.

The capping insulating layer 26 may be disposed on the gate conductive layer 24 and may fill an upper space of the trench. 2 illustrates that the gate insulating layer 22 covers all sidewalls of the trench, the gate insulating layer 22 may cover only the lower portion of the sidewalls of the trench and may contact the upper sidewalls with the capping insulating layer 26 .

The capping insulating layer 26 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. may contain one.

The direct contact DC is positioned between two word lines WL crossing the active region AC and may contact the active region AC through a direct contact hole formed in the active region AC. The direct contact DC may include a conductor such as polysilicon or metal. A direct contact (DC) may be connected to the bit line.

The buried contact BC overlaps both ends of the active region AC and exposes the active region AC and the barrier layer 15 through buried contact holes exposing the active region AC and the barrier layer 15. make contact The buried contact BC may be connected to the capacitor.

The buried contact BC may include, for example, at least one of a semiconductor material containing impurities, a conductive silicide compound, a conductive metal nitride, and a metal. The buried contact BC may include, for example, polysilicon containing impurities. The buried contact BC may include, for example, polysilicon containing phosphorus, arsenic, boron, or a combination thereof as an impurity.

The direct contact hole and the buried contact hole may be formed in an insulating buffer layer (not shown) stacked on the substrate 10 .

In the semiconductor memory device having such a structure, when storing 1, the barrier layer 15 is positively charged, so the electric field is reduced, and when storing 0, the barrier layer 15 is charged with electrons, so the electric field is also reduced. This is equivalent to an increase in the electrode area of the capacitor connected to the buried contact BC, and accordingly, capacitance may increase and loss data may decrease.

Figure 3 shows the potential according to the depth in the case of the presence and absence of the barrier layer in the structures shown in Figures 1 and 2. In the case of the absence of the barrier layer, the potential rises / falls rapidly even if it goes down a little, but the barrier layer This shows that the potential difference according to the depth is not sharp when there is .

Then, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 10 .

4, 7, and 9 are layout views in an intermediate process of manufacturing the semiconductor device of FIG. 2, FIGS. 5 and 6 are cross-sectional views of the semiconductor device of FIG. 4 taken along the line V-V, and FIG. 7 is a cross-sectional view of the semiconductor device taken along line VIII-VIII, and FIG. 10 is a cross-sectional view of the semiconductor device of FIG. 9 taken along line X-X.

Referring to FIGS. 4 and 5 , a trench 13 defining an active region AC is formed in the substrate 10, and then referring to FIG. 6 , a barrier layer 15 and a boundary insulating layer 16 are formed. layer up

Referring to FIGS. 7 and 8 , the barrier layer 15 and the boundary insulating layer 16 are dry etched to form the barrier layer 15 and the boundary insulating layer 16 positioned on the bottom surface of the trench 13 and the upper portion of the substrate 10 . ) is removed. Then, the barrier layer 15 and the boundary insulating layer 16 remain only on the sidewall of the trench 13 and surround the active region AC.

Next, the trench 13 is filled with the region isolation layer 14 . Specifically, the height of the insulating film may be reduced by stacking the insulating film and dry etching or polishing.

Next, referring to FIGS. 9 and 10 , a plurality of trenches 20 extending across the active region AC in one direction are formed in the substrate 10 . Two trenches 20 cross one active region AC, and the depth of the trenches 20 may be greater than that of the previously formed trench 13 . Accordingly, the barrier layer 15 and the boundary insulating layer 16 surrounding one active region AC are separated into four parts, namely two central parts and both end parts.

Subsequently, as shown in FIGS. 1 and 2 , gate structures 22 , 24 , 25 , and 26 are formed in the trench 20 , and a direct contact DC and a buried contact BC are formed.

Next, referring to FIG. 11 , a semiconductor device according to another exemplary embodiment of the present invention will be described in detail.

11 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 11 , the semiconductor device according to the present embodiment, like the semiconductor device shown in FIG. 2 , includes an active region AC, a direct contact DC, a buried contact BC, gate structures 22, 24, 25 and 26), a region isolation layer 14, and a boundary insulating layer 16 and a barrier layer 15.

The region isolation layer 14 according to the present embodiment is deeper than the gate structures 22, 24, 25, and 26, but the barrier layer 15 is the capping conductive layer 25 of the gate structures 22, 24, 25, and 26. ) does not reach Accordingly, the barrier layer 15 can be separated even if the trenches ( 20 in FIGS. 9 and 10 ) for the gate structures 22 , 24 , 25 , and 26 are not deeper than the region isolation layer 14 .

Next, referring to FIGS. 12 to 17 , a semiconductor device according to another embodiment of the present invention will be described in detail.

12 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention, and FIGS. 13 to 17 are schematic cross-sectional views in an intermediate stage of manufacturing the semiconductor device shown in FIG. 12 along line XIII-XIII in FIG. It is cut along and shown.

Referring to FIGS. 12 and 17 , the semiconductor device according to the present embodiment, like the semiconductor device shown in FIG. 2 , has an active region AC, a direct contact DC, a buried contact BC, a gate structure 22, 24 and 26), a region isolation layer 14, and a boundary insulating layer 16 and a barrier layer 15.

In this embodiment, the barrier layer 15 is integrated with the buried contact BC, and the barrier layer 15 covers the top surface of the sidewall of the boundary insulating layer 16 . The boundary insulating layer 16 is also present on the lower surface of the region isolation layer 14 .

The gate structures 22, 24, and 26 include a gate insulating layer 22, a gate conductive layer 24, and a capping insulating layer 26, and unlike FIG. 2, the capping conductive layer 25 is not separately formed.

In the manufacturing method of the semiconductor device according to the present embodiment, first, referring to FIG. 13 , after forming the trench for the active region AC, the boundary insulating layer 16 is deposited and the remaining portion except for the inside of the trench is removed. The sacrificial layer 12 is deposited and etched to remove only the portion covering the boundary insulating layer 16 and the sidewall. Next, the inside of the trench is filled with the region isolation layer 14 .

Referring to FIG. 14 , trenches for the gate structures 22 , 24 , and 26 are formed and a gate insulating layer 22 is formed inside the trenches. Referring to FIG. 15 , a gate conductive layer 24 and a capping insulating layer 26 are formed inside the trench formed on the surface of the gate insulating layer 22 .

Referring to FIG. 16 , a pair of adjacent gate structures 22 , 24 , and 26 and an area between them are covered with the photoresist layer 30 and the exposed portion of the sacrificial layer 12 is removed. Reference numeral 17 denotes an empty space after the sacrificial layer 12 is removed.

Referring to FIG. 17, a conductive layer for the buried contact BC is stacked. At this time, the sacrificial layer 12 is removed and the empty space 17 is filled with the conductive layer, and this portion becomes the barrier layer 15. . Subsequently, the conductive layer is etched to form a buried contact BC, and the photoresist layer 30 is removed.

Claims (10)

semiconductor substrate,
an active region located within the substrate;
A boundary insulating layer surrounding the active region;
A barrier layer positioned around the insulating layer,
A first gate structure crossing the active region;
a first contact in contact with a first portion of the active area; and
a second contact in contact with the second portion of the active region and the barrier layer;
Including,
The first part and the second part of the active region are located on opposite sides of the first gate structure.
semiconductor device. In paragraph 1,
The semiconductor device further includes a second gate structure crossing the active region in parallel with the first gate structure;
The active region further includes a third portion located on the opposite side of the first portion of the active region with respect to the gate structure;
the barrier layer includes first, second, and third portions positioned around the first, second, and third portions of the active region, respectively;
The semiconductor device further comprises a third contact contacting the third portion of the active region and the third portion of the barrier layer.
semiconductor device. In paragraph 2,
the barrier layer is located in the first trench of the substrate;
The gate structure is located in the second trench of the substrate
semiconductor device. In paragraph 3,
The second trench is deeper than the first trench. In paragraph 3,
The gate structure includes a gate conductive layer and a capping insulating layer sequentially stacked,
The bottom surface of the barrier layer is less than the bottom surface of the capping insulating layer.
semiconductor device. In paragraph 5,
The second trench is shallower than the first trench. Forming a first trench in the semiconductor substrate to define an active region;
Forming a first insulating layer and a barrier layer on sidewalls of the first trench;
forming second and third trenches that are parallel to each other and cross the active region;
forming gate structures in the second and third trenches; and
forming first, second and third contacts respectively contacting the first, second and third portions of the active region;
Including,
a first portion of the active region is located between the second trench and the third trench;
The second and third portions of the active region are positioned on opposite sides of the first portion with the second and third trenches interposed therebetween;
The second contact and the third contact contact the barrier layer.
A method of manufacturing a semiconductor device. In paragraph 7,
The barrier layer is separated into a plurality of parts by the second and third trenches,
The second contact and the third contact contact different portions of the barrier layer.
A method of manufacturing a semiconductor device. In paragraph 8,
The method of claim 1 , wherein the first contact does not contact the barrier layer. In paragraph 8,
The second and third trenches are deeper than the first trench.

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