KR20200107895A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same and, more specifically, to a semiconductor device and a method for manufacturing the same, which are to insulate the remaining portions using an ion implantation process, in an embedded contact which is not partially etched. A semiconductor device according to some embodiments for achieving the technical problem of the present invention comprises: a substrate; a gate structure extended in a first direction in the substrate; a fence formed on the gate structure to be extended in a second direction perpendicular to the first direction; and embedded contacts placed on both sides of the substrate with the fence therebetween. The fence includes a lower fence and an upper fence on the lower fence. The lower fence includes a portion in which the width of the lower fence in a third direction gradually decreases as the lower fence moves away from the substrate in the second direction, and the third direction is perpendicular to the first and second directions.

Description

A semiconductor device and its manufacturing method TECHNICAL FIELD

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to insulate the remaining portions of a buried contact that is not partially etched by using an ion implantation process.

As semiconductor devices become increasingly highly integrated, individual circuit patterns are becoming more refined in order to implement more semiconductor devices in the same area. That is, as the degree of integration of semiconductor devices increases, design rules for components of semiconductor devices are decreasing.

In highly scaled semiconductor devices, the process of forming a plurality of wiring lines and buried contacts (BCs) interposed therebetween is becoming increasingly complex and difficult. In particular, in the embossed gate buried contact (GBC) structure in which the buried contact BC is first formed and then a fence is formed, irregular or partially unetched portions may occur due to non-uniformity in the etching process. This causes a defect in which current flows between GBCs.

The technical problem to be solved by the present invention is to provide a semiconductor device and a method of manufacturing the same for insulating a remaining portion by performing an ion implantation process in a partially etched buried contact.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to some embodiments of the present invention for achieving the above technical problem includes a substrate, a gate structure extending in a first direction in the substrate, a fence extending in a second direction perpendicular to the first direction on the gate structure, and a substrate. The upper fence includes buried contacts disposed on both sides with the fence interposed therebetween, and the fence includes a lower fence and an upper fence on the lower fence, and the lower fence moves away from the substrate in the second direction in the third direction of the lower fence. And a portion in which the width of the furnace gradually decreases, and the third direction includes those perpendicular to the first direction and the second direction.

In the semiconductor device manufacturing method according to some embodiments of the present invention for achieving the above technical problem, a gate structure extending in a first direction is formed in a substrate, and on the substrate, in a second direction perpendicular to the first direction. A first trench exposing the buried contact and the gate structure by forming an extending buried contact pattern, forming a hard mask layer on the buried contact pattern, and etching the buried contact pattern and the hard mask layer in a second direction, and a gate structure Forming a second trench that does not expose to, performing an ion implantation process, and forming a fence filling the first and second trenches, wherein the fence includes a lower fence and an upper fence disposed on the lower fence, The lower fence includes one formed by performing an ion implantation process.

Specific details of other embodiments are included in the description and drawings of the invention.

1 is a schematic layout diagram for describing a semiconductor device according to some embodiments of the present invention.
2A and 2B are cross-sectional views taken along line AA′ of FIG. 1.
3A and 3B are cross-sectional views taken along line B-B' of FIG. 1.
4A and 4B are various enlarged views in which the area P of FIGS. 2A and 2B is enlarged.
5 to 18 are diagrams of intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.

Hereinafter, a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 1 to 4B.

1 is a layout diagram illustrating a semiconductor device according to some embodiments of the present invention. 2A and 2B are cross-sectional views taken along line AA′ of FIG. 1. 3A and 3B are cross-sectional views taken along line B-B' of FIG. 1.

In the drawings of the semiconductor device according to some embodiments of the present invention, a dynamic random access memory (DRAM) is illustrated as an example, but the present invention is not limited thereto.

Referring to FIGS. 1 to 4B, a semiconductor device according to some exemplary embodiments includes a substrate 110, an isolation layer 120, an insulating layer 130, a bit line BL, a spacer structure SP, and a word line. A word line (WL), a direct contact (DC), a fence 170, a buried contact (BC), a landing pad LP, an interlayer insulating layer 180, and a capacitor 190 are included.

The substrate 110 may be bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate 110 may be a silicon substrate, or other material, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenic, indium phosphide, gallium arsenide, or It may contain gallium antimonide, but is not limited thereto. In the following description, the substrate 110 will be described as being a silicon substrate.

The substrate 110 may include an active area AR. As the design rule of the semiconductor device decreases, as shown in FIG. 1, the active area AR may be formed in a shape of a diagonal bar.

For example, the active region AR is a plane extending in the first direction X and the second direction Y, and extends in an arbitrary direction other than the first direction X and the second direction Y. It can be formed in a bar shape. Also, the active region AR may have a shape of a plurality of bars extending in parallel directions. In addition, the center of one active area AR among the plurality of active areas AR may be disposed to be adjacent to the distal end of the other active area AR.

The active region AR may include impurities to form source and drain regions.

For example, the center of the active area AR may be connected to the bit line BL by a direct contact DC. Accordingly, the center of the active region AR may form one of a source and a drain region. Further, for example, both ends of the active region AR may be connected to the buried contact BC. Accordingly, the center of the active region AR may form the other one of the source and drain regions.

The device isolation layer 120 may be formed in the substrate 110. The device isolation layer 120 may have a shallow trench isolation (STI) structure having excellent device isolation characteristics. The device isolation layer 120 may define a plurality of active regions AR.

In FIGS. 2A to 4B, the device isolation layer 120 is illustrated to have an inclination of the sidewall, but this is only a feature of the process, and the technical idea of the present invention is not limited thereto.

The active region AR defined by the device isolation layer 120 may have a long island formation including a short axis and a long axis as illustrated in FIG. 1. The active region AR may have an oblique shape to have an angle of less than 90 degrees with respect to the word line WL formed in the device isolation layer 120. Also, the active region AR may have a diagonal shape to have an angle of less than 90 degrees with respect to the bit line BL formed on the device isolation layer 120. That is, the active region AR may extend in any direction having a predetermined angle with respect to the first direction X and the second direction Y.

The device isolation layer 120 may include an oxide layer, a nitride layer, or a combination thereof, but the technical idea of the present invention is not limited thereto. The device isolation layer 120 may be a single layer made of one type of insulating material, or may be a multilayer made of a combination of several types of insulating materials. In the semiconductor device according to some embodiments of the present invention, the device isolation layer 120 will be described as including a silicon oxide layer.

In FIGS. 2A to 3B, the top surface of the device isolation layer 120 and the top surface of the substrate 110 are shown to lie on the same plane, but this is for convenience of description and is not limited thereto.

The word line 160 (WL of FIG. 1) may extend long along the first direction X across the active area AR. A plurality of word lines 160 may extend parallel to each other. Also, the plurality of word lines 160 may be spaced apart from each other at equal intervals. Since the active area AR is arranged in a diagonal shape, the word line WL may have an angle less than 90 degrees with the active area AR.

In some embodiments, as shown in FIGS. 2A and 2B, the word line 160 may be buried in the substrate 110 and extend along the first direction X. The word line 160 may include a gate insulating layer 161, a gate conductive layer 162, and a gate electrode 163.

A first trench TR1 extending in the first direction X may be formed in the substrate 110. A gate structure GST may be formed in the first trench TR1. The gate structure GST may include a word line 160, a first capping pattern 164, and a second capping pattern 165.

A gate insulating layer 161, a gate conductive layer 162, and a gate electrode 163 may be sequentially buried in the first trench TR1 to be formed. The gate insulating layer 161 may extend along at least a partial profile of the first trench TR1. That is, the word line 160 may be formed in the first trench TR1.

The gate insulating layer 161 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. High-k materials are, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium. Oxide (zirconium oxide), zirconium silicon oxide (zirconium silicon oxide), tantalum oxide (tantalum oxide), titanium oxide (titanium oxide), barium strontium titanium oxide (barium strontium titanium oxide), barium titanium oxide (barium titanium oxide), strontium Titanium oxide (strontium titanium oxide), yttrium oxide (yttrium oxide), aluminum oxide (aluminum oxide), lead scandium tantalum oxide (lead scandium tantalum oxide), lead zinc niobate (lead zinc niobate), and combinations thereof Can include.

The above-described high-k material has been described centering on the oxide, but in contrast, the high-k material is a nitride (for example, hafnium nitride) or an oxynitride (for example, hafnium) of the metallic material (for example, hafnium). It may include one or more of hafnium oxynitride, but is not limited thereto.

In FIGS. 2A and 2B, the word line 160 is illustrated as a multilayer including the gate conductive layer 162 and the gate electrode 163, but the word line 160 may be a single layer.

The gate electrode 163 may be formed on the gate insulating layer 161 and the gate conductive layer 162. The gate electrode 163 may fill a part of the first trench TR1.

The gate conductive film 162 and the gate electrode 163 are, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), Tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum Carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel ( Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), Among tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof It may include at least one.

The gate electrode 163 may include a conductive metal oxide, a conductive metal oxynitride, or the like, and may include a form in which metallic materials among the aforementioned materials are oxidized.

On the gate electrode 163, a first capping pattern 164 and a second capping pattern 165 filling the first trench TR1 may be sequentially formed. The first capping pattern 164 may include, for example, polysilicon. The second capping pattern 165 is, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. It can contain one.

Although not shown, an impurity doped region may be formed on at least one side of the word line 160. The impurity-doped regions may be source and drain regions of the transistor.

The second trench TR2 may be formed in the substrate 110. The second trench TR2 may be a trench formed in the substrate 110 to contact the bit line BL with the active region AR. For example, a direct contact DC may be formed in the second trench TR2.

The insulating layer 130 may be formed on the substrate 110 and the device isolation layer 120. Specifically, as shown in FIGS. 3A and 3B, the insulating layer 130 may be formed on the substrate 110 and the device isolation layer 120 in a region of the substrate 110 in which the direct contact DC is not formed. .

The insulating layer 130 may be a single layer, but as shown, the insulating layer 130 may be a multilayer including a first insulating layer 131, a second insulating layer 132, and a third insulating layer 133.

The first insulating layer 131 may include, for example, silicon oxide. The second insulating layer 132 may include a material having an etching selectivity different from that of the first insulating layer 131. For example, the second insulating layer 132 may include silicon nitride. The third insulating layer 133 may include a material having a lower dielectric constant than the second insulating layer 132. For example, the third insulating layer 133 may include silicon oxide.

In some embodiments, the width of the third insulating layer 133 may be substantially the same as the width of the bit line BL. In the present specification, "the same" means not only the exact same thing, but also includes a minute difference that may occur due to a margin on a process.

The bit line 140 (BL of FIG. 1) may include a first bit line 140a and a second bit line 140b. The bit line 140 may be disposed on the substrate 110 and the insulating layer 130. The bit line 140 may extend long in a second direction Y different from the first direction X across the active area AR and the word line 160. For example, the second direction Y may be a direction perpendicular to the first direction X. Accordingly, the bit line 140 may obliquely cross the active area AR.

The bit line 140 may vertically cross the word line 160. A plurality of bit lines 140 may extend parallel to each other. In addition, the plurality of bit lines 140 may be spaced apart from each other at equal intervals.

The bit line 140 may be a single layer, but as shown in FIGS. 3A and 3B, the bit line 140 includes a first conductive layer 141, a second conductive layer 142, a third conductive layer 143, and It may be a multilayer including direct contact (DC).

For example, the first conductive layer 141, the second conductive layer 142, and the third conductive layer 143 may each include polysilicon, TiN, TiSiN, tungsten, tungsten silicide, or a combination thereof. . For example, the first conductive layer 141 may include polysilicon, the second conductive layer 142 may include TiSiN, and the third conductive layer 143 may include tungsten. The technical idea of the present invention is not limited thereto.

The direct contact DC may be formed in the second trench TR2. Also, the direct contact DC may contact the substrate 110. For example, the direct contact DC may contact the center of the active area AR exposed by the second trench TR2. The active region AR of the substrate 110 in contact with the direct contact DC may function as a source and drain region.

The rest of the bit line 140 in which the direct contact DC is not formed may be formed on the insulating layer 130.

The direct contact DC may include a conductive material. Accordingly, a part of the bit line 140 may be electrically connected to the active area AR.

In some embodiments, the direct contact DC may include the same material as the first conductive layer 141. For example, the direct contact DC may include polysilicon. However, the technical idea of the present invention is not limited thereto, and the direct contact DC may include a material different from the first conductive layer 141 according to a manufacturing process.

The bit line 140 may include a third capping pattern 144 thereon. The third capping pattern 144 may include a silicon nitride layer, but the technical idea of the present invention is not limited thereto.

The first bit line 140a is a part of the bit line 140 in contact with the active area AR. The second bit line 140b is a part of the bit line 140 that does not contact the active area AR. That is, as shown in FIGS. 3A and 3B, the first bit line 140a may be a part of the bit line 140 including the direct contact DC. The second bit line 140b may be a part of the bit line 140 that does not include a direct contact (DC).

In some embodiments, the first bit line 140a may not include the first conductive layer 141. For example, the first conductive layer 141 of the second bit line 140b may be replaced with a direct contact DC in the first bit line 140a. However, the technical idea of the present invention is not limited thereto, and the direct contact DC of the first bit line 140a may be formed under the first conductive layer 141.

In some embodiments, the width of the bit line 140 may be smaller than the width of the second trench TR2. Here, the width of the bit line 140 and the second trench TR2 means a width in the first direction X crossing the second direction Y, which is a direction in which the bit line 140 extends long. . For example, as illustrated in FIGS. 3A and 3B, the width of the bit line 140 may be smaller than the width of the second trench TR2.

The spacer structure 150 (SP of FIG. 1) may be disposed on sidewalls of the bit line 140 and the third capping pattern 144. The spacer structure 150 may be formed on the substrate 110 and the device isolation layer 120 in the portion of the first bit line 140a on which the direct contact DC is formed. The spacer structure 150 may extend in the second direction Y on sidewalls of the first bit line 140a and the third capping pattern 144.

However, in the rest of the second bit line 140b on which the direct contact DC is not formed, the spacer structure 150 may be formed on the first insulating layer 131 and the second insulating layer 132. The spacer structure 150 may extend in the second direction Y on sidewalls of the second bit line 140b and the third capping pattern 144.

For example, the spacer structure 150 may contact the substrate 110 and the device isolation layer 120 on a sidewall of the first bit line 140a. The spacer structure 150 may contact the insulating layer 130 on the sidewall of the second bit line 140b.

The spacer structure 150 may be a single layer, but as shown in FIGS. 3A and 3B, the spacer structure 150 may be a multilayer including the first spacer 151 and the second spacer 152. For example, the first and second spacers 151 and 152 may include one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), air, and a combination thereof. However, it is not limited thereto.

The fence 170 may be formed on the substrate 110 and the device isolation layer 120. The fence 170 may be formed to overlap the word line 160 formed in the substrate 110 and the device isolation layer 120.

The fence 170 may be formed on the gate structure GST. The fence 170 may be elongated along the first direction X. The fence 170 may cross the bit line 140 extending in the second direction (Y). The fence 170 may support the buried contact BC formed between the word lines 160. The fence 170 may include a lower fence 172 and an upper fence 171 on the lower fence 172.

The fence 170 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but the technical idea of the present invention is not limited thereto.

The buried contact BC may contact the substrate 110. For example, the buried contact BC may contact an end of the active region AR of FIG. 1. The active region AR of the substrate 110 in contact with the buried contact BC may function as a source and drain region.

In some embodiments, the buried contact BC may be disposed on both sides of the substrate 110 with the fence 170 interposed therebetween. The buried contact BC may extend in the third direction Z. The buried contact BC may cross the bit line 140 extending in the second direction Y.

The buried contact BC may include a conductive material. Accordingly, the buried contact BC may be electrically connected to the active area AR. The buried contact BC may include, for example, polysilicon, but the technical idea of the present invention is not limited thereto.

The landing pad LP may be disposed on a part of an upper surface of the bit line 140 and an upper surface of the buried contact BC. Also, the landing pad LP may contact the buried contact BC. Similar to the buried contact BC, the landing pad LP may form a plurality of isolated regions spaced apart from each other.

The landing pad LP may include a conductive material. Accordingly, the landing pad LP may be electrically connected to the buried contact BC. For example, the landing pad LP may include tungsten (W), but the technical idea of the present invention is not limited thereto.

The interlayer insulating layer 180 may be formed on a part of the upper surface of the landing pad LP and a part of the bit line 140. Also, the interlayer insulating layer 180 may define a region of the landing pad LP forming a plurality of isolated regions. That is, the interlayer insulating layer 180 may separate the plurality of landing pads LP from each other. In addition, the interlayer insulating layer 180 may be patterned to expose a portion of the upper surface of each landing pad LP.

The interlayer insulating layer 180 may include an insulating material to electrically separate the plurality of landing pads LP from each other. For example, the interlayer insulating layer 180 may include silicon oxide, but the technical idea of the present invention is not limited thereto.

The capacitor 190 may be disposed on the interlayer insulating layer 180 and the landing pad LP. The capacitor 190 may contact a portion of the upper surface of the landing pad LP exposed by the interlayer insulating layer 180. As a result, the capacitor 190 may be electrically connected to the source and drain regions connected to the buried contact BC. Accordingly, the capacitor 190 may store electric charges in a semiconductor memory device or the like.

For example, as shown in FIGS. 2A to 3B, the capacitor 190 may include a lower electrode 191, a capacitance dielectric layer 192, and an upper electrode 193. The capacitor 190 may store electric charges in the capacitance dielectric layer 192 due to a potential difference generated between the lower electrode 191 and the upper electrode 193.

The lower electrode 191 is, for example, a doped semiconductor material, a conductive metal nitride (eg, titanium nitride, tantalum nitride, tungsten nitride, etc.), a metal (eg, rucenium, iridium, titanium or tantalum, etc.) , And a conductive metal oxide (eg, iridium oxide, etc.) may be included, but is not limited thereto.

The capacitance dielectric layer 192 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide. ), zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide ), strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof It may include one, but is not limited thereto.

The upper electrode 193 may include, for example, at least one of a doped semiconductor material, a metal, a conductive metal nitride, and a metal silicide, but is not limited thereto.

As shown in FIGS. 2A and 3A, the capacitor 190 may have a pillar shape extending long in the thickness direction of the substrate 110. In addition, the capacitor 190 may have a cylindrical shape as shown in FIGS. 3A and 3B. However, the technical idea of the present invention is not limited thereto.

As semiconductor devices become highly integrated, the influence of parasitic capacitance and leakage current gradually increases. For example, as the spacing between bit lines of a dynamic random access memory (DRAM) is narrowed, a parasitic capacitance between a bit line and a bit line and between a bit line and a buried contact may increase.

However, the semiconductor device according to some embodiments may minimize parasitic capacitance by using silicon oxide. For example, the semiconductor device according to some embodiments may include a first spacer 151 in contact with the bit line 140. Since the first spacer 151 includes silicon oxide, the semiconductor device according to some embodiments may maximize a silicon oxide content between the bit line 140 and the buried contact BC.

Since silicon oxide has a lower dielectric constant than silicon nitride, the semiconductor device according to some embodiments can effectively reduce parasitic capacitance. For example, compared to a semiconductor device in which a spacer in contact with the bit line 140 is formed of silicon nitride, the semiconductor device according to some embodiments may effectively reduce parasitic capacitance.

In addition, since the semiconductor device according to some embodiments can effectively reduce the parasitic capacitance, high integration of the semiconductor device can be realized within an allowable parasitic capacitance range.

Also, the semiconductor device according to some embodiments may improve a process margin. When the spacer in contact with the bit line 140 is formed of silicon nitride, in the semiconductor device according to some embodiments, the silicon nitride contacts the depletion region of the substrate 110 to form an interface trap N _it . There is a problem to form. These interfacial traps cause an increase in leakage current.

However, in the semiconductor device according to some embodiments, since the first spacer 151 is formed of silicon oxide, even if the first spacer 151 contacts the deficient region, leakage current can be minimized. This is because silicon oxide can effectively prevent leakage current due to an interface trap (N _it ) compared to silicon nitride.

In a semiconductor device according to some embodiments, a fence 170 will be described with reference to FIGS. 4A and 4B. 4A and 4B are various enlarged views in which the area P of FIGS. 2A and 2B is enlarged. For convenience of explanation, the overlapping ones described with reference to FIGS. 1 to 3B will be briefly described or omitted.

The fence 170 may extend in the first direction X parallel to the word line 160. The fence 170 may extend in a third direction Z different from the first direction X on the gate structure GST. For example, the third direction Z may be perpendicular to the first direction X.

The fence 170 may include a lower fence 172 and an upper fence 171 on the lower fence 172. The fence 170 may have a flask formation. The lower fence 172 may include a portion in which the width W of the lower fence 172 gradually decreases as it moves away from the substrate 110 in the third direction Z. Here, the width W of the lower fence 172 means the width W in the second direction Y crossing the first direction X, which is a direction in which the word line 160 extends long.

The lower fence 172 may include a first lower fence 172_1 and a second lower fence 172_2 on the first lower fence 172_1. As the first lower fence 172_1 moves away from the substrate 110 in the third direction Z, the width W1 in the second direction Y may gradually increase. As the second lower fence 172_2 moves away from the substrate 110 in the third direction Z, the width W2 in the second direction Y may gradually decrease.

The first lower fence 172_1 may have a first height H1 in the third direction Z. The second lower fence 172_2 may have a second height H2 in the third direction Z. The first height H1 may be smaller than the second height H2. However, the technical idea of the present invention is not limited thereto, and it goes without saying that the first height H1 of the first lower fence 172_1 may be greater than the second height H2 of the second lower fence 172_2. .

The upper fence 171 may contact the lower fence 172. At the boundary between the upper fence 171 and the lower fence 172, the upper fence 171 may have a downward convex shape. However, the technical idea of the present invention is not limited thereto.

The upper fence 171 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The lower fence 172 may include, for example, at least one of silicon oxide or silicon nitride, and combinations thereof. The upper fence 171 and the lower fence 172 may be formed of different materials. However, the technical idea of the present invention is not limited thereto, and it goes without saying that the upper fence 171 and the lower fence 172 may be formed of the same material.

Hereinafter, a method of manufacturing a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 1 to 18. For convenience of description, the overlapping ones described with reference to FIGS. 1 to 4B will be briefly described or omitted.

5 to 18 are diagrams of intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.

5 to 7, a semiconductor device according to some embodiments provides a substrate 110, an isolation layer 120, a word line 160, and a bit line 140. For reference, FIG. 6 is a cross-sectional view taken along line C-C' of FIG. 5, and FIG. 7 is a cross-sectional view taken along line D-D' of FIG. 5.

The substrate 110 may include an active area AR. As shown in FIG. 5, the active area AR may be formed in a shape of an oblique bar. The active region AR may be formed by implanting impurities into the substrate 110. In this case, implantation of impurities may be performed by an ion implantation process, but the technical idea of the present invention is not limited thereto.

The device isolation layer 120 may be formed on the substrate 110. The device isolation layer 120 may define a plurality of active regions AR.

The gate structure GST may be formed to be buried and extended in the substrate 110. The gate structure GST may include a word line 160, a first capping pattern 164, and a second capping pattern 165.

The word line 160 may be formed to be buried in the substrate 110 and extended. The word line 160 may include a gate insulating layer 161, a gate conductive layer 162, and a gate electrode 163. A first capping pattern 164 and a second capping pattern 165 may be formed on the word line 160.

The bit line 140 may include a first bit line 140a and a second bit line 140b. The first bit line 140a may be formed on the direct contact DC. The second bit line 140b may be formed on the substrate 110.

The direct contact DC may be buried in the substrate 110 and may contact the substrate 110. The second bit line 140b may be formed on the insulating layer 130.

8 to 12, a buried contact pattern BCP may be formed on the substrate 110. A hard mask layer 200 may be formed on the buried contact pattern BCP. For reference, FIGS. 9 and 11 are cross-sectional views taken along E-E' of FIG. 8. 10 and 12 are cross-sectional views taken along line F-F' of FIG. 8.

The buried contact pattern BCP may be formed to cover the substrate 110 and the gate structure GST. The buried contact pattern BCP may be formed so as not to cover the upper surface of the bit line 140. That is, the top surface of the buried contact pattern BCP may be formed on the same plane as the top surface of the bit line 140.

The hard mask layer 200 may be formed on the buried contact pattern BCP. The hard mask layer 200 may be formed to cover the buried contact pattern BCP. The hard mask layer 200 may include silicon oxide, but the technical idea of the present invention is not limited thereto.

13 to 16, a buried contact BC may be formed by using the hard mask layer 200 as an etching mask. For reference, FIGS. 14 to 16 are cross-sectional views taken along G-G' of FIG. 13.

A trench TR may be formed using the hard mask layer 200 as an etch mask. The trench TR may include a third trench TR3 and a fourth trench TR4. The third trench TR3 may expose the gate structure GST. The fourth trench TR4 may not expose the gate structure GST. When etching the hard mask layer 200 and the buried contact pattern BCP, a dry etching process may be used.

The third trench TR3 and the fourth trench TR4 may define a buried contact BC.

Subsequently, an ion implantation process may be performed in the third direction Z. The lower fence 172 may be formed by performing an ion implantation process. Specifically, an ion implantation process may be performed in a portion of the buried contact pattern BCP overlapping the gate electrode 163 in the fourth trench TR4.

Oxygen or nitrogen may be injected in the third direction Z. Accordingly, the lower fence 172 may include silicon oxide or silicon nitride.

The lower fence 172 may have various shapes. The lower fence 172 may have a flask shape. Also, the lower fence 172 may include a portion in which the width of the lower fence 172 gradually decreases as it moves away from the substrate 110 in the third direction Z. Here, the width of the lower fence 172 means the width in the second direction Y, which is a direction perpendicular to the first direction X in which the word line 160 extends.

Although not shown in the drawing, the lower fence 172 includes a portion in which the width of the lower fence 172 in the second direction (Y) gradually increases as it moves away from the substrate 110 in the third direction (Z). You may.

17 and 18, a fence 170 may be formed. For reference, FIG. 18 is a cross-sectional view taken along line H-H' of FIG. 17.

The fence 170 may be formed by filling the third trench (eg, TR3 in FIG. 16) and the fourth trench (eg, TR4 in FIG. 16 ). Although not shown in the drawing, a fence pattern may be formed to fill the third trench and the fourth trench and cover the upper surface of the hard mask layer (eg, 200 of FIG. 16 ). Subsequently, the fence 170 may be formed by etching the fence pattern and the hard mask layer.

The fence 170 may include an upper fence 171 and a lower fence 172. The upper fence 171 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but the technical idea of the present invention is not limited thereto.

The lower fence 172 may include silicon oxide or silicon nitride. The upper fence 171 and the lower fence 172 may be formed of different materials. However, the present invention is not limited thereto, and it goes without saying that the upper fence 171 and the lower fence 172 may be formed of the same material.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those skilled in the art to which the present invention pertains. It will be understood that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting.

110: substrate 120: device isolation film
AR: active area BL: bit line
WL: word line SP: spacer structure
DC: direct contact BC: buried contact
LP: landing pad 170: fence

Claims (10)

Board;
A gate structure extending in a first direction in the substrate;
A fence extending in a second direction perpendicular to the first direction on the gate structure; And
On the substrate, including buried contacts disposed on both sides with the fence interposed,
The fence includes a lower fence and an upper fence on the lower fence,
The lower fence includes a portion in which a width of the lower fence in a third direction gradually decreases as it moves away from the substrate in the second direction,
The third direction is perpendicular to the first and second directions. The method of claim 1,
The lower fence includes a first lower fence and a second lower fence on the first lower fence,
The first lower fence includes a portion in which a width of the first lower fence in the third direction gradually increases as the first lower fence moves away from the substrate in the second direction. The method of claim 2,
The semiconductor device, wherein the lower fence has a first height of the first lower fence in the second direction less than a second height of the second lower fence in the second direction. The method of claim 1,
The fence is a semiconductor device having a flask shape. The method of claim 1,
And the upper fence and the lower fence are made of different materials. The method of claim 1,
At a boundary between the upper fence and the lower fence, the upper fence has a convex downward shape. Forming a gate structure extending in a first direction in the substrate,
Forming a buried contact pattern extending in a second direction perpendicular to the first direction on the substrate,
Forming a hard mask layer on the buried contact pattern,
Etching the buried contact pattern and the hard mask layer in the second direction to form a buried contact, a first trench exposing the gate structure, and a second trench unexposing the gate structure,
Performing an ion implantation process,
Forming a fence filling the first and second trenches,
The fence includes a lower fence and an upper fence on the lower fence,
And the lower fence is formed by performing the ion implantation process. The method of claim 7,
The lower fence includes a portion in which the width of the lower fence in the third direction gradually decreases as it moves away from the substrate in the second direction,
The method of manufacturing a semiconductor device in which the third direction is perpendicular to the first direction and the second direction. The method of claim 8,
The lower fence includes a first lower fence and a second lower fence disposed on the first lower fence,
The method of manufacturing a semiconductor device of the first lower fence including a portion in which a width of the first lower fence in the third direction gradually increases as the first lower fence moves away from the substrate in the second direction. The method of claim 7,
A method of manufacturing a semiconductor device, wherein at a boundary between the upper fence and the lower fence, the upper fence has a convex downward shape.

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