KR20230043014A - Semiconductor devices and Methods for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device according to the present invention includes: a first semiconductor chip having a recessed part on one surface thereof; a first adhesive pattern filled in the recess part of the first semiconductor chip; and a second semiconductor chip disposed on the first adhesive pattern. The second semiconductor chip may exhibit improved heat dissipation characteristics.

Description

Semiconductor devices and methods for manufacturing the same}

The present invention relates to a semiconductor device, and more particularly, to an adhesive pattern of a semiconductor device and a manufacturing method thereof.

A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. In general, a semiconductor package generally mounts semiconductor chips on a printed circuit board (PCB) and electrically connects them using bonding wires or bumps. With the development of the electronic industry, demands for high functionality, high speed, and miniaturization of electronic components are increasing. In response to this trend, a method of stacking several semiconductor chips on one substrate has emerged. In a manufacturing process of a semiconductor package, a wafer bonding technology that bonds two semiconductor chips having different lattice constants into a single unit has attracted attention. Wafer bonding may be performed by direct bonding or indirect bonding. Direct bonding can be performed at high temperatures. In addition, pretreatment processes may be required prior to the bonding process. Indirect bonding can be performed more simply and at a lower temperature than direct bonding. Accordingly, indirect bonding technology is attracting attention.

An object of the present invention is to provide a semiconductor device with improved heat dissipation characteristics and a manufacturing method thereof.

A semiconductor device and a manufacturing method thereof are provided. A semiconductor device according to the concept of the present invention includes a first semiconductor chip having a recessed portion on one surface thereof; a first adhesive pattern filled in the recess portion of the first semiconductor chip; and a second semiconductor chip attached to the first semiconductor chip by the first adhesive pattern, wherein the first adhesive pattern may be disposed between the first semiconductor chip and the second semiconductor chip.

According to an embodiment, the second semiconductor chip may physically contact the first adhesive pattern and the first semiconductor chip, respectively.

According to an embodiment, the first semiconductor chip may have higher thermal conductivity than the first bonding pattern.

According to an embodiment, the first semiconductor chip may further include a metal pattern, and the recess portion may be disposed within the metal pattern.

According to an embodiment, the second semiconductor chip may physically contact the metal pattern and the first adhesive pattern, respectively.

According to an embodiment, a metal layer interposed between the first adhesive pattern and the second semiconductor chip may be further included, and the metal layer may have higher thermal conductivity than the first adhesive pattern.

According to an embodiment, a second adhesive pattern provided on the one surface of the first semiconductor chip and the side surface of the second semiconductor chip may be further included, wherein the second adhesive pattern may include the same material as the first adhesive pattern. can

According to an embodiment, the recess portion may have a height of 100 nm to 10 μm.

According to an embodiment, a substrate may be further included, and the first semiconductor chip may be disposed on the substrate.

A method of manufacturing a semiconductor device according to the present invention includes preparing a first semiconductor chip having a recessed portion on one surface thereof; forming an adhesive pattern in the recess portion; and disposing a second semiconductor chip on the first semiconductor chip and the adhesive pattern.

According to an embodiment, the second semiconductor chip may contact the adhesive pattern and the first semiconductor chip, respectively, and the first semiconductor chip may have higher thermal conductivity than the adhesive pattern.

According to an embodiment, preparing the first semiconductor chip may include: forming a mask pattern on the one surface of the first semiconductor chip; and etching the first semiconductor chip exposed by the mask pattern to form the recess portion.

According to an embodiment, forming the adhesive pattern may include applying the adhesive pattern on the first semiconductor chip to cover the one surface of the first semiconductor chip.

According to the embodiment, after disposing the second semiconductor chip, applying pressure on the second semiconductor chip to physically contact the lower surface of the second semiconductor chip with the one surface of the first semiconductor chip can do.

According to an embodiment, the method may further include disposing the first semiconductor chip on a substrate.

According to the present invention, the bonding pattern may be provided in the recessed portion. During operation of the second semiconductor chip, heat may be generated in the second semiconductor chip. The first semiconductor chip may have higher thermal conductivity than the first adhesive pattern. Accordingly, heat generated in the second semiconductor chip can be quickly dissipated to the outside through the first semiconductor chip and the substrate. As the volume of the first adhesive pattern decreases, heat generated in the second semiconductor chip may be released more quickly. Accordingly, heat dissipation characteristics of the second semiconductor chip may be improved.

1A is a plan view illustrating a semiconductor device according to example embodiments.
Figure 1b is a cross-section taken along line AB of Figure 1a.
1C is a plan view illustrating a semiconductor device according to other embodiments.
FIG. 1D is a plan view illustrating a semiconductor device according to still other embodiments, and corresponds to a cross section taken along line AB of FIG. 1A .
2A and 2B are plan views illustrating first adhesive patterns according to still other embodiments.
3A is a plan view illustrating a semiconductor device according to still another exemplary embodiment of the present invention.
FIG. 3B is a cross-section taken along line A'-B' of FIG. 3A.
4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment, and correspond to cross-sections taken along line AB of FIG. 1A.
5 is a cross-sectional view illustrating a semiconductor device according to still other embodiments.
6 is a cross-sectional view illustrating a semiconductor device according to still other embodiments.

In order to fully understand the configuration and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various forms and various changes may be made. However, it is provided to complete the disclosure of the present invention through the description of the present embodiments, and to completely inform those skilled in the art of the scope of the invention to which the present invention belongs. Those of ordinary skill in the art will understand that the inventive concepts may be practiced in any suitable environment.

Terms used in this specification are for describing embodiments and are not intended to limit the present invention. In this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. As used herein, 'comprises' and/or 'comprising' means that a stated component, step, operation, and/or element is the presence of one or more other components, steps, operations, and/or elements. or do not rule out additions.

In this specification, when a film (or layer) is referred to as being on another film (or layer) or substrate, it may be formed directly on the other film (or layer) or substrate, or a third film ( or layer) may be interposed.

In various embodiments of this specification, terms such as first, second, and third are used to describe various regions, films (or layers), etc., but these regions and films should not be limited by these terms. do. These terms are only used to distinguish one region or film (or layer) from another region or film (or layer). Therefore, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. Parts designated with like reference numerals throughout the specification indicate like elements.

Terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those skilled in the art unless otherwise defined.

Hereinafter, semiconductor devices according to the concept of the present invention will be described.

1A is a plan view illustrating a semiconductor device according to example embodiments. FIG. 1B is a cross-section taken along line A-B of FIG. 1A.

Referring to FIGS. 1A and 1B , a semiconductor device 1 may include a first semiconductor chip 200 , a first bonding pattern 310 , and a second semiconductor chip 400 . The first semiconductor chip 200 may include bulk silicon, silicon on insulator (SOI), or a III-V compound semiconductor. The first semiconductor chip 200 may have a thermal conductivity of about 149 W/mk (in the case of silicon). The first semiconductor chip 200 may include a logic circuit. A recessed portion 201 may be provided on the upper surface 200a of the first semiconductor chip 200 . The recess portion 201 may have a height H of about 100 nm to about 10 μm.

A first adhesive pattern 310 may be provided in the recessed portion 201 . The first adhesive pattern 310 may be localized within the recessed portion 201 . For example, the first adhesive pattern 310 may not extend onto the upper surface 200a of the first semiconductor chip 200 . The upper surface of the first adhesive pattern 310 may be provided at the same or similar level as the upper surface 200a of the first semiconductor chip 200 . As shown in FIG. 1A , the first adhesive pattern 310 may have a quadrangular shape in a plan view. The first adhesive pattern 310 may have a thermal conductivity of about 0.5 W/mk. The first adhesive pattern 310 may include a heat-curable material or a photo-curable material. For example, the first adhesive pattern 310 may include a polymer such as polyimide or benzocyclobutene (BCB). As another example, the first adhesive pattern 310 may include spin on glass (SOG).

The second semiconductor chip 400 may be disposed on the first semiconductor chip 200 and the first adhesive pattern 310 . The lower surface of the second semiconductor chip 400 may physically contact the first adhesive pattern 310 and the first semiconductor chip 200 . When viewed from a plan view, the second semiconductor chip 400 may overlap the first bonding pattern 310 . The second semiconductor chip 400 may be attached to the first semiconductor chip 200 by the first adhesive pattern 310 . The second semiconductor chip 400 may be an optical chip, an image sensor chip, or a memory chip. When the semiconductor device 1 operates, heat may be generated in the second semiconductor chip 400 . The first semiconductor chip 200 may have higher thermal conductivity than the first adhesive pattern 310 . Since the second semiconductor chip 400 is in physical contact with the first semiconductor chip 200 , heat generated in the second semiconductor chip 400 can be quickly discharged to the outside through the first semiconductor chip 200 . As the volume of the first adhesive pattern 310 decreases, heat generated from the second semiconductor chip 400 may be released more quickly. According to example embodiments, the number, planar shape, and height of the first adhesive patterns 310 may be adjusted to improve heat dissipation characteristics of the second semiconductor chip 400 .

The second adhesive pattern 320 may be provided on the top surface 200a of the first semiconductor chip 200 and the side surface 400c of the second semiconductor chip 400 . The second adhesive pattern 320 may include the same material as the first adhesive pattern 310 . As shown in FIG. 1A , the second adhesive pattern 320 may not overlap the second semiconductor chip 400 . The second adhesive pattern 320 may be spaced laterally from the first adhesive pattern 310 .

1C is a plan view illustrating a semiconductor device according to other embodiments.

Referring to FIG. 1C , the semiconductor device 2 may include a first semiconductor chip 200 , a first bonding pattern 310 , a second bonding pattern 320 , and a second semiconductor chip 400 . The first semiconductor chip 200 may be the same as that described with reference to FIGS. 1A and 1B . The first semiconductor chip 200 may have a recessed portion 201 on its top surface 200a. The first adhesive pattern 310 may extend onto the top surface 200a of the first semiconductor chip 200 within the recess portion 201 . The first adhesive pattern 310 is connected to the second adhesive pattern 320 and may include the same material as the second adhesive pattern 320 . Here, the first adhesive pattern 310 is a portion on the lower surface 400b of the second semiconductor chip 400, and the second adhesive pattern 320 is a portion on the side surface 400c of the second semiconductor chip 400. can mean

A second semiconductor chip 400 may be provided on the first semiconductor chip 200 . The second semiconductor chip 400 may physically contact the first adhesive pattern 310 . The second semiconductor chip ( Heat generated in 400 may be quickly transferred to the first semiconductor chip 200 . A thickness D of the adhesive pattern on the top surface 200a of the first semiconductor chip 200 may be reduced by providing the recessed portion 201 . Accordingly, heat dissipation characteristics of the second semiconductor chip 400 may be improved.

FIG. 1D is a plan view illustrating a semiconductor device according to still other embodiments, and corresponds to a cross section taken along line A-B of FIG. 1A. Hereinafter, contents overlapping with those described above will be omitted.

Referring to FIG. 1D together with FIG. 1A , the semiconductor device 3 includes a first semiconductor chip 200, a first bonding pattern 310, a second semiconductor chip 400, and a second bonding pattern 320. can do. A second semiconductor chip 400 may be provided on the first semiconductor chip 200 . A recessed portion 401 may be provided on the lower surface 400b of the second semiconductor chip 400 . The first bonding pattern 310 may be provided in the recess portion 401 between the first semiconductor chip 200 and the second semiconductor chip 400 . The second semiconductor chip 400 may be attached to the first semiconductor chip 200 by the first adhesive pattern 310 . The first adhesive pattern 310 may be localized in the recess portion 401 to expose the lower surface 400b of the second semiconductor chip 400 . The second semiconductor chip 400 may physically contact the upper surface 200a of the first semiconductor chip 200 .

2A and 2B are plan views illustrating first adhesive patterns according to still other embodiments. Hereinafter, contents overlapping with those described above will be omitted.

Referring to FIGS. 2A and 2B together with FIG. 1B , the semiconductor devices 4 and 5 include a first semiconductor chip 200, a first bonding pattern 310, a second semiconductor chip 400, and a second bonding Pattern 320 may be included. The first adhesive pattern 310 may overlap the second semiconductor chip 400 . The first adhesive pattern 310 may have a circular shape in a plan view, as shown in FIG. 2A . According to another embodiment, the first adhesive pattern 310 may extend in one direction in a plan view as shown in FIG. 2B. However, the planar shape of the first adhesive pattern 310 is not limited thereto and may vary.

3A is a plan view illustrating a semiconductor device according to still another exemplary embodiment of the present invention. FIG. 3B is a cross-section taken along line A-B of FIG. 3B. Hereinafter, contents overlapping with those described above will be omitted.

Referring to FIGS. 3A and 3B , the semiconductor device 6 may include a first semiconductor chip 200 , a first bonding pattern 310 , and a second semiconductor chip 400 . The first semiconductor chip 200 may have a recessed portion 201 on its top surface 200a. A first adhesive pattern 310 may be provided in the recessed portion 201 . The first adhesive pattern 310 may be provided on an edge area of the first semiconductor chip 200 . The first adhesive pattern 310 may expose the top surface 200a of the core region of the first semiconductor chip 200 . A second semiconductor chip 400 may be provided on the first semiconductor chip 200 . The second semiconductor chip 400 may physically contact the first adhesive pattern 310 and the first semiconductor chip 200 respectively. As shown in FIG. 3A , the second semiconductor chip 400 partially overlaps the first adhesive pattern 310 when viewed from a plan view, and may not overlap other portions. Unlike FIGS. 1A and 1B , the second adhesive pattern 320 may not be provided.

4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment, and correspond to cross-sections taken along line A-B of FIG. 1A.

Referring to FIG. 4A together with FIG. 1A , a mask pattern 500 may be provided on the first semiconductor chip 200 . The mask pattern 500 may expose the top surface 200a of the first semiconductor chip 200 . The first semiconductor chip 200 may be etched using the mask pattern 500 to form a recess 201 on the top surface 200a of the first semiconductor chip 200 . The first semiconductor chip 200 may be wet-etched or dry-etched. The mask pattern 500 may be removed.

Referring to FIG. 4B and FIG. 1A , the adhesive pattern 300 may be formed on the top surface 200a of the first semiconductor chip 200 to cover the top surface 200a of the first semiconductor chip 200 . The adhesive pattern 300 may be filled in the recessed portion 201 .

Referring to FIGS. 4C and 4D in turn, the second semiconductor chip 400 may be disposed on the adhesive pattern 300 . The adhesive pattern 300 may have fluidity. Pressure may be applied to the second semiconductor chip 400 until the second semiconductor chip 400 contacts the first semiconductor chip 200 . The adhesive pattern 300 between the upper surface 200a of the first semiconductor chip 200 and the lower surface 400b of the second semiconductor chip 400 may move onto the side surface 400c of the second semiconductor chip 400. . By the pressure, the second adhesive pattern 320 may be separated from the first adhesive pattern 310 as shown in FIG. 4D . Accordingly, the first adhesive pattern 310 localized within the recess portion 201 may be formed. The first adhesive pattern 310 may not cover the upper surface 200a of the first semiconductor chip 200 . The second adhesive pattern 320 may be provided on the top surface 200a of the first semiconductor chip 200 and the side surface 400c of the second semiconductor chip 400 . The first adhesive pattern 310 and the second adhesive pattern 320 may be cured by light or heat. Manufacturing of the semiconductor device 1 can be completed by the example described so far.

5 is a cross-sectional view of a semiconductor device according to still other embodiments, corresponding to a cross-section taken along line A-B of FIG. 1A.

Hereinafter, contents overlapping with those described above will be omitted.

Referring to FIG. 5 together with FIG. 1A , the semiconductor device 7 includes a connection terminal 105, a first semiconductor chip 200, a first adhesive pattern 310, a second semiconductor chip 400, and a second adhesive. Pattern 320 may be included. The first semiconductor chip 200 may include a base layer 210 and a metal pattern 220 on the base layer 210 . The base layer 210 may include bulk silicon, silicon on insulator (SOI), or a III-V compound semiconductor. The base layer 210 may have a thermal conductivity of approximately 149 W/mk (in the case of silicon). The metal pattern 220 may be adjacent to the top surface 200a of the first semiconductor chip 200 . The metal pattern 220 may have a thermal conductivity of 400 W/mk or more. The metal pattern 220 may include gold (Au), silver (Ag), aluminum (Al), titanium (Ti), or an alloy thereof. The recess portion 201 may be provided in the metal pattern 220 and may expose the top surface 210a of the base layer 210 . The first adhesive pattern 310 is provided in the recess portion 201 and may expose an upper surface of the metal pattern 220 . Here, the upper surface of the metal pattern 220 may mean the upper surface 200a of the first semiconductor chip 200 . The first adhesive pattern 310 may include any one of the materials described with reference to FIGS. 1A and 1B. As another example, the first adhesive pattern 310 may have a shape as described in the examples of FIG. 2A , FIG. 2B , or FIGS. 3A and 3B .

A second semiconductor chip 400 may be provided on the first semiconductor chip 200 and the first adhesive pattern 310 . The second semiconductor chip 400 may physically contact the metal pattern 220 and the first adhesive pattern 310 respectively. As the first semiconductor chip 200 has a higher thermal conductivity than the first adhesive pattern 310 , heat from the second semiconductor chip 400 can be transferred to the first semiconductor chip 200 more quickly. According to embodiments, the metal pattern 220 may have higher thermal conductivity than the first adhesive pattern 310 and the base layer 210 . Accordingly, heat dissipation characteristics of the second semiconductor chip 400 may be further improved by the metal pattern 220 .

FIG. 6 is a cross-sectional view of a semiconductor device according to still other embodiments, and corresponds to a cross-section taken along line A-B of FIG. 1A.

Hereinafter, contents overlapping with those described above will be omitted.

Referring to FIG. 6 together with FIG. 1A , the semiconductor device 8 includes a substrate 100, a connection terminal 105, a first semiconductor chip 200, a first adhesive pattern 310, and a second semiconductor chip 400. , and may include the second adhesive pattern 320 . The substrate 100 , the first semiconductor chip 200 , the first bonding pattern 310 , and the second semiconductor chip 400 may be the same as those described in FIG. 5 . For example, the first semiconductor chip 200 may include a base layer 210 and a metal pattern 220 . The recessed portion 201 may be provided in the metal pattern 220 . A first adhesive pattern 310 may be provided in the recessed portion 201 . The first adhesive pattern 310 may expose the upper surface 200a of the first semiconductor chip 200 . The first adhesive pattern 310 may have a thermal conductivity of about 0.5 W/mk.

A metal layer 410 may be interposed between the first semiconductor chip 200 and the second semiconductor chip 400 . The metal layer 410 may physically contact the metal pattern 220 and the first adhesive pattern 310 respectively. For example, the metal layer 410 may have a thermal conductivity of 400 W/mK or more. The metal layer 410 may include gold (Au), silver (Ag), aluminum (Al), titanium (Ti), or an alloy thereof.

A second semiconductor chip 400 may be disposed on the metal layer 410 . The metal layer 410 may have higher thermal conductivity than the first adhesive pattern 310 . As the contact area between the second semiconductor chip 400 and the metal layer 410 increases, heat generated from the second semiconductor chip 400 can be quickly released. The lower surface 400b of the second semiconductor chip 400 may physically contact the metal layer 410 but may not contact the first adhesive pattern 310 . During operation of the second semiconductor chip 400 , heat generated in the second semiconductor chip 400 may be quickly transferred to the metal layer 410 . Heat transferred to the metal layer 410 may be emitted to the outside through the metal pattern 220 and the base layer 210 . According to example embodiments, heat dissipation characteristics of the second semiconductor chip 400 may be further improved.

According to another embodiment, the metal pattern 220 may be omitted and the recessed portion 201 may be formed in the base layer 210 . In this case, the metal layer 410 may contact the base layer 210 and the first adhesive pattern 310 of the first semiconductor chip 200 , respectively.

Claims (9)

a first semiconductor chip having a recessed portion on one surface thereof;
a first adhesive pattern filled in the recess portion of the first semiconductor chip; and
A second semiconductor chip attached to the first semiconductor chip by the first bonding pattern;
The first bonding pattern is disposed between the first semiconductor chip and the second semiconductor chip. According to claim 1,
The second semiconductor chip physically contacts the first adhesive pattern and the first semiconductor chip, respectively. According to claim 1,
The first semiconductor chip has a higher thermal conductivity than the first bonding pattern. According to claim 1,
The first semiconductor chip further includes a metal pattern,
The semiconductor device of claim 1 , wherein the recess portion is disposed within the metal pattern. According to claim 4,
The second semiconductor chip is a semiconductor device that physically contacts the metal pattern and the first adhesive pattern, respectively. According to claim 1,
A metal layer interposed between the first adhesive pattern and the second semiconductor chip, wherein the metal layer comprises the first contact
A semiconductor device having a higher thermal conductivity than the complex pattern. According to claim 1,
Further comprising a second adhesive pattern disposed on the one surface of the first semiconductor chip and the side surface of the second semiconductor chip,
The second adhesive pattern includes the same material as the first adhesive pattern semiconductor device. According to claim 1,
The semiconductor device having a height of 100 nm to 10 μm of the recess portion. According to claim 1,
The semiconductor device further comprising a substrate, wherein the first semiconductor chip is disposed on the substrate.

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