CN210167347U - Integrated circuit packaging structure and semiconductor packaging device - Google Patents

Abstract

The utility model provides an integrated circuit packaging structure, which comprises a crystal grain, a sealing ring, a residual test structure and a protective layer, wherein the crystal grain is provided with a circuit area, a boundary area, a side wall and a cutting boundary, and the cutting boundary and the side wall are positioned in the boundary area; the sealing ring is arranged on the crystal grain and positioned between the circuit area and the boundary area; the residual test structure is arranged on the crystal grain and is positioned between the cutting boundary and the side wall; the protective layer extends from the circuit area to be arranged on the boundary area and covers the sealing ring and the residual test structure, and the protective layer covers the boundary area between the sealing ring and the residual test structure. The utility model discloses another provide a semiconductor package device who contains above-mentioned integrated circuit's packaging structure.

Description

Integrated circuit packaging structure and semiconductor packaging device

Technical Field

The present invention relates to an integrated circuit package, and more particularly to an integrated circuit package and a semiconductor package with improved process yield.

Background

In recent years, with the increasing integration of the arrangement of the dies on the wafer, the arrangement of the test structure is closer to the dies, so that the cut dies have residual test structures, which may cause incomplete glue filling in the subsequent packaging process, resulting in poor yield of the subsequent metallization process.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an integrated circuit's packaging structure can effectively restrain the influence that residual test structure caused to promote the yield of follow-up encapsulation metallization technology.

In one embodiment, the present invention provides an integrated circuit package structure, which comprises a die, a sealing ring, a residual test structure and a protection layer, wherein the die has a circuit region, a boundary region, a sidewall and a cutting boundary, and the cutting boundary and the sidewall are located in the boundary region; the sealing ring is arranged on the crystal grain and positioned between the circuit area and the boundary area; the residual test structure is arranged on the crystal grain and is positioned between the cutting boundary and the side wall; the protective layer extends from the circuit area to the boundary area and covers the sealing ring and the residual test structure, and the protective layer covers the boundary area between the sealing ring and the residual test structure.

In one embodiment, the residual test structure includes a metal layer.

In one embodiment, the passivation layer is an organic insulating material layer.

In an embodiment, the package structure of the integrated circuit of the present invention further comprises a metallurgy layer disposed on the protection layer and electrically connected to the die.

In another embodiment, the present invention provides a semiconductor package device, which comprises the above-mentioned package structure of the integrated circuit, a passive device, a package body and a metal layer, wherein the passive device and the package structure of the integrated circuit are separately and horizontally disposed; the packaging body wraps the packaging structure and the passive element of the integrated circuit, the packaging body is provided with a top surface, the passive element and the packaging structure of the integrated circuit are provided with exposed parts on the top surface, and the exposed parts and the top surface are coplanar; the metal layer is configured on the top surface and electrically connected with the passive element and the packaging structure of the integrated circuit.

In one embodiment, the residual test structure includes a metal layer.

In one embodiment, the protection layer is an organic insulating material layer.

In an embodiment, the package structure of the integrated circuit further includes a metallurgy layer disposed on the protection layer and electrically connecting the die and the metal layer.

In one embodiment, the metal layer is a patterned metal layer conformally formed on the top surface.

Compared with the prior art, according to the utility model discloses an integrated circuit's packaging structure and contain this integrated circuit's packaging structure's semiconductor packaging device is through disposing the protective layer on test structure, can press test structure in cutting procedure, prevents to remain test structure warpage production deckle edge, just can not hinder packaging material flow and reduce the technology yield in follow-up packaging technology.

The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.

Drawings

Fig. 1 is a schematic perspective view of a package structure of an integrated circuit according to an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view of an integrated circuit package structure along a tangent line AA according to an embodiment of the present invention.

Fig. 3A to fig. 3C are schematic cross-sectional views illustrating steps of a method for fabricating a package structure of an integrated circuit according to an embodiment of the present invention.

Fig. 3D is a partial schematic plan view of fig. 3B.

Fig. 4A and 4B are a schematic cross-sectional view and a schematic partial plan view illustrating a method for manufacturing a package structure of an integrated circuit according to another embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view of a semiconductor package device according to an embodiment of the present invention.

Fig. 6A to 6D are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor package device according to the present invention.

Description of the main element symbols:

1 semiconductor package device

10 package structure of integrated circuit

12 exposed part

20 passive component

22 exposed part

30 Package

32 top surface

40 metal layer

50 insulating layer

60 carrier plate

100 crystal grains

102 circuit area

104 boundary region

106 side wall

108 cutting boundary

110 sealing ring

120 residual test structure

125 test structure

130 protective layer

140 contact part

150 metallurgical layer

155 test metal part

160 insulating layer

200 cutting tool

CL cutting way

Width of W1

Width of W2

Detailed Description

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In order to simplify the drawings, conventional structures and elements are shown in simplified schematic form in the drawings. Additionally, the same or similar numbered elements/components used in the drawings and the embodiments are used to represent the same or similar parts. In the embodiments described below, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements or certain materials may be present, for example: a gel or solder.

According to a preferred embodiment of the present invention, an integrated circuit package structure is provided. Referring to fig. 1, fig. 1 is a schematic perspective view of a package structure of an integrated circuit according to an embodiment of the present invention, as shown in fig. 1, in an embodiment, a package structure 10 of an integrated circuit includes a die 100, a seal ring 110, a residual test structure 120, and a protection layer 130. The die 100 has a circuit region 102, a boundary region 104, sidewalls 106 and a dicing boundary 108, and the dicing boundary 108 and the sidewalls 106 are located at the boundary region 104. The seal ring 110 is disposed on the die 100 and between the circuit region 102 and the boundary region 104. The residual test structure 120 is disposed on the die 100 between the dicing border 108 and the sidewall 106. The protection layer 130 extends from the circuit region 102 to the boundary region 104 and covers the seal ring 110 and the residual test structure 120, and the protection layer 130 covers the boundary region 104 between the seal ring 110 and the residual test structure 120.

Specifically, the die 100 has integrated circuits, and the integrated circuits in the die 100 are preferably disposed in, for example, the circuit region 102. In one embodiment, the integrated circuit in the die 100 may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Driver (Driver), or an integrated circuit with other functions. The seal ring 104 is disposed on the die 100 for protecting the circuit in the circuit region 102. As shown in fig. 1, the sealing ring 104 preferably completely surrounds the circuit region 102, and may be used as a crack stop, moisture prevention, or electrostatic protection component, but not limited thereto. In other embodiments, the seal ring 104 surrounds the periphery of the circuit region 102 and may have a local opening according to practical applications.

The dies 100 are cut from the wafer, and scribe lines are designed in the wafer between the dies 100. Since the dicing blade usually has a certain thickness (width), for example, 30 micrometers (μm), the designed scribe line has a predetermined width, for example, about 70 to 90 micrometers (μm), which is larger than the thickness (width) of the dicing blade, so as to prevent the circuit region 102 of the die 100 from being damaged due to the deviation generated when the dicing blade performs the dicing operation. Therefore, when the dicing blade cuts and separates the die 100 from the wafer, the dicing boundary 108 is formed at the edge of the die 100, such that the boundary region 104 is formed between the dicing boundary 108 and the seal ring 110, and the sidewall 106 of the die 100 is formed extending downward along the dicing direction (or the dicing boundary 108). In other words, the dicing boundaries 108 and the sidewalls 106 are the side edges and sidewalls of the boundary region 104 of the die 100.

Since the width of the scribe line is larger than the thickness (width) of the dicing tool, the test structures disposed on the scribe line will remain on the boundary region 104 of the die 100 after the die 100 is diced and separated from the wafer, thereby forming the residual test structure 120. Since the test structure is used for electrical testing of the wafer, the residual test structure 120 is a conductive layer, such as a metal layer.

The passivation layer 130 is disposed on the die 100 and extends from the circuit region 102 to the boundary region 104. The protection layer 130 covers the seal ring 110 and the residual test structure 120, and covers the boundary region 104 between the seal ring 110 and the residual test structure 120, such that the die 100, the residual test structure 120, and the protection layer 130 are substantially aligned along the dicing boundary 108. That is, the sidewalls 106, the residual test structure 120 and the passivation layer 130 are substantially coplanar in the plane in which the sidewalls 106 extend. The passivation layer 130 is preferably an organic insulating material layer to isolate the residual test structure 120 from metal layers in subsequent packaging processes, thereby preventing short circuits. In one embodiment, the protection layer 130 is preferably an organic insulating material layer that can be used as a photoresist layer, such as Polyimide (PI) or any suitable photoresist material, so that the protection layer 130 can not only isolate the residual test structure 120, but also be used as a photoresist layer for subsequent metallurgy layers.

Fig. 2 is a schematic cross-sectional view of an integrated circuit package structure along a tangent line AA according to an embodiment of the present invention. As shown in fig. 2, in one embodiment, the die 100 has a contact portion 140 in the circuit region 102, i.e., the contact portion 140 is disposed inside the seal ring 110 relative to the boundary region 104. The contact portion 140 is used as an electrical connection portion for an integrated circuit in the die 100 in a subsequent package. The passivation layer 130 is disposed on the die 100, extends from the circuit region 102 to the boundary region 104 to cover the seal ring 110 and the residual test structure 120, and has an opening to expose the contact portion 140. In this embodiment, the package structure of the integrated circuit further includes a metallurgy layer 150, the metallurgy layer 150 is disposed on the protection layer 130 and electrically connected to the die 100 through the opening of the protection layer 130, for example, electrically connected to the contact 140 of the die 100. Specifically, the metallurgical layer 150 may be an Under Bump Metallurgy (UBM) layer, which may be a single or multi-layer structure including chromium, titanium, tungsten, nickel, palladium, molybdenum, copper, gold, or a combination thereof.

The passivation layer 130 may be disposed on the wafer before or after the wafer test, so as to not hinder the test of the test structure, and prevent the residual test structure from warping and generating burrs after the wafer is cut. Referring to fig. 3A to 3D, fig. 3A to 3C are schematic cross-sectional views illustrating steps of a method for fabricating a package structure of an integrated circuit according to an embodiment of the present invention, and fig. 3D is a schematic partial plan view of fig. 3B. It should be noted that the embodiment is only illustrated with two adjacent dies 100, but the wafer may actually include a plurality of dies arranged in an array. As shown in fig. 3A, a scribe line CL is formed between two adjacent dies 100, and the test structure 125 is disposed in the scribe line CL. Each die 100 has a contact portion 140 disposed in the circuit region 102, a seal ring 110 disposed between the circuit region 102 and the boundary region 104, and an insulating layer 160 filled between the contact portion 140, the seal ring 110 and the test structure 125. The insulating layer 160 is an organic insulating material layer, such as, but not limited to, a polyimide layer, used for patterning the contacts 140, the seal ring 110 and the test structure 125. The insulating layer 160 can be other non-organic material layers with suitable dielectric constant, such as oxide, nitride, oxynitride, etc., depending on the application. At this stage, the contact portion 140, the seal ring 110 and the test structure 125 are exposed on the surface of the insulating layer 160, for example, the top surfaces of the contact portion 140, the seal ring 110 and the test structure 125 are preferably substantially coplanar with the top surface of the insulating layer 160. In addition, the details of the structure and the position relationship of the contact portion 140 and the seal ring 110 can refer to the related descriptions of the above embodiments, and are not repeated herein.

In this embodiment, after the wafer of fig. 3A passes the test structure 125 for testing, as shown in fig. 3B and 3D, the protection layer 130 and the metallurgy layer 150 are formed. As described above, in one embodiment, the protection layer 130 may be an organic insulating material layer (e.g., polyimide) as a photoresist layer, which is formed on the wafer surface in a coating manner, i.e., extending from each die 100 to the scribe line CL to cover the surfaces of the contact 140, the seal ring 110, the insulating layer 160 and the test structure 125. Next, the passivation layer 130 is partially opened by a patterning technique (e.g., exposure, development) to expose only the contact portion 140, and the seal ring 110 and the insulating layer 160 of each die 100 are remained covered and extended to cover the test structure 125. After patterning the passivation layer 130, one or more metal layers are formed on the wafer to cover the passivation layer 130 and fill the openings to electrically connect the contacts 140. Next, one or more metal layers are patterned by a patterning technique (e.g., photolithography, etching) to form the metallurgy layer 150.

As shown in fig. 3C and 3D, a die 100 is cut from a wafer to form the package structure 10 of the integrated circuit of the present invention, such as shown in the embodiments of fig. 1 and 2. That is, since the dicing blade 200 generally has a certain thickness (width) W1, such as 30 micrometers (μm), the width W2 of the scribe line CL is greater than the width W1 of the dicing blade 200, such as about 70 to 90 micrometers (μm), when the dicing blade 200 cuts and separates the dies 100 from the wafer, the test structure 125 is simultaneously cut, and the dicing boundaries 108 are formed at the edges of each die 100, the boundary region 104 is the region between the dicing boundary 108 and the boundary of the circuit region 102 (or the seal ring 110), and the side walls 106 of the dies 100 are formed extending downward along the dicing direction (or the dicing boundary 108). The seal ring 110 is disposed on the die 100 and between the circuit region 102 and the boundary region 104. The residual test structure 120 is disposed on the die 100 between the dicing border 108 and the sidewall 106. The protection layer 130 extends from the circuit region 102 to the boundary region 104 and covers the seal ring 110 and the residual test structure 120. The protection layer 130 covers the boundary region 104 between the seal ring 110 and the residual test structure 120.

In another embodiment, referring to fig. 4A and 4B, fig. 4A and 4B are a schematic cross-sectional view and a schematic partial plan view illustrating a method for manufacturing a package structure of an integrated circuit according to another embodiment of the present invention. In this embodiment, as shown in fig. 4A and 4B, before the wafer test is performed through the test structure 125, the protection layer 130 and the metallurgy layer 150 are formed on the wafer of fig. 3A. As described above, in one embodiment, the protection layer 130 may be an organic insulating material layer (e.g., polyimide) as a photoresist layer, which is formed on the wafer surface in a coating manner, i.e., extending from each die 100 to the scribe line CL to cover the surfaces of the contact 140, the seal ring 110, the insulating layer 160 and the test structure 125. Then, by a patterning technique (e.g., exposure, development), the protection layer 130 is partially opened to expose the contact portion 140 and partially expose the test structure 125, i.e., the protection layer 130 remains covering the seal ring 110 and the insulating layer 160 of each die 100 and extends to cover a portion of the test structure 125. After patterning the passivation layer 130, one or more metal layers are formed on the wafer to cover the passivation layer 130 and fill the openings to electrically connect the contacts 140 and the test structures 125. Next, one or more metal layers are patterned by a patterning technique (e.g., photolithography, etching) to form the metallurgy layer 150 and the test metal portion 155. The test metal portion 155 is preferably located completely within the width of the dicing blade 200, i.e., the protection layer 130 preferably completely covers the portion of the test structure 125 in the boundary region 104, and even extends to the width of the dicing blade 200, so as to ensure complete coverage of the residual test structure 120 after dicing.

In this embodiment, the process integration of the metallurgy layer 150 and the test metal portion 155 can be formed simultaneously to save the manufacturing cost, but not limited thereto. In other embodiments, the metallurgy layer 150 and the test metal portion 155 may be formed separately or only the metallurgy layer 150, depending on the application.

In this embodiment, a wafer test can be performed through the test metal portion 155 formed in fig. 4A. After wafer testing, the die 100 may be cut from the wafer as shown in fig. 3C and 4B to form the integrated circuit package structure 10 of the present invention, for example, as shown in the embodiments of fig. 1 and 2. That is, when the dicing tool 200 cuts and separates the die 100 from the wafer, the test metal portion 155 is cut and the test structure 125 is cut, so that the residual test structure 120 is formed on the die 100 between the cutting boundary 108 and the sidewall 106. The protection layer 130 extends from the circuit region 102 to the boundary region 104 and covers the seal ring 110 and the residual test structure 120. The protection layer 130 covers the boundary region 104 between the seal ring 110 and the residual test structure 120.

Because the metal is ductile, the residual test structure 120 is curled to form burrs when the die 100 is cut, which may hinder the flow of the package material and prevent the package material from completely covering the ic package structure 10 in the subsequent packaging step, thereby affecting the yield of the subsequent packaging metallization process. The utility model discloses a configuration protective layer 130 on test structure 125 can live test structure in cutting procedure, prevents to remain test structure 120 warpage production deckle edge, just can not obstruct the encapsulating material flow and reduce the technology yield in follow-up packaging technology.

In another embodiment, the present invention further provides a semiconductor package device including the package structure 10 of the integrated circuit. Referring to fig. 5, fig. 5 is a schematic cross-sectional view of a semiconductor package device according to an embodiment of the present invention. As shown in fig. 5, the semiconductor package device 1 of the present invention includes a package structure 10 of an integrated circuit, a passive element 20, a package 30 and a metal layer 40. The passive component 20 is disposed separately from the package structure 10 of the integrated circuit. The package 30 encapsulates the package structure 10 of the integrated circuit and the passive component 20, and the package 30 has a top surface 32. The passive component 20 and the package structure 10 of the integrated circuit have exposed portions 22 and 12 on the top surface 300, respectively, and the exposed portions 22 and 12 are substantially coplanar with the top surface 32. The metal layer 40 is disposed on the top surface 32 and electrically connects the passive component 20 and the package structure 10 of the integrated circuit.

Specifically, the package structure 10 of the integrated circuit includes a die 100, a seal ring 110, a residual test structure 120 and a protection layer 130, and the details of the structure and the manufacturing method thereof can refer to the related descriptions of fig. 1 to fig. 4B, which are not repeated herein. The passive element 20 is disposed separately from the package structure 10 of the integrated circuit, and two passive elements 20 are illustrated in this embodiment, but not limited thereto. Depending on the application, one or more passive elements 20 may be disposed in the semiconductor package 1, and the passive elements 20 may be, for example, resistors, capacitors, inductors, or combinations thereof. The package 30 encapsulates the package structure 10 and the passive component 20 of the integrated circuit, such that the package structure 10 and the passive component 20 of the integrated circuit are flush with one side of the package 30 to be exposed at the side. For example, the package 30 is a package structure 10 and a passive component 20 of an integrated circuit, and the package structure 10 and the passive component 20 are molded by a molding material, and preferably only one side of the passive component 20 and the package structure 10 of the integrated circuit is exposed from the package 30 to form the exposed portions 22 and 12. The metal layer 40 is a patterned metal layer conformally formed on the top surface 32 to electrically connect the exposed portion 22 of the passive component 20 and the exposed portion 12 of the package structure 10 of the integrated circuit, such that the passive component 20 and the package structure 10 of the integrated circuit are electrically connected to each other. In addition, before the metal layer 40 is formed, the insulating layer 50 is patterned by a patterning technique (e.g., exposure, development), and the patterned metal layer 40 is formed. In one embodiment, the insulating layer 50 may be an organic insulating material layer as a photoresist layer, but not limited thereto.

Next, a method for manufacturing the semiconductor package 1 according to the present invention will be described with reference to fig. 6A to 6D. As shown in fig. 6A, the package structure 10 of the integrated circuit and the one or more passive components 20 of the above embodiment are disposed on a carrier 60 at intervals. In one embodiment, the carrier 60 is preferably a sheet material with adhesive property (such as an adhesive tape or a film with adhesive property), so that the package structure 10 of the integrated circuit and the passive component 20 can be fixed by adhesion when disposed on the carrier 60. Thus, the package structure 10 of the integrated circuit and the surfaces (e.g., 22, 12) of the passive components 20 and the carrier 60 are substantially located at the same level by the positioning of the carrier 60. For example, the carrier 60 is flexible and provides a coplanar surface for the package structure 10 of the integrated circuit and the bonding surfaces of the passive device 20 and the carrier 60, and the package structure 10 of the integrated circuit and the bonding surfaces of the passive device 20 and the carrier 60 are surfaces having electrical connection portions. For example, the package structure 10 of the integrated circuit preferably has an exposed surface of the metallurgy layer 150 as a bonding surface. Therefore, in the subsequent process of forming the package 30, the electrical connection portions of the package structure 10 and the passive component 20 of the integrated circuit can be protected by the carrier 60, so as to ensure the subsequent electrical connection.

As shown in fig. 6B, the carrier 60 with the package structure 10 of the integrated circuit and the passive component 20 is disposed in a mold, and an encapsulant is injected, so that the encapsulant is cured to form the package 30. The package 30 covers all portions of the package structure 10 and the passive component 20 of the integrated circuit not connected to the carrier 60 to prevent moisture or other substances from corroding or damaging the package structure 10 and the passive component 20 of the integrated circuit. The material of the package body 30 may include Epoxy Molding Compound (EMC), but is not limited thereto. The material of the package body 30 may be any convenient packaging insulating material that is injected into a mold in a fluid state and then cured (e.g., thermally or photo-cured) to form.

As shown in fig. 6C, the carrier 60 is removed to expose the top surface 32 of the package body 30, the exposed portion 12 of the package structure 10 of the integrated circuit on the top surface 32, and the exposed portion 22 of the passive component 20 on the top surface 32. In other words, the surfaces of the integrated circuit package structure 10 and the passive components 20, which are connected to the carrier 60, are exposed as the exposed portions 22 and 12 after the carrier 60 is removed.

As shown in fig. 6D, an insulating layer 50 is formed on the top surface 32 of the package body 30. The insulating layer 50 is a patterned insulating layer having openings to expose the exposed portion 12 of the package structure 10 of the integrated circuit and the exposed portion 22 of the passive element 20 through the openings. The photoresist layer may be formed on the top surface 32 of the package 30 by a coating method, and then patterned by a patterning technique (e.g., exposure, development) to form the insulating layer 50, thereby at least partially exposing the exposed portion 12 of the package structure 10 of the integrated circuit and the exposed portion 22 of the passive device 20. The insulating layer 50 is patterned to expose electrical connections (e.g., the metallurgy layer 150) of the exposed portion 12 of the package structure 10 and electrical connections of the passive component 20 at the exposed portion 22 of the integrated circuit. After the patterned insulating layer 50 is formed, one or more metal layers may be conformally formed on the patterned insulating layer 50 by, for example, deposition, sputtering, electroplating, etc., and the openings of the patterned insulating layer 50 are filled to electrically connect the electrical connection portions of the package structure 10 of the integrated circuit on the exposed portion 12 and the electrical connection portions of the passive component 20 on the exposed portion 22. Next, a patterning technique (e.g., photolithography, etching) is performed to pattern one or more metal layers to form a metal layer 40, thereby forming the semiconductor package device 1 shown in fig. 5.

It should be noted that, in one embodiment, a plurality of integrated circuit package structures 10 and corresponding passive components 20 may be respectively disposed on different regions of the carrier 60 to form a package array, and a plurality of semiconductor package devices 1 may be formed in batch by disposing the package array in a mold and performing a process of filling and curing an encapsulant. When a plurality of semiconductor packages 1 are formed in a batch, the method for forming the semiconductor packages 1 further includes a cutting step to singulate a plurality of semiconductor package structures connected to each other through the carrier 60 or the package 30, thereby forming the semiconductor package 1 shown in fig. 5. The dicing step may be performed after the package body 300 is formed, for example, before or after the carrier board 60 is removed. Depending on the application, the dicing step may also be performed after the metal layer 40 is formed to singulate the semiconductor package device 1.

It should be noted that, in the process of forming the metal layer 40, since the residual test structure 120 of the package structure 10 of the integrated circuit is covered by the protection layer 130, the protection layer 130 can electrically isolate the residual test structure 120 from the metal layer 40, so as to prevent the metal layer 40 from contacting the residual test structure 120 to form a short circuit, thereby effectively improving the process yield.

The present invention has been described in terms of the above embodiments, which are provided for illustrative purposes only and are not intended to be limiting. Other modifications to the exemplary embodiments specifically illustrated herein will be apparent to those skilled in the art without departing from the spirit of the invention. Accordingly, such modifications are also encompassed within the scope of the present invention and are limited only by the appended claims.

Claims (9)

1. An integrated circuit package structure, comprising:

a die having a circuit region, a boundary region, a sidewall, and a dicing boundary, wherein the dicing boundary and the sidewall are located in the boundary region;

the sealing ring is arranged on the crystal grain and positioned between the circuit area and the boundary area;

a residual test structure disposed on the die and between the cutting boundary and the sidewall; and

and the protective layer extends from the circuit region, is arranged on the boundary region and covers the sealing ring and the residual test structure, and covers the boundary region between the sealing ring and the residual test structure.

2. The package structure of claim 1, wherein the residual test structure comprises a metal layer.

3. The package structure of claim 1, wherein the protective layer is an organic insulating material layer.

4. The package structure of claim 1, further comprising a metallurgical layer, wherein the metallurgical layer is disposed on the protective layer and electrically connects the die.

5. A semiconductor package device, comprising:

an integrated circuit package structure comprising:

a die having a circuit region, a boundary region, a sidewall and a dicing boundary, wherein the dicing boundary and the sidewall are located in the boundary region;

the sealing ring is arranged on the crystal grain and positioned between the circuit area and the boundary area;

a residual test structure disposed on the die and between the cutting boundary and the sidewall; and

a protective layer extending from the circuit region to the boundary region and covering the sealing ring and the residual test structure, wherein the protective layer covers the boundary region between the sealing ring and the residual test structure;

a passive element horizontally disposed separately from a package structure of the integrated circuit;

the packaging body is used for coating the packaging structure of the integrated circuit and the passive element and is provided with a top surface, wherein the passive element and the packaging structure of the integrated circuit are respectively provided with an exposed part on the top surface, and the exposed part and the top surface are coplanar; and

and the metal layer is configured on the top surface and electrically connected with the passive element and the packaging structure of the integrated circuit.

6. The semiconductor package device of claim 5, wherein the residual test structure comprises a metal layer.

7. The semiconductor package device of claim 5, wherein the protective layer is an organic insulating material layer.

8. The semiconductor package device according to claim 5, wherein the package structure of the integrated circuit further comprises a metallurgy layer disposed on the protection layer and electrically connecting the die and the metal layer.

9. The semiconductor package device of claim 5, wherein the metal layer is a patterned metal layer conformally formed on the top surface.

Images