KR20230037113A - Display device - Google Patents

Abstract

A display device comprises: a substrate including a display area having a plurality of pixels arranged therein, a pad area having a plurality of pads arranged therein, and a non-display area including a fan-out area between the display area and the pad area; at least one first fan-out line in the fan-out area; at least one second fan-out line in the fan-out area and electrically disconnected from the first fan-out line; first, second, and third insulating layers sequentially arranged on the substrate; and a first conductive layer arranged between the substrate and the first insulating layer, a second conductive layer arranged on the second insulating layer, and a third conductive layer arranged on the third insulating layer. The first fan-out line may be located closer to an edge of the non-display area than the second fan-out line. Each of the first and second fan-out lines has a multi-layered stacking structure in which a first sub-line, a second sub-line, and a third sub-line provided in different layers are stacked. The first fan-out line and the second fan-out line may have a same length as each other. According to the present invention, image quality is improved by preventing distortion of signals transmitted to the pixels.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

Recently, as interest in information displays has increased, research and development on display devices have been continuously conducted.

An object of the present invention is to provide a display device capable of improving reliability by reducing resistance variation of fan-out lines.

A display device according to an embodiment of the present invention includes a display area on which a plurality of pixels are disposed, a pad area on which a plurality of pads are disposed, and a non-display area including a fan-out area located between the display area and the pad area. Board; at least one first fan-out line located in the fan-out area; at least one second fan-out line located in the fan-out area and electrically separated from the first fan-out line; first, second, and third insulating layers sequentially disposed on the substrate; and a first conductive layer disposed between the substrate and the first insulating layer, a second conductive layer disposed on the second insulating layer, and a third conductive layer disposed on the third insulating layer. there is. The first fan-out line may be located closer to an edge of the non-display area than the second fan-out line.

In an embodiment, each of the first and second fan-out lines may include a multilayer stack structure in which first sub-lines, second sub-lines, and third sub-lines provided on different layers are stacked. there is. The first fan-out line and the second fan-out line may have the same wiring length.

In an embodiment, the first sub-line may include the first conductive layer, the second sub-line may include the second conductive layer, and the third sub-line may include the third conductive layer. there is.

In an embodiment, in each of the first and second fan-out lines, the first sub-line and the second sub-line may overlap each other with the first and second insulating layers interposed therebetween, and the second sub-line may overlap each other with the first and second insulating layers interposed therebetween. The sub-line and the third sub-line may overlap each other with the third insulating layer interposed therebetween.

In an embodiment, in each of the first and second fan-out lines, the first sub-line and the second sub-line may be electrically connected through a first contact hole penetrating the first and second insulating layers. there is. Here, in each of the first and second fan-out lines, the second sub-line and the third sub-line may be electrically connected through a second contact hole penetrating the third insulating layer.

In an embodiment, in each of the first and second fan-out lines, the second sub-line may directly contact the first sub-line through the first contact hole. Also, in each of the first and second fan-out lines, the third sub-line may directly contact the second sub-line through the second contact hole.

In an embodiment, the first contact hole and the second contact hole in each of the first and second fan-out lines may not correspond to each other.

In an embodiment, an overlapping area of the first sub-line and the second sub-line of the second fan-out line is greater than an overlapping area of the first sub-line and the second sub-line of the first fan-out line. can An overlapping area of the second sub-line and the third sub-line of the second fan-out line may be greater than an overlapping area of the second sub-line and the third sub-line of the first fan-out line.

In an embodiment, the pads may include at least one first pad electrically connected to the first sub line of the first fan-out line; and at least one second pad electrically connected to the second sub-line of the second fan-out line. Here, the first and second pads may include one of the first conductive layer, the second conductive layer, and the third conductive layer.

In an embodiment, the first and second pads may include the third conductive layer and may be provided on the same layer as the third sub line of each of the first and second fan-out lines.

In an embodiment, the first sub-line of the first fan-out line and the first pad are formed through a third contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer. can be electrically connected.

The first sub-line of the second fan-out line and the second pad may be electrically connected through third contact holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer. .

In an embodiment, the first pad may directly contact the first sub-line of the first fan-out line through the third contact hole, and the second pad may directly contact the first sub-line through the third contact hole. 2 can directly contact the first sub-line of the fan-out line.

In an embodiment, the first and second pads may include the second conductive layer and may be provided on the same layer as the second sub line of each of the first and second fan-out lines.

In an embodiment, the first sub-line of the first fan-out line and the first pad may be electrically connected through a third contact hole penetrating the first and second insulating layers. Also, the first sub-line of the second fan-out line and the second pad may be electrically connected through a third contact hole penetrating the first and second insulating layers.

In an embodiment, each of the first sub-line, the second sub-line, and the third sub-line in the second fan-out line may extend in one direction. Also, the width of the first sub-line in a direction crossing the one direction may be greater than those of the second and third sub-lines.

In an embodiment, a size of an overlapping area between the first sub line and the second sub line in the second fan-out line may be different from a size of an overlapping area between the second sub line and the third sub line. .

In an embodiment, the second sub-line in the second fan-out line may completely overlap the first sub-line with the first and second insulating layers interposed therebetween.

In an embodiment, the first sub-line, the second sub-line, and the third sub-line in the first fan-out line may extend in an oblique direction inclined in the one direction.

In an embodiment, the display device may include a driver located in the non-display area and electrically connected to each of the first and second fan-out lines; and data lines electrically connected to the driver to transfer data signals to each of the pixels. Here, the third sub-line of each of the first and second fan-out lines may be integrally provided with a corresponding data line among the data lines.

A display device according to another embodiment of the present invention includes a non-display area including a display area on which a plurality of pixels are disposed, a pad area on which a plurality of pads are disposed, and a fan-out area located between the display area and the pad area. substrate including; at least one first fan-out line located in the fan-out area; at least one second fan-out line located in the fan-out area and electrically separated from the first fan-out line; first, second, and third insulating layers sequentially disposed on the substrate; and a first conductive layer disposed between the substrate and the first insulating layer, a second conductive layer disposed on the second insulating layer, and a third conductive layer disposed on the third insulating layer. there is. The first fan-out line may be located closer to an edge of the non-display area than the second fan-out line.

In an embodiment, each of the first and second fan-out lines has a multi-layered stacked structure in which first sub-lines, second sub-lines, and third sub-lines are provided on different layers and electrically connected to each other. can include In each of the first and second fan-out lines, the first sub-line and the second sub-line may overlap each other, and the second sub-line and the third sub-line may overlap each other.

In an embodiment, an overlapping area between the first sub line and the second sub line may have a different size from an overlapping area between the second sub line and the third sub line.

According to an embodiment of the present invention, a stacked structure constituting each fan-out line is designed differently according to the positions of the fan-out lines in the fan-out area so that the fan-out lines have the same wiring length and wiring resistance regardless of positions. A display device may be provided.

In addition, according to an embodiment of the present invention, a display device with improved image quality can be provided by preventing distortion of signals transmitted to pixels.

The effects according to the embodiments of the present invention are not limited by the contents exemplified above, and various more effects are included in the present specification.

1 and 2 are plan views schematically illustrating a display device according to an exemplary embodiment.
3 and 4 are circuit diagrams illustrating electrical connection relationships of components included in the pixel shown in FIG. 1 according to an exemplary embodiment.
5A and 5B are schematic cross-sectional views of a pixel according to an exemplary embodiment.
FIG. 6 is an enlarged schematic plan view of an EA1 portion of FIG. 2 .
FIG. 7 is a perspective view schematically illustrating components included in a portion EA1 of FIG. 6 .
8 and 9 are cross-sectional views along lines Ⅰ to Ⅰ′ of FIG. 6 .
FIG. 10 is an enlarged schematic plan view of a portion EA2 of FIG. 2 .
FIG. 11 is a perspective view schematically illustrating components included in a portion EA2 of FIG. 10 .
12 and 13 are cross-sectional views taken along lines II to II' of FIG. 10 .
14 is a cross-sectional view along lines Ⅲ to Ⅲ′ of FIG. 10 .

Since the present invention may have various changes and various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Like reference numbers have been used for like elements in describing each figure. In the accompanying drawings, the dimensions of the structures are shown enlarged than actual for clarity of the present invention. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention.

In this application, the terms "include" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof. In addition, when a part such as a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where another part is present in the middle. In addition, in this specification, when it is said that a part such as a layer, film, region, plate, etc. is formed on another part, the formed direction is not limited to the upper direction, but includes those formed in the lateral or lower direction. . Conversely, when a part such as a layer, film, region, plate, etc. is said to be "under" another part, this includes not only the case where it is "directly below" the other part, but also the case where another part exists in the middle.

In the present application, "a component (eg 'first component') is connected (functionally or communicatively) to another component (eg 'second component') ((operatively or communicatively) When it is referred to as "coupled with/to" or "connected to", the certain component is directly connected to the other component, or another component (eg 'third component'). In addition, in this application, "connection" or "connection" may mean a physical and/or electrical connection or connection comprehensively.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention and other matters necessary for those skilled in the art to easily understand the contents of the present invention will be described in detail. In the following description, expressions in the singular number also include plural expressions unless the context clearly dictates that only the singular number is included.

1 and 2 are plan views schematically illustrating a display device DD according to an exemplary embodiment.

1 and 2, for convenience, the structure of the display device DD, in particular, the display panel DP provided in the display device DD, is briefly shown centering on the display area DA where an image is displayed. did

In an embodiment, "connection" between two components may mean that both electrical connection and physical connection are used inclusively.

The display device (DD) is a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, PDA, PMP (portable multimedia player), MP3 player, The present invention may be applied to any electronic device having a display surface applied to at least one surface, such as a medical device, camera, or wearable device.

Referring to FIGS. 1 and 2 , a display device DD according to an exemplary embodiment may include a substrate SUB, a plurality of pixels PXL, and a wiring unit.

The display device DD may be provided in various shapes, and for example, may be provided in a rectangular plate shape having two pairs of sides parallel to each other, but the present invention is not limited thereto. When the display device DD is provided in a rectangular plate shape, one pair of two pairs of sides may be provided longer than the other pair of sides. In the drawings, the display device DD is illustrated as having an angled corner portion formed of a straight line, but is not limited thereto. Depending on the embodiment, the display device DD provided in the shape of a rectangular plate may have a round shape at a corner where one long side and one short side come into contact.

In FIGS. 1 and 2 , for convenience of description, a case in which the display device DD has a rectangular shape having a pair of long sides and a pair of short sides is shown, and the extending direction of the long sides is the second direction DR2. , the extension direction of the short side is indicated as the first direction DR1, and the thickness direction of the display device DD is indicated as the third direction DR3. The first to third directions DR1 , DR2 , and DR3 may refer to directions indicated by the first to third directions DR1 , DR2 , and DR3 , respectively.

The display panel DP may display an image. As the display panel (DP), an organic light emitting display panel (OLED panel) using an organic light emitting diode as a light emitting element and a nano-scale LED display panel using a subminiature light emitting diode as a light emitting element are used. , a display panel capable of self-emission such as a quantum dot organic light emitting display panel (QD OLED panel) using quantum dots and organic light emitting diodes may be used. In addition, the display panel (DP) includes a liquid crystal display panel (LCD panel), an electro-phoretic display panel (EPD panel), and an electro-wetting display panel (EWD panel). ) may be used. When a non-emissive display panel is used as the display panel DP, the display device DD may include a backlight unit supplying light to the display panel DP.

The substrate SUB may be formed of one area having an approximately rectangular shape. However, the number of areas provided on the substrate SUB may be different from the above example, and the shape of the substrate SUB may have a different shape depending on the area provided on the substrate SUB.

The substrate SUB may include a transparent insulating material to transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

The flexible substrate may be one of a film substrate including a polymeric organic material and a plastic substrate. For example, the flexible substrate is polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide ), polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose ( It may include at least one of triacetate cellulose) and cellulose acetate propionate. However, the material constituting the substrate SUB is not limited to the above-described embodiments.

The pixels PXL may be provided in the display area DA of the substrate SUB. Each of the pixels PXL may be provided (or provided) in the pixel area PXA of the display area DA. Each of the pixels PX may be a minimum unit for displaying an image. The pixels PXL may include a light emitting element emitting white light and/or color light. Each of the pixels PXL may emit one color of red, green, and blue, but is not limited thereto, and may emit colors such as cyan, magenta, and yellow.

Each of the pixels PXL may include a light emitting element driven by a corresponding scan signal and data signal. The light emitting device may be, for example, an organic light emitting diode, but is not limited thereto. Depending on the embodiment, the light emitting device may be an inorganic light emitting device including an inorganic light emitting material or a light emitting device (quantum dot display device) that emits light by changing the wavelength of emitted light using quantum dots. An organic light emitting diode may have, for example, a form in which an anode, a hole transport layer, an organic light emitting layer, an electron transport layer, and a cathode are sequentially stacked, but is not limited thereto.

The pixels PXL may be arranged in a matrix form along rows extending in the first direction DR1 and columns extending in the second direction DR2 crossing the first direction DR1 . However, the arrangement form of the pixels PXL is not particularly limited and may be arranged in various forms. In the drawings, the pixels PXL are illustrated as having a rectangular shape, but are not limited thereto and may be deformed into various shapes. Also, when a plurality of pixels PXL are provided, they may be provided to have different areas (or sizes). For example, in the case of the pixels PXL having different colors of light emitted, the pixels PXL for each color may be provided in different areas (or sizes) or different shapes.

The substrate SUB may include a display area DA and a non-display area NDA. The display area DA is an area where the pixels PXL are provided to display an image, and the non-display area NDA is an area where the pixels PXL are not provided and may not display an image.

The non-display area NDA may be provided on at least one side of the display area DA. The non-display area NDA may surround the circumference (or edge) of the display area DA. A part of the wiring part connected to the pixels PXL and a driver DIC connected to the wiring part and driving the pixels PXL may be provided in the non-display area NDA.

The non-display area NDA includes predetermined wires electrically connected to the pixels PXL (eg, fan-out lines LP), pads PD, And/or it may be an area where built-in circuitry is provided.

In an embodiment, the non-display area NDA may include a fan-out area FTA and a pad area PDA.

The pad area PDA is an area of the non-display area NDA where the pad part PDP is located, and may be positioned closest to an edge (or edge) of the non-display area NDA. The fan-out area FTA is another area of the non-display area NDA where the fan-out lines LP, which are part of the wiring part, are located, and may be located adjacent to the display area DA in the non-display area NDA. . For example, the fan-out area FTA may be one area of the non-display area NDA located between the pad area PDA and the display area DA. Depending on the embodiment, the non-display area NDA may include an anti-static circuit area where an anti-static circuit is electrically connected to signal lines located in the display area DA to prevent generation of static electricity. The static electricity prevention circuit area may be an area of the non-display area NDA between the display area DA and the fan-out area FTA. Also, according to embodiments, the non-display area NDA may include an area where a demultiplexer is located.

The pad part PDP may be positioned in the pad area PDA, and the fan-out lines LP, which are part of the wiring part, may be positioned in the fan-out area FTA.

The fan-out lines LP are physically and/or electrically connected to the data lines DL provided to the pixels PXL to transmit predetermined signals (eg, data signals) applied from the driver DIC to the data. It can be delivered through the line DL. The fan-out lines LP may be positioned in the fan-out area FTA and may be connecting means electrically connecting the driver DIC and the pixels PXL.

Each of the fan-out lines LP may be designed to have the same or substantially similar wiring length and wiring resistance to adjacent fan-out lines LP.

In an embodiment, the fan-out lines LP may include at least one first fan-out line LP1 and at least one second fan-out line LP2.

In an embodiment, the first fan-out line LP1 is electrically connected to some of the pixels PXL disposed adjacent to the boundary BD between the display area DA and the non-display area NDA. can be connected to For example, the first fan-out line LP1 may be electrically connected to the data lines DL of some of the pixels PXL located at the outermost part of the display area DA. In other words, the first fan-out line LP1 may be a part of the fan-out lines LP positioned adjacent to the edge of the non-display area NDA among the fan-out lines LP.

The first fanout line LP1 may be located at the outermost part of the fanout area FTA. The first fan-out line LP1 may include an oblique portion inclined in the first direction DR1 (or the second direction DR2).

In an exemplary embodiment, the second fan-out line LP2 is positioned at the center (or center) of the display area DA of the pixels PXL in the first direction DR1 to divide the display area DA into two halves. It may be electrically connected to some pixels PXL adjacent to or overlapping the line VL of . For example, the second fan-out line LP2 may include some pixels PXL positioned adjacent to or overlapping a virtual line VL among the pixels PXL (or a pixel positioned in the center of the display area DA). may be electrically connected to the data lines DL of the PXL. Here, the imaginary line VL may extend along the second direction DR2.

The second fan-out line LP2 may include only a straight line extending in a direction parallel to the second direction DR2 positioned adjacent to or overlapping the imaginary line VL in the fan-out area FTA. . For example, the second fan-out line LP2 may have a straight line shape (or bar shape) extending in a direction parallel to the second direction DR2 .

In an embodiment, the fan-out lines LP including the first fan-out line LP1 and the second fan-out line LP2 have the same wire length or substantially the same wire length regardless of their positions in the fan-out area FTA. It can be designed to have a similar wiring length and the same wiring resistance or substantially similar wiring resistance. A detailed description thereof will be described later with reference to FIGS. 6 to 14 .

The pad part PDP may include a plurality of pads PD. The pads PD may supply (or transfer) driving power supplies and signals for driving the pixels PXL and/or the embedded circuit provided in the display area DA. According to an embodiment, when the driving unit DIC is mounted on the non-display area NDA of the substrate SUB, the pad unit PDP overlaps the output pads of the driving unit IC to generate output from the driving unit IC. signals can be received.

The pads PD may include at least one first pad PD1 and at least one second pad PD2 .

The first pad PD1 may be electrically connected to the first fan-out line LP1. In this case, the first pad PD1 may supply (or transmit) driving power and signals to some pixels PXL electrically connected to the first fan-out line LP1. For example, when the first fan-out line LP1 is a data fan-out line electrically connected to the data line DL provided to some pixels PXL, the first pad PD1 is the first fan-out line LP1. ) and may supply data signals to the data lines DL of some pixels PXL.

The second pad PD2 may be electrically connected to the second fan-out line LP2. In this case, the second pad PD2 may supply (or transmit) driving power and signals to some pixels PXL electrically connected to the second fan-out line LP2. For example, when the second fan-out line LP2 is a data fan-out line electrically connected to the data line DL provided to some of the pixels PXL, the second pad PD2 is the second fan-out line LP2. ) and may supply data signals to the data lines DL of some pixels PXL.

The display device DD may further include a circuit board FPCB connected to the display panel DP through the pad part PDP. The circuit board FPCB may be a flexible circuit board, but is not limited thereto.

The circuit board FPCB may process various signals input from the printed circuit board and output them to the display panel DP. To this end, one end of the circuit board FPCB may be attached to the display panel DP, and the other end (not shown) of the circuit board FPCB facing the one end may be attached to the printed circuit board. The circuit board FPCB may be connected to the display panel DP and the printed circuit board by conductive adhesive members. The conductive adhesive member may include an anisotropic conductive film.

The driver DIC may be positioned on the circuit board FPCB. The driving unit DIC may include input/output pads connected to the pads PD included in the pad unit PDP. For example, the driver DIC may be an integrated circuit (IC). The driving unit DIC may receive driving signals output from the printed circuit board and output predetermined signals to be provided to the pixels PXL and a predetermined voltage of driving power based on the received driving signals. . The predetermined signals and the voltage of the predetermined driving power supply may be supplied to corresponding pads PD of the pad part PDP through some of the input/output pads.

3 and 4 are circuit diagrams illustrating electrical connection relationships of components included in the pixel PXL shown in FIG. 1 according to an exemplary embodiment.

For example, FIGS. 3 and 4 illustrate electrical connection relationships of components included in a pixel PXL applicable to an active display device according to embodiments. However, the types of components included in the pixel PXL applicable to the embodiment of the present invention are not limited thereto.

In FIGS. 3 and 4 , not only components included in a pixel but also an area where the components are provided are collectively referred to as a pixel PXL.

3 , the pixel PXL may include a pixel circuit PXC and a light emitting device LD, and the light emitting device LD may be an organic light emitting diode. 4 , the pixel PXL may include a pixel circuit PXC and a light emitting element LD, and the light emitting element LD has a micro-scale (or micrometer) structure formed by growing a nitride-based semiconductor. to a plurality of subminiature inorganic light emitting diodes as small as a nanoscale (or nanometer).

3 and 4 illustrate the pixels PXL disposed in the ith row (or pixel row) and the jth column (or pixel column) of the display area DA of the display panel DP.

1 to 3 , the pixel PXL may include a light emitting unit (EMU) (or light emitting unit) including the light emitting element LD and a pixel circuit PXC for driving the light emitting element LD. can In an embodiment, the light emitting device LD may be an organic light emitting diode, but is not limited thereto.

The pixel circuit PXC may be connected to the scan line Si, the emission control line Ei, and the data line DLj of the corresponding pixel PXL. According to exemplary embodiments, the pixel circuit PXC may be connected to at least other scan lines. For example, the pixel circuit PXC may be connected to the i−1 th scan line Si−1 and/or the i+1 th scan line Si+1. Also, according to exemplary embodiments, the pixel circuit PXC may be connected to the first and second pixel power sources ELVDD and ELVSS and the initialization power source Vint.

The pixel circuit PXC may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

One electrode of the first transistor T1 (or driving transistor), for example, a source electrode is connected to the first power line PL1 to which the first pixel power source ELVDD is applied via the fifth transistor T5. Another electrode, for example, the drain electrode may be connected to the light emitting element LD of the light emitting unit EMU via the sixth transistor T6. Also, a gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls the driving current flowing between the first pixel power source ELVDD and the second pixel power source ELVSS via the light emitting element LD in response to the voltage of the first node N1. You can control it.

The second transistor T2 (or switching transistor) may be connected between the data line DLj connected to the pixel PXL and the source electrode of the first transistor T1. Also, the gate electrode of the second transistor T2 may be connected to the scan line Si connected to the pixel PXL. The second transistor T2 is turned on when a scan signal of a gate-on voltage (eg, a low voltage) is supplied from the scan line Si, so that the data line DLj is connected to the first transistor ( It can be electrically connected to the source electrode of T1). Therefore, when the second transistor T2 is turned on, the data signal supplied from the data line DLj can be transferred to the first transistor T1.

The third transistor T3 may be connected between the drain electrode of the first transistor T1 and the first node N1. Also, a gate electrode of the third transistor T3 may be connected to the scan line Si. The gate electrode of the third transistor T3 is turned on when the scan signal of the gate-on voltage is supplied from the scan line Si, and connects the drain electrode of the first transistor T1 and the first node N1. can be electrically connected.

The fourth transistor T4 may be connected between the first node N1 and the initialization power supply line IPL to which the initialization power source Vint is applied. Also, a gate electrode of the fourth transistor T4 may be connected to a previous scan line, for example, an i−1 th scan line Si−1. The fourth transistor T4 is turned on when a gate-on voltage scan signal is supplied to the i−1 th scan line Si−1, and the voltage of the initialization power source Vint is applied to the first node N1. can be forwarded to Here, the initialization power source Vint may have a voltage equal to or lower than the lowest voltage of the data signal.

The fifth transistor T5 may be connected between the first power line PL1 to which the first pixel power ELVDD is applied and the first transistor T1. Also, a gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the emission control line Ei, and may be turned on in other cases.

The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. Also, a gate electrode of the sixth transistor T6 may be connected to the emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the emission control line Ei, and may be turned on in other cases.

The seventh transistor T7 may be connected between the light emitting element LD and the initialization power supply line IPL to which the initialization power source Vint is applied. Also, the gate electrode of the seventh transistor T7 may be connected to one of the scan lines of the next stage, for example, the i+1 th scan line Si+1. The seventh transistor T7 is turned on when a gate-on voltage scan signal is supplied to the i+1th scan line Si+1, and the voltage of the initialization power source Vint is transmitted to the light emitting element LD. can supply A timing of the gate-on voltage may be the same as the i-th scan signal applied to the i-th scan line Si.

The storage capacitor Cst may be connected between the first power line PL1 to which the first pixel power ELVDD is applied and the first node N1. The storage capacitor Cst may store a data signal and a voltage corresponding to the threshold voltage of the first transistor T1.

The first electrode AE (or anode) of the light emitting element LD is connected to the first transistor T1 via the sixth transistor T6, and the second electrode CE (or cathode) is connected to the second pixel. It may be connected to the second power line PL2 to which power ELVSS is applied. The above-described light emitting unit EMU including the first electrode AE, the light emitting element LD, and the second electrode CE has a predetermined luminance of light (or light) corresponding to the amount of current supplied from the first transistor T1. ) to create A voltage value of the first pixel power source ELVDD may be set higher than a voltage value of the second pixel power source ELVSS so that current may flow to the light emitting element LD.

The light emitting device LD may be, for example, an organic light emitting diode. The light emitting element LD may emit light of one of red, green, and blue. However, it is not limited thereto.

In FIG. 3 , the first to seventh transistors T1 to T7 included in the pixel circuit PXC are all P-type transistors, but the embodiment is not limited thereto. According to exemplary embodiments, all of the first to seventh transistors T1 to T7 may be changed to N-type transistors or some of the first to seventh transistors T1 to T7 may be changed to N-type transistors.

The structure of the pixel circuit PXC is not limited to the embodiment shown in FIG. 3 . For example, it goes without saying that currently known pixel circuits PXC having various structures may be applied to the pixel PXL.

Hereinafter, referring to FIG. 4 , each pixel PXL including a plurality of light emitting elements LD having a structure in which a nitride-based semiconductor is grown will be described.

Referring to FIGS. 1, 2, and 4 , the pixel PXL may include a light emitting unit (EMU) (or a light emitting unit) that generates light having a luminance corresponding to a data signal. Also, the pixel PXL may selectively further include a pixel circuit PXC for driving the light emitting unit EMU.

According to an embodiment, the light emitting unit EMU includes a first power line PL1 to which the voltage of the first driving power source VDD is applied and a second power line PL2 to which the voltage of the second driving power source VSS is applied. It may include at least one or more light emitting devices LD connected therebetween. For example, the light emitting unit EMU may include a plurality of light emitting elements LD connected between the first electrode AE and the second electrode CE. In an embodiment, the first electrode AE may be an anode, and the second electrode CE may be a cathode.

Each of the light emitting elements LD included in the light emitting unit EMU includes first and second semiconductor layers (not shown) made of different types of semiconductor layers and an active layer (not shown) interposed therebetween. can include For example, each of the light emitting elements LD may be implemented as a light emitting stack in which a first semiconductor layer, an active layer, and a second semiconductor layer are sequentially stacked along one direction. Here, the first semiconductor layer may be an n-type semiconductor layer, and the second semiconductor layer may be a p-type semiconductor layer.

The light emitting elements LD included in the light emitting unit EMU are connected to the first end connected to the first driving power source VDD through the first electrode AE and the second driving power source (CE) through the second electrode CE. and a second end connected to VSS). The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power supply VDD may be set to a high-potential power supply, and the second driving power supply VSS may be set to a low-potential power supply. In this case, the potential difference between the first and second driving power supplies VDD and VSS may be set to be higher than or equal to the threshold voltage of the light emitting element LD during the light emitting period of the pixel PXL.

As described above, the light emitting element LD connected between the first electrode AE and the second electrode CE, to which voltages of different potentials are supplied, constitutes an effective light source and is a light emitting unit EMU of the pixel PXL. can be implemented.

The light emitting element LD may emit light with a luminance corresponding to the driving current supplied through the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to a grayscale value of corresponding frame data to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU may flow through the light emitting element LD. Accordingly, the light emitting unit (EMU) may emit light while the light emitting device (LD) emits light with a luminance corresponding to the driving current.

The pixel circuit PXC may be connected to the scan line Si and the data line DLj of the pixel PXL. Also, the pixel circuit PXC may be connected to the control line CLi and the sensing line SENj of the pixel PXL.

The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

The first transistor T1 is a driving transistor for controlling the driving current applied to the light emitting unit EMU, and may be connected between the first driving power source VDD and the light emitting unit EMU. Specifically, the first terminal of the first transistor T1 may be connected (or connected) to the first driving power supply VDD through the first power line PL1, and the second terminal of the first transistor T1 is connected to the second node N2, and the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls the amount of driving current applied from the first driving power source VDD to the light emitting unit EMU through the second node N2 according to the voltage applied to the first node N1. can do. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode, but is not limited thereto. Depending on embodiments, the first terminal may be a source electrode and the second terminal may be a drain electrode.

The second transistor T2 is a switching transistor that selects the pixel PXL in response to a scan signal and activates the pixel PXL, and may be connected between the data line DLj and the first node N1. A first terminal of the second transistor T2 is connected to the data line DLj, a second terminal of the second transistor T2 is connected to the first node N1, and a gate electrode of the second transistor T2. may be connected to the scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals. For example, when the first terminal is the drain electrode, the second terminal may be the source electrode.

The second transistor T2 is turned on when a scan signal of a gate-on voltage (eg, a high level voltage) is supplied from the scan line Si, so that the data line DLj and the first node ( N1) can be electrically connected. The first node N1 is a point where the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected, and the second transistor T2 is connected to the gate electrode of the first transistor T1. Data signals can be transmitted.

The third transistor T3 obtains a sensing signal through the sensing line SENj by connecting the first transistor T1 to the sensing line SENj, and uses the sensing signal to obtain a threshold voltage of the first transistor T1. It is possible to detect characteristics of the pixel PXL, including the like. Information on the characteristics of the pixels PXL may be used to convert image data so that characteristic deviations between the pixels PXL can be compensated for. The second terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 may be connected to the sensing line SENj, and the third transistor T3 may be connected to the sensing line SENj. The gate electrode of (T3) may be connected to the control line CLi. Also, a first terminal of the third transistor T3 may be connected to the initialization power supply. The third transistor T3 is an initialization transistor capable of initializing the second node N2, and is turned on when a sensing control signal is supplied from the control line CLi to supply the voltage of the initialization power supply to the second node N2. can be forwarded to Accordingly, the second storage electrode of the storage capacitor Cst connected to the second node N2 may be initialized.

A first storage electrode of the storage capacitor Cst may be connected to the first node N1, and a second storage electrode of the storage capacitor Cst may be connected to the second node N2. The storage capacitor Cst is charged with a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Accordingly, the storage capacitor Cst may store a voltage corresponding to a difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second node N2.

In FIG. 4 , an embodiment in which all light emitting devices LD constituting the light emitting unit EMU are connected in parallel is illustrated, but is not limited thereto. Depending on the embodiment, the light emitting unit (EMU) may be configured to include at least one serial stage (or stage) including a plurality of light emitting elements (LD) connected in parallel with each other.

In FIG. 4 , the first, second, and third transistors T1 , T2 , and T3 included in the pixel circuit PXC are all N-type transistors, but the embodiment is not limited thereto. Depending on the embodiment, at least one of the above-described first, second, and third transistors T1, T2, and T3 may be changed to a P-type transistor.

The structure of the pixel PXL applicable to the present invention is not limited to the embodiments illustrated in FIGS. 3 and 4 , and the corresponding pixel PXL may have various structures.

5A and 5B are schematic cross-sectional views of a pixel PXL according to an exemplary embodiment.

In FIGS. 5A and 5B , the thickness direction of the substrate SUB is indicated as the third direction DR3 for convenience of description. The third direction DR3 may refer to a direction indicated by the third direction DR3.

For convenience, in FIG. 5A, only a cross section of a portion corresponding to the first and sixth transistors among the first to seventh transistors T1 to T7 shown in FIG. 3 is shown, and in FIG. Among the first to third transistors T1 , T2 , and T3 , only the driving transistor T corresponding to the first transistor T1 is shown.

Hereinafter, the pixel PXL shown in FIG. 5A will be described first, and then the pixel PXL shown in FIG. 5B will be described later.

Referring to FIGS. 1 to 3 and FIG. 5A , the pixel PXL may be located in a pixel area PXA provided (or provided) on the substrate SUB.

The pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

The pixel circuit layer PCL and the display element layer DPL may be disposed to overlap each other on one surface of the substrate SUB. For example, the display area DA of the substrate SUB includes a pixel circuit layer PCL disposed on one surface of the substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL. can include However, mutual positions of the pixel circuit layer PCL and the display element layer DPL on the substrate SUB may vary depending on the embodiment. When the pixel circuit layer PCL and the display element layer DPL are separated into separate layers and designed to overlap each other, each layout space for forming the pixel circuit PXC and the light emitting unit EMU on a plane is It is sufficiently secured to easily implement a display device with high resolution and high resolution.

The substrate SUB may include a transparent insulating material to transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

In each pixel area PXA of the pixel circuit layer PCL, circuit elements constituting the pixel circuit PXC of the corresponding pixel PXL (for example, transistors T) and electrically connected to the circuit elements Certain signal lines may be arranged. In addition, the light emitting element LD constituting the light emitting unit EMU of the corresponding pixel PXL and the first and second electrodes AE and CE are disposed in each pixel area PXA of the display element layer DPL. It can be.

The pixel circuit layer PCL may include at least one insulating layer in addition to circuit elements and signal lines. For example, the pixel circuit layer PCL includes a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer (which are sequentially stacked on the substrate SUB) along the third direction DR3. PSV), and a via layer (PSV). Also, the pixel circuit layer PCL may include conductive layers disposed between the aforementioned insulating layers. For example, the pixel circuit layer PCL includes a first conductive layer CL1 disposed between the substrate SUB and the buffer layer BFL, a second conductive layer CL2 disposed on the gate insulating layer GI, It may include a third conductive layer CL3 disposed on the interlayer insulating layer ILD, and a fourth conductive layer CL4 disposed on the passivation layer PSV.

The buffer layer BFL may be provided and/or formed on the entire surface of the substrate SUB. The buffer layer BFL may be a first insulating layer of the pixel circuit layer PCL disposed on the substrate SUB. The buffer layer BFL may prevent diffusion of impurities into the transistor T included in the pixel circuit PXC. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. The buffer layer BFL may include at least one of metal oxides such as silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (AlO _x ). The buffer layer (BFL) may be provided as a single layer, but may also be provided as multiple layers of at least a double layer or more. When the buffer layer BFL is provided in multiple layers, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material of the substrate SUB and process conditions.

The transistor T may include a first transistor T1 for controlling a driving current of the light emitting element LD and a sixth transistor T6 electrically connected to the light emitting element LD.

Each of the first and sixth transistors T1 and T6 may include an active pattern (or semiconductor layer) and a gate electrode GE overlapping a portion of the active pattern. Here, the active pattern may include a channel region CHA, a first contact region SE, and a second contact region DE.

The gate electrode GE may be a second conductive layer CL2 provided and/or formed on the gate insulating layer GI. The gate electrode GE is selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. Double or multi-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag), which are low-resistance materials, to form a single layer alone or as a mixture or to reduce wiring resistance can be formed with

The gate insulating layer GI may be provided and/or formed on the entire surface of the active pattern and the buffer layer BFL. The gate insulating layer GI may be a second insulating layer of the pixel circuit layer PCL stacked on the substrate SUB. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include at least one of metal oxides such as silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (AlO _x ). can However, the material of the gate insulating layer GI is not limited to the above-described embodiments. Depending on the exemplary embodiment, the gate insulating layer GI may be formed of an organic insulating layer including an organic material. The gate insulating layer GI may be provided as a single layer, but may also be provided as multiple layers of at least a double layer.

The active pattern may be made of poly silicon, amorphous silicon, or an oxide semiconductor. The channel region CHA, the first contact region SE, and the second contact region DE may be formed of a semiconductor layer undoped or doped with impurities. For example, the first contact region SE and the second contact region DE may be formed of a semiconductor layer doped with impurities, and the channel region CHA may be formed of a semiconductor layer not doped with impurities.

The channel region CHA of each of the first and sixth transistors T1 and T6 may be a region of an active pattern overlapping the gate electrode GE of the corresponding transistor T. For example, the channel region CHA of the first transistor T1 may be a region of an active pattern overlapping the gate electrode GE of the first transistor T1, and the channel region of the sixth transistor T6 ( CHA) may be a region of an active pattern overlapping the gate electrode GE of the sixth transistor T6.

The first contact region SE of each of the first and sixth transistors T1 and T6 may be connected to (or contacted with) one end of the channel region CHA. The first contact region SE of each of the first and sixth transistors T1 and T6 may be connected to the first connection member TE1.

The first connecting member TE1 may be a third conductive layer CL3 provided and/or formed on the interlayer insulating layer ILD. The first connection member TE1 is formed through a contact hole sequentially penetrating the interlayer insulating layer ILD and the gate insulating layer GI, and the first contact region SE of each of the first and sixth transistors T1 and T6. ) and electrically and/or physically connected. In an embodiment, the first connecting member TE1 connected to the first contact region SE of the first transistor T1 is through a contact hole penetrating the passivation layer PSV located on the interlayer insulating layer ILD. It may be electrically and/or physically connected to the bridge pattern BRP.

The first connection member TE1 may include the same material as the gate electrode GE, or may include one or more materials selected from materials exemplified as constituent materials of the gate electrode GE.

The interlayer insulating layer ILD may be provided and/or formed on the entire surface of the gate electrode GE and the gate insulating layer GI. The interlayer insulating layer ILD may be a third insulating layer of the pixel circuit layer PCL stacked on the substrate SUB. The interlayer insulating layer ILD may include the same material as the gate insulating layer GI or may include one or more materials selected from materials exemplified as constituent materials of the gate insulating layer GI.

The bridge pattern BRP may be a fourth conductive layer CL4 provided and/or formed on the passivation layer PSV. The bridge pattern BRP may be connected to the first contact region SE of the first transistor T1 through the first connecting member TE1. In addition, the bridge pattern (BRP) is electrically connected to the bottom metal layer (BML) through contact holes that sequentially penetrate the passivation layer (PSV), the interlayer insulating layer (ILD), the gate insulating layer (GI), and the buffer layer (BFL). and/or physically connected. The bottom metal layer BML and the first contact region SE of the first transistor T1 may be electrically connected through the bridge pattern BRP and the first connection member TE1.

The bottom metal layer BML may be a first conductive layer among conductive layers provided on the substrate SUB. For example, the bottom metal layer BML may be a first conductive layer CL1 positioned between the substrate SUB and the buffer layer BFL. The bottom metal layer BML may be electrically connected to the first transistor T1 to widen a driving range of a predetermined voltage supplied to the gate electrode GE of the first transistor T1. For example, the bottom metal layer BML may be electrically connected to the first contact region SE of the first transistor T1 to stabilize the channel region of the first transistor T1. In addition, since the bottom metal layer BML is electrically connected to the first contact region SE of the first transistor T1, floating of the bottom metal layer BML may be prevented.

The second contact region DE of each of the first and sixth transistors T1 and T6 may be connected to (or contacted with) the other end of the channel region CHA of the corresponding transistor T. For example, the second contact area DA of the first transistor T1 may be connected to the other end of the channel area CHA of the first transistor T1, and the second contact area of the sixth transistor T6 ( DE) may be connected to the other terminal of the channel region CHA of the sixth transistor T6. Also, the second contact area DE of each of the first and sixth transistors T1 and T6 may be connected to (or contacted with) the second connection member TE2 .

The second connection member TE2 may be a third conductive layer CL3 provided and/or formed on the interlayer insulating layer ILD. The second connecting member TE2 is connected to the second contact region DE of each of the first and sixth transistors T1 and T6 through a contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. They may be electrically and/or physically connected.

In the embodiment, the second connecting member TE2 connected to the second contact region DE of the sixth transistor T6 is a contact portion CNT sequentially penetrating the via layer VIA and the passivation layer PSV. It may be electrically and/or physically connected to some components of the display element layer DPL through the . The second connection member TE2 may be a medium for electrically connecting the sixth transistor T6 of the pixel circuit layer PCL and some components of the display element layer DPL.

In the above-described embodiment, a case in which each of the first and sixth transistors T1 and T6 is a top gate structure thin film transistor has been described as an example, but is not limited thereto, and the first and sixth transistors (T1, T6) Each structure can be changed in various ways.

A passivation layer PSV may be provided and/or formed on the first and sixth transistors T1 and T6 and the first and second connection members TE1 and TE2 .

The passivation layer PSV (or protective layer) may be provided and/or formed entirely on the first and second connecting members TE1 and TE2 and the interlayer insulating layer ILD. The passivation layer PSV may be a fourth insulating layer of the pixel circuit layer PCL stacked on the substrate SUB. The passivation layer PSV may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of metal oxides such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (AlO _x ). . The organic insulating film may be, for example, acrylic resin (polyacrylates resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamide resin (polyamides resin), polyimide resin (polyimides rein), unsaturated poly At least one of an unsaturated polyesters resin, a poly-phenylen ethers resin, a poly-phenylene sulfides resin, and a benzocyclobutene resin can include

Depending on embodiments, the passivation layer PSV may include the same material as the interlayer insulating layer ILD, but is not limited thereto. The passivation layer (PSV) may be provided as a single layer, but may also be provided as multiple layers of at least a double layer.

A via layer VIA may be provided and/or formed on the fourth conductive layer CL4 (eg, the bridge pattern BRP).

The via layer VIA may be provided in a form including an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on the inorganic insulating layer. The inorganic insulating layer may include, for example, at least one of metal oxides such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), and aluminum oxide (AlO _x ). . The organic insulating film may be, for example, acrylic resin (polyacrylates resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamide resin (polyamides resin), polyimide resin (polyimides rein), unsaturated poly At least one of an unsaturated polyesters resin, a poly-phenylen ethers resin, a poly-phenylene sulfides resin, and a benzocyclobutene resin can include

The via layer VIA may include a contact portion CNT corresponding to the contact portion CNT of the passivation layer PSV exposing the second connecting member TE2 electrically connected to the sixth transistor T6. there is.

A display element layer DPL may be provided and/or formed on the via layer VIA.

The display element layer DPL may include a light emitting element LD that is provided on the via layer VIA and emits light. The light emitting element LD may include first and second electrodes AE and CE, and a light emitting layer EML provided between the two electrodes AE and CE. In this case, one of the first and second electrodes AE and CE may be an anode, and the other electrode may be a cathode. When the light emitting element LD is a top emission organic light emitting diode, the first electrode AE may be a reflective electrode, and the second electrode CE may be a transmissive electrode. Hereinafter, a case where the light emitting element LD is a top emission type organic light emitting diode and the first electrode AE is an anode will be described as an example.

The first electrode AE may be electrically connected to the sixth transistor T6 through the contact portion CNT penetrating the via layer VIA and the passivation layer PSV and the second connecting member TE2. The first electrode AE may include a reflective film (not shown) capable of reflecting light or a transparent conductive film (not shown) disposed above or below the reflective film. For example, the first electrode AE is provided on a lower transparent conductive layer made of indium tin oxide (ITO), a reflective layer formed on the lower transparent conductive layer and made of silver (Ag), and a reflective layer provided on the reflective layer and made of indium It may be composed of a multilayer including an upper transparent conductive layer made of indium tin oxide (ITO). At least one of the transparent conductive layer and the reflective layer may be electrically connected to the driving transistor T.

The display element layer DPL may further include a bank BNK including an opening exposing a portion of the first electrode AE, for example, a top surface of the first electrode AE. The bank BNK is a structure that defines (or partitions) a pixel region or a light emitting region of each pixel PXL and the pixel PXL adjacent thereto, and may be, for example, a pixel defining layer. The bank BNK may include an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the bank BNK is made of an organic insulating film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can However, the material of the bank BNK is not limited to the above-described embodiments.

The light emitting layer EML may be disposed in an area corresponding to the opening of the bank BNK. For example, the light emitting layer EML may be disposed on one surface of the exposed first electrode AE. The light emitting layer EML may include at least a light generation layer.

The color of light generated in the light generating layer may be one of red, green, blue, and white, but is not limited thereto in the present embodiment. For example, the color of light generated in the light generating layer of the light emitting layer EML may be one of magenta, cyan, and yellow.

According to the embodiment, the light emitting layer (EML) is a hole injection layer for injecting holes, has excellent hole transportability, and suppresses the movement of electrons that have not been combined in the light generating layer to increase the chance of recombination of holes and electrons. A hole transport layer to prevent the movement of holes not bound in the light generating layer, a hole blocking layer to suppress the movement of holes not bound in the light generating layer, and an electron transport layer for smoothly transporting electrons to the light generating layer. ), and an electron injection layer for injecting electrons. The hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may be layers patterned to correspond to light emitting regions or common films commonly provided to adjacent light emitting regions. The hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may be positioned above and/or below the light generation layer.

A second electrode CE may be provided and/or formed on the light emitting layer EML.

The second electrode CE may be a common layer commonly provided to the pixel PXL and the adjacent pixels PXL, but is not limited thereto. The second electrode CE is a transmissive electrode and may include a transparent conductive material (or material). As the transparent conductive material (or material), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO _x ), indium gallium zinc oxide , IGZO), conductive oxides such as indium tin zinc oxide (ITZO), and conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)). Here, zinc oxide (ZnO _x ) may be zinc oxide (ZnO) and/or zinc peroxide (ZnO ₂ ).

A thin film encapsulation layer TFE may be provided and/or formed on the second electrode CE.

The thin film encapsulation layer (TFE) may be formed of a single film or may be formed of a multi-layer. The thin film encapsulation layer TFE may include a plurality of insulating films covering the light emitting element LD. Specifically, the thin film encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the thin film encapsulation layer (TFE) may have a structure in which inorganic layers and organic layers are alternately stacked. Depending on the embodiment, the thin film encapsulation layer TFE may be an encapsulation substrate disposed on the light emitting device LD and bonded to the substrate SUB through a sealant.

In the above-described embodiment, the display element layer DPL includes the light emitting element LD including the top emission type organic light emitting diode having the first electrode AE, the light emitting layer EML, and the second electrode CE. Although it has been described as an example to do, it is not limited thereto.

According to an embodiment, as shown in FIG. 5B , the display element layer DPL includes at least a subminiature inorganic light emitting element (LD, or light emitting diode) having a structure in which a nitride-based semiconductor is grown and is as small as a nanoscale or microscale. It may contain more than one.

Hereinafter, the pixel PXL shown in FIG. 5B will be described.

Referring to FIGS. 1, 2, 4, and 5B , the pixel circuit layer PCL includes a first transistor T1, a bridge pattern BRP, a bottom metal layer BML, and a predetermined power line. can do.

The first transistor T1 may include an active pattern and a gate electrode GE overlapping a part of the active pattern. Since the first transistor T1 corresponds to a configuration substantially similar to that of the first transistor T1 described with reference to FIG. 5A , a detailed description thereof will be omitted.

The first transistor T1 may be electrically connected to the bottom metal layer BML through the bridge pattern BRP.

The bridge pattern BRP is a fourth conductive layer CL4 provided and/or formed on the passivation layer PSV, and may have a configuration substantially similar to the bridge pattern BRP described with reference to FIG. 5A .

The bottom metal layer BML is a first conductive layer CL1 provided and/or formed on the substrate SUB, and may have a configuration substantially similar to the bottom metal layer BML described with reference to FIG. 5A .

The predetermined power line may include, for example, the second power line PL2 . The second power line PL2 may be a fourth conductive layer CL4 provided and/or formed on the passivation layer PSV. The second power line PL2 may be provided on the same layer as the bridge pattern BRP. However, it is not limited thereto, and the position of the second power line PL2 in the pixel circuit layer PCL may be variously changed. A voltage of the second driving power source VSS described with reference to FIG. 4 may be applied to the second power line PL2 . The second power line PL2 may include a conductive material (or material). For example, the second power line PL2 includes copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. Molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or It may be formed in a double-layer (or double-layer) or multi-layer (or multi-layer) structure of silver (Ag). For example, the second power line PL2 may be formed of a double layer (or double film) in which titanium (Ti)/copper (Cu) are stacked in this order.

Although not directly shown in FIGS. 5A and 5B , the pixel circuit layer PCL may further include the first power line PL1 described with reference to FIGS. 3 and 4 . The voltage of the first pixel power source ELVDD described with reference to FIG. 3 or the voltage of the first driving power source VDD described with reference to FIG. 4 may be applied to the first power line PL1 according to an exemplary embodiment.

A display element layer DPL may be provided and/or formed on the pixel circuit layer PCL.

The display element layer DPL includes a bank pattern BNKP, a bank BNK, first and second alignment electrodes ALE1 and ALE2, first and second electrodes AE and CE, and first to fourth alignment electrodes ALE1 and ALE2. It may include insulating layers INS1 , INS2 , INS3 , and INS4 . Here, the light emitting element LD may have the same configuration as each light emitting element LD described with reference to FIG. 4 and may replace each of the plurality of light emitting elements LD.

The bank pattern BNKP is provided and/or formed on the via layer VIA, and may be positioned in a light emitting area where light is emitted from the pixel PXL. The bank pattern BNKP includes first and second alignment electrodes ALE1 and ALE2 to guide light emitted from the light emitting element LD in an image display direction of the display panel DP (or display device DD), respectively. In order to change the surface profile (or shape) of the first and second alignment electrodes ALE1 and ALE2 , respectively, may be supported. The bank pattern BNKP may include an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. According to embodiments, the bank pattern BNKP may include a single organic insulating layer and/or a single inorganic insulating layer, but is not limited thereto. Depending on the embodiment, the bank pattern BNKP may be provided in the form of a multilayer in which at least one organic insulating layer and at least one inorganic insulating layer are stacked. However, the material of the bank pattern BNKP is not limited to the above-described embodiment, and depending on the embodiment, the bank pattern BNKP may include a conductive material.

The bank BNK may surround at least one side of a peripheral area (eg, a non-emission area in which no light is emitted) of the pixel PXL. The bank BNK may be a pixel defining layer or a dam structure defining a light emitting region to which the light emitting elements LD are supplied in the process of supplying the light emitting elements LD to the pixels PXL. For example, since the light emitting area of the pixel PXL is partitioned by the bank BNK, a liquid mixture (eg, ink) containing a desired amount and/or type of light emitting elements LD is supplied (or injected) to the light emitting area. ) can be The bank BNK is configured to include at least one light-blocking material and/or a reflective material to prevent a light leakage defect in which light (or light) leaks between the pixel PXL and adjacent pixels PXL. According to exemplary embodiments, the bank BNK may include a transparent material (or material). Examples of the transparent material include, but are not limited to, polyamides resin and polyimide resin. According to another embodiment, a reflective material layer may be separately provided and/or formed on the bank BNK to further improve the efficiency of light emitted from the pixel PXL.

In an embodiment, the bank BNK may have the same configuration as the bank BNK described with reference to FIG. 5A.

Each of the first and second alignment electrodes ALE1 and ALE2 may be provided and/or formed on the bank pattern BNKP to have a surface profile corresponding to the shape of the bank pattern BNKP. Each of the first and second alignment electrodes ALE1 and ALE2 has a constant reflectance in order to guide the light emitted from the light emitting element LD in the image display direction of the display panel DP (or display device DD). material can be made. For example, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be made of a conductive material (or material) having a constant reflectance. The conductive material (or material) may include an opaque metal that is advantageous for reflecting light emitted from the light emitting elements LD in an image display direction of the display panel DP (or display device DD). As an opaque metal, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium ( Ir), chromium (Cr), titanium (Ti), and alloys thereof. According to exemplary embodiments, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may include a transparent conductive material (or material). When the first alignment electrode ALE1 and the second alignment electrode ALE2 include a transparent conductive material (or material), the light emitted from the light emitting device LD is transmitted to the display panel DP (or display device DD). A separate conductive layer made of an opaque metal for reflection in the image display direction of ) may be added. However, the materials of the first alignment electrode ALE1 and the second alignment electrode ALE2 are not limited to the above materials.

The first alignment electrode ALE1 may be electrically connected to the driving transistor T through the first contact portion CNT1 penetrating the via layer VIA and the passivation layer PSV and the second connection member TE2. , The second alignment electrode ALE2 may be electrically connected to the second power line PL2 through the second contact portion CNT2 passing through the via layer VIA.

The light emitting element LD is disposed between the first and second alignment electrodes ALE1 and ALE2 and may be electrically connected to the first and second alignment electrodes ALE1 and ALE2, respectively. The light emitting device LD may emit any one of color light and/or white light. The light emitting element LD may be provided in a sprayed form in the liquid mixture and applied to the pixel PXL. The light emitting device LD may include a light emitting stack pattern in which the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are sequentially stacked along one direction. In addition, the light emitting element LD may include an insulating film (not shown) surrounding an outer circumferential surface of the light emitting stacked pattern.

In an embodiment, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 includes a semiconductor material of any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and includes a first conductive dopant (or an n-type dopant) such as Si, Ge, or Sn. may be an n-type semiconductor layer doped with The active layer 12 is disposed on the first semiconductor layer 11 and may be formed in a single or multi-quantum well structure. The second semiconductor layer 13 is disposed on the active layer 12 and may include a semiconductor layer of a different type from the first semiconductor layer 11 . For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 includes at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a second conductive dopant (or p-type dopant) such as Mg. A p-type semiconductor layer may be included.

The light emitting elements LD may be mixed in a volatile solvent and inputted (or supplied) to the pixel area PXA through an inkjet printing method or a slit coating method. At this time, when an alignment signal corresponding to each of the first alignment electrode ALE1 and the second alignment electrode ALE2 is applied, an electric field may be formed between the first alignment electrode ALE1 and the second alignment electrode ALE2. . Due to this, the light emitting elements LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 .

The light emitting element LD may be provided and/or formed on the first insulating layer INS1.

The first insulating layer INS1 may be provided and/or formed between each of the first and second alignment electrodes ALE1 and ALE2 and the via layer VIA. The first insulating layer INS1 may stably support the light emitting element LD by filling a space between the light emitting element LD and the via layer VIA. The first insulating layer INS1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. The first insulating layer INS1 may be partially opened to expose a portion of the first alignment electrode ALE1 and a portion of the second alignment electrode ALE2 , respectively.

A second insulating layer INS2 may be provided and/or formed on the light emitting element LD. The second insulating layer INS2 may be provided and/or formed on the light emitting element LD to cover a portion of the upper surface of the light emitting element LD and expose both ends of the light emitting element LD to the outside. The second insulating layer INS2 may further fix the light emitting element LD.

The first electrode AE and the second electrode CE may be spaced apart from each other on the second insulating layer INS2 of the light emitting element LD.

The first electrode AE may be formed on the first alignment electrode ALE1 and one end of the light emitting element LD and electrically connected to one end of the light emitting element LD. The first electrode AE may be electrically and/or physically connected to the first alignment electrode ALE1 by directly contacting the exposed first alignment electrode ALE1 by removing a portion of the first insulating layer INS1. there is. In an embodiment, the first electrode AE may be an anode.

The second electrode CE may be formed on the second alignment electrode ALE2 and the other end of the light emitting element LD and electrically connected to the other end of the light emitting element LD. The second electrode CE may be electrically and/or physically connected to the second alignment electrode AEL2 by directly contacting the second alignment electrode ALE2 exposed by removing another portion of the first insulating layer INS1. can In an embodiment, the second electrode CE may be a cathode.

The first electrode AE and the second electrode CE may be formed of various transparent conductive materials so that light emitted from the light emitting element LD proceeds in the image display direction of the display device DD without loss.

In an embodiment, the first electrode AE and the second electrode CE may be provided on different layers. In this case, a third insulating layer INS3 may be provided and/or formed between the first electrode AE and the second electrode CE. The third insulating layer INS3 is provided on the first electrode AE to cover the first electrode AE (or prevent the first electrode AE from being exposed to the outside) so as to prevent the first electrode AE from being exposed to the outside. Corrosion can be prevented. The third insulating layer INS3 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material.

A fourth insulating layer INS4 may be provided and/or formed on the first electrode AE and the second electrode CE. The fourth insulating layer INS4 may be an inorganic film (or inorganic insulating film) containing an inorganic material or an organic film (or organic insulating film) containing an organic material. For example, the fourth insulating layer INS4 may have a structure in which at least one inorganic layer or at least one organic layer is alternately stacked. The fourth insulating layer INS4 may entirely cover the display element layer DPL to block moisture or moisture from entering the display element layer DPL including the light emitting elements LD from the outside.

6 is an enlarged schematic plan view of a portion EA1 of FIG. 2, FIG. 7 is a perspective view schematically illustrating components included in a portion EA1 of FIG. 6, and FIGS. 10 is a schematic plan view in which the EA2 portion of FIG. 2 is enlarged, FIG. 11 is a perspective view schematically showing components included in the EA2 portion of FIG. 10, and FIGS. 12 and 13 are These are cross-sectional views taken along lines II to II', and FIG. 14 is a cross-sectional view taken along lines III to III' in FIG. 10 .

The embodiments of FIGS. 8 and 9 show different embodiments in relation to the position of the first pad PD1 . For example, FIG. 8 discloses an embodiment in which the first pad PD1 is the third conductive layer CL3 positioned on the interlayer insulating layer ILD, and in FIG. 9 the first pad PD1 is a gate insulating layer. An embodiment of the second conductive layer CL2 disposed on the layer GI is disclosed.

The embodiments of FIGS. 12 and 13 show different embodiments in relation to the position of the second pad PD2 . For example, FIG. 12 discloses an embodiment in which the second pad PD2 is the third conductive layer CL3 positioned on the interlayer insulating layer ILD, and in FIG. 13 the second pad PD2 is a gate insulating layer. An embodiment of the second conductive layer CL2 disposed on the layer GI is disclosed.

In describing the embodiments, "formed and/or provided in the same layer" may mean formed in the same process, and "formed in and/or provided in different layers" may mean formed in different processes. .

In FIGS. 8, 9, and 12 to 14, each electrode is shown as a single-layer (or single-film) electrode and each insulating layer is shown only as a single-layer (or single-film) insulating layer. Although some components arranged in (NDA) are simplified and shown, it is not limited thereto.

In addition, in FIGS. 6 to 14 , for convenience of description, the horizontal direction (or horizontal direction) on the plane is the first direction DR1 and the vertical direction (or vertical direction) on the plane is the second direction DR2. , the thickness direction of the substrate SUB on the cross section is indicated as the third direction DR3. The first, second, and third directions DR1 , DR2 , and DR3 may mean directions indicated by the first, second, and third directions DR1 , DR2 , and DR3 , respectively.

1 to 14 , fan-out lines LP and a pad part PDP may be positioned in the non-display area NDA of the display panel DP (or display device DD).

The fan-out lines LP may be positioned in the fan-out area FTA, and the pads PD included in the pad part PDP may be positioned in the pad area PDA.

Each of the fan-out lines LP may have a multilayer stack structure in which first sub-lines, second sub-lines, and third sub-lines are sequentially stacked on different layers. For example, the first fan-out line LP1 has a multi-layered structure in which the 1-1 sub-line LP1a, the 1-2 sub-line LP1b, and the 1-3 sub-line LP1c are stacked. can have In addition, the second fan-out line LP2 has a multi-layered stacked structure in which the 2-1st sub-line LP2a, 2-2nd sub-line LP2b, and 2-3rd sub-line LP2c are stacked. can have

Hereinafter, for convenience, the first fan-out line LP1 will be first described with reference to FIGS. 6 to 9 , and then the second fan-out line LP2 will be described with reference to FIGS. 10 to 14 .

6 to 9, the first fan-out line LP1 includes a 1-1 sub-line LP1a, a 1-2-th sub-line LP1b, and a 1-3 sub-line LP1c. can do.

The 1-1st sub-line LP1a may be the first conductive layer CL1 positioned between the substrate SUB and the buffer layer BFL, and the 1-2nd sub-line LP1b may be on the gate insulating layer GI. It may be the second conductive layer CL2 positioned on the , and the 1st - 3rd sub-line LP1c may be the third conductive layer CL3 positioned on the interlayer insulating layer ILD.

The 1-1st sub-line LP1a may be provided and/or formed on the same layer as the bottom metal layer BML located in the pixel area PXA and may include the same material as the bottom metal layer BML. The 1-1st sub line LP1a and the bottom metal layer BML may be formed through the same process.

The 1st-2nd sub-line LP1b is provided and/or formed on the same layer as the gate electrode GE positioned in the pixel area PXA and may include the same material as the gate electrode GE. The 1-2nd sub-line LP1b and the gate electrode GE may be formed through the same process.

The first to third sub-lines LP1c are provided and/or formed on the same layer as the first and second connecting members TE1 and TE2 located in the pixel area PXA, and the first and second connecting members ( TE1, TE2) may include the same material. The first to third sub-lines LP1c and the first and second connection members TE1 and TE2 may be formed through the same process.

The first fan-out line LP1 including the 1-1, 1-2, and 1-3 sub lines LP1a, LP1b, and LP1c may be electrically and/or physically connected to the first pad PD1. can In addition, the first fan-out line LP1 including the first-first, first-second, and first-third sub-lines LP1a, LP1b, and LP1c corresponds to a pixel PXL located in the display area DA. ) may be electrically and/or physically connected to the data line DL.

The first pad PD1 may be electrically and/or physically connected to the 1-1st sub line LP1a. As shown in FIG. 8 , the first pad PD1 may be a third conductive layer CL3 disposed on the interlayer insulating layer ILD. In this case, the first pad PD1 may be provided and/or formed on the same layer as the first to third sub lines LP1c and may include the same material as the first to third sub lines LP1c. As shown in FIG. 8 , the first pad PD1 disposed on the interlayer insulating layer ILD may be electrically connected to the circuit board FPCB. At least a portion of the first pad PD1 may be exposed without being covered by the passivation layer PSV, the via layer VIA, the bank BNK, and the thin film encapsulation layer TFE. The exposed first pad PD1 may be electrically connected to the circuit board FPCB by a conductive adhesive member ACF.

The circuit board FPCB may include a third pad PD3 electrically connected to the pads PD of the pad part PDP. For example, the circuit board FPCB may include at least one third pad PD3 electrically connected to the first pad PD1 . The third pad PD3 may be positioned on the base layer BSL of the circuit board FPCB.

The conductive adhesive member ACF may include conductive particles PI formed in the adhesive film PF having adhesive properties. The conductive particles PI may electrically connect the first pad PD1 of the pad part PDP and the third pad PD3 of the circuit board FPCB. Accordingly, a signal (eg, a data signal) transmitted from the driver DIC mounted on the circuit board FPCB to the third pad PD3 is transferred to the first pad part PDP through the conductive adhesive member ACF. It is transferred to the pad PD1 and transferred to the data line DL of the pixels PXL corresponding to the first fan-out line LP1.

Depending on the embodiment, the first pad PD1 may be a second conductive layer CL2 disposed on the gate insulating layer GI as shown in FIG. 9 . In this case, the first pad PD1 may be provided and/or formed on the same layer as the first-second sub-line LP1b and may include the same material as the first-second sub-line LP1b. As shown in FIG. 9 , the first pad PD1 disposed on the gate insulating layer GI may be electrically connected to the circuit board FPCB. At least a portion of the first pad PD1 may be exposed without being covered by the interlayer insulating layer ILD, the passivation layer PSV, the via layer VIA, the bank BNK, and the thin film encapsulation layer TFE. there is. The exposed first pad PD1 may be electrically connected to a corresponding third pad PD3 of the circuit board FPCB by a conductive adhesive member ACF.

In an embodiment, one end of the 1-1 sub-line LP1a may be electrically and/or physically connected to the first pad PD1 through the third contact hole CH3. For example, as shown in FIG. 8 , one end of the 1-1st sub line LP1a sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. It may be electrically and/or physically connected to the first pad PD1 through the contact hole CH3. According to an embodiment, as shown in FIG. 9 , when the first pad PD1 is the second conductive layer CL2, one end of the 1-1 sub-line LP1a is a buffer layer BFL and a gate. It may be electrically and/or physically connected to the first pad PD1 through the third contact hole CH3 that sequentially penetrates the insulating layer GI.

The other end of the 1-1st sub line LP1a may be electrically and/or physically connected to the 1-2nd sub line LP1b through the first contact hole CH1. For example, as shown in FIGS. 8 and 9 , the other end of the 1-1st sub line LP1a includes a first contact hole CH1 sequentially penetrating the gate insulating layer GI and the buffer layer BFL. It may be electrically and/or physically connected to the 1st-2nd sub-line LP1b through .

One end of the 1-2nd sub-line LP1b may be electrically and/or physically connected to the 1-1st sub-line LP1a through the first contact hole CH1.

The other end of the 1-2nd sub line LP1b may be electrically and/or physically connected to the 1-3rd sub line LP1c through the second contact hole CH2. For example, as shown in FIGS. 8 and 9 , the other end of the 1-2 sub-line LP1b passes through the second contact hole CH2 penetrating the interlayer insulating layer ILD, and then the 1-3 sub-line LP1b. It may be electrically and/or physically connected to the line LP1c.

In an embodiment, one end of the 1-3 sub line LP1c may be electrically and/or physically connected to the 1-2 sub line LP1b through the second contact hole CH2. The other end of the 1st to 3rd sub line LP1c may be electrically and/or physically connected to the data line DL of the corresponding pixel PXL. The data line DL may be a third conductive layer CL3 provided and/or formed on the interlayer insulating layer ILD. In this case, the first to third sub-lines LP1c may be integrally formed with the data line DL and may be considered as one area of the data line DL.

Each of the 1-1, 1-2, and 1-3 sub-lines LP1a, LP1b, and LP1c is an oblique line inclined in the first direction DR1 (or the second direction DR2) when viewed on a plane. direction can be extended. Accordingly, each of the 1-1, 1-2, and 1-3 sub-lines LP1a, LP1b, and LP1c may constitute a slanted portion of the first fan-out line LP1.

In the embodiment, the 1-2nd sub-line LP1b directly contacts the 1-1st sub-line LP1a through the first contact hole CH1 and is electrically connected to the 1-1st sub-line LP1a. can be connected The 1-3 sub-line LP1c may directly contact the 1-2 sub-line LP1b through the second contact hole CH2 and be electrically connected to the 1-2 sub-line LP1b. Also, as shown in FIGS. 8 and 9 , the first pad PD1 directly contacts the 1-1 sub-line LP1a through the third contact hole CH3 to form the 1-1 sub-line LP1a. can be electrically connected to

When a predetermined signal (eg, a data signal) is applied from the driver DIC to the first pad PD1, the signal is transmitted to the first pad PD1, the 1-1 sub line LP1a, and the 1-2 The data may be transmitted to the data line DL of the corresponding pixel PXL through the sub line LP1b and the first to third sub lines LP1c.

In the first fan-out line LP1, a length L1 in the extension direction of the 1-1 sub-line LP1a (hereinafter, referred to as “first length L1”), a 1-2 sub-line ( A length L2 (hereinafter, referred to as “second length L2”) in the extension direction of LP1b), and a length L3 (hereinafter referred to as “second length L2”) in extension direction of 1-3 sublines LP1c (hereinafter referred to as “second length L2”). 3 length (L3)") may be different from each other, but is not limited thereto. According to the embodiment, in the first fan-out line LP1, the first length L1 of the 1-1st sub-line LP1a, the second length L2 of the 1-2nd sub-line LP1b, and The third lengths L3 of the 1-3 sub-lines LP1c may be the same as each other. Further, according to another embodiment, in the first fan-out line LP1, the first length L1 of the 1-1 sub-line LP1a and the second length L2 of the 1-2-th sub line LP1b ), and the third length L3 of the 1st to 3rd sublines LP1c, the length of at least two sublines may be the same and the length of the other subline may be different from the length of the two sublines. However, it is not limited thereto.

The width of the 1-1st sub-line LP1a (for example, the width in a direction crossing the extending direction of the 1-1st sub-line LP1a), the width of the 1-2nd sub-line LP1b (one For example, the width in a direction crossing the extending direction of the 1-2 sub-line LP1b), the width of the 1-3 sub-line LP1c (for example, the width of the 1-3 sub-line LP1c) width in a direction crossing the extension direction) may be different from each other, but is not limited thereto. Depending on embodiments, the width of the 1-1st sub-line LP1a, the width of the 1-2nd sub-line LP1b, and the width of the 1-3th sub-line LP1c may be the same as each other.

In the embodiment, the width and/or the first length L1 of the 1-1st sub-line LP1a, the width and/or the second length L2 of the 1-2nd sub-line LP1b, and The width and/or the third length L3 of the 1-3 sub-line LP1c is determined when the fan-out lines LP located in the fan-out area FTA have the same wiring length L and the same wiring resistance. It can be variously changed within the range. The first length L1 of the 1-1st sub-line LP1a, the second length L2 of the 1-2nd sub-line LP1b, and the third length L3 of the 1-3rd sub-line LP1c. ) may be equal to or substantially similar to the wiring length L of the second fan-out line LP2 . Also, the wiring resistance of the first fan-out line LP1 may be the same as that of the second fan-out line LP2 .

The first, second, and third contact holes CH1 , CH2 , and CH3 may not correspond to each other in the fan-out area FTA. For example, the first contact hole CH1 may be positioned not to correspond to the second and third contact holes CH2 and CH3 in the fanout area FTA, and the second contact hole CH2 may be located in the fanout area FTA. In the area FTA, the first and third contact holes CH1 and CH3 may not correspond to each other, and the third contact hole CH3 may be located in the fan-out area FTA to the first and second contact holes (CH1 and CH3). CH1, CH2) may not correspond to each other.

Positions of the first, second, and third contact holes CH1 , CH2 , and CH3 in the non-display area NDA are respectively the 1-1 , 1-2 , and 1-3 sub lines LP1a, Two components electrically connected to each other by direct contact among the LP1b and LP1c and the first pad PD1 may correspond to the overlapping region OVA.

In the non-display area NDA, the third contact hole CH3 is an overlapping area OVA1 (hereinafter referred to as “1-1 referred to as "overlapping area"). In addition, in the non-display area NDA, the first contact hole CH1 is an overlapping area OVA2 where the other end of the 1-1st sub line LP1a and one end of the 1-2nd sub line LP2b overlap each other. (hereinafter, referred to as "2-1st overlapping area"). Additionally, in the non-display area NDA, the second contact hole CH2 is an overlapping area OVA3 where the other end of the 1-2 sub line LP1b and one end of the 1-3 sub line LP1c overlap each other. (hereinafter, referred to as “3-1 overlapping region”).

The size of the 1-1st overlapping area OVA1 , the size of the 2-1st overlapping area OVA2 , and the size of the 3-1st overlapping area OVA3 may be different from each other, but are not limited thereto.

Hereinafter, the 2-1, 2-2, and 2-3 sub lines LP2a, LP2b, and LP2c included in the second fan-out line LP2 will be described with reference to FIGS. 10 to 14. I'm going to do it.

Referring to FIGS. 2 and 10 to 14 , the second fan-out line LP2 includes a 2-1 sub line LP2a, a 2-2 sub line LP2b, and a 2-3 sub line LP2c. ) may be included.

The 2-1st sub-line LP2a may be the first conductive layer CL1 positioned between the substrate SUB and the buffer layer BFL, and the 2-2nd sub-line LP2b may be on the gate insulating layer GI. may be the second conductive layer CL2 located on the , and the 2-3rd sub line LP2c may be the third conductive layer CL3 located on the interlayer insulating layer ILD.

The 2-1st sub-line LP2a is provided and/or formed on the same layer as the bottom metal layer BML and the 1-1st sub-line LP1a located in the pixel area PXA, and the bottom metal layer BML and the same material as that of the 1-1st sub line LP1a. The 2-1st sub-line LP2a, the bottom metal layer BML, and the 1-1st sub-line LP1a may be formed through the same process.

The 2-2nd sub-line LP2b is provided and/or formed on the same layer as the gate electrode GE and the 1-2nd sub-line LP1b located in the pixel area PXA, and the gate electrode GE and the It may include the same material as the 1-2nd sub line LP1b. The 2-2nd sub-line LP2b, the gate electrode GE, and the 1-2nd sub-line LP1b may be formed through the same process.

The 2-3 sub-line LP2c is provided and/or formed on the same layer as the first and second connecting members TE1 and TE2 and the 1-3 sub-line LP1c located in the pixel area PXA. The first and second connecting members TE1 and TE2 and the first to third sub lines LP1c may include the same material.

The second fan-out line LP2 including the 2-1, 2-2, and 2-3 sub lines LP2a, LP2b, and LP2c may be electrically and/or physically connected to the second pad PD2. can In addition, the second fan-out line LP2 including the 2-1, 2-2, and 2-3 sub-lines LP2a, LP2b, and LP2c corresponds to the pixel PXL located in the display area DA. ) may be electrically and/or physically connected to the data line DL.

The second pad PD2 may be electrically and/or physically connected to the 2-1st sub line LP2a. As shown in FIG. 12 , the second pad PD may be a third conductive layer CL3 disposed on the interlayer insulating layer ILD. In this case, the second pad PD2 may be provided and/or formed on the same layer as the 2-3rd sub-line LP2c and may include the same material as the 2-3rd sub-line LP2c. As shown in FIG. 12 , the second pad PD2 disposed on the interlayer insulating layer ILD may be electrically connected to the circuit board FPCB. At least a portion of the second pad PD2 may be exposed without being covered by the passivation layer PSV, the via layer VIA, the bank BNK, and the thin film encapsulation layer TFE. The exposed second pad PD2 may be electrically connected to the circuit board FPCB by a conductive adhesive member ACF. The conductive adhesive member (ACF) may be the conductive adhesive member (ACF) described with reference to FIG. 8 .

The circuit board FPCB may include at least one third pad PD3 electrically connected to the second pad PD2. The third pad PD3 may be positioned on the base layer BSL of the circuit board FPCB. A signal (for example, a data signal) transmitted from the driving unit DIC mounted on the circuit board FPCB to the third pad PD3 is transmitted through the conductive adhesive member ACF to the second pad PD2 of the pad unit PDP. ) and may be transferred to the data line DL of the pixels PXL corresponding to the second fan-out line LP2.

Depending on the embodiment, the second pad PD2 may be a second conductive layer CL2 disposed on the gate insulating layer GI as shown in FIG. 13 . In this case, the second pad PD2 may be provided and/or formed on the same layer as the 2-2nd sub-line LP2b and may include the same material as the 2-2nd sub-line LP2b. As shown in FIG. 13 , the second pad PD2 disposed on the gate insulating layer GI may be electrically connected to the circuit board FPCB. At least a portion of the second pad PD2 may be exposed without being covered by the interlayer insulating layer ILD, the passivation layer PSV, the via layer VIA, the bank BNK, and the thin film encapsulation layer TFE. there is. The exposed second pad PD2 may be electrically connected to a corresponding third pad PD3 of the circuit board FPCB by a conductive adhesive member ACF.

In an embodiment, one end of the 2-1st sub line LP2a may be electrically and/or physically connected to the second pad PD2 through the sixth contact hole CH6. For example, as shown in FIG. 12 , one end of the 2-1st sub line LP2a sequentially passes through the buffer layer BFL, the gate insulating layer GI, and the interlayer insulating layer ILD. It may be electrically and/or physically connected to the second pad PD2 through the contact hole CH6. According to an embodiment, as shown in FIG. 13 , when the second pad PD2 is the second conductive layer CL2, the 2-1 sub-line LP2a includes the buffer layer BFL and the gate insulating layer ( It may be electrically and/or physically connected to the second pad PD2 through the sixth contact hole CH6 sequentially penetrating the GI.

The other end of the 2-1st sub line LP2a may be electrically and/or physically connected to the 2-2nd sub line LP2b through the fourth contact hole CH4. For example, as shown in FIGS. 12 and 13 , the other end of the 2-1 sub-line LP2a includes a fourth contact hole CH4 sequentially penetrating the gate insulating layer GI and the buffer layer BFL. It may be electrically and/or physically connected to the 2-2nd sub line LP2b through .

One end of the 2-2 sub line LP2b may be electrically and/or physically connected to the 2-1 sub line LP2a through the fourth contact hole CH4.

The other end of the 2-2nd sub line LP2b may be electrically and/or physically connected to the 2-3rd sub line LP2c through the fifth contact hole CH5. For example, as shown in FIGS. 12 and 13 , the other end of the 2-2 sub line LP2b passes through the fifth contact hole CH5 penetrating the interlayer insulating layer ILD, It may be electrically and/or physically connected to the line LP2c.

In an embodiment, one end of the 2-3 sub line LP2c may be electrically and/or physically connected to the 2-2 sub line LP2b through a fifth contact hole CH5. The other end of the 2-3rd sub line LP2c may be electrically and/or physically connected to the data line DL of the corresponding pixel PXL. The data line DL may be a third conductive layer CL3 provided and/or formed on the interlayer insulating layer ILD. In this case, the second-third sub-line LP2c may be integrally formed with the data line DL and may be considered as one area of the data line DL.

Each of the 2-1, 2-2, and 2-3 sub-lines LP2a, LP2b, and LP2c may extend in a direction parallel to the second direction DR2. Accordingly, each of the 2-1, 2-2, and 2-3 sub-lines LP2a, LP2b, and LP2c may be a straight portion of the second fan-out line LP2.

In the embodiment, the 2-2nd sub-line LP2b is electrically connected to the 2-1st sub-line LP2a by directly contacting the 2-1st sub-line LP2a through the fourth contact hole CH4. can be connected The 2-3rd sub-line LP2c may directly contact the 2-2nd sub-line LP2b through the fifth contact hole CH5 and be electrically connected to the 2-2nd sub-line LP2b. Also, the second pad PD2 may directly contact the 2-1st sub-line LP2a through the sixth contact hole CH6 and be electrically connected to the 2-1st sub-line LP2a. The aforementioned second pad PD2, the 2-1st sub-line LP2a, the 2-2nd sub-line LP2b, and the 2-3rd sub-line LP2c may be electrically connected to each other.

When a predetermined signal (for example, a data signal) is applied from the driver DIC to the second pad PD2, the signal is transmitted to the second pad PD2, the 2-1st sub line LP2a, and the 2nd pad PD2. It may be transmitted to the data line DL of the corresponding pixel PXL through the second sub-line LP2b and the second-third sub-line LP2c.

In the second fan-out line LP2, a length L4 in the extension direction of the 2-1 sub-line LP2a (hereinafter referred to as a "fourth length"), a length of the 2-2 sub-line LP2b Length L5 in the extension direction (hereinafter referred to as "fifth length"), and length L6 in the extension direction of the 2-3 sub-line LP2c (hereinafter referred to as "sixth length") may be different from each other, but is not limited thereto. According to the embodiment, in the second fan-out line LP2, the fourth length L4 of the 2-1st sub-line LP2a, the fifth length L5 of the 2-2nd sub-line LP2b, and The sixth lengths L6 of the 2-3rd sub line LP2c may be the same as each other. In addition, according to another embodiment, the fourth length L4 of the 2-1 sub line LP2a and the fifth length L5 of the 2-2 sub line LP2b in the second fan-out line LP2 , and the length of at least two sub lines of the sixth length L6 of the 2-3 sub line LP2c may be the same and the length of the other sub line may be different from the length of the two sub lines. , but is not limited thereto.

The width W1 of the 2-1st sub-line LP2a (for example, the width in a direction crossing the extending direction of the 2-1st sub-line LP2a), the width of the 2-2nd sub-line LP2b A width W2 (for example, a width in a direction crossing the extending direction of the 2-2nd sub line LP2b), and a width W3 (for example, the 2-3rd sub line LP2c) The widths of the 2-3 sub-lines LP2c in the extending direction and the crossing direction) may be different from each other. For example, as shown in FIG. 14 , among the 2-1st, 2-2nd, and 2-3rd sublines LP2a, LP2b, and LP2c, the 2-1st sub-line LP2a positioned at the lowest layer The width W1 of may be designed to be the largest. When the width W1 of the 2-1st sub-line LP2a is the largest, the buffer layer BFL and the gate insulating layer GI disposed on the 2-1st sub-line LP2a are Since line LP2a has a flat surface profile, the 2-2 sub-line LP2b positioned on the gate insulating layer GI may have a flat surface. When the width W1 of the 2-1st sub-line LP2a is greater than the width W2 of the 2-2nd sub-line LP2, the 2-2nd sub-line LP2 is the 2-1st sub-line LP2. It may completely overlap the line LP2a.

Also, the width W2 of the 2-2nd sub-line LP2b may be designed to be greater than the width W3 of the 2-3rd sub-line LP2c. In this case, the interlayer insulating layer ILD positioned on the 2-2nd sub line LP2b has a flat surface profile on the 2-2nd sub line LP2b and is positioned on the interlayer insulating layer ILD. The 2-3 sub-line LP2c may have a flat surface.

In the above-described embodiment, it has been described that the 2-1, 2-2, and 2-3 sub-lines LP2a, LP2b, and LP2c have different widths, but it is not limited thereto. Depending on embodiments, the 2-1st, 2-2nd, and 2-3rd sublines LP2a, LP2b, and LP2c may have the same width as each other.

In the embodiment, the width W1 and/or the fourth length L4 of the 2-1st sub line LP2a, the width W2 and/or the fifth length of the 2-2nd sub line LP2b ( L5), the width W3 and/or the sixth length L6 of the 2-3 sub-line LP2c are the same as (or substantially similar to) the wiring length L of the first fan-out line LP1 and They may be variously changed within a range having the same (or substantially similar) wiring resistance.

In the embodiment, the fourth length L4 of the 2-1st sub line LP2a, the fifth length L5 of the 2-2nd sub line LP2b, and the 2nd length L5 of the 2-3rd sub line LP2c. The wire length L of the second fan-out line LP2, which is the sum of all six lengths L6, may be the same as or substantially similar to the wire length L of the first fan-out line LP1. Also, the wiring resistance of the second fan-out line LP2 may be the same as that of the first fan-out line LP1.

The fourth, fifth, and sixth contact holes CH4 , CH5 , and CH6 may not correspond to each other. For example, the fourth contact hole CH4 may be positioned not to correspond to the fifth and sixth contact holes CH5 and CH6 in the fan-out area FTA, and the fifth contact hole CH5 may be located in the fan-out area FTA. In the area FTA, the fourth and sixth contact holes CH4 and CH6 may not correspond to each other. CH4, CH5) may not correspond to each other. However, it is not limited thereto, and according to embodiments, the fourth, fifth, and sixth contact holes CH4 , CH5 , and CH6 may be positioned to correspond to each other in the fan-out area FAT.

Positions of the fourth, fifth, and sixth contact holes CH4 , CH5 , and CH6 in the non-display area NDA are located on the 2-1 , 2-2 , and 2-3 sub lines LP2a, An overlapping region OVA′ may correspond to two components electrically connected to each other through direct contact among the LP2b and LP2c and the second pad PD2 .

In the non-display area NDA, the sixth contact hole CH6 is an overlapping area OVA1' where the 2-1st sub-line LP2a and the second pad PD2 overlap each other (hereinafter referred to as "1-2 overlapping overlapping area"). It may be positioned to correspond to one of the areas). In addition, in the non-display area NDA, the fourth contact hole CH4 is an overlapping area OVA2' (hereinafter referred to as "" It may be positioned to correspond to one of the 2-2nd overlapping areas"). Additionally, in the non-display area NDA, the fifth contact hole CH5 is an overlapping area OVA3' (hereinafter referred to as " It may be positioned to correspond to one of the 3-2 overlapping regions").

The size of the 1-2 overlapping area OVA1', the size of the 2-2 overlapping area OVA2', and the size of the 3-2 overlapping area OVA3' may be different from each other, but are not limited thereto. no.

In an embodiment, the size of the 2-2nd overlapping area OVA2' may be larger than the 2-1st overlapping area OVA2, and the size of the 3-2nd overlapping area OVA3' may be larger than the 3-1st overlapping area OVA2'. It may be larger than the area OVA3.

In an embodiment, the first fan-out line LP1 may be located outside the fan-out area FTA relative to the second fan-out line LP2. Accordingly, the first fan-out line LP1 may be configured to include the oblique portion in the fan-out area FTA, and the second fan-out line LP2 may be configured to include only the straight portion in the fan-out area FTA. It can be.

In an existing display device, a wiring length difference may occur between some fan-out lines located at the outermost part of the fan-out area and some fan-out lines located at the center of the fan-out area. A resistance deviation may occur between fan-out lines due to the difference in wiring length. In particular, as the non-display area becomes narrower, the aforementioned resistance deviation may increase according to positions of the fan-out lines. For example, as the non-display area becomes narrower, a resistance deviation between some fan-out lines located at the outermost part of the fan-out area and some fan-out lines located at the center of the fan-out area may be greater. A signal transmitted (or supplied) to pixels may be distorted due to a resistance deviation between the fan-out lines, and light emission uniformity between adjacent pixels may be degraded.

Therefore, in the embodiment, the fan-out lines LP, for example, the first and second fan-out lines LP1 and LP2 have the same (or substantially similar) wire length L and the same (or substantially similar) wiring lengths. through corresponding contact holes among the 1-1, 1-2, and 1-3 sublines LP1a, LP1b, and LP1c of the first fan-out line LP1 in order to have a wiring resistance similar to LP1. Reducing (or minimizing) the size of the overlapping area OVA between the two elements in direct contact, and the 2-1, 2-2, and 2-3 sub-lines of the second fan-out line LP2 ( The first and second fan-out lines LP1 and LP2 may be designed to maximize the size of an overlapping area OVA' between two components LP2a, LP2b, and LP2c that directly contact each other through corresponding contact holes. can

In the second fan-out line LP2, the fourth length L4 of the 2-1st sub-line LP2a and the 2-2nd sub-line LP2b are sequentially stacked with at least one insulating layer interposed therebetween and overlap each other. ) of the fifth length L5 and the sixth length L6 of the 2-3 sub line LP2c are intentionally formed to be long, respectively, so that the 2-1, 2-2, and 2-3 sub-lines LP2c are intentionally long. When the overlapping area OVA' between the lines LP2a, LP2b, and LP2c is secured as much as possible, the second fan-out line LP2 has the same or substantially similar wiring length L as the first fan-out line LP1. and wiring resistance.

The second fan-out line LP2 includes the fourth length L4 of the 2-1st sub-line LP2a and the 2-2nd sub-line LP2a overlapping each other with the buffer layer BFL and the gate insulating layer GI interposed therebetween. By forming the fifth length L5 of the line LP2b long, the 2-2nd overlapping area OVA2' can be secured as much as possible. In this case, the size of the 2-2nd overlapping area OVA2' may be larger than that of the 2-1st overlapping area OVA2. In addition, the second fan-out line LP2 has the fifth length L5 of the 2-2nd sub-line LP2b and the 2-3rd sub-line LP2c overlapping each other with the interlayer insulating layer ILD interposed therebetween. ), the 3-2 overlapping region OVA3' can be secured as long as possible. In this case, the size of the 3-2 overlapping area OVA3 ′ may be larger than that of the 3-1 overlapping area OVA3 .

In the above-described embodiment, each of the first and second fan-out lines LP1 and LP2 is formed in a multi-layer including the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3. is implemented as a stacked structure, and the first to third conductive layers CL1 , CL2 , and CL3 (or the 2-1 to 2-3 sub-lines LP2a, LP2b, Of the LP2c), the overlapping region OVA' of the two conductive layers directly contacting through the corresponding contact hole is the first to third conductive layers CL1 , CL2 , and CL3 (or Among the 1-1 to 1-3 sub-lines LP1a, LP1b, and LP1c, it may be designed to be larger than the overlapping area OVA of two components directly contacting through corresponding contact holes. Accordingly, the wiring length L of the first fan-out line LP1 positioned at the outermost part of the fan-out area FTA is the wiring length L of the second fan-out line LP2 positioned at the center of the fan-out area FTA. It may be equal to or substantially similar to the length (L). Also, wiring resistance of the first fan-out line LP1 and wiring resistance of the second fan-out line LP2 may be the same or substantially similar.

According to the above-described embodiment, the area of the non-display area NDA is narrowed so that the fan-out lines LP include only the slanted portion, only the straight portion, or both the slanted portion and the straight portion, depending on the location. Therefore, each of the fan-out lines LP is implemented as a multi-layered structure in which the first to third conductive layers CL1, CL2, and CL3 are stacked and overlapped, even though they have different wiring shapes on a plane, so that the first to third conductive layers CL1, CL2, and CL3 are stacked and overlapped. The fan-out lines LP are formed by differently designing overlapping regions between two components of the through third conductive layers CL1 , CL2 , and CL3 that are in direct contact through corresponding contact holes for each fan-out line LP. All may have the same or substantially similar wire lengths and wire resistances.

As described above, when the wiring resistance deviation between the fan-out lines LP decreases, a uniform signal is applied to the pixels PXL electrically connected to the fan-out lines LP, and the adjacent pixels PXL Light emission uniformity between the liver can be improved. Accordingly, reliability of the display device DD (or display panel DP) can be improved by displaying an image of improved quality.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art or those having ordinary knowledge in the art do not deviate from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that the present invention can be variously modified and changed within the scope not specified.

Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUB: substrate
LD: light emitting element
PXL: pixels
PXA: pixel area
PCL: pixel circuit layer
DPL: display element layer
DA: display area
NDA: non-display area
FTA: Fanout Area
PDA: pad area
LP1, LP2: first and second fanout lines
PD1, PD2: first and second pads
CL1, CL2, CL3: first, second, and third conductive layers
LP1a, LP1b, LP1c: 1-1, 1-2, and 1-3 sub lines
LP2a, LP2b, LP2c: 2-1, 2-2, and 2-3 sub lines
OVA, OVA': overlapping area

Claims (20)

a substrate including a display area on which a plurality of pixels are disposed, a pad area on which a plurality of pads are disposed, and a non-display area including a fan-out area located between the display area and the pad area;
at least one first fan-out line located in the fan-out area;
at least one second fan-out line located in the fan-out area and electrically separated from the first fan-out line;
first, second, and third insulating layers sequentially disposed on the substrate; and
A first conductive layer disposed between the substrate and the first insulating layer, a second conductive layer disposed on the second insulating layer, and a third conductive layer disposed on the third insulating layer,
the first fan-out line is located closer to the edge of the non-display area than the second fan-out line;
Each of the first and second fan-out lines includes a multi-layered stacked structure in which first sub-lines, second sub-lines, and third sub-lines provided on different layers are stacked;
The display device of claim 1 , wherein the first fan-out line and the second fan-out line have the same length. According to claim 1,
wherein the first sub-line includes the first conductive layer, the second sub-line includes the second conductive layer, and the third sub-line includes the third conductive layer. According to claim 2,
In each of the first and second fan-out lines, the first sub-line and the second sub-line overlap each other with the first and second insulating layers interposed therebetween, and the second sub-line and the third sub-line overlap each other. The display device of claim 1 , wherein the lines overlap each other with the third insulating layer interposed therebetween. According to claim 3,
In each of the first and second fan-out lines, the first sub-line and the second sub-line are electrically connected through a first contact hole penetrating the first and second insulating layers;
In each of the first and second fan-out lines, the second sub-line and the third sub-line are electrically connected through a second contact hole penetrating the third insulating layer. According to claim 4,
In each of the first and second fan-out lines, the second sub-line directly contacts the first sub-line through the first contact hole;
In each of the first and second fan-out lines, the third sub-line directly contacts the second sub-line through the second contact hole. According to claim 5,
wherein the first contact hole and the second contact hole do not correspond to each other in each of the first and second fan-out lines. According to claim 5,
an overlapping area of the first sub-line and the second sub-line of the second fan-out line is greater than an overlapping area of the first sub-line and the second sub-line of the first fan-out line;
and an overlapping area of the second sub-line and the third sub-line of the second fan-out line is greater than an overlapping area of the second sub-line and the third sub-line of the first fan-out line. According to claim 7,
the pads,
at least one first pad electrically connected to the first sub-line of the first fan-out line; and
at least one second pad electrically connected to the second sub-line of the second fan-out line;
The first and second pads include one conductive layer among the first conductive layer, the second conductive layer, and the third conductive layer. According to claim 8,
wherein the first and second pads include the third conductive layer and are provided on the same layer as a third sub-line of each of the first and second fan-out lines. According to claim 9,
The first sub-line of the first fan-out line and the first pad are electrically connected through a third contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer;
The first sub-line of the second fan-out line and the second pad are electrically connected through a third contact hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer. display device. According to claim 10,
the first pad directly contacts the first sub-line of the first fan-out line through the third contact hole;
wherein the second pad directly contacts the first sub-line of the second fan-out line through the third contact hole. According to claim 8,
wherein the first and second pads include the second conductive layer and are provided on the same layer as a second sub line of each of the first and second fan-out lines. According to claim 12,
The first sub-line of the first fan-out line and the first pad are electrically connected through a third contact hole penetrating the first and second insulating layers;
The display device of claim 1 , wherein the first sub-line of the second fan-out line and the second pad are electrically connected through a third contact hole penetrating the first and second insulating layers. According to claim 8,
In the second fan-out line, each of the first sub-line, the second sub-line, and the third sub-line extends in one direction;
The display device of claim 1 , wherein a width of the first sub-line in a direction crossing the one direction is greater than that of the second and third sub-lines. According to claim 14,
and a size of an overlapping area of the first sub line and the second sub line in the second fan-out line is different from a size of an overlapping area of the second sub line and the third sub line. According to claim 14,
In the second fan-out line, the second sub-line completely overlaps the first sub-line with the first and second insulating layers interposed therebetween. According to claim 12,
In a first fan-out line, the first sub-line, the second sub-line, and the third sub-line extend in an oblique direction inclined in the one direction. According to claim 7,
a driver located in the non-display area and electrically connected to each of the first and second fan-out lines; and
Further comprising data lines electrically connected to the driver to transfer data signals to each of the pixels;
wherein the third sub-line of each of the first and second fan-out lines is integrally provided with a corresponding one of the data lines. a substrate including a display area on which a plurality of pixels are disposed, a pad area on which a plurality of pads are disposed, and a non-display area including a fan-out area located between the display area and the pad area;
at least one first fan-out line located in the fan-out area;
at least one second fan-out line located in the fan-out area and electrically separated from the first fan-out line;
first, second, and third insulating layers sequentially disposed on the substrate; and
A first conductive layer disposed between the substrate and the first insulating layer, a second conductive layer disposed on the second insulating layer, and a third conductive layer disposed on the third insulating layer,
the first fan-out line is located closer to the edge of the non-display area than the second fan-out line;
Each of the first and second fan-out lines includes a multi-layered stacked structure in which first sub-lines, second sub-lines, and third sub-lines are provided on different layers and electrically connected to each other, and
In each of the first and second fan-out lines, the first sub-line and the second sub-line overlap each other, and the second sub-line and the third sub-line overlap each other. According to claim 19,
and an overlapping area of the first sub line and the second sub line has a different size from an overlapping area of the second sub line and the third sub line.

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