KR20210132786A - Pixel and display device including the same - Google Patents

Abstract

The present invention provides a pixel and a display device including the same that may improve a light emission efficiency of light emitted from a light emitting element by disposing an intermediate pattern between the light emitting element and a substrate. The pixel includes a first electrode and a second electrode spaced from each other in a first direction on a substrate; a plurality of light emitting elements between the first electrode and the second electrode; an intermediate pattern located between the first electrode and the second electrode when viewed in a plan view and located between the substrate and the plurality of light emitting elements in a thickness direction of the substrate; a first contact electrode electrically connecting one end portion of each of the light emitting elements and the first electrode; and a second contact electrode electrically connecting an other end portion of each of the light emitting elements and the second electrode, wherein one side of the intermediate pattern is spaced from the first electrode with a first gap therebetween in the first direction, and an other side of the intermediate pattern is spaced from the second electrode with a second gap therebetween in the first direction. In addition, the intermediate pattern comprises a same material as that of the first and second electrodes.

Description

Pixel and display device having same

The present invention relates to a pixel and a display device having the same.

A light emitting diode (LED) exhibits relatively good durability even in harsh environmental conditions, and has excellent performance in terms of lifespan and luminance. Recently, research for applying such a light emitting diode to various display devices has been actively conducted.

In order to apply the light emitting diode to a lighting device or a display device, it is necessary to connect an electrode capable of applying power to the light emitting diode, and it is related to the purpose of use, reduction of the space occupied by the electrode, a manufacturing method, or a driving method. The arrangement relationship between the light emitting diode and the electrode has been studied in various ways.

It is an object of the present invention to provide a pixel capable of improving light output efficiency of light emitted from a light emitting device by arranging an intermediate pattern between a light emitting device and a substrate, and a display device having the same.

A pixel according to an embodiment of the present invention includes: a first electrode and a second electrode spaced apart from each other in a first direction on a substrate; a plurality of light emitting elements disposed between the first electrode and the second electrode; an intermediate pattern disposed between the first electrode and the second electrode in a plan view and positioned between the substrate and the plurality of light emitting devices in a thickness direction of the substrate; a first contact electrode electrically connecting one end of each of the light emitting devices to the first electrode; and a second contact electrode electrically connecting the other end of each of the light emitting devices to the second electrode. Here, one side of the intermediate pattern may be spaced apart from the first electrode at a first interval in the first direction, and the other side of the intermediate pattern may be spaced apart from the second electrode at a second interval in the first direction. have. In addition, the intermediate pattern may include the same material as the first and second electrodes.

In an embodiment of the present invention, when viewed in a plan view, the intermediate pattern may overlap the light emitting devices.

In an embodiment of the present invention, the first and second electrodes and the intermediate pattern may be provided on the same layer.

In an embodiment of the present invention, the first interval and the second interval may be the same as or different from each other.

In one embodiment of the present invention, each of the first and second intervals may be smaller than a length of each of the light emitting devices parallel to the extending direction of each of the light emitting devices. In addition, a width of the intermediate pattern in the first direction may be greater than a length of each of the light emitting devices.

In an embodiment of the present invention, the pixel may further include an insulating layer provided on the first and second electrodes and the intermediate pattern and disposed under the light emitting devices. Here, the insulating layer may expose a portion of the first electrode and a portion of the second electrode, and may completely cover the intermediate pattern.

In an embodiment of the present invention, the intermediate pattern may be covered by the insulating layer to be electrically insulated from the first electrode, the second electrode, the first contact electrode, and the second contact electrode.

In an embodiment of the present invention, the intermediate pattern may reflect light emitted from each of the light emitting devices in one direction.

In an embodiment of the present invention, the pixel includes a first bank pattern disposed between the substrate and the first electrode; and a second bank pattern disposed between the substrate and the second electrode. Here, the one side of the intermediate pattern may correspond to the first bank pattern, and the other side of the intermediate pattern may correspond to the second bank pattern.

In an embodiment of the present invention, the first electrode and the one side of the intermediate pattern may be spaced apart from each other by the first interval on the first bank pattern, and the other side of the second electrode and the intermediate pattern may be the The second bank pattern may be spaced apart from each other at the second interval.

In an embodiment of the present invention, the pixel includes a first dummy pattern spaced apart from the first electrode in the first direction; and a second dummy pattern spaced apart from the second electrode in the first direction. Here, the first electrode may be disposed between the first dummy pattern and the intermediate pattern in a plan view. Also, the second electrode may be disposed between the second dummy pattern and the intermediate pattern when viewed in a plan view.

In an embodiment of the present invention, the first and second dummy patterns may include the same material as the first and second electrodes and be provided on the same layer as the first and second electrodes.

In an embodiment of the present invention, the insulating layer may be provided on the first and second dummy patterns to completely cover the first and second dummy patterns. Here, the first and second dummy patterns may reflect the light emitted from the light emitting devices in the one direction.

A display device according to an exemplary embodiment may include a plurality of pixels provided on a substrate. Each of the pixels may include: a first electrode and a second electrode spaced apart from each other in a first direction on the substrate; a plurality of light emitting elements disposed between the first electrode and the second electrode; an intermediate pattern disposed between the first electrode and the second electrode in a plan view and positioned between the substrate and the plurality of light emitting devices in a thickness direction of the substrate; a first contact electrode electrically connecting one end of each of the light emitting devices to the first electrode; and a second contact electrode electrically connecting the other end of each of the light emitting devices to the second electrode. Here, one side of the intermediate pattern may be spaced apart from the first electrode at a first interval in the first direction, and the other side of the intermediate pattern may be spaced apart from the second electrode at a second interval in the first direction. can be

In an embodiment of the present invention, the intermediate pattern may include the same material as the first and second electrodes.

According to an embodiment of the present invention, by arranging an intermediate pattern between the light emitting element and the substrate to reflect light emitted from the light emitting element in the direction of the substrate using the intermediate pattern in the image display direction (or the front direction), the image display direction It is possible to increase the amount of light that proceeds to Accordingly, a pixel having improved light output efficiency and a display device having the same may be provided.

Effects according to an embodiment of the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1A is a perspective view schematically illustrating a light emitting device according to an embodiment of the present invention.
1B is a cross-sectional view of the light emitting device of FIG. 1A.
2A is a perspective view schematically illustrating a light emitting device according to another embodiment of the present invention.
2B is a cross-sectional view of the light emitting device of FIG. 2A.
3A is a perspective view schematically illustrating a light emitting device according to another embodiment of the present invention.
3B is a cross-sectional view of the light emitting device of FIG. 3A.
4A is a perspective view schematically illustrating a light emitting device according to another embodiment of the present invention.
4B is a cross-sectional view of the light emitting device of FIG. 4A.
5 is a view showing a display device according to an embodiment of the present invention, and in particular, the light emitting devices shown in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B. It is a schematic plan view of a display device using any one of the light emitting elements as a light emitting source.
6A and 6B are circuit diagrams illustrating electrical connection relationships between components included in one pixel illustrated in FIG. 5 according to various embodiments of the present disclosure;
7 is a plan view schematically illustrating one of the pixels illustrated in FIG. 5 .
8 is a cross-sectional view taken along line I to I' of FIG. 7 .
9 is a cross-sectional view taken along line II to II′ of FIG. 7 .
10 is a plan view schematically illustrating a pixel according to another exemplary embodiment of the present invention.
11 is a cross-sectional view taken along line III to III' of FIG. 10 .
12 is a cross-sectional view taken along line IV to IV' of FIG. 10 .
FIG. 13 is a cross-sectional view of the first bank pattern shown in FIG. 12 that is implemented according to another embodiment, and is a cross-sectional view taken along line IV to IV′ of FIG. 10 .
14 is a cross-sectional view of the second contact electrode shown in FIG. 12 , which is implemented according to another embodiment, and is a cross-sectional view taken along line IV to IV′ of FIG. 10 .
15 is a plan view schematically illustrating a pixel according to another embodiment of the present invention.
16 is a cross-sectional view taken along line V to V' of FIG. 15 .
17 is a plan view schematically illustrating a pixel according to another exemplary embodiment of the present invention.
18 is a cross-sectional view taken along line VI to VI' of FIG. 17 .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

In describing each figure, like reference numerals have been used for like elements. In the accompanying drawings, the dimensions of the structures are enlarged than the actual size for clarity of the present invention. Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof. Also, when a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the case where it is "directly on" another part, but also the case where another part is in the middle. In addition, in the present specification, when a portion such as a layer, film, region, or plate is formed on another portion, the formed direction is not limited only to the upper direction, and includes those formed in the side or lower direction. . Conversely, when a part of a layer, film, region, plate, etc. is said to be “under” another part, this includes not only cases where it is “directly under” another part, but also a case where another part is in between.

In the present application, "a certain component (eg 'first component') is "(functionally or communicatively) connected to another component (eg 'second component') ((operatively or communicatively) When referring to "coupled with/to)" or "connected to", the certain component is directly connected to the other component, or another component (eg, a 'third component') On the other hand, it should be understood that a certain element (eg, 'first element') is "directly connected" or "directly connected" to another element (eg, 'second element'). When referring to "connected", it may be understood that no other element (eg, a 'third element') exists between the certain element and the other element.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention and other matters necessary for those skilled in the art to easily understand the contents of the present invention will be described in detail. In the description below, expressions in the singular also include the plural, unless the context clearly includes only the singular.

1A is a perspective view schematically showing a light emitting device according to an embodiment of the present invention, FIG. 1B is a cross-sectional view of the light emitting device of FIG. 1A, and FIG. 2A is a schematic view of a light emitting device according to another embodiment of the present invention One perspective view, FIG. 2B is a cross-sectional view of the light-emitting device of FIG. 2A, FIG. 3A is a perspective view schematically illustrating a light-emitting device according to another embodiment of the present invention, and FIG. 3B is a cross-sectional view of the light-emitting device of FIG. 3A, FIG. 4A is a perspective view schematically illustrating a light emitting device according to another embodiment of the present invention, and FIG. 4B is a cross-sectional view of the light emitting device of FIG. 4A .

For convenience, after explaining FIGS. 1A, 1B, 2A, 2B, 3A, and 3B illustrating a light emitting device manufactured by an etching method, FIGS. 4A and 4A and FIG. 3B showing a light emitting device manufactured by a growth method 4b will be described. In one embodiment of the present invention, the type and/or shape of the light emitting device is limited to the embodiments shown in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B it doesn't happen

First, referring to FIGS. 1A, 1B, 2A, 2B, 3A, and 3B , the light emitting device LD includes a first semiconductor layer 11 , a second semiconductor layer 13 , and first and second semiconductor layers. An active layer 12 interposed between the two semiconductor layers 11 and 13 may be included. For example, the light emitting device LD may implement a light emitting stack in which the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are sequentially stacked.

The light emitting device LD may be provided in a shape extending in one direction. When the extending direction of the light emitting device LD is referred to as a longitudinal direction, the light emitting device LD may include one end (or lower end) and the other end (or upper end) along the extending direction. At one end (or lower end) of the light emitting device LD, any one of the first and second semiconductor layers 11 and 13 is formed, and at the other end (or upper end) of the light emitting device LD, the second semiconductor layer is disposed. The remaining semiconductor layers among the first and second semiconductor layers 11 and 13 may be disposed. For example, the first semiconductor layer 11 is disposed at one end (or lower end) of the light emitting device LD, and the second semiconductor layer 13 is disposed at the other end (or upper end) of the light emitting device LD. can be placed.

The light emitting device LD may be provided in various shapes. For example, the light emitting device LD may have a long rod-like shape in the longitudinal direction (ie, an aspect ratio greater than 1) or a bar-like shape. In one embodiment of the present invention, the length L of the light emitting device LD in the longitudinal direction may be greater than the diameter D or the width of the cross-section. The light emitting device LD is, for example, a light emitting diode (LED) manufactured so as to have a diameter (D) and/or a length (L) of about a micro scale or a nano scale. ) may be included.

The diameter D of the light emitting device LD may be about 0.5 μm to 500 μm, and the length L thereof may be about 1 μm to 10 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto, and the light emitting element LD is not limited thereto so as to meet the requirements (or design conditions) of a lighting device or a self-luminous display device to which the light emitting element LD is applied. The size of the light emitting device LD may be changed.

The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 includes a semiconductor material of any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and includes a first conductive dopant (or an n-type dopant) such as Si, Ge, Sn, or the like. ) may be a doped n-type semiconductor layer. However, the material constituting the first semiconductor layer 11 is not limited thereto, and in addition to this, the first semiconductor layer 11 may be formed of various materials. In an embodiment of the present invention, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or an n-type dopant). For example, the first semiconductor layer 11 may be an n-type GaN semiconductor layer. The first semiconductor layer 11 may include an upper surface in contact with the active layer 12 and a lower surface exposed to the outside along the length L direction of the light emitting device LD. The lower surface of the first semiconductor layer 11 may be one end (or lower end) of the light emitting device LD.

The active layer 12 is disposed on the first semiconductor layer 11 and may be formed in a single or multiple quantum well structure. For example, when the active layer 12 has a multi-quantum well structure, the active layer 12 includes a barrier layer (not shown), a strain reinforcing layer, and a well layer. It can be repeatedly stacked as a unit of The strain reinforcing layer may have a smaller lattice constant than the barrier layer to further enhance the strain applied to the well layer, for example, the compressive strain. However, the structure of the active layer 12 is not limited to the above-described embodiment.

The active layer 12 may emit light having a wavelength of 400 nm to 900 nm, and a double hetero structure may be used. In an embodiment of the present invention, a clad layer (not shown) doped with a conductive dopant is formed on the upper and/or lower portions of the active layer 12 along the length L of the light emitting device LD. may be For example, the clad layer may be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, a material such as AlGaN or InAlGaN may be used to form the active layer 12 , and in addition to this, various materials may constitute the active layer 12 . The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13 . The first surface and the second surface of the active layer 12 may face each other in the length L direction of the light emitting device LD.

When an electric field greater than or equal to a predetermined voltage is applied to both ends of the light emitting device LD, the light emitting device LD emits light while electron-hole pairs are combined in the active layer 12 . By controlling the light emission of the light emitting device LD using this principle, the light emitting device LD can be used as a light source (or light emitting source) of various light emitting devices including pixels of a display device.

The second semiconductor layer 13 is disposed on the second surface of the active layer 12 , and may include a semiconductor layer of a different type from that of the first semiconductor layer 11 . For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 includes at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a second conductive dopant (or p-type dopant) such as Mg. It may include a p-type semiconductor layer. However, the material constituting the second semiconductor layer 13 is not limited thereto, and various materials other than this may constitute the second semiconductor layer 13 . In an embodiment of the present invention, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or a p-type dopant). For example, the second semiconductor layer 13 may be a p-type GaN semiconductor. As shown in FIGS. 1A and 1B , the second semiconductor layer 13 has a lower surface in contact with the second surface of the active layer 12 along the length L direction of the light emitting device LD and exposed to the outside. It may include a top surface. Here, the upper surface of the second semiconductor layer 13 may be the other end (or upper end) of the light emitting device LD.

In one embodiment of the present invention, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses in the length L direction of the light emitting device LD. For example, the first semiconductor layer 11 may have a relatively greater thickness than the second semiconductor layer 13 in the length L direction of the light emitting device LD. Accordingly, the active layer 12 of the light emitting device LD is located closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11 as shown in FIGS. 1A and 1B. can

Meanwhile, in FIGS. 1A and 1B , the first semiconductor layer 11 and the second semiconductor layer 13 are illustrated as one layer, but the present invention is not limited thereto. In one embodiment of the present invention, depending on the material of the active layer 12, each of the first semiconductor layer 11 and the second semiconductor layer 13 is at least one or more layers, for example, a clad layer and/or TSBR (Tensile Strain) It may further include a barrier reducing) layer. The TSBR layer may be a strain mitigating layer disposed between semiconductor layers having different lattice structures to serve as a buffer for reducing a lattice constant difference. The TSBR layer may be formed of a p-type semiconductor layer such as p-GaInP, p-AlInP, or p-AlGaInP, but the present invention is not limited thereto.

According to an embodiment, the light emitting device LD may include, in addition to the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 , as shown in FIGS. 2A to 3B , the second semiconductor layer. An additional electrode 15 (hereinafter, referred to as a 'first additional electrode') disposed on the layer 13 may be further included. In addition, according to another embodiment, one additional electrode (not shown, hereinafter referred to as a 'second additional electrode') disposed on one end of the first semiconductor layer 11 may be further included.

The first additional electrode 15 and the second additional electrode may be ohmic contact electrodes, but are not limited thereto, and may be Schottky contact electrodes according to embodiments. The first additional electrode 15 and the second additional electrode may comprise a conductive material (or material). For example, the first additional electrode 15 and the second additional electrode may include chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and oxides or alloys thereof. may include an opaque metal used alone or in combination, but the present invention is not limited thereto. In some embodiments, the first additional electrode 15 and the second additional electrode may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO, zinc oxide), and indium oxide. A transparent conductive oxide such as indium tin zinc oxide (ITZO) may be included.

Materials included in the first additional electrode 15 and the second additional electrode may be the same or different from each other. The first further electrode 15 and the second further electrode may be substantially transparent or translucent. Accordingly, the light generated by the light emitting device LD may pass through the first additional electrode 15 and the second additional electrode to be emitted to the outside of the light emitting device LD. In some embodiments, light generated by the light emitting device LD does not pass through the first additional electrode 15 and the second additional electrode and passes through a region except for both ends of the light emitting device LD. ), when emitted to the outside, the first additional electrode 15 and the second additional electrode may include an opaque metal.

In an embodiment of the present invention, the light emitting device LD may further include an insulating layer 14 . However, in some embodiments, the insulating layer 14 may be omitted or provided to cover only a portion of the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .

The insulating layer 14 may prevent an electrical short circuit that may occur when the active layer 12 comes into contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13 . In addition, by forming the insulating layer 14 , surface defects of the light emitting device LD may be minimized, thereby improving lifespan and efficiency. In addition, when the plurality of light emitting devices LD are closely disposed, the insulating layer 14 may prevent an unwanted short circuit between the light emitting devices LD. As long as the active layer 12 can prevent a short circuit with an external conductive material, whether or not the insulating layer 14 is provided is not limited.

As shown in FIGS. 1A and 1B , the insulating film 14 is formed to completely surround the outer circumferential surface of the light emitting stack including the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 . may be provided. For convenience of explanation, FIG. 1A illustrates a state in which a portion of the insulating layer 14 is removed, and the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer included in the actual light emitting device LD. (13) may be surrounded by the insulating layer (14).

In the above-described embodiment, the insulating film 14 has been described in the form of enclosing the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 as a whole, but the present invention is not limited thereto. it is not According to an embodiment, when the light emitting device LD includes the additional electrode 15 , the insulating layer 14 may include a first semiconductor layer 11 , an active layer 12 , and a second insulating layer 14 as shown in FIGS. 2A and 2B . 2 The semiconductor layer 13 and the additional electrode 15 may completely surround the outer peripheral surface of each. In addition, according to another embodiment, the insulating film 14 does not entirely surround the outer circumferential surface of the additional electrode 15 disposed on the second semiconductor layer 13 as shown in FIGS. 3A and 3B or the additional electrode ( 15) may surround only a portion of the outer circumferential surface and not surround the rest of the outer circumferential surface of the additional electrode 15 . However, the insulating layer 14 exposes at least both ends of the light emitting device LD, and for example, the first semiconductor layer 11 together with the additional electrode 15 disposed at one end of the second semiconductor layer 13 . ) can be exposed at one end. In addition, according to an embodiment, the first additional electrode 15 is disposed at the other end (or upper end) of the light emitting device LD, and the second additional electrode 15 is disposed at one end (or lower end) of the light emitting device LD. In this arrangement, the insulating layer 14 may expose at least one region of the first additional electrode 15 and at least one region of the second additional electrode. Alternatively, in another embodiment, the insulating film 14 may not be provided.

According to an embodiment of the present invention, the insulating layer 14 may include a transparent insulating material. For example, the insulating layer 14 may include at least one insulating material selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), and titanium dioxide (TiO _{2 ).} may include, but is not limited thereto, and various materials having insulating properties may be used.

When the insulating layer 14 is provided on the light emitting device LD, it is possible to prevent the active layer 12 from being shorted with driving electrodes (not shown). In addition, by forming the insulating layer 14 , surface defects of the light emitting device LD may be minimized, so that the lifetime and light output efficiency of the light emitting device LD may be improved. In addition, when the plurality of light emitting devices LD are closely disposed, the insulating layer 14 may prevent an unwanted short circuit between the light emitting devices LD.

The above-described light emitting device LD may be used as a light emitting source of various display devices. The light emitting device LD may be manufactured through a surface treatment process. For example, when a plurality of light emitting devices LD are mixed with a fluid solution (or solvent) and supplied to each pixel area (eg, a light emitting area of each pixel or a light emitting area of each sub-pixel), the light emission Each of the light emitting elements LD may be surface-treated so that the elements LD may be uniformly sprayed without agglomeration in the solution.

The light emitting unit (or light emitting device) including the above-described light emitting element LD may be used in various types of electronic devices requiring a light source, including a display device. For example, when a plurality of light emitting devices LD are disposed in a pixel area of each pixel of the display panel, the light emitting devices LD may be used as light sources of each pixel. However, the field of application of the light emitting device LD is not limited to the above-described example. For example, the light emitting device LD may be used in other types of electronic devices that require a light source, such as a lighting device.

Next, a light emitting device LD manufactured by a growth method will be described with reference to FIGS. 4A and 4B .

In the description of the light emitting device LD manufactured by the growth method, different points from the above-described embodiment will be mainly described, and parts not specifically described in the light emitting device LD manufactured by the growth method are described above. In accordance with one embodiment, the same numbers are assigned to components similar and/or identical to those of the above-described embodiment.

4A and 4B , a light emitting device LD according to an embodiment of the present invention includes a first semiconductor layer 11 and a second semiconductor layer 13 , and the first and second semiconductor layers. It may include an active layer 12 interposed between (11, 13). According to an embodiment, the light emitting device LD includes a first semiconductor layer 11 positioned in the center (or the middle) of the light emitting device LD, and an active layer 12 surrounding at least one side of the first semiconductor layer 11 . , a second semiconductor layer 13 surrounding at least one side of the active layer 12 , and a core-shell having an additional electrode 15 surrounding at least one side of the second semiconductor layer 13 . ) may include a light emitting pattern 10 having a structure.

The light emitting device LD may be provided in the shape of a polygonal pyramid extending in one direction. For example, the light emitting device LD may be provided in a hexagonal pyramid shape. If the extending direction of the light emitting device LD is referred to as a length (L) direction, the light emitting device LD may have one end (or lower end) and the other end (or upper end) along the length (L) direction. have. A portion of one of the first and second semiconductor layers 11 and 13 is exposed at one end (or lower end) of the light emitting device LD, and the other end (or upper end of the light emitting device LD) is exposed. end) of the first and second semiconductor layers 11 and 13 , a portion of the remaining semiconductor layer may be exposed. For example, a portion of the first semiconductor layer 11 is exposed at one end (or lower end) of the light emitting device LD, and the second semiconductor layer 11 is exposed at the other end (or upper end) of the light emitting device LD (or upper end). 13) may be exposed. In this case, when the light emitting device LD is applied as a light source of the display device, a portion of the exposed first semiconductor layer 11 is in contact with and exposed to one of the driving electrodes driving the light emitting device LD. A portion of the second semiconductor layer 13 may be in contact with another driving electrode.

According to an embodiment, when the light emitting device LD includes the additional electrode 15 , the additional electrode surrounds at least one side of the second semiconductor layer 13 at the other end (or upper end) of the light emitting device LD. A part of (15) may be exposed. In this case, a portion of the additional electrode 15 exposed when the light emitting element LD is applied as a light source of the display device may contact the other driving electrode to be electrically connected to the one electrode.

In an embodiment of the present invention, the first semiconductor layer 11 may be positioned at a core, that is, a center (or a center) of the light emitting device LD. The light emitting device LD may be provided in a shape corresponding to the shape of the first semiconductor layer 11 . For example, when the first semiconductor layer 11 has a hexagonal pyramid shape, the light emitting device LD and the light emitting pattern 10 may also have a hexagonal pyramid shape.

The active layer 12 may be provided and/or formed in a shape surrounding the outer circumferential surface of the first semiconductor layer 11 in the length L direction of the light emitting device LD. Specifically, the active layer 12 is provided in a form surrounding the remaining region except for the other end disposed on the lower side among both ends of the first semiconductor layer 11 in the length L direction of the light emitting device LD and/or can be formed.

The second semiconductor layer 13 is provided and/or formed to surround the active layer 12 in the length (L) direction of the light emitting device LD, and includes a semiconductor layer of a different type from that of the first semiconductor layer 11 . may include For example, when the first semiconductor layer 11 includes an n-type semiconductor layer, the second semiconductor layer 13 may include a p-type semiconductor layer.

In an embodiment of the present invention, the light emitting device LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13 . The additional electrode 15 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13 or a Schottky contact electrode, but is not limited thereto.

As described above, the light emitting device LD may be configured in a hexagonal pyramid shape having both ends protruding, the first semiconductor layer 11 provided in the center thereof, and surrounding the first semiconductor layer 11 . is a core-shell structure light emitting pattern including an active layer 12, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13 ( 10) can be implemented. The first semiconductor layer 11 is disposed at one end (or lower end) of the light emitting device LD having a hexagonal pyramid shape, and the additional electrode 15 is disposed at the other end (or upper end) of the light emitting device LD. can be

Also, according to an embodiment, the light emitting device LD may further include an insulating layer 14 provided on an outer circumferential surface of the light emitting pattern 10 having a core-shell structure. The insulating layer 14 may include a transparent insulating material.

5 is a view showing a display device according to an embodiment of the present invention, and in particular, the light emitting devices shown in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B. It is a schematic plan view of a display device using any one of the light emitting elements as a light emitting source.

5 , for convenience, the structure of the display device is schematically illustrated with the display area DA in which an image is displayed. However, according to an embodiment, at least one driver (eg, a scan driver and a data driver) and/or a plurality of signal wires not shown may be further disposed in the display device.

1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, and 5 , a display device according to an exemplary embodiment includes a substrate SUB and a substrate SUB. ) provided on the plurality of pixels PXL and each including at least one light emitting element LD, a driver provided on the substrate SUB and driving the pixels PXL, and the pixels PXL; It may include a wiring unit for connecting the driving unit.

Display devices are smartphones, televisions, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbook computers, workstations, servers, PDA, PMP (portable multimedia players), MP3 players, medical devices, The present invention may be applied to any electronic device in which a display surface is applied to at least one surface, such as a camera or a wearable device.

The display device may be classified into a passive matrix type display device and an active matrix type display device according to a driving method of the light emitting element LD. For example, when the display device is implemented as an active matrix type, each of the pixels PXL includes a driving transistor that controls the amount of current supplied to the light emitting device LD, a switching transistor that transmits a data signal to the driving transistor, and the like. can do.

Recently, in terms of resolution, contrast, and operation speed, an active matrix type display device that selectively lights for each pixel (PXL) has become mainstream, but the present invention is not limited thereto, and lighting is performed for each pixel (PXL) group. A passive matrix type display device may also use components (eg, first and second electrodes, etc.) for driving the light emitting device LD.

The substrate SUB may include a display area DA and a non-display area NDA.

In some embodiments, the display area DA may be disposed in a central area of the display device, and the non-display area NDA may be disposed at an edge area of the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and positions thereof may be changed.

The display area DA may be an area in which pixels PXL displaying an image are provided. The non-display area NDA may be an area in which a driver for driving the pixels PXL and a portion of a wiring connecting the pixels PXL and the driver are provided. For convenience of description, although only one pixel PXL is illustrated in FIG. 5 , a plurality of pixels PXL may be substantially disposed in the display area DA of the substrate SUB.

The display area DA may have various shapes. For example, the display area DA may be provided as a closed polygon including straight sides. Also, the display area DA may be provided in a circular shape and/or an elliptical shape including curved sides. In addition, the display area DA may be provided in various shapes, such as a semicircle including straight and curved sides, and a semi-ellipse.

The non-display area NDA may be provided on at least one side of the display area DA. In an embodiment of the present invention, the non-display area NDA may surround a circumference (or an edge) of the display area DA.

In the non-display area NDA, a wiring unit connected to the pixels PXL and a driving unit connected to the wiring unit and driving the pixels PXL may be provided.

The wiring unit may electrically connect the driver and the pixels PXL. The wiring unit provides a signal to each pixel PXL and may be a fan-out line connected to signal lines connected to each pixel PXL, for example, a scan line, a data line, a light emission control line, and the like. In addition, the wiring unit is a fan-out line connected to signal lines connected to each pixel PXL, for example, a control line, a sensing line, etc. in order to compensate for the change in electrical characteristics of each pixel PXL in real time. can

The substrate SUB may include a transparent insulating material to allow light to pass therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

One area on the substrate SUB may serve as the display area DA so that the pixels PXL are disposed, and the remaining area on the substrate SUB may serve as the non-display area NDA. For example, the substrate SUB may include a display area DA including pixel areas in which each pixel PXL is disposed, and a non-display area NDA disposed around the display area DA. have.

Each of the pixels PXL may be provided in the display area DA on the substrate SUB. In an embodiment of the present invention, the pixels PXL may be arranged in the display area DA in a stripe or pentile arrangement structure, but the present invention is not limited thereto.

Each pixel PXL may include at least one light emitting element LD driven by a corresponding scan signal and data signal. The light emitting device LD has a size as small as a micro-scale or nano-scale and may be connected in parallel to adjacent light emitting devices, but the present invention is not limited thereto. The light emitting element LD may constitute a light source of each pixel PXL.

Each pixel PXL includes at least one light source driven by a predetermined signal (eg, a scan signal and a data signal) and/or a predetermined power (eg, a first driving power and a second driving power) can do. For example, each pixel PXL includes the light emitting device LD shown in FIGS. 1A to 4B , for example, at least one ultra-small light emitting device LD having a size as small as a nano-scale to a micro-scale, respectively. may include However, in the exemplary embodiment of the present invention, the type of the light emitting device LD that can be used as a light source of each pixel PXL is not limited thereto.

In one embodiment of the present invention, the color, type, and/or number of the pixels PXL is not particularly limited, and for example, the color of light emitted from each pixel PXL may be variously changed. .

The driver may provide a predetermined signal and a predetermined power to each pixel PXL through the wiring unit, and thus may control driving of the pixel PXL.

The driver includes a scan driver that provides a scan signal to the pixels PXL through a scan line, a light emission driver that provides a light emission control signal to the pixels PXL through an emission control line, and the pixels PXL through a data line. It may include a data driver providing a data signal to the , and a timing controller. The timing controller may control the scan driver, the light emission driver, and the data driver.

6A and 6B are circuit diagrams illustrating electrical connection relationships between components included in one pixel illustrated in FIG. 5 according to various embodiments.

For example, FIGS. 6A and 6B illustrate an electrical connection relationship between components included in a pixel PXL that can be applied to an active display device according to different embodiments. However, the types of components included in the pixel PXL to which the embodiment of the present invention can be applied are not limited thereto.

In FIGS. 6A and 6B , not only components included in each of the pixels illustrated in FIG. 5 , but also regions in which the components are provided are collectively referred to as a pixel PXL. According to an exemplary embodiment, each of the pixels PXL illustrated in FIGS. 6A and 6B may be any one of the pixels PXL included in the display device of FIG. 5 , and the pixels PXL are substantially connected to each other. It may have the same or similar structure.

1A to 4B, 5, 6A, and 6B, one pixel (PXL, hereinafter referred to as a 'pixel') includes a light emitting unit (EMU) that generates light having a luminance corresponding to a data signal can do. Also, the pixel PXL may optionally further include a pixel circuit 144 for driving the light emitting unit EMU.

According to an embodiment, the light emitting unit EMU includes a first power line PL1 to which a voltage of the first driving power VDD is applied and a second power line PL2 to which a voltage of the second driving power VSS is applied. It may include a plurality of light emitting devices LD connected in parallel therebetween. For example, the light emitting unit EMU may have a first electrode EL1 connected to the first driving power VDD via the pixel circuit 144 and the first power line PL1 (or “first alignment electrode”). and the second electrode EL2 or “second alignment electrode” connected to the second driving power source VSS through the second power supply line PL2 and the first and second electrodes EL1 and EL2 may include a plurality of light emitting devices LD connected in parallel in the same direction. In one embodiment of the present invention, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

In one embodiment of the present invention, each of the light emitting elements LD included in the light emitting unit EMU has one end and a second electrode connected to the first driving power VDD through the first electrode EL1 . The other end may be connected to the second driving power VSS through the EL2. The first driving power VDD and the second driving power VSS may have different potentials. For example, the first driving power VDD may be set as a high potential power, and the second driving power VSS may be set as a low potential power. In this case, the potential difference between the first and second driving power sources VDD and VSS may be set to be greater than or equal to the threshold voltage of the light emitting elements LD during the light emission period of the pixel PXL.

As described above, each light emitting element LD connected in parallel in the same direction (for example, forward direction) between the first electrode EL1 and the second electrode EL2 to which voltages of different potentials are respectively supplied is An effective light source can be configured. These effective light sources may be gathered to configure the light emitting unit EMU of the pixel PXL.

The light emitting elements LD of the light emitting unit EMU may emit light with a luminance corresponding to the driving current supplied through the corresponding pixel circuit 144 . For example, during each frame period, the pixel circuit 144 may supply a driving current corresponding to a grayscale value of the corresponding frame data to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU may flow through the light emitting devices LD. Accordingly, the light emitting unit EMU may emit light having a luminance corresponding to the driving current while each light emitting element LD emits light with a luminance corresponding to the current flowing therein.

Meanwhile, in FIGS. 6A to 6B , an embodiment in which both ends of the light emitting elements LD are connected in the same direction between the first and second driving power sources VDD and VSS is illustrated, but the present invention is limited thereto it doesn't happen According to an embodiment, the light emitting unit EMU may further include at least one ineffective light source, for example, a reverse light emitting device (not shown) in addition to the light emitting devices LD constituting each effective light source. Such a reverse light emitting device is connected in parallel between the first and second electrodes EL1 and EL2 together with the light emitting devices LD constituting the effective light sources, in the opposite direction to the light emitting devices LD. It may be connected between the first and second electrodes EL1 and EL2. The reverse light emitting device maintains an inactive state even when a predetermined driving voltage (for example, a forward driving voltage) is applied between the first and second electrodes EL1 and EL2, and accordingly, the reverse light emitting device has Practically no current flows.

The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, when the pixel PXL is disposed in the i (i is a natural number)-th row and j (j is a natural number)-th column of the display area DA, the pixel circuit 144 of the pixel PXL is the display area It may be connected to the i-th scan line Si and the j-th data line Dj of (DA). In some embodiments, the pixel circuit 144 may include first and second transistors T1 and T2 and a storage capacitor Cst. However, the structure of the pixel circuit 144 is not limited to the embodiment illustrated in FIGS. 6A and 6B .

First, referring to FIG. 6A , the pixel circuit 144 may include first and second transistors T1 and T2 and a storage capacitor Cst.

A first terminal of the second transistor T2 (switching transistor) may be connected to the j-th data line Dj, and a second terminal may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 are different terminals, for example, if the first terminal is a source electrode, the second terminal may be a drain electrode. In addition, the gate electrode of the second transistor T2 may be connected to the i-th scan line Si.

The second transistor T2 is turned on when a scan signal of a voltage at which the second transistor T2 can be turned on (eg, a low voltage) is supplied from the i-th scan line Si. Thus, the j-th data line Dj and the first node N1 are electrically connected. At this time, the data signal of the corresponding frame is supplied to the j-th data line Dj, and accordingly, the data signal is transmitted to the first node N1. The data signal transferred to the first node N1 is charged in the storage capacitor Cst.

A first terminal of the first transistor T1 may be connected to the first driving power source VDD, and a second terminal may be electrically connected to the first electrode EL1 of each of the light emitting elements LD. can The gate electrode of the first transistor T1 may be connected to the first node N1 . The first transistor T1 controls the amount of driving current supplied to the light emitting devices LD in response to the voltage of the first node N1 .

One electrode of the storage capacitor Cst may be connected to the first driving power VDD, and the other electrode may be connected to the first node N1 . The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1 and maintains the charged voltage until the data signal of the next frame is supplied.

In each of FIGS. 6A and 6B , a second transistor T2 for transferring a data signal to the inside of the pixel PXL, a storage capacitor Cst for storing the data signal, and a driving current corresponding to the data signal are applied. The pixel circuit 144 including the first transistor T1 for supplying the light emitting devices LD is illustrated.

However, the present invention is not limited thereto, and the structure of the pixel circuit 144 may be variously changed. For example, the pixel circuit 144 adjusts the emission time of the transistor device for compensating the threshold voltage of the first transistor T1 , the transistor device for initializing the first node N1 , and/or the light emitting devices LDs. At least one transistor element, such as a transistor element for controlling, or other circuit elements such as a boosting capacitor for boosting the voltage of the first node N1 may be further included.

Also, although transistors included in the pixel circuit 144, for example, the first and second transistors T1 and T2, are all P-type transistors in FIG. 6A , the present invention is not limited thereto. That is, at least one of the first and second transistors T1 and T2 included in the pixel circuit 144 may be changed to an N-type transistor.

Next, referring to FIGS. 1A to 4B , 5 , and 6B , according to an embodiment of the present invention, the first and second transistors T1 and T2 may be implemented as N-type transistors. The pixel circuit 144 illustrated in FIG. 6B has a configuration and operation similar to that of the pixel circuit 144 of FIG. 6A except for a change in connection positions of some components due to a change in transistor type. Accordingly, a description thereof will be brief.

In an embodiment of the present invention, the pixel circuit 144 illustrated in FIG. 6B may include first and second transistors T1 and T2 formed of N-type transistors and a storage capacitor Cst. When the first and second transistors T1 and T2 are formed of N-type transistors, the light emitting unit is used to stabilize the storage capacitor Cst that charges a voltage corresponding to the data signal supplied to the first node N1. The EMU may be connected between the first driving power VDD and the pixel circuit 144 . However, the present invention is not limited thereto, and according to embodiments, the light emitting unit EMU illustrated in FIG. 6B may be connected between the pixel circuit 144 and the second driving power VSS. In one embodiment of the present invention, the configuration of the pixel circuit 144 is not limited to the embodiment shown in FIGS. 6A and 6B .

In some embodiments, the pixel circuit 144 may be connected to a control line, a sensing line, etc. to compensate for a change in electrical characteristics in real time. In this case, the pixel circuit 144 may include a sensing transistor that is turned on by a control signal supplied to the control line to electrically connect the sensing line and the first transistor T1 . Accordingly, characteristic information of each pixel PXL including the threshold voltage of the first transistor T1 may be extracted through the sensing line, and the extracted characteristic information is used to compensate for characteristic deviation between the pixels PXL. It can be used to convert image data.

6A and 6B illustrate an embodiment in which all of the light emitting elements LD constituting each light emitting unit EMU are connected in parallel, but the present invention is not limited thereto. According to an embodiment, the light emitting unit EMU may be configured to include at least one serial stage including a plurality of light emitting devices LD connected in parallel to each other. That is, the light emitting unit EMU may be configured in a series/parallel mixed structure.

The structure of the pixel PXL applicable to the present invention is not limited to the embodiments illustrated in FIGS. 6A and 6B , and the pixel PXL may have various structures. For example, each pixel PXL may be configured in a passive light emitting display device or the like. In this case, the pixel circuit 144 is omitted, and both ends of the light emitting devices LD included in the light emitting unit EMU have the i-th scan line Si, the j-th data line Dj, and the first driving unit. The first power line PL1 to which the power VDD is applied, the second power line PL2 to which the second driving power VSS is applied, and/or a predetermined control line may be directly connected.

7 is a plan view schematically illustrating one pixel among the pixels shown in FIG. 5 , FIG. 8 is a cross-sectional view taken along line I to I' of FIG. 7 , and FIG. is a cross-sectional view.

The pixel illustrated in FIG. 7 may be the pixel illustrated in FIG. 6A .

In FIG. 7 , illustration of a transistor connected to the light emitting devices and some signal lines connected to the transistor is omitted for convenience.

7 to 9, the structure of one pixel PXL is simplified, such as showing each electrode as a single-layered electrode and each insulating layer as only a single-layered insulating layer, but the present invention is not limited thereto no.

Additionally, in one embodiment of the present invention, "formed and/or provided on the same layer" means formed in the same process, and "formed and/or provided on a different layer" means formed in different processes. can mean

In addition, in an embodiment of the present invention, the term “connection” between two components may mean that both an electrical connection and a physical connection are used inclusively.

In addition, in one embodiment of the present invention, for convenience of explanation, the horizontal direction (or horizontal direction) is the first direction DR1 , the vertical direction (or vertical direction) is the second direction DR2 , and the substrate SUB ) is indicated as a third direction DR3. The first to third directions DR1 , DR2 , and DR3 may refer to directions indicated by the first to third directions DR1 , DR2 , and DR3 , respectively.

1A to 5 , 6A , and 7 to 9 , a display device according to an exemplary embodiment may include a plurality of pixels PXL provided on a substrate SUB.

The substrate SUB may include a transparent insulating material to allow light to pass therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

The flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, and polyetherimide. ), polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose ( It may include at least one of triacetate cellulose) and cellulose acetate propionate.

However, the material constituting the substrate SUB may be variously changed, and may include fiber reinforced plastic (FRP) or the like. The material applied to the substrate SUB may preferably have resistance (or heat resistance) to a high processing temperature during a manufacturing process of the display device.

The substrate SUB may include a display area DA including at least one pixel area PXA in which the pixel PXL is disposed, and a non-display area NDA disposed around the display area DA. have.

The pixels PXL have a plurality of pixel rows extending in the first direction DR1 in the display area DA on the substrate SUB and a second direction different from, for example, crossing the first direction DR1 . A plurality of pixel columns extending to DR2 may be arranged in a matrix form and/or a stripe form, but the present invention is not limited thereto. According to an embodiment, the pixels PXL may be provided in the display area DA on the substrate SUB in various arrangements.

The pixel area PXA in which each pixel PXL is provided (or provided) may include a light emitting area from which light is emitted and a peripheral area adjacent to (or surrounding the periphery of the light emitting area) from the light emitting area. . In an embodiment of the present invention, the peripheral region may include a non-emission region from which light is not emitted.

A wiring portion electrically connected to the pixels PXL may be positioned on the substrate SUB. The wiring unit may include a plurality of signal lines that transmit a predetermined signal (or a predetermined voltage) to each pixel PXL. The signal lines include an i-th scan line Si transmitting a scan signal to each pixel PXL, a j-th data line Dj transmitting a data signal to each pixel PXL, and each pixel PXL. It may include power lines PL1 and PL2 for transferring driving power to the . In some embodiments, the wiring unit may further include a light emission control line that transmits a light emission control signal to each pixel PXL. Also, according to another exemplary embodiment, the wiring unit may further include a sensing line and a control line connected to each pixel PXL.

Each pixel PXL is provided on a substrate SUB and may include a pixel circuit layer PCL including a pixel circuit 144 and a display device layer DPL including a plurality of light emitting devices LD. . The light emitting elements LD may be located in the pixel area PXA of each pixel PXL.

For convenience, the pixel circuit layer PCL will be described first, and then the display device layer DPL will be described.

The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit 144 provided on the buffer layer BFL, and a protective layer PSV provided on the pixel circuit 144 .

The buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit 144 . The buffer layer BFL may be an inorganic insulating layer including an inorganic material. The buffer layer BFL may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (AlOx). The buffer layer BFL may be provided as a single layer, or may be provided as a multilayer of at least a double layer. When the buffer layer BFL is provided as a multilayer, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material and process conditions of the substrate SUB.

The pixel circuit 144 may include at least one transistor T and a storage capacitor Cst. The transistor T may include a driving transistor Tdr for controlling driving currents of the light emitting devices LD and a switching transistor Tsw connected to the driving transistor Tdr. However, the present invention is not limited thereto, and the pixel circuit 144 may further include circuit elements performing other functions in addition to the driving transistor Tdr and the switching transistor Tsw. In the following embodiments, when the driving transistor Tdr and the switching transistor Tsw are collectively named, they will be referred to as a transistor T or transistors T. The driving transistor Tdr may have the same configuration as the first transistor T1 described with reference to FIG. 6A , and the switching transistor Tsw may have the same configuration as the second transistor T2 described with reference to FIG. 6A .

Each of the driving transistor Tdr and the switching transistor Tsw may include a semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be one of the source electrode and the drain electrode, and the second terminal DE may be the other electrode. For example, when the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

The semiconductor pattern SCL may be provided and/or formed on the buffer layer BFL. The semiconductor pattern SCL may include a first contact area contacting the first terminal SE and a second contact area contacting the second terminal DE. A region between the first contact region and the second contact region may be a channel region. This channel region may overlap the gate electrode GE of the corresponding transistor T. The semiconductor pattern SCL may be a semiconductor pattern made of polysilicon, amorphous silicon, an oxide semiconductor, or the like. The channel region is, for example, a semiconductor pattern that is not doped with impurities, and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities.

The gate electrode GE may be provided and/or formed on the gate insulating layer GI to correspond to the channel region of the semiconductor pattern SCL. The gate electrode GE may be provided on the gate insulating layer GI to overlap the channel region of the semiconductor pattern SCL. The gate electrode GE is selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. Double or multi-layer structure of low-resistance materials such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or silver (Ag) to form a single film alone or a mixture thereof or to reduce wiring resistance can be formed with

The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (AlOx). However, the material of the gate insulating layer GI is not limited to the above-described embodiments. In some embodiments, the gate insulating layer GI may be formed of an organic insulating layer including an organic material. The gate insulating layer GI may be provided as a single layer, but may also be provided as a multilayer of at least a double layer.

Each of the first terminal SE and the second terminal DE is provided and/or formed on the second interlayer insulating layer ILD2 , and includes the gate insulating layer GI and the first and second interlayer insulating layers ILD1 . , ILD2 may be in contact with the first contact region and the second contact region of the semiconductor pattern SCL through a contact hole sequentially passing through the . For example, the first terminal SE may contact the first contact area of the semiconductor pattern SCL, and the second terminal DE may contact the second contact area of the semiconductor pattern SCL. Each of the first and second terminals SE and DE may include the same material as the gate electrode GE, or may include one or more materials selected from the exemplified materials of the gate electrode GE.

The first interlayer insulating layer ILD1 may include the same material as the gate insulating layer GI, or may include one or more materials selected from materials exemplified as a constituent material of the gate insulating layer GI.

A second interlayer insulating layer ILD2 may be provided and/or formed on the first interlayer insulating layer ILD1 . The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In some embodiments, the second interlayer insulating layer ILD2 may include the same material as the first interlayer insulating layer ILD1 , but the present invention is not limited thereto. The second interlayer insulating layer ILD2 may be provided as a single layer, or may be provided as a multilayer of at least a double layer.

In the above-described embodiment, the first and second terminals SE and DE of the driving transistor Tdr and the switching transistor Tsw, respectively, are connected to the gate insulating layer GI and the first and second interlayer insulating layers ILD1. , ILD2 has been described as a separate electrode electrically connected to the semiconductor pattern SCL through a contact hole sequentially passing through the electrode, but the present invention is not limited thereto. In some embodiments, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw may be a first contact region adjacent to the channel region of the corresponding semiconductor pattern SCL, and may be connected to the driving transistor Tdr and The second terminal DE of each of the switching transistors Tsw may be a second contact region adjacent to the channel region of the semiconductor pattern SCL. In this case, the second terminal DE of the driving transistor Tdr may be electrically connected to the light emitting elements LD of the corresponding pixel PXL through a separate connection means such as a bridge electrode.

In one embodiment of the present invention, the transistors T included in the pixel circuit 144 may be configured as LTPS (low temperature polysilicon) thin film transistors, but the present invention is not limited thereto. , may be composed of an oxide semiconductor thin film transistor. In addition, although the case where the transistors T are thin film transistors having a top gate structure has been described as an example, the present invention is not limited thereto, and the structures of the transistors T may be variously changed.

The storage capacitor Cst may include a lower electrode LE provided on the gate insulating layer GI and an upper electrode UE provided on the first interlayer insulating layer ILD1 and overlapping the lower electrode LE. can

The lower electrode LE is provided on the same layer as the gate electrode GE of each of the driving transistor Tdr and the switching transistor Tsw and may include the same material. The lower electrode LE may be provided integrally with the gate electrode GE of the driving transistor Tdr. In this case, the lower electrode LE may be regarded as a region of the gate electrode GE of the driving transistor Tdr. In some embodiments, the lower electrode LE may be provided as a separate structure from the gate electrode GE of the driving transistor Tdr. In this case, the lower electrode LE and the gate electrode GE of the driving transistor Tdr may be electrically connected through a separate connection means.

The upper electrode UE may overlap the lower electrode LE and cover the lower electrode LE. The capacitance of the storage capacitor Cst may be increased by increasing the overlapping area of the upper electrode UE and the lower electrode LE. The upper electrode UE may be electrically connected to the first power line PL1 . The storage capacitor Cst may be covered by the second interlayer insulating layer ILD2 .

The pixel circuit layer PCL may include a driving voltage line DVL provided and/or formed on the second interlayer insulating layer ILD2 . The driving voltage line DVL may have the same configuration as the second power line PL2 described with reference to FIG. 6A . The second driving power VSS may be applied to the driving voltage lines DVL and PL2 . The pixel circuit layer PCL may further include a first power line PL1 to which the first driving power VDD is applied. The first power line PL1 may be provided on the same layer as the driving voltage line DVL or may be provided on a different layer from the driving voltage line DVL and PL2 . In the exemplary embodiment of the present invention, it has been described that the driving voltage lines DVL and PL2 are provided on the same layer as the first and second terminals SE and DE of the driving transistor Tdr, but the present invention is limited thereto. it's not going to be In some embodiments, the driving voltage lines DVL and PL2 may be provided on the same layer as any one of the conductive layers included in the pixel circuit layer PCL. That is, the positions of the driving voltage lines DVL and PL2 in the pixel circuit layer PCL may be variously changed.

The first power line PL1 is electrically connected to a part of the display element layer DPL, for example, the first electrode EL1 , and the driving voltage lines DVL and PL2 are a part of the display element layer DPL. In a configuration, for example, it may be electrically connected to the second electrode EL2 . The first power line PL1 and the driving voltage lines DVL and PL2 are connected to the first and second electrodes EL1 and EL1 to align the light emitting devices LD in the pixel area PXA of each of the pixels PXL. An alignment signal (or alignment voltage) may be transmitted to EL2). In addition, each of the first power line PL1 and the driving voltage lines DVL and PL2 transmits the corresponding driving power to each pixel PXL after the light emitting devices LD are aligned to each of the light emitting devices LD. ) can be driven.

Each of the first power line PL1 and the driving voltage lines DVL and PL2 may include a conductive material. For example, each of the first power line PL1 and the driving voltage lines DVL and PL2 may include copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), and aluminum (Al). ), silver (Ag), and alloys thereof alone or a mixture thereof to form a single film or to reduce wiring resistance, molybdenum (Mo), titanium (Ti), copper (Cu), aluminum, which are low-resistance materials It can be formed in a double-layer or multi-layer structure of (Al) or silver (Ag). For example, each of the first power line PL1 and the driving voltage lines DVL and PL2 may be formed of a double layer stacked in the order of titanium (Ti)/copper (Cu).

A passivation layer PSV may be provided and/or formed on the transistors T and the driving voltage lines DVL and PL2 .

The passivation layer PSV may be provided in a form including an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on the inorganic insulating layer. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and aluminum oxide (AlOx). The organic insulating film is, for example, acrylic resin (polyacrylates resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamides resin (polyamides resin), polyimide resin (polyimides rein), unsaturated poly At least one of unsaturated polyesters resin, poly-phenylen ethers resin, poly-phenylene sulfides resin, and benzocyclobutene resin may include

The passivation layer PSV includes a first contact hole CH1 exposing the second terminal DE of the driving transistor Tdr and a second contact hole CH2 exposing a region of the driving voltage lines DVL and PL2. may include.

A display device layer DPL may be provided on the passivation layer PSV.

The display element layer DPL includes a bank BNK, first and second electrodes EL1 and EL2, an intermediate pattern CP, light emitting elements LD, and first and second contact electrodes CNE1 and CNE2. ) may be included. Also, the display device layer DPL may include first to third insulating layers INS1 to INS3 .

The bank BNK may be located in a peripheral area surrounding at least one side of the emission area of the corresponding pixel PXL. The peripheral region may include a non-emissive region from which light is not emitted.

The bank BNK is a structure defining (or partitioning) each pixel PXL and a pixel area PXA or a light emitting area of each of the pixels PXL adjacent thereto, and may be, for example, a pixel defining layer. The bank BNK is configured to include at least one light blocking material and/or a reflective material to prevent a light leakage defect in which light (or light) leaks between each pixel PXL and pixels PXL adjacent thereto. have. According to an embodiment, the bank BNK may include a transparent material (or material). The transparent material may include, for example, polyamides resin, polyimides rein, and the like, but the present invention is not limited thereto. According to another exemplary embodiment, a reflective material layer may be formed on the bank BNK to further improve the efficiency of light emitted from each pixel PXL. The bank BNK may be provided and/or formed on the first insulating layer INS1 .

The first electrode EL1 may be electrically connected to a part, for example, the driving transistor Tdr, included in the pixel circuit layer PCL of the corresponding pixel PXL through the first contact hole CH1 . The second electrode EL2 may be electrically connected to some components included in the pixel circuit layer PCL of the corresponding pixel PXL, for example, the driving voltage lines DVL and PL2 through the second contact hole CH2. have.

Each of the first and second electrodes EL1 and EL2 is provided in the pixel area PXA of each of the pixels PXL and may extend in the second direction DR2 . The first electrode EL1 and the second electrode EL2 may be provided on the same surface, for example, on one surface (or upper surface) of the passivation layer PSV, and may be spaced apart from each other in the first direction DR1 . .

Each of the first and second electrodes EL1 and EL2 may be made of a material having a constant reflectance to allow light emitted from each of the light emitting elements LD to travel in the image display direction of the display device. Each of the first and second electrodes EL1 and EL2 may be formed of a conductive material (or material) having a constant reflectance. The conductive material (or material) may include an opaque metal advantageous for reflecting light emitted from the light emitting elements LD in the image display direction of the display device. As the opaque metal, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium ( Ir), chromium (Cr), titanium (Ti), and a metal such as alloys thereof may be included. According to an embodiment, each of the first and second electrodes EL1 and EL2 may include a transparent conductive material (or material). Examples of the transparent conductive material include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO, zinc oxide), indium tin zinc oxide (ITZO), and A conductive oxide such as a conductive oxide, a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT) may be included. When each of the first and second electrodes EL1 and EL2 includes a transparent conductive material, a separate conductive material made of an opaque metal for reflecting the light emitted from the light emitting elements LD in the image display direction of the display device Additional layers may be included. However, the material of each of the first and second electrodes EL1 and EL2 is not limited to the above-described materials.

In addition, each of the first and second electrodes EL1 and EL2 may be provided and/or formed as a single layer, but the present invention is not limited thereto. According to an embodiment, each of the first and second electrodes EL1 and EL2 may be provided and/or formed as a multilayer in which at least two or more of metals, alloys, conductive oxides, and conductive polymers are stacked. . Each of the first and second electrodes EL1 and EL2 is formed of at least a double layer in order to minimize distortion due to signal delay when transmitting a signal (or voltage) to both ends of each of the light emitting devices LD. could be For example, each of the first and second electrodes EL1 and EL2 may be formed of a multilayer sequentially stacked in the order of indium tin oxide (ITO)/silver (Ag)/indium tin oxide (ITO).

In an embodiment of the present invention, the first electrode EL1 and the second electrode EL2 receive an alignment signal (or an alignment voltage) to align the light emitting elements LD by receiving an alignment electrode (or alignment line) can function as For example, the first electrode EL1 may receive a first alignment signal (or a first alignment voltage) from the first power line PL1 to function as a first alignment electrode (or a first alignment line), The second electrode EL2 may receive a second alignment signal (or a second alignment voltage) from the driving voltage lines DVL and PL2 to function as a second alignment electrode (or a second alignment line). Here, the first and second alignment signals (or alignment voltages) may have a voltage difference between the first and second electrodes EL1 and EL2 to which the light emitting elements LD can be aligned and/or Alternatively, they may be signals having a phase difference. At least one alignment signal (or alignment voltage) of the first and second alignment signals (or alignment voltages) may be an AC signal (or voltage), but the present invention is not limited thereto.

After the light emitting devices LD are aligned in the pixel area PXA of each pixel PXL, pixels adjacent to each other in the second direction DR2 to drive each pixel PXL individually (or independently). A portion of the first electrode EL1 positioned between the PXL may be removed. In addition, after the light emitting elements LD are aligned in the pixel area PXA, the first electrode EL1 and the second electrode EL2 may function as driving electrodes for driving the light emitting elements LD. can In one embodiment of the present invention, the first electrode EL1 may be an anode electrode and the second electrode EL2 may be a cathode electrode.

The intermediate pattern CP may be provided between the first electrode EL1 and the second electrode EL2 when viewed in a plan view. The first side surface FS of the intermediate pattern CP may be located adjacent to the first electrode EL1 , and the second side surface SS of the intermediate pattern CP may be located adjacent to the second electrode EL2 . have. The first side surface FS of the intermediate pattern CP may be spaced apart from the first electrode EL1 with a first gap GAP1 in the first direction DR1 , and the second side surface of the intermediate pattern CP The SS may be spaced apart from the second electrode EL2 with a second gap GAP2 in the first direction DR1 .

In one embodiment of the present invention, the first gap GAP1 between the first electrode EL1 and the first side surface FS of the intermediate pattern CP is the second electrode EL2 and the intermediate pattern CP. It may be the same as the second gap GAP2 between the second side surfaces SS of the . For example, the first gap GAP1 and the second gap GAP2 may be smaller than the length L of each light emitting device LD parallel to the extending direction of the light emitting devices LD. For example, when the length L of each of the light emitting devices LD is 3.5 μm, the first gap GAP1 and the second gap GAP2 may be smaller than 3.5 μm. However, the present invention is not limited thereto, and according to embodiments, the first gap GAP1 and the second gap GAP2 may be the same as the length L of each of the light emitting devices LD.

The intermediate pattern CP may be provided on the same layer as the first and second electrodes EL1 and EL2 . For example, the intermediate pattern CP may be provided and/or formed on one surface (or an upper surface) of the passivation layer PSV. In one embodiment of the present invention, the intermediate pattern CP may be made of a material having a constant reflectance so that light emitted to the rear surface of each of the light emitting elements LD proceeds in the image display direction of the display device. The intermediate pattern CP may include the same material as the first and second electrodes EL1 and EL2 . For example, the intermediate pattern CP may include a material having high reflectance, such as aluminum (Al) or silver (Ag).

The width W of the intermediate pattern CP in the first direction DR1 reflects light emitted from each light emitting element LD to the pixel circuit layer PCL in the image display direction (or the front direction) of the display device. In order to achieve this, the length L of each light emitting device LD parallel to the extending direction of each light emitting device LD may be designed. For example, when the length L of each of the light emitting devices LD is 3.5 μm, the width W of the intermediate pattern CP in the first direction DR1 may be designed to be greater than 3.5 μm. However, the present invention is not limited thereto, and according to embodiments, the width W of the intermediate pattern CP in the first direction DR1 is the same as the length L of each of the light emitting elements LD. may be designed.

The intermediate pattern CP may have a bar shape extending in the second direction DR2 when viewed in a plan view. Also, when viewed in a plan view, the intermediate pattern CP may overlap the light emitting devices LD. The shape of the intermediate pattern CP may be variously changed within a range in which the intermediate pattern CP overlaps the light emitting devices LD.

Each of the light emitting devices LD may be a light emitting device using a material having an inorganic crystal structure, for example, having a size as small as a nano-scale to a micro-scale. For example, each of the light emitting devices LD may be a micro light emitting device manufactured by an etching method or a micro light emitting device manufactured by a growth method.

At least two to tens of light emitting devices LD may be arranged and/or provided in the pixel area PXA of each pixel PXL, but the number of the light emitting devices LD is not limited thereto. . According to an embodiment, the number of light emitting devices LD arranged and/or provided in the pixel area PXA may be variously changed.

Each of the light emitting devices LD may emit any one of color light and/or white light. Each of the light emitting elements LD is formed on the intermediate pattern CP between the first electrode E1 and the second electrode EL2 so that the extension direction (or the length L direction) is parallel to the first direction DR1 . can be sorted. The light emitting elements LD may be provided in the form of being sprayed in a solution and may be injected into the pixel area PXA of each pixel PXL.

The light emitting devices LD may be input to the pixel area PXA of each pixel PXL through an inkjet printing method, a slit coating method, or other various methods. For example, the light emitting devices LD may be mixed with a volatile solvent and supplied to the pixel area PXA through an inkjet printing method or a slit coating method. At this time, when an alignment signal (or alignment voltage) corresponding to each of the first and second electrodes EL1 and EL2 provided in the pixel area PXA is applied, the first side surface FS of the intermediate pattern CP and An electric field may be formed between the second side surfaces SS of the intermediate pattern CP. Accordingly, the light emitting devices LD may be aligned between the first side surface FS of the intermediate pattern CP and the second side surface SS of the intermediate pattern CP.

After the light emitting devices LD are aligned, the solvent is evaporated or removed in other ways to finally arrange and/or provide the light emitting devices LD in the pixel area PXA of each pixel PXL. can

One end (eg, a p-type semiconductor layer) of each of the light emitting elements LD may be directly connected to the first electrode EL1 or connected to the first electrode EL1 through the first contact electrode CNE1 . can In addition, the other end (eg, an n-type semiconductor layer) of each of the light emitting elements LD is directly connected to the second electrode EL2 or connected to the second electrode EL2 through the second contact electrode CNE2 . can be connected

When the light emitting devices LD are aligned in the pixel area PXA of each of the pixels PXL, a corresponding alignment signal (or alignment voltage) is transmitted to each of the first and second electrodes EL1 and EL2 . can For example, a first alignment signal having a negative polarity may be transmitted to the first electrode EL1 , and a second alignment signal having a positive polarity may be transmitted to the second electrode EL. In this case, a charge having a positive polarity opposite to the negative polarity may be induced to the first side surface FS of the intermediate pattern CP adjacent to the first electrode EL1 . In addition, charges having a negative polarity that are opposite to the positive polarity may be induced to the second side surface SS of the intermediate pattern CP adjacent to the second electrode EL2 . Accordingly, an electric field may be formed between the first side surface FS of the intermediate pattern CP and the second side surface SS of the intermediate pattern CP.

As described above, when an alignment signal (or alignment voltage) corresponding to each of the first and second electrodes EL1 and EL2 is transmitted, an intermediate position between the first electrode EL1 and the second electrode EL2 is transmitted. An induced charge may be formed in the pattern CP to form an electric field between the first side surface FS of the intermediate pattern CP and the second side surface SS of the intermediate pattern CP. The light emitting devices LD may be aligned on the intermediate pattern CP positioned between the first electrode EL1 and the second electrode EL2 by the electric field. When viewed in plan and cross-section, the light emitting devices LD may overlap the intermediate pattern CP.

The above-described light emitting devices LD may be provided and/or formed on the first insulating layer INS1 on the intermediate pattern CP.

The first insulating layer INS1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. In an embodiment of the present invention, the first insulating layer INS1 may be formed of an inorganic insulating layer advantageous for protecting the light emitting devices LD from the pixel circuit layer PCL of each pixel PXL. For example, the first insulating layer INS1 may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (AlOx). The invention is not limited thereto. In some embodiments, the first insulating layer INS1 may be formed of an organic insulating layer advantageous for planarizing the supporting surfaces of the light emitting devices LD.

The first insulating layer INS1 may include a first opening OPN1 exposing a region of the first electrode EL1 and a second opening OPN2 exposing a region of the second electrode EL2 . . The first electrode EL1 may be directly connected to and connected to the first contact electrode CNE1 through the first opening OPN1 , and the second electrode EL2 may be connected to the second contact electrode CNE1 through the second opening OPN2 . CNE2) can be directly contacted and connected.

The first insulating layer INS1 may cover regions other than one region of the first electrode EL1 and one region of the second electrode EL2 . In an exemplary embodiment, the first insulating layer INS1 may be provided on the intermediate pattern CP to completely cover the intermediate pattern CP.

The intermediate pattern CP may be completely covered by the first insulating layer INS1 to be electrically insulated from components adjacent to the intermediate pattern CP. For example, the intermediate pattern CP may be covered by the first insulating layer INS1 to be electrically insulated from each of the first and second electrodes EL1 and EL2 adjacent in the first direction DR1 . In addition, the intermediate pattern CP is covered by the first insulating layer INS1 and the first and second contact electrodes CNE1 and CNE2 are positioned on the first insulating layer INS1 in the third direction DR3 . may be electrically isolated from each other. In an embodiment of the present invention, the intermediate pattern CP is covered by the first insulating layer INS1 to adjacent electrodes, for example, the first and second electrodes EL1 and EL2 and the first and second electrodes EL1 and EL2. It may be isolated from the two contact electrodes CNE1 and CNE2.

After the light emitting devices LD are aligned in the pixel area PXA of each of the pixels PXL, the intermediate pattern CP is covered by the first insulating layer INS1 and is applied to each of the adjacent electrodes. It may not be affected by the signal (or voltage). The intermediate pattern CP emits light from the active layer 12 of each of the light emitting elements LD and proceeds to the first insulating layer INS1 (or proceeds in a downward direction of each of the light emitting elements LD). It can be reflected in the image display direction (or front direction) of a display device. In other words, the intermediate pattern CP is light emitted from each of the light emitting elements LD and traveling in a rear direction (eg, an image non-display direction) of the display device opposite to the image display direction (or front direction). can be reflected in the image display direction. Accordingly, light emitted from each of the light emitting elements LD may proceed in the image display direction of the display device without loss. As a result, light output efficiency of each pixel PXL may be improved by minimizing loss of light emitted from each of the light emitting devices LD.

In an embodiment of the present invention, the intermediate pattern CP reflects light emitted from the light emitting devices LD together with the first and second electrodes EL1 and EL2 in the image display direction of the display device. It can function as an absence.

A second insulating layer INS2 may be provided and/or formed on each of the light emitting devices LD. The second insulating layer INS2 is provided and/or formed on each of the light emitting devices LD to cover a portion of the upper surface of each of the light emitting devices LD, and externally both ends of each of the light emitting devices LD can be exposed as The second insulating layer INS2 may be formed as an independent insulating pattern in the pixel area PXA of each of the pixels PXL, but the present invention is not limited thereto.

The second insulating layer INS2 may be configured as a single layer or a multilayer, and may include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The second insulating layer INS2 may further fix each of the light emitting devices LD aligned (or disposed) in the pixel area PXA of each of the pixels PXL. The second insulating layer INS2 may include an inorganic insulating layer advantageous for protecting the active layer 12 of each of the light emitting devices LD from external oxygen and moisture. However, the present invention is not limited thereto. In some embodiments, the second insulating layer INS2 may include an organic insulating layer including an organic material according to design conditions of a display device to which the light emitting elements LD are applied.

The second insulating layer INS2 may be formed on the light emitting devices LD to prevent the active layer 12 of each of the light emitting devices LD from coming into contact with an external conductive material. The second insulating layer INS2 may cover only a portion of a surface (or outer circumferential surface) of each of the light emitting devices LD and may expose both ends of each of the light emitting devices LD to the outside.

The first contact electrode CNE1 electrically stably connects one end of each of the first electrode EL1 and the light emitting devices LD, and the second contact electrode CNE2 includes the second electrode EL2 and the light emitting device. The other end of each of the LDs may be electrically stably connected.

The first contact electrode CNE1 may be provided and/or formed on the first electrode EL1 . The first contact electrode CNE1 may directly contact the first electrode EL1 to be connected to the first electrode EL1 . According to an embodiment, when a capping layer (not shown) is disposed on the first electrode EL1 , the first contact electrode CNE1 is disposed on the capping layer and passes through the capping layer to the first electrode EL1 . ) can be associated with Here, the capping layer protects the first electrode EL1 from defects occurring during the manufacturing process of the display device, and further strengthens the adhesive force between the first electrode EL1 and the pixel circuit layer PCL positioned thereunder. can The capping layer is a transparent conductive layer such as indium zinc oxide (IZO) to minimize loss of light emitted from each of the light emitting elements LD and reflected by the first electrode EL1 in the image display direction of the display device. material may be included.

Also, the first contact electrode CNE1 may be provided and/or formed on one end of each of the light emitting devices LD to be connected to one end of each of the light emitting devices LD. Accordingly, the first electrode EL1 and one end of each of the light emitting devices LD may be connected to each other through the first contact electrode CNE1 .

The second contact electrode CNE2 may be provided and/or formed on the second electrode EL2 . The second contact electrode CNE2 may directly contact the second electrode EL2 to be connected to the second electrode EL2 . In some embodiments, when the capping layer is disposed on the second electrode EL2 , the second contact electrode CNE2 may be disposed on the capping layer and connected to the second electrode EL2 through the capping layer. have. In addition, the second contact electrode CNE2 may be provided and/or formed on the other end of each of the light emitting elements LD to be connected to the other end of each of the light emitting elements LD. Accordingly, the second electrode EL2 and the other end of each of the light emitting devices LD may be connected to each other through the second contact electrode CNE2 .

When viewed in a plan view, the first contact electrode CNE1 may overlap at least one region (eg, the first side surface FS) of the intermediate pattern CP, and the second contact electrode CNE2 may include the intermediate pattern CP. It may overlap with at least another area (eg, the second side surface SS) of the CP. The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed to be spaced apart from each other on the same surface. The first contact electrode CNE1 and the second contact electrode CNE2 are provided on the same layer and may be formed through the same process, but the present invention is not limited thereto. In some embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may be provided on different layers and may be formed through different processes. In one embodiment of the present invention, the first contact electrode CNE1 and the second contact electrode CNE2 are provided on the second insulating layer INS2 to form a first direction DR1 on the second insulating layer INS2 . ) can be spaced apart from each other at regular intervals.

The first and second contact electrodes CNE1 and CNE2 lose light emitted from each of the light emitting devices LD and reflected by the first and second electrodes EL1 and EL2 and the intermediate pattern CP. It may be composed of various transparent conductive materials (or materials) in order to proceed in the image display direction of the display device without the need to. For example, the first and second contact electrodes CNE1 and CNE2 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin oxide. It includes at least one of various transparent conductive materials including indium tin zinc oxide (ITZO), and may be substantially transparent or semi-transparent to satisfy a predetermined light transmittance (or transmittance). However, materials of the first and second contact electrodes CNE1 and CNE2 are not limited to the above-described embodiment. According to an embodiment, the first and second contact electrodes CNE1 and CNE2 may be formed of various opaque conductive materials. The first and second contact electrodes CNE1 and CNE2 may be formed of a single layer or a multilayer.

When viewed in a plan view, each of the first and second contact electrodes CNE1 and CNE2 may have a bar shape extending along the second direction DR2, but the present invention is not limited thereto. According to an embodiment, the shapes of the first and second contact electrodes CNE1 and CNE2 may be variously changed within a range electrically stably connected to each of the light emitting devices LD. Also, the shapes of the first and second contact electrodes CNE1 and CNE2 may be variously changed in consideration of a connection relationship with electrodes disposed thereunder.

A third insulating layer INS3 may be provided and/or formed on the first and second contact electrodes CNE1 and CNE2 . The third insulating layer INS3 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the third insulating layer INS3 may have a structure in which at least one inorganic insulating layer or at least one organic insulating layer is alternately stacked. The third insulating layer INS3 may be an encapsulation layer that completely covers the display element layer DPL and blocks moisture or moisture from flowing into the display element layer DPL including the light emitting elements LD.

According to the above-described exemplary embodiment, the intermediate pattern CP is disposed between the protective layer PSV and the first insulating layer INS1 between the first electrode EL1 and the second electrode EL2, and the intermediate pattern The light emitting devices LD may be aligned on the first insulating layer INS1 on the intermediate pattern CP due to the induced charge formed in the CP. As the intermediate pattern CP is disposed under the light emitting devices LD, the light emitting devices LD emit light and proceed in a downward direction of the light emitting devices LD (or an image non-display direction of the display device). The generated light may be reflected in the image display direction of the display device by the intermediate pattern CP.

Accordingly, among the light emitted from the light emitting devices LD, light traveling in the downward direction of the light emitting devices LD is reflected by the intermediate pattern CP in the image display direction of the display device, so that the pixels PXL The light output efficiency of each of the pixels PXL may be further improved by increasing the amount (or intensity) of light finally emitted from each.

10 is a plan view schematically illustrating a pixel according to another embodiment of the present invention, FIG. 11 is a cross-sectional view taken along line III to Ⅲ' of FIG. 10, and FIG. 12 is a cross-sectional view taken along line IV to IV' of FIG. , and FIG. 13 is a cross-sectional view corresponding to the line IV to IV' of FIG. 10 as an implementation of the first bank pattern shown in FIG. 12 according to another embodiment, and FIG. 14 is the second contact electrode shown in FIG. It is implemented according to another embodiment and is a cross-sectional view corresponding to line IV to IV' of FIG. 10 .

With respect to the embodiment of FIGS. 10 to 14 , differences from the above-described embodiment will be mainly described in order to avoid overlapping description. Parts not specifically described in the present invention are in accordance with the above-described embodiment, and the same numbers indicate the same components and similar numbers indicate similar components.

1A to 5 , 6A , and 10 to 14 , the substrate SUB, the pixel circuit layer PCL, and the display element layer DPL are disposed in the pixel area PXA of each pixel PXL. This can be placed

In an embodiment of the present invention, the display element layer DPL includes first and second bank patterns BNK1 and BNK2, first and second electrodes EL1 and EL2, an intermediate pattern CP, and light emission. It may include the elements LD, first and second contact electrodes CNE1 and CNE2 , and first to third insulating layers INS1 to INS3 .

The first bank pattern BNK1 may be located in a light emitting area in which light is emitted from the pixel area PXA of each of the pixels PXL. The first bank pattern BNK1 changes the surface profile (or shape) of each of the first and second electrodes EL1 and EL2 to guide the light emitted from the light emitting elements LD in the image display direction of the display device. In order to do this, it may be a support member supporting each of the first and second electrodes EL1 and EL2 .

The first bank pattern BNK1 may be provided and/or formed between the passivation layer PSV and a corresponding electrode in the emission area of the corresponding pixel PXL. For example, the first bank pattern BNK1 may be provided and/or formed between the passivation layer PSV and the first electrode EL1 and between the passivation layer PSV and the second electrode EL2 , respectively.

The first bank pattern BNK1 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In some embodiments, the first bank pattern BNK1 may include a single-layered organic insulating layer and/or a single-layered inorganic insulating layer, but the present invention is not limited thereto. According to an exemplary embodiment, the first bank pattern BNK1 may be provided in the form of a multilayer in which at least one organic insulating layer and at least one inorganic insulating layer are stacked. However, the material of the first bank pattern BNK1 is not limited to the above-described embodiment, and according to the embodiment, the first bank pattern BNK1 may include a conductive material.

The first bank pattern BNK1 may have a cross section of a trapezoidal shape in which the width becomes narrower from one surface (eg, the upper surface) of the passivation layer PSV toward the upper side in the third direction DR3. This is not limited thereto. According to an exemplary embodiment, as shown in FIG. 13 , the first bank pattern BNK1 has a semi-elliptical shape, a semi-circle in which the width becomes narrower toward the top in the third direction DR3 from one surface of the passivation layer PSV. It may include a curved surface having a cross section such as a shape (or a hemispherical shape). When viewed in cross section, the shape of the first bank pattern BNK1 is not limited to the above-described embodiments and may be variously changed within a range capable of improving the efficiency of light emitted from each of the light emitting devices LD. have. The first bank patterns BNK1 adjacent in the first direction DR1 may be disposed on the same surface of the passivation layer PSV, and may have the same height (or thickness) in the third direction DR3 . .

The first bank pattern BNK1 may have a bar shape extending along the second direction DR2 when viewed in a plan view, but the present invention is not limited thereto. According to an embodiment, the shape of the first bank pattern BNK1 may be variously changed.

The second bank pattern BNK2 may be provided and/or formed in a peripheral area of the pixel area PXA of each pixel PXL. The second bank pattern BNK2 may have the same configuration as the bank BNK described with reference to FIGS. 7 to 9 . Accordingly, a description of the second bank pattern BNK2 will be omitted.

Each of the first and second electrodes EL1 and EL2 may be provided and/or formed on the first bank pattern BNK1 . For example, each of the first and second electrodes EL1 and EL2 may be provided and/or formed on one surface (eg, an upper surface) of the first bank pattern BNK1 .

The intermediate pattern CP may be provided between the first electrode EL1 and the second electrode EL2 when viewed in a plan view. In addition, the intermediate pattern CP includes the passivation layer PSV and the first insulating layer INS1 of the pixel circuit layer PCL when viewed from a cross-section (or viewed in the third direction DR3 of the substrate SUB). may be provided in between.

The first side surface FS of the intermediate pattern CP may be located adjacent to the first electrode EL1 , and the second side surface SS of the intermediate pattern CP may be located adjacent to the second electrode EL2 . have. The first side surface FS of the intermediate pattern CP may be spaced apart from the first electrode EL1 with a first gap GAP1 in the first direction DR1 , and the second side surface of the intermediate pattern CP The SS may be spaced apart from the second electrode EL2 with a second gap GAP2 in the first direction DR1 .

The intermediate pattern CP is provided on the same layer as the first and second electrodes EL1 and EL2 and may be formed by the same process. The intermediate pattern CP and the first and second electrodes EL1 and EL2 may be formed of a material having a constant reflectance so that light emitted from the light emitting devices LD may travel in an image display direction of the display device. .

The first gap GAP1 between the first electrode EL1 and the first side surface FS of the intermediate pattern CP is a first bank pattern BNK1 below the first electrode EL1, hereinafter referred to as a 'first-1-1 bank. pattern'). The second gap GAP2 between the second electrode EL2 and the second side surface SS of the intermediate pattern CP is a first bank pattern BNK1 below the second electrode EL2, hereinafter referred to as a 'second bank' pattern').

In an embodiment of the present invention, one side FS of the first electrode EL1 and the intermediate pattern CP is disposed at a first interval ( ) in the first direction DR1 on the 1-1 bank pattern BNK1 . GAP1) can be separated. The second electrode EL2 and the other side SS of the intermediate pattern CP may be spaced apart from each other with a second gap GAP2 in the first direction DR1 on the 1-2 bank pattern BNK1 .

The first side surface FS of the intermediate pattern CP may overlap the 1-1 bank pattern BNK1, and the second side surface SS of the intermediate pattern CP may have the 1-2 bank pattern. (BNK1) can be nested. The first side surface FS of the intermediate pattern CP is provided and/or formed on one side surface of the 1-1 bank pattern BNK1 to correspond to the shape of one side surface of the 1-1 bank pattern BNK1. It may have a surface profile. For example, as shown in FIG. 11 , when one side surface of the 1-1 bank pattern BNK1 has a predetermined slope, the first side surface FS of the intermediate pattern CP also has a surface profile corresponding to the slope. can have When one side surface of the 1-2-th bank pattern BNK1 has a predetermined inclination, the second side surface SS of the intermediate pattern CP may also have a surface profile corresponding to the inclination.

As described above, since each of the first side surface FS and the second side surface SS of the intermediate pattern CP has a surface profile corresponding to the shape of the first bank pattern BNK1 located thereunder, the light emitting device Light emitted from each of the LDs may be reflected by each of the first side surface FS and the second side surface SS of the intermediate pattern CP to further progress in the image display direction of the display device. In one embodiment of the present invention, the intermediate pattern CP is a direction in which light emitted from the light emitting devices LD together with the first bank pattern BNK1 and the first and second electrodes EL1 and EL2 is desired. may function as a reflective member to improve the light efficiency of the display device.

The first insulating layer INS1 may be provided and/or formed on the protective layer PSV provided with the first and second electrodes EL1 and EL2 and the intermediate pattern CP. The first insulating layer INS1 may cover regions other than one region of each of the first and second electrodes EL1 and EL2 . As the intermediate pattern CP is covered by the first insulating layer INS1 , the intermediate pattern CP includes the first electrode EL1 , the second electrode EL2 , the first contact electrode CNE1 , and the second Each of the contact electrodes CNE2 may be electrically insulated.

The first electrode EL1 and the first contact electrode CNE1 may be directly connected to each other through the first opening OPN1 of the first insulating layer INS1 , and the second opening OPN2 of the first insulating layer INS2 . Thus, the second electrode EL2 and the second contact electrode CNE2 may be directly connected.

The first contact electrode CNE1 and the second contact electrode CNE2 may be provided on the same layer and formed through the same process. However, the present invention is not limited thereto, and according to embodiments, the first and second contact electrodes CNE1 and CNE2 may be provided on different layers and formed through different processes. When the first contact electrode CNE1 and the second contact electrode CNE2 are provided on different layers and formed through different processes, as shown in FIG. 14 , the first contact electrode CNE1 and the second contact electrode CNE2 . ) may be provided and/or formed with an auxiliary insulating layer AUINS. The auxiliary insulating layer AUINS includes the same material as the first insulating layer INS1 described with reference to FIGS. 7 to 9 , or includes one or more materials selected from the materials exemplified as constituent materials of the first insulating layer INS1 . may include For example, the auxiliary insulating layer AUINS may be an inorganic insulating layer including an inorganic material. The inorganic insulating layer may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (AlOx).

According to the above-described exemplary embodiment, the intermediate pattern CP is disposed on the protective layer PSV between the first electrode EL1 and the second electrode EL2, and the charge induced in the intermediate pattern CP is applied. The light emitting devices LD may be aligned on the first insulating layer INS1 on the intermediate pattern CP due to the electric field formed by the electric field.

When a driving current flows from the first power line PL1 to the driving voltage lines DVL and PL2 by the driving transistor Tdr in each pixel PXL and light is emitted from the light emitting devices LD, the middle The pattern CP, together with the first and second electrodes EL1 and EL2 , may reflect light emitted radially (or radially) from the light emitting elements LD in an image display direction of the display device. In addition, the intermediate pattern CP may reflect light emitted from the light emitting elements LD and traveling downwards of the light emitting elements LD in the image display direction of the display device.

Accordingly, among the light emitted from the light emitting devices LD, light traveling in the downward direction of the light emitting devices LD is reflected by the intermediate pattern CP in the image display direction of the display device, so that the pixels PXL Each light output efficiency may be improved.

15 is a plan view schematically illustrating a pixel according to another embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along line V to V' of FIG. 15 .

The pixels illustrated in FIGS. 15 and 16 are illustrated in FIGS. 10 to 16 , except that first and second dummy patterns DP1 and DP2 are additionally disposed in the pixel area PXA of each pixel PXL. It may have a configuration substantially the same as or similar to the pixel of 14 .

Accordingly, in relation to the pixels of FIGS. 15 and 16 , differences from the above-described exemplary embodiment will be mainly described in order to avoid overlapping descriptions.

1A to 5 , 15 , and 16 , a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL are disposed in the pixel area PXA of each pixel PXL can be

In an embodiment of the present invention, the display element layer DPL includes first and second bank patterns BNK1 and BNK2, first and second electrodes EL1 and EL2, an intermediate pattern CP, and light emission. to include the elements LD, first and second contact electrodes CNE1 and CNE2, first to third insulating layers INS1 to INS3, and first and second dummy patterns DP1 and DP2. can

The first dummy pattern DP1 may be spaced apart from the first electrode EL1 in the first direction DR1 . When viewed in a plan view, the first electrode EL1 may be disposed between the first dummy pattern DP1 and the intermediate pattern CP. The middle pattern CP is positioned adjacent to one side (eg, a right side on a plane) of the first electrode EL1 , and the first dummy pattern DP1 is located on the other side (eg, a flat surface) of the first electrode EL1 . It may be located adjacent to the left side).

The second dummy pattern DP2 may be spaced apart from the second electrode EL2 in the first direction DR1 . When viewed in a plan view, the second electrode EL2 may be disposed between the second dummy pattern DP2 and the intermediate pattern CP. The middle pattern CP is located adjacent to one side (eg, a left side on a plane) of the second electrode EL2 and the second dummy pattern DP2 is located on the other side (eg, a left side in a plane) of the second electrode EL2. It may be located adjacent to the right side on the plane.

In one embodiment of the present invention, the first and second dummy patterns DP1 and DP2, the first and second electrodes EL1 and EL2, and the intermediate pattern CP are provided on the same layer, It can be formed by a process. Also, the first and second dummy patterns DP1 and DP2, the first and second electrodes EL1 and EL2, and the intermediate pattern CP may include the same material. For example, the first and second dummy patterns DP1 and DP2, the first and second electrodes EL1 and EL2, and the intermediate pattern CP may include an opaque metal made of a material having a constant reflectance. . Examples of opaque metals include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), It may include a metal such as chromium (Cr), titanium (Ti), or an alloy thereof.

The first dummy pattern DP1 is provided on the first bank pattern BNK1 (hereinafter referred to as the '1-1 bank pattern') positioned below the first electrode EL1 to provide the 1-1 bank pattern BNK1. can be overlapped with In addition, at least one region (eg, the first side surface FS) of the intermediate pattern CP is provided on the 1-1 bank pattern BNK1 to overlap the 1-1 bank pattern BNK1. can The first electrode EL1 and the intermediate pattern CP may be spaced apart from each other with a first gap GAP1 on the first-first bank pattern BNK1. Also, the first electrode EL1 and the first dummy pattern DP1 may be spaced apart from each other at a predetermined distance on the 1-1 bank pattern BNK1. On the 1-1 bank pattern BNK1, the first electrode EL1 and the first dummy pattern DP1 and between the first electrode EL1 and the intermediate pattern CP may have the same distance, The present invention is not limited thereto. According to an exemplary embodiment, on the 1-1 bank pattern BNK1 , a gap is different between the first electrode EL1 and the first dummy pattern DP1 and between the first electrode EL1 and the intermediate pattern CP may have

The second dummy pattern DP2 is provided on the first bank pattern BNK1 (hereinafter referred to as 'the 1-2 bank pattern') positioned under the second electrode EL2 to provide the 1-2 bank pattern BNK1 . can be overlapped with In addition, at least another area (eg, the second side surface SS) of the intermediate pattern CP is provided on the 1-2 bank pattern BNK1 to overlap the 1-2 bank pattern BNK1. can The second electrode EL2 and the intermediate pattern CP may be spaced apart from each other with a second gap GAP2 on the 1-2 first bank pattern BNK1 . Also, the second electrode EL2 and the second dummy pattern DP2 may be spaced apart from each other at a predetermined distance on the 1-2 bank pattern BNK1 . On the 1-2 bank pattern BNK1, the same spacing may be provided between the second electrode EL2 and the second dummy pattern DP2 and between the second electrode EL2 and the intermediate pattern CP, The present invention is not limited thereto. According to an embodiment, on the 1-2 first bank pattern BNK1 , a different interval between the second electrode EL2 and the second dummy pattern DP2 and between the second electrode EL2 and the intermediate pattern CP is different. may have

A first insulating layer INS1 may be provided and/or formed on the first and second dummy patterns DP1 and DP2 , the first and second electrodes EL1 and EL2 , and the intermediate pattern CP. The first insulating layer INS1 may cover regions other than one region of each of the first and second electrodes EL1 and EL2 . As the intermediate pattern CP and the first and second dummy patterns DP1 and DP2 are covered by the first insulating layer INS1 , the intermediate pattern CP and the first and second dummy patterns DP1 , DP2 may be electrically insulated from each of the first and second electrodes EL1 and EL2 and the first and second contact electrodes CNE1 and CNE2 .

In an embodiment of the present invention, the first and second dummy patterns DP1 and DP2 may reflect a portion of light traveling radially (or radially) from the light emitting elements LD in the image display direction of the display device. can Accordingly, the first and second dummy patterns DP1 and DP2 are formed together with the intermediate pattern CP and the first and second electrodes EL1 and EL2 in a direction in which light emitted from the light emitting devices LD is desired. may serve as a reflective member to improve light output efficiency of the display device.

17 is a plan view schematically illustrating a pixel according to another embodiment of the present invention, and FIG. 18 is a cross-sectional view taken along line VI to VI′ of FIG. 17 .

In the pixel illustrated in FIGS. 17 and 18 , first to third electrodes EL1 to EL3 and first and second intermediate patterns CP1 and CP2 are formed in the pixel area PXA of each pixel PXL. The pixels may have substantially the same or similar configuration to the pixels of FIGS. 10 to 14 except for the arrangement.

Accordingly, in relation to the pixels of FIGS. 17 and 18 , differences from the above-described exemplary embodiment will be mainly described in order to avoid overlapping descriptions.

1A to 5 , 17 , and 18 , a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL are disposed in the pixel area PXA of each pixel PXL can be

In an embodiment of the present invention, the display element layer DPL includes first and second bank patterns BNK1 and BNK2, first to third electrodes EL1 to EL3, and first and second intermediate patterns. The electrodes CP1 and CP2 may include light emitting devices LD, first to third contact electrodes CNE1 to CNE3 , and first to third insulating layers INS1 to INS3 .

The first electrode EL1 , the second electrode EL2 , and the third electrode EL3 may be sequentially arranged along the first direction DR1 . The first electrode EL1 and the second electrode EL2 are spaced apart from each other with a predetermined distance therebetween in the first direction DR1 , and the second electrode EL2 and the third electrode EL3 are spaced apart from each other in the first direction DR1 . ) can be spaced apart with a predetermined interval between them. In the pixel area PXA of each pixel PXL, the same distance may be between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL3. . However, the present invention is not limited thereto, and according to an exemplary embodiment, there may be different distances between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL3 . may be

A second electrode EL2 may be disposed between the first electrode EL1 and the third electrode EL3 . The first electrode EL1 may be electrically and/or physically connected to a part, for example, the driving transistor Tdr, included in the pixel circuit layer PCL of the corresponding pixel PXL through the first contact hole CH1. can The third electrode EL3 may be electrically and/or physically connected to the driving transistor Tdr through the third contact hole CH3 . The second electrode EL2 may be electrically and/or connected to some components included in the pixel circuit layer PCL of the corresponding pixel PXL, for example, the driving voltage lines DVL and PL2 through the second contact hole CH2. It can be physically connected. In one embodiment of the present invention, each of the first and third electrodes EL1 and EL3 may be an anode electrode of the corresponding pixel PXL, and the second electrode EL2 may be the pixel PXL. It may be a cathode electrode of

Each of the first to third electrodes EL1 to EL3 may be provided and/or formed on the first bank pattern BNK1. For example, each of the first to third electrodes EL1 to EL3 may include a first It may be provided and/or formed on one surface (eg, an upper surface) of the bank pattern BNK1 .

The first intermediate pattern CP1 may be disposed between the first electrode EL1 and the second electrode EL2 when viewed in a plan view. In addition, the first intermediate pattern CP1 includes the protective layer PSV of the pixel circuit layer PCL and the first insulating layer ( INS1) may be provided. The first side surface FS of the first intermediate pattern CP1 is adjacent to the first electrode EL1 , and the second side surface SS of the first intermediate pattern CP1 is adjacent to the second electrode EL2 . can be positioned The first side surface FS of the first intermediate pattern CP1 may be spaced apart from the first electrode EL1 with a first gap GAP1 in the first direction DR1 , and the first intermediate pattern CP1 may be spaced apart from the first electrode EL1 . The second side surface SS may be spaced apart from the second electrode EL2 with a second gap GAP2 in the first direction DR1 . The first gap GAP1 and the second gap GAP2 may be equal to each other, but the present invention is not limited thereto. According to an exemplary embodiment, the first interval GAP1 and the second interval GAP2 may be different from each other.

The second intermediate pattern CP2 may be disposed between the second electrode EL2 and the third electrode EL3 when viewed in a plan view. In addition, the second intermediate pattern CP2 includes the protective layer PSV of the pixel circuit layer PCL and the first insulating layer ( INS1) may be provided. The first side surface FS of the second intermediate pattern CP2 is adjacent to the third electrode EL3 , and the second side surface SS of the second intermediate pattern CP2 is adjacent to the second electrode EL2 . can be positioned The first side surface FS of the second intermediate pattern CP2 may be spaced apart from the third electrode EL3 with a fourth gap GAP4 in the first direction DR1 . The second side surface SS of the second intermediate pattern CP2 may be spaced apart from the second electrode EL2 with a third gap GAP3 in the first direction DR1 . The third interval GPA3 and the fourth interval GAP4 may be equal to each other, but the present invention is not limited thereto. According to an exemplary embodiment, the third interval GAP3 and the fourth interval GAP4 may be different from each other.

The first and second intermediate patterns CP1 and CP2 may be provided on the same layer as the first to third electrodes EL1 to EL3 and formed by the same process. The first and second intermediate patterns CP1 and CP2 and the first to third electrodes EL1 to EL3 are emitted from the light emitting devices LD to allow light to travel in the image display direction of the display device. It may be made of a material having a constant reflectance.

The first gap GAP1 between the first electrode EL1 and the first side surface FS of the first intermediate pattern CP1 is a first bank pattern BNK1 under the first electrode EL1, hereinafter referred to as 'first- 1 bank pattern). The second gap GAP2 between the second side surface SS of the first intermediate pattern CP1 and the second electrode EL2 is a first bank pattern BNK1 under the second electrode EL2, hereinafter referred to as 'first- It may correspond to a 'two-bank pattern'). A third gap GAP3 between the second electrode EL2 and the second side surface SS of the second intermediate pattern CP2 may correspond to the 1-2 first bank pattern BNK1 . The fourth gap GAP4 between the third electrode EL3 and the first side surface FS of the second intermediate pattern CP2 is a first bank pattern BNK1 below the third electrode EL3, hereinafter referred to as 'first- 3 bank pattern).

A first side surface FS of the first intermediate pattern CP1 may overlap the first-first bank pattern BNK1 , and a second side surface SS of the first intermediate pattern CP1 may be formed on the first It may overlap with the -2 bank pattern (BNK1). The first side surface FS of the first intermediate pattern CP1 is provided and/or formed on one side surface of the 1-1 bank pattern BNK1 to have a shape of one side surface of the 1-1 bank pattern BNK1. It may have a corresponding surface profile. The second side surface SS of the first intermediate pattern CP1 is provided and/or formed on one side surface of the 1-2 bank pattern BNK1 to have a shape of one side surface of the 1-2 bank pattern BNK1. It may have a corresponding surface profile.

The first side surface FS of the second intermediate pattern CP2 may overlap the first 1-3 bank patterns BNK1 , and the second side surface SS of the second intermediate pattern CP2 may be formed with the first It may overlap with the -2 bank pattern (BNK1). The first side surface FS of the second intermediate pattern CP2 is provided and/or formed on one side surface of the 1-3 bank pattern BNK1 to have a shape of one side surface of the first 1-3 bank pattern BNK1. It may have a corresponding surface profile. The second side surface SS of the second intermediate pattern CP2 is provided and/or formed on the other side surface of the 1-2 bank pattern BNK1 to have a shape on the other side surface of the 1-2 bank pattern BNK1. It may have a corresponding surface profile.

As described above, the first side surface FS and the second side surface SS of each of the first and second intermediate patterns CP1 and CP2 correspond to the shape of the first bank pattern BNK1 located thereunder. Since it has a surface profile, light emitted from each of the light emitting devices LD is reflected by the first and second side surfaces FS and SS of the first and second intermediate patterns CP1 and CP2, respectively. to further progress in the image display direction of the display device. In one embodiment of the present invention, each of the first and second intermediate patterns CP1 and CP2 includes the first bank pattern BNK1 and the first to third electrodes EL1 to EL3 together with the light emitting devices ( LD) may serve as a reflective member to improve light efficiency of a display device by guiding light emitted from the LD in a desired direction.

A first insulating layer INS1 may be provided and/or formed on the first and second intermediate patterns CP1 and CP2 and the first to third electrodes EL1 to EL3 . The first insulating layer INS1 includes a first opening OPN1 exposing a region of the first electrode EL1 , a second opening OPN2 exposing a region of the second electrode EL2 , and a third electrode A third opening OPN3 exposing one region of the EL3 may be included. The first and second intermediate patterns CP1 and CP2 are completely covered by the first insulating layer INS1 to be electrically insulated from the first to third electrodes EL1 to EL3 adjacent in the first direction DR1 . can be In addition, the first and second intermediate patterns CP1 and CP2 are completely covered by the first insulating layer INS1 to form the first to third contact electrodes CNE1 to CNE3 adjacent to each other in the third direction DR3. may be electrically insulated.

The light emitting devices LD may include first light emitting devices LD1 and second light emitting devices LD2 .

The first light emitting devices LD1 may be aligned on the first insulating layer INS1 on the first intermediate pattern CP1 between the first electrode EL1 and the second electrode EL2 . The second light emitting devices LD2 may be aligned on the first insulating layer INS1 on the second intermediate pattern CP2 between the second electrode EL2 and the third electrode EL3 .

When the light emitting devices LD are aligned in the pixel area PXA of each of the pixels PXL, a corresponding alignment signal (or alignment voltage) is transmitted to each of the first to third electrodes EL1 to EL3 . can For example, a first alignment signal having a negative polarity may be transmitted to each of the first and third electrodes EL1 and EL3 , and a second alignment signal having a positive polarity may be transmitted to the second electrode EL2 , respectively. can be transmitted. In this case, a charge having a positive polarity that is opposite to the negative polarity may be induced to the first side surface FS of the first intermediate pattern CP1 adjacent to the first electrode EL1 , and the second electrode EL2 and Charges having a negative polarity opposite to the positive polarity may be induced to the second side surface SS of the adjacent first intermediate pattern CP1 . In addition, a charge having a positive polarity that is opposite to the negative polarity may be induced to the first side surface FS of the second intermediate pattern CP2 adjacent to the third electrode EL3 and adjacent to the second electrode EL2 . Charges having a negative polarity that are opposite to the positive polarity may be induced to the second side surface SS of the second intermediate pattern CP2 .

Accordingly, an electric field may be formed between the first side surface FS and the second side surface SS of each of the first and second intermediate patterns CP1 and CP2 . The first light emitting devices are formed on the first insulating layer INS1 on the first intermediate pattern CP1 due to the electric field formed between the first side surface FS and the second side surface SS of the first intermediate pattern CP1. LD1 may be aligned, and due to an electric field formed between the first side surface FS and the second side surface SS of the second intermediate pattern CP2, the first insulating layer ( The second light emitting devices LD2 may be aligned on the INS1 .

The first electrode EL1 and the first contact electrode CNE1 may be directly connected to each other by the first opening OPN1 of the first insulating layer INS1 , and the second opening OPN2 of the first insulating layer INS1 . The second electrode EL2 and the second contact electrode CNE2 may be directly connected by the CNE3) can be directly connected.

The first to third contact electrodes CNE1 to CNE3 may be provided on the same layer and formed through the same process. The first to third contact electrodes CNE1 to CNE3 may be spaced apart from each other in the first direction DR1 . In addition, each of the first to third contact electrodes CNE1 to CNE3 may have a bar shape extending in the second direction DR2 .

When a driving current flows from the first power line PL1 to the driving voltage lines DVL and PL2 by the driving transistor Tdr in each pixel PXL and light is emitted from the light emitting devices LD, the first The first and second intermediate patterns CP1 and CP2 together with the first to third electrodes EL1 to EL3 emit light radially (or radially) from the light emitting devices LD in the image display direction of the display device. can be reflected by In addition, each of the first and second intermediate patterns CP1 and CP2 may reflect light emitted from the light emitting devices LD and traveling downward in the light emitting devices LD in the image display direction of the display device. have.

Accordingly, the first and second intermediate patterns CP1 and CP2 from the light emitted from the light emitting elements LD to the light traveling in the downward direction of the light emitting elements LD in the image display direction of the display device. As the light is reflected, the amount (or intensity) of light finally emitted from each of the pixels PXL increases, so that the light output efficiency of each of the pixels PXL may be further improved.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art or those having ordinary knowledge in the technical field will not depart from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that various modifications and variations of the present invention can be made without departing from the scope of the present invention.

Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUB: Substrate PXL: Pixel
EMU: light emitting unit LD: light emitting element
PCL: pixel circuit layer DPL: display element layer
EL1 to EL3: first to third electrodes C P: middle pattern
CP1, CP2: first and second intermediate patterns BNK: bank
DP1, DP2: first and second dummy patterns FS, SS: first and second sides
BNK1, BNK2: first and second bank patterns
CNE1 to CNE3: first to third contact electrodes

Claims (20)

a first electrode and a second electrode spaced apart from each other in a first direction on the substrate;
a plurality of light emitting elements disposed between the first electrode and the second electrode;
an intermediate pattern disposed between the first electrode and the second electrode in a plan view and positioned between the substrate and the plurality of light emitting devices in a thickness direction of the substrate;
a first contact electrode electrically connecting one end of each of the light emitting devices to the first electrode; and
a second contact electrode electrically connecting the other end of each of the light emitting devices to the second electrode;
One side of the intermediate pattern is spaced apart from the first electrode at a first interval in the first direction, and the other side of the intermediate pattern is spaced apart from the second electrode at a second interval in the first direction,
The intermediate pattern includes the same material as the first and second electrodes. The method of claim 1,
In a plan view, the intermediate pattern overlaps the light emitting elements. 3. The method of claim 2,
wherein the first and second electrodes and the intermediate pattern are provided on the same layer. 3. The method of claim 2,
wherein the first interval and the second interval are equal to or different from each other. 5. The method of claim 4,
each of the first and second intervals is smaller than a length of each of the light emitting elements parallel to an extension direction of each of the light emitting elements. 6. The method of claim 5,
A width of the intermediate pattern in a first direction is greater than a length of each of the light emitting elements. 3. The method of claim 2,
Further comprising an insulating layer provided on the first and second electrodes and the intermediate pattern and disposed under the light emitting devices,
The insulating layer exposes a portion of the first electrode and a portion of the second electrode, and completely covers the intermediate pattern. 8. The method of claim 7,
The intermediate pattern is covered by the insulating layer to be electrically insulated from the first electrode, the second electrode, the first contact electrode, and the second contact electrode. 8. The method of claim 7,
The intermediate pattern reflects the light emitted from each of the light emitting devices in one direction. 10. The method of claim 9,
a first bank pattern disposed between the substrate and the first electrode; and
a second bank pattern disposed between the substrate and the second electrode;
The one side of the intermediate pattern corresponds to the first bank pattern, and the other side of the intermediate pattern corresponds to the second bank pattern. 11. The method of claim 10,
The first electrode and the one side of the intermediate pattern are spaced apart from each other by the first interval on the first bank pattern,
The second electrode and the other side of the intermediate pattern are spaced apart from each other by the second interval on the second bank pattern. 12. The method of claim 11,
a first dummy pattern spaced apart from the first electrode in the first direction; and
a second dummy pattern spaced apart from the second electrode in the first direction;
The first electrode is disposed between the first dummy pattern and the intermediate pattern in a plan view,
The second electrode is disposed between the second dummy pattern and the intermediate pattern when viewed in a plan view. 13. The method of claim 12,
The first and second dummy patterns include the same material as the first and second electrodes and are provided on the same layer as the first and second electrodes. 14. The method of claim 13,
The insulating layer is provided on the first and second dummy patterns to completely cover the first and second dummy patterns. 14. The method of claim 13,
The first and second dummy patterns reflect the light emitted from the light emitting devices in the one direction. a plurality of pixels provided on a substrate;
Each of the pixels,
a first electrode and a second electrode spaced apart from each other in a first direction on the substrate;
a plurality of light emitting elements disposed between the first electrode and the second electrode;
an intermediate pattern disposed between the first electrode and the second electrode in a plan view and positioned between the substrate and the plurality of light emitting devices in a thickness direction of the substrate;
a first contact electrode electrically connecting one end of each of the light emitting devices to the first electrode; and
a second contact electrode electrically connecting the other end of each of the light emitting devices to the second electrode;
One side of the intermediate pattern is spaced apart from the first electrode at a first interval in the first direction, and the other side of the intermediate pattern is spaced apart from the second electrode at a second interval in the first direction,
The intermediate pattern includes the same material as the first and second electrodes. 17. The method of claim 16,
When viewed in a plan view, the intermediate pattern overlaps the light emitting elements,
and the first and second electrodes and the intermediate pattern are provided on the same layer. 18. The method of claim 17,
Further comprising an insulating layer provided on the first and second electrodes and the intermediate pattern and disposed under the light emitting devices,
The insulating layer exposes a portion of the first electrode and a portion of the second electrode, and completely covers the intermediate pattern. 19. The method of claim 18,
The intermediate pattern is covered by the insulating layer to be electrically insulated from the first electrode, the second electrode, the first contact electrode, and the second contact electrode. 20. The method of claim 19,
The intermediate pattern reflects the light emitted from each of the light emitting elements in one direction.

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