KR20230036437A - Radiation-resilient latch circuit and memory cell having dual redundancy - Google Patents

Abstract

The present invention relates to a radiation-resistant latch circuit and memory cell having double redundancy. The memory cell of the present invention includes: a storage cell that stores data; an access transistor module that controls access to the storage cell; a clocked output inverter for controlling the output of the storage cell; a transmission gate for controlling whether to output input data; and a clock inverter that inverts and outputs the clock frequency for operation of the memory cell. The storage cell includes: a first latch element in which a plurality of pMOSFETs are stacked at a first node and a plurality of nMOSFETs are stacked at a second node; and a second latch element in which a plurality of pMOSFETs are stacked at a third node and a plurality of nMOSFETs are stacked at a fourth node. The present invention is easy to manufacture and/or design with minimized latch redundancy.

Description

Radiation tolerant latch circuit and memory cell having double redundancy

The present invention relates to a radiation tolerant latch circuit and memory cell having double redundancy.

With advances in scaling down technologies in integrated circuits (ICs), integrated circuits have significantly reduced their supply voltage and node capacitance, and have a small amount of critical charge (e.g., maintaining logic states). minimum charge) is required. For this reason, the integrated circuit may generate a soft error not only in a harsh radiation environment at a high altitude, but also in a terrestrial level radiation environment.

In addition, as size decreases on the order of nanometers, integrated circuits are increasingly subject to multiple node upsets (MNUs) due to charge sharing between nodes. For example, 40 nanometer flip-flops implemented using a single node upset (SNU) hardened dual-interlocked cell element (DICE) are completely immune to soft errors. Compared to conventional flip-flops, it shows a prevention effect of about 30%.

Accordingly, interest in the design of a radiation hardening by design (RHBD) robust against a dual node upset (DNU) and/or a multi-node upset has recently increased. Currently proposed dual node upset (DNU) robust designs are generally based on Muller C-element (MCE) or dual-interlocked cell element (DICE).

However, the above designs have problems such as charge sharing during read/write operations at the system level, design complexity, and/or high power consumption. For example, an MCE-based memory cell has a simple design, but has a problem in that a state of a floating output node may be changed during reading due to charge sharing between a bus line and a floating output node of a memory. In addition, DICE-based memory cells consume a lot of power and have a long write time because all feedback loops are activated during a write operation of new data.

Accordingly, an object of the present invention is to solve the above problems, to minimize latch redundancy, and to maximize a node insensitive to a single event upset (SEU). It is to provide a radiation-tolerant latch circuit and memory cell having double redundancy.

A memory cell of the present invention for achieving the above object includes a storage cell for storing data; an access transistor module controlling access to the storage cell; a clocked output inverter for controlling the output of the storage cell; a transmission gate for controlling whether input data is output; and a clock inverter for inverting and outputting a clock frequency for operation of the memory cell, wherein the storage cell has a first latch element in which a plurality of pMOSFETs are stacked on a first node and a plurality of nMOSFETs are stacked on a second node. ; and a second latch element in which a plurality of pMOSFETs are stacked on a third node and a plurality of nMOSFETs are stacked on a fourth node.

A radiation-tolerant latch circuit having dual redundancy of the present invention includes a first latch element in which a plurality of pMOSFETs are stacked at a first node and a plurality of nMOSFETs are stacked at a second node; and a second latch element in which a plurality of pMOSFETs are stacked on a third node and a plurality of nMOSFETs are stacked on a fourth node.

The present invention as described above is easy to manufacture and / or design by minimizing latch redundancy, and maximizes the number of nodes insensitive to the SEU through the application of upset polarity to perform radiation resistance (error resistance). resilience) can be improved, and power performance can be improved (eg, power consumption reduced) through the use of transistors having multiple threshold voltages.

1 is a diagram illustrating a memory cell including a latch circuit according to an exemplary embodiment of the present invention.
2 is a diagram illustrating simulation results of a single node upset and a dual node upset of a memory cell according to an embodiment of the present invention.
3 is a table showing results of evaluating the performance of a memory cell according to an exemplary embodiment of the present invention.

Objects and effects of the present invention, and technical configurations for achieving them will become clear with reference to embodiments described later in detail in conjunction with the accompanying drawings. In describing the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

In addition, terms to be described later are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or operator.

However, the present invention is not limited to the embodiments disclosed below and may be implemented in a variety of different forms. Only these embodiments are provided to complete the disclosure of the present invention and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined by the scope of the claims. only become Therefore, the definition should be made based on the contents throughout this specification.

1 is a diagram illustrating a memory cell including a latch circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a memory cell 100 according to an embodiment of the present invention includes a storage cell 110, an access transistor module 120, a clock inverter 130, a transmission gate 140, and a clocked output inverter. (150) may be included.

The clocked output inverter 150 may control the output of the storage cell 110 . For example, clocked output inverter 150 may control the output of storage cell 110 using two inputs X2 and X3 having different signal strengths. For example, when the input data D is "0", X2 is a weak "1" and X3 is a strong "1". At this time, the transistor N14 of the clocked output inverter 150 is turned on by X2 having a value of weak "1", and the transistor P13 of the clocked output inverter 150 has a strong "1". It can be turned off by X3 having a value. Therefore, the leakage power of transistor P13 can be reduced compared to the input of weak "1".

The transmission gate 140 may control (eg, transmit or block) whether to output the input data D. For example, the transfer gate 140 may transmit or block input data D according to clock signals CLK and CLK_b to provide output data Q. Using the transfer gate 140, the memory cell 100 of the present invention can provide fast output for input data D.

The clock inverter 130 may invert and output clock frequencies for operations (eg, read/write/erase) of the memory cell 100 .

Access transistor module 120 may include access transistors positioned between an input and a latch element. Access transistors may be implemented with the same types of transistors as those used in the stacked structure. The access transistor module 120 may include an input inverter 121 that inverts and outputs input data.

The storage cell 110 (also termed a "latch circuit" or "latch module") may store data. The storage cell 110 may be configured with dual latch redundancy including two latch elements 111 and 112 . For example, the storage cell 110 may include a first latch element 111 positioned on the left side in FIG. 1 and a second latch element 112 positioned on the right side in FIG. 1 .

The first latch element 111 may include three nMOSFETs (N1, N2, and N3) stacked and three pMOSFETs (P1, P2, and P3) stacked, and the second latch element 112 is stacked. It may include three nMOSFETs (N6, N7, N8) and three pMOSFETs (P6, P7, P8) stacked. Due to this, the storage cell 110 of the present invention has an upset polarity (or error polarity) characteristics.

Due to the upset polarity characteristic, the pMOSFETs (P1, P2, P3 P4 P5) included in the first latch element 111 or the pMOSFETs (P6, P7, P8 P9 P10) included in the second latch element 112 ) is off, only positive upsets can occur at the corresponding node of the first latch element 111 or the second latch element 112 (sensitive to positive upsets). Also, when the nMOSFETs N1 , N2 , N3 N4 N5 included in the first latch element 111 or the nMOSFETs N6 , N7 , N8 N9 N10 included in the second latch element 112 are off. In the corresponding node of the first latch element 111 or the second latch element 112, only negative upsets can occur (only negative upsets are sensitive).

Meanwhile, in corresponding nodes of the first latch element 111 or the second latch element 112, pMOSFETs and nMOSFETs included in the first latch element 111 or the second latch element 112 are in an on state. If , it is incentive to SEU. For example, when the logic value of the input D is “0”, the pMOSFETs and nMOSFETs included in the second latch element 112 are in an on state, and the corresponding nodes of the second latch element 112 are connected to the SEU. be sensitive Therefore, the nodes X3, A3, and A7 of the pMOSFETs P6, P7, and P8 included in the second latch element 112 generate a logic value of “1” even when energy particles (or radiation particles) collide with each other. maintained, and not converted to a logical value of "0". In addition, the nodes X4, A4, and A8 of the nMOSFETs N6, N7, and N8 included in the second latch element 112 maintain the logic value "0" and are not converted to the logic value "1". don't

All transistors included in the first latch element 111 or the second latch element 112 may be turned on or off according to the logic value of the input D (eg, “0” or “1”). there is. For example, when the logic value of the input D is “1” (eg, X1=X4=1”, X2=X3=0”), all transistors P1 included in the first latch element 111 P2, P3, P4, P5, N1, N2, N3, N4, and N5 are turned on, and all transistors P6, P7, P8, P9, P10, N6, N7, N8, N9, N10) can be turned off. At this time, when the clock is in a transparent mode having a value of “1”, the nodes X1, X2, X3, and X4 of the first latch element 111 and the second latch element 112 access It is driven by input D through transistor module 120, and output Q is driven by input D through a transmission gate (TR). On the other hand, when the clock is in the hold mode (transparent mode) having a value of “0”, all internal nodes of the off-state second latch element 112 are in a floating state, and the output Q is stable It may not be. Thus, all internal nodes of the second latch element 112 in the OFF state can be driven by the corresponding internal nodes of the first latch element 111 in the ON state to accurately maintain the original output.

As another example, when the logic value of input D is “0” (eg, X1=X4=0”, X2=X3=1”), all transistors P1 and P2 included in the first latch element 111 , P3, P4, P5, N1, N2, N3, N4, and N5 are turned off, and all transistors P6, P7, P8, P9, P10, N6, and N7 included in the second latch element 112 are turned off. , N8, N9, N10) may be turned on. At this time, the nodes of the first latch element 111 in a floating state are driven by corresponding internal nodes of the second latch element 112, so that the output Q may maintain “0”.

Meanwhile, the first latch element 111 and the second latch element 112 have a drop in threshold voltage Vth in the off state due to a structure (or architecture) in which a plurality of transistors are stacked. can happen A drop in the threshold voltage (Vth) may cause high power consumption. The storage cell 110 according to the present invention may use high-threshold voltage transistors to reduce power consumption due to a drop in the threshold voltage Vth. For example, some transistors (P1, P6, N3, and N8 of FIG. 1) included in the storage cell 110 may have relatively high threshold voltages. Meanwhile, other transistors (P2, P3, P7, P8, N1, N2, N6, and N7 in FIG. 1) may have low threshold voltages in order to prevent a signal from being weakened at a corresponding node.

On the other hand, the storage cell 110 has one latch element completely immune to all kinds of upsets, and soft errors generated by other latch elements (e.g., single node upset (SNU), dual node upset (dual node upset)). upset: DNU)) can be recovered (recovered). For example, all transistors of one latch element of the first latch element 111 and the second latch element 1112 are fully operated (eg, in an on state), and current is supplied to all nodes. On the other hand, all transistors of other latch elements are not operating (eg, off state), and all nodes have a floating state. In other words, all nodes of the first latch element 111 that are turned off when the input D is “0” are sensitive to SEU. Therefore, the nodes of the second latch element 112 in the on state must be stable in order to play a role of restoring the upset node of the first latch element 111 . That is, when an upset occurs at a node of the first latch element 111, the transistors P9, P10, N9, and N10 of the second latch element 112 are connected to the nodes of the first latch element 111 ( In order to supply feedback current (recovery current) to X1, A1, X2, and A2), it must be stable. At this time, the transistor of the first latch element 111 in the off state is controlled by the node of the second latch element 112 in the on state, so that an error generated at the node of the first latch element 111 occurs in the first latch element 111 ) plays a role in blocking propagation to other nodes.

Meanwhile, the first latch element 111 and the second latch element 112 may include core parts 111a and 112a and error recovery auxiliary parts 111b and 112b. At this time, a ratio issue may occur in the core part 111a of the first latch element 111 due to an upset of node A1 or A2. For example, when node A1 is flipped to “1”, off-state transistors N4 and N5 are turned on, and the states of nodes X3 and A3 may be disturbed. Similarly, when node A2 is flipped to “1”, off-state transistors P4 and P5 are turned on, and the states of nodes X4 and A4 may be disturbed.

In order to solve the ratio problem of the node A1 and/or A2, the aspect ratio of the transistors P6, P7, P8, N6, N7, and N8 of the core part 112a of the second latch element 112 can be set high. In addition, more stacked nodes may be added to the storage cell 110 to block SEU propagation through the transistors P4 , P5 , N4 and N5 to the on-state second latch element 112 .

On the other hand, the core part 112a of the second latch element 112 may have a ratio issue in the upset of node A3 or A4, the same as (or similar to) the first latch element 111, can be resolved in the same (or similar) way.

2 is a diagram illustrating simulation results of a single node upset and a dual node upset of a memory cell according to an embodiment of the present invention.

Referring to FIG. 2 , a memory cell according to an embodiment of the present invention can recover (restore) a soft error (eg, single node upset (SNU) or dual node upset (DNU)). That is, the performance of the memory cell according to the present invention can be improved.

Hereinafter, a case in which the input D is "0" will be described as an example. This is because those skilled in the art (hereinafter, those skilled in the art) can easily know about the case where the input D is "1" through the following description.

First, when input D is “0”, nodes X1 and X4 have initial values of “0” and nodes X2 and X3 have initial values of “1”. That is, when the input D is “0”, all transistors included in the first latch element 111 may be turned off, and all transistors included in the second latch element 112 may be turned on. Therefore, some nodes (eg, nodes included in the second latch element 112) of the memory cell according to the present invention are insensitive to the SEU, and the remaining nodes (eg, nodes included in the first latch element 111) are sensitive to upsets in a single direction (ie only positive or negative upsets occur). Accordingly, a memory cell according to an embodiment of the present invention may generate soft errors (eg, SNU or DNU) in various cases as shown in Table 1 below.

SNU CASE 1 X1 CASE 2 A1 CASE 3 A5 DNU CASE 4 X1/A1 CASE 5 X1/X2 CASE 6 A1/A2 CASE 7 X1/A2 CASE 8 X1 or X2 or A1 or A2 / A5 or A6

Referring to <Table 1>, an error (SNU) may occur in node X1 (case 1). For example, when an energy particle collides with a node X1 in a low (“0”) state, as shown by identification code 201, the node X1 is flipped from a low state to a high (“1”) state. Upsets can happen. The node X1 where the error occurred may turn on the transistor N3 and turn off the transistors P7 and P8. Also, due to transistors N2 and P3 being off, errors at node X1 do not propagate to nodes X2 and A1. As a result, the node X1 of the first latch element 111 flipped to a high state is recovered (restored) to a low state by the transistor P9 of the second latch element 112 . Meanwhile, although not shown, an error (SNU) generated in node X2 may be recovered in a manner similar to that of node X1. That is, a negative upset generated at the node X2 of the first latch element 111 may be recovered by the transistor N9 of the second latch element 112 .

As another example, an error (SNU) may occur at node A1 (case 2). For example, when an energy particle collides with node A1, a positive upset may occur, flipping from a low state to a high state. Node A1 where the error occurred can turn on transistors N4 and N5. Transistors N4 and N5 turned on can supply current to nodes X4 and A4. However, the states of nodes X4 and A4 are not changed because the aspect ratios of transistors N6 to N8 are not greater than those of transistors N4 and N5. At this time, the transistor P10 of the second latch element 112 supplies a recovery current to the node A1 of the first latch element 111 . As a result, the error of node A1 can be recovered. Meanwhile, although not shown, an error (SNU) generated in node A2 may be recovered in a manner similar to that of node A1. That is, a negative upset generated at the node A2 of the first latch element 111 may be recovered by the transistor N10 of the second latch element 112 .

As another example, an error (SNU) may occur at node A5 (case 3). For example, when an energy particle collides with node A5, a positive upset may occur in which node A5 is flipped from a low state to a high state. Node A5 is not connected to the input of the transistor. Also, the error at node A5 is blocked by transistor P2 in the off state. Thus, node A5 does not affect other nodes. Thereafter, the error of the node A5 may be recovered by the leakage current passing through the transistor P1. Meanwhile, although not shown, an error (SNU) generated in node A6 may be recovered in a manner similar to that of node A5. That is, the negative upset generated at node A6 can be recovered by transistor N3.

As another example, an error (DNU) may occur at nodes X1 and A1 (case 4). For example, when an energy particle collides with nodes X1 and A1 in a low state, a positive upset may occur in which the nodes X1 and A1 are flipped from a low state to a high state, as shown by identification numeral 203 . At this time, as described in cases 1 and 2, the states of nodes X2, X4, and A4 do not change. Thus, transistors P9 and P10 can recover errors at nodes X1 and A1, respectively. Meanwhile, although not shown, errors (DNU) generated in nodes X2 and A2 may be recovered in a manner similar to recovery of errors generated in nodes X1 and A1. That is, negative upsets generated at nodes X2 and A2 can be recovered by transistors N9 and N10, respectively.

As another example, an error (DNU) may occur at nodes X1 and X2 (case 5). For example, when an energy particle collides with nodes X1 and X2, a positive upset occurs in which node X1 is flipped from a low state to a high state, as shown at 205, and node X2 is flipped from a high state to a low state. A flipped negative upset can occur. At this time, transistors P2 and P3 are turned off by node X3, and transistors N1 and N2 are turned off by node X4. Thus, errors in nodes X1 and X2 do not propagate to other nodes. After that, the errors of the nodes X1 and X2 can be recovered by the feedback current (recovery current) from the second latch element 112 . That is, the errors of nodes X1 and X2 can be recovered by transistors P9 and N9.

As another example, an error (DNU) may occur at nodes A1 and A2 (case 6). For example, when an energy particle collides with nodes A1 and A2, a positive upset occurs in which node A1 is flipped from a low state to a high state, as shown at 207, and node A2 is flipped from a high state to a low state. A flipped negative upset can occur. Due to the error at node A1, transistors N4 and N5 can be turned on. Also, due to the error at node A2, transistors P4 and P5 can be turned on. That is, transistors N4, N5, P4, and P5 can supply current to nodes X4, A4, X3, and A3, respectively. Similar to case 2, since the transistors N6 and N8 and P6 and P8 are relatively strong, and the state of the nodes X1 and X2 of the first latch element 111 is maintained, the core of the second latch element 112 Part works normally. Thus, nodes A3, A4, X3, and X4 do not change state. As a result, the error of node A1 can be recovered by transistor P10, and the error of node A2 can be recovered by transistor N10.

As another example, an error (DNU) may occur at nodes X1 and A2 (case 7). For example, when an energy particle collides with nodes X1 and A2, a positive upset occurs in which node X1 is flipped from a low state to a high state, as shown at 209, and node A2 is flipped from a high state to a low state. A flipped negative upset can occur. Since transistors P3 and N1 are off, nodes A1 and X2 remain in their initial state. The second latch element 112 operates normally and can supply recovery current to the nodes X1 and A2. That is, the errors of the nodes X1 and A2 of the first latch element 111 may be recovered by the transistors P9 and N10 of the second latch element 112, respectively.

As another example, an error DNU may occur in one of nodes X1, X2, A1 or A2, and one of A5 or A6 (case 8). For example, an upset may occur in one of nodes X1, X2, A1 or A2, and an upset in one of A5 or A6. At this time, node A5 is surrounded by off-state transistors P1 and P2, and node A6 is surrounded by off-state transistors N2 and N3. Due to this, the nodes where errors occur can be recovered similarly to the SNUs of cases 1 to 3, respectively.

As described above, even if soft errors (eg, SNU and DNU) occur in various cases, the memory cell according to an embodiment of the present invention does not change its output Q and has resilience against errors. Meanwhile, <Table 1> and FIG. 2 show some examples of soft errors that may occur, and the present invention can also recover other soft errors.

3 is a table showing results of evaluating the performance of a memory cell according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , it can be seen that the memory cell according to an embodiment of the present invention has been compared in various aspects with conventionally known representative DNU designs (e.g., identification codes 5, 6, 7, and 8 of FIG. 3). . For example, FIG. 3 shows comparison results for the number of transistors (circuit complexity), the number of sensitive nodes, delay time, average power, and power-delay product (PDP).

First, comparing the number of transistors (# of transistors), the MCE-based DNU design with identification code 7 requires the largest number of transistors, and the DNU design according to the present invention (“DR2MC” in FIG. 3) has the most It can be seen that a small number of transistors are required.

In addition, comparing the number of sensitive nodes (# of sensitive nodes), it can be seen that the identification code 8 using the upset polarity and the DNU design according to the present invention have a relatively small number of sensitive nodes. In particular, the DNU design according to the present invention can have the smallest number of sensitive nodes by minimizing latch redundancy (eg, double redundancy). Meanwhile, in the DICE-based DNU design of identification codes 5 and 6 and the MCE-based DNU design of identification code 7, all nodes are sensitive.

In addition, when data-to-Q delay is compared, it can be seen that the DICE-based DNU designs of identification codes 5 and 6 have relatively long delay times. On the other hand, it can be seen that the DNU design according to the present invention has the shortest delay time even when compared with the DNU designs of identification codes 7 and 8, which have a relatively short delay time.

In addition, comparing average power, the DNU design of identification code 8 consumes the most power. This is due to the six-complex latch redundancy. Meanwhile, although the power consumption of the DNU design according to the present invention is not the lowest, it can be seen that the power consumption of the DNU design according to the present invention is similar to that of the DNU designs with identification codes 5 to 7. This is due to the minimization of latch redundancy, the use of multiple threshold voltage transistors (e.g., some transistors have high threshold voltages), and the combined use of strong and weak signals in the output buffer.

Finally, comparing power-delay products (PDPs), the DNU designs of identification codes 5 and 6 have relatively very high PDPs, and the DNU designs of identification codes 7 and 8 have relatively high PDPs. It can be seen that the following DNU design has the lowest PDP. For example, it can be seen that the DNU design according to the present invention has a PDP that is about 2 to 11 times lower than that of other DNU cells.

The memory cell described above with reference to FIGS. 1 to 3 minimizes (eg, 50%) the number of SEU-sensitive nodes (ie, maximizes the number of SEU-sensitive nodes) by using the upset polarity characteristic. It can be hardened against dual node upsets, and latch redundancy can be minimized through a dual redundancy structure. In addition, the memory cell according to the present invention uses a multi-threshold transistor and can connect two inputs having different signal strengths. Due to this, the memory cell according to the present invention may have advantages in various aspects (eg, circuit complexity, immunity to SEU, time delay, and power consumption).

Although the above has been described with reference to the illustrated embodiments of the present invention, these are only examples, and those skilled in the art to which the present invention belongs can variously It will be apparent that other embodiments that are variations, modifications and equivalents are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: memory cell 110: storage cell
111: first latch element 112: second latch element
120: access transistor module 130: clock inverter
140: transfer gate 150: clocked output inverter

Claims (10)

In the memory cell,
storage cells that store data;
an access transistor module controlling access to the storage cell;
a clocked output inverter for controlling the output of the storage cell;
a transfer gate that controls whether input data is output; and
A clock inverter inverting and outputting a clock frequency for operation of the memory cell;
The storage cell is
a first latch element in which a plurality of pMOSFETs are stacked on a first node and a plurality of nMOSFETs are stacked on a second node; and
A memory cell comprising a second latch element in which a plurality of pMOSFETs are stacked at a third node and a plurality of nMOSFETs are stacked at a fourth node.
According to claim 1,
The first latch element and the second latch element
A memory cell comprising three stacked nMOSFETs and three stacked pMOSFETs, respectively.
According to claim 1,
A plurality of nMOSFETs and a plurality of pMOSFETs included in the first latch element and the second latch element
A memory cell characterized by being sensitive to single-way single event upsets (SEUs) when in an off state and insensitive to SEUs when in an on state.
According to claim 1,
Some of the plurality of nMOSFETs and some of the plurality of pMOSFETs included in the first latch element and the second latch element have a first threshold voltage, and others have a second threshold voltage higher than the first threshold voltage. A memory cell characterized in that it has a voltage.
According to claim 1,
The access transistor module
A memory cell, characterized in that it is implemented with a combination of a pMOSFET and an nMOSFET.
According to claim 1,
The clocked output inverter is
A memory cell characterized by using two input signals having different intensities.
In a radiation-tolerant latch circuit having dual redundancy,
a first latch element in which a plurality of pMOSFETs are stacked on a first node and a plurality of nMOSFETs are stacked on a second node; and
and a second latch element in which a plurality of pMOSFETs are stacked at a third node and a plurality of nMOSFETs are stacked at a fourth node.
According to claim 7,
The first latch element and the second latch element
A latch circuit comprising three stacked nMOSFETs and three stacked pMOSFETs, respectively.
According to claim 7,
A plurality of nMOSFETs and a plurality of pMOSFETs included in the first latch element and the second latch element
A latch circuit characterized in that it is sensitive to a single event upset (SEU) in one direction when in an off state and insensitive to a SEU when in an on state.
According to claim 7,
Some of the plurality of nMOSFETs and some of the plurality of pMOSFETs included in the first latch element and the second latch element have a first threshold voltage, and others have a second threshold voltage higher than the first threshold voltage. A latch circuit characterized in that it has a voltage.

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