KR20230015627A - Circuit board and package substrate having the same - Google Patents

Abstract

A circuit board according to an embodiment comprises: an insulating layer which includes an upper surface and a lower surface; and a through electrode which penetrates the upper and lower surfaces of the insulating layer. The through electrode includes: a first electrode part which is arranged adjacent to the lower surface of the insulating layer and has a first slope such that the width gradually decreases toward the upper surface of the insulating layer; a second electrode part which is arranged above the first electrode part and has a second slope such that the width gradually increases toward the upper surface of the insulating layer; and a third electrode part which is arranged between the first electrode part and the second electrode part and has a third slope different from the first and second slopes, wherein the width of the third electrode part is the same as the width of the area which has the smallest width among the first and second electrode parts. The circuit board can improve the physical reliability and electrical reliability of the through electrode.

Description

Circuit board and package substrate including the same {CIRCUIT BOARD AND PACKAGE SUBSTRATE HAVING THE SAME}

The embodiment relates to a circuit board and a package board including the circuit board.

As the miniaturization, weight reduction, and integration of electronic components accelerate, the line width of circuits is miniaturized. In particular, as the design rules of semiconductor chips are integrated on a nanometer scale, the circuit line width of a package substrate or circuit board on which semiconductor chips are mounted is miniaturized to several micrometers or less.

In order to increase the degree of circuit integration of the circuit board, that is, to refine the line width of the circuit, various methods have been proposed. For the purpose of preventing loss of circuit line width in the step of etching to form a pattern after copper plating, a semi-additive process (SAP) method and a modified semi-additive process (MSAP) have been proposed.

Since then, in order to implement a finer circuit pattern, an embedded trace substrate (hereinafter referred to as 'ETS') method in which copper foil is buried in an insulating layer and embedded is used in the related art. The ETS method is advantageous in miniaturizing the circuit pitch because there is no circuit loss due to etching because the copper foil circuit is manufactured by embedding it in the insulating layer instead of forming it on the surface of the insulating layer.

Meanwhile, in order to meet the recent wireless data traffic demand, efforts are being made to develop an improved 5 ^th generation (5G) communication system or pre-5G communication system. Here, the 5G communication system uses mmWave bands (sub 6 gigabytes (6GHz), 28 gigabytes 28GHz, 38 gigabytes 38GHz or higher frequencies) to achieve high data rates.

In addition, in order to mitigate the path loss of radio waves and increase the propagation distance of radio waves in the ultra-high frequency band, in the 5G communication system, beamforming, massive MIMO, and integration of array antennas, etc. Technologies are being developed. Given that these frequency bands can consist of hundreds of active antennas of wavelength, the antenna system becomes relatively large.

Since these antennas and AP modules are patterned or mounted on a circuit board, low loss of the circuit board is very important. This means that several substrates that make up an active antenna system, that is, an antenna substrate, an antenna feed substrate, a transceiver substrate, and a baseband substrate, must be integrated into one compact unit. .

Meanwhile, such a circuit board includes through electrodes. The through-electrode performs various functions, such as signal transmission, heat dissipation, and shielding.

However, the conventional circuit board has various problems such as voids when the through electrode is formed on an insulating layer having a thickness of 300 μm or more. In this case, when the through electrode includes a void, the strength of the through electrode is reduced due to the void, and accordingly, cracks are highly likely to occur in use environments of various circuit boards.

On the other hand, the void as described above may be caused when the center of the through electrode is smaller than the upper and lower widths of the through electrode. For example, a through hole in a conventional circuit board may have an hourglass shape. Through this, in the process of forming the through electrode by filling the through hole with the conductive material, it is difficult to uniformly fill the through hole with the conductive material in the center of the through hole, causing various problems. Furthermore, as the through-electrode of the conventional circuit board has an hourglass shape in which the width is narrowed at the center, the total area of the through-electrode is reduced, and accordingly, signal transmission characteristics, heat dissipation characteristics, and There is a problem that the shielding property is lowered.

In an embodiment, a circuit board including a through electrode having a novel structure and a package substrate including the same are provided.

In addition, in the embodiment, a circuit board including a through electrode having at least three curved portions along a side slope and a package substrate including the same are provided.

In addition, in the embodiment, a circuit board and a package substrate including the same are provided so that the area of the through hole and the through electrode can be increased by including a glass fiber dense region in the central region of the core layer.

The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned are clear to those skilled in the art from the description below to which the proposed embodiment belongs. will be understandable.

A circuit board according to an embodiment includes an insulating layer including upper and lower surfaces; and a through-electrode penetrating upper and lower surfaces of the insulating layer, wherein the through-electrode is disposed adjacent to the lower surface of the insulating layer and has a first slope such that a width gradually decreases toward the upper surface of the insulating layer. A first electrode part having a; a second electrode part disposed on the first electrode part and having a second slope such that a width thereof gradually increases toward an upper surface of the insulating layer; and a third electrode part disposed between the first electrode part and the second electrode part and having a third inclination different from the first and second inclinations, wherein the third electrode part has a width of the first electrode part. and the width of the region having the smallest width among the second electrode parts.

Meanwhile, a circuit board according to another embodiment includes an insulating layer including upper and lower surfaces and a through hole penetrating the upper and lower surfaces, the through hole being disposed adjacent to the lower surface of the insulating layer, a first hole part having a first slope such that a width gradually decreases toward the top surface of the insulating layer; a second hole part disposed on the first hole part and having a second slope such that a width gradually increases toward the upper surface; and a third hole part disposed between the first hole part and the second hole part and having a third inclination different from the first and second inclinations, wherein the third hole part has a width of the first hole part. and the width of the region having the smallest width among the second hole parts.

The circuit board penetrates the insulating layer and includes a through electrode corresponding to the through hole, wherein the through electrode includes a first electrode part corresponding to the first hole part and the second hole part. It includes a second electrode part corresponding to and a third electrode part corresponding to the third hole part.

Further, the width of the upper and lower surfaces of the third electrode part is the same, the width of the lower surface of the third electrode part is equal to the width of the region having the smallest width in the first electrode part, and the third electrode part has the same width. The width of the upper surface of the part is equal to the width of the small-width region of the second electrode part.

In addition, the insulating layer includes a first region in which the first electrode part is disposed, a second region in which the second electrode part is disposed, and a third region in which the third electrode part is disposed, and the The density of the glass fibers in the three regions is greater than the densities of the glass fibers in the first and second regions.

The insulating layer includes a first insulating part and a second insulating part on the first insulating part, wherein the first insulating part includes a 1-1 region adjacent to a lower surface of the insulating layer and the insulating layer. A 1-2 region adjacent to a lower surface of the second insulating part includes a 2-1 region adjacent to a lower surface of the insulating layer and a 2-2 region adjacent to an upper surface of the insulating layer, The first region of the insulating layer corresponds to the 1-1 region of the first insulating part, the second region of the insulating layer corresponds to the 2-1 region of the second insulating part, The third region of the insulating layer corresponds to the 1-2 region of the first insulating part and the 2-1 region of the second insulating part.

In addition, a first pad disposed on the lower surface of the insulating layer and connected to the first electrode part; and a second pad disposed on an upper surface of the insulating layer and connected to the second electrode part.

In addition, a width of a portion closest to the first pad among the first electrode parts is smaller than a width of the first pad, and a width of a portion closest to the second pad among the second electrode parts has a width of the second pad. less than the width

In addition, the width of the upper surface of the third electrode part satisfies a range between 95% and 105% of the width of the lower surface of the third electrode part.

In addition, the third slope is perpendicular to the upper or lower surface of the insulating layer.

In addition, the first electrode part and the second electrode part have mutually symmetrical shapes with respect to the third electrode part.

In addition, the first slope and the second slope are inclined in different directions.

In addition, the insulating layer includes a prepreg containing resin and glass fibers.

In addition, the first electrode part has a trapezoidal shape in which the width of the lower surface is greater than the width of the upper surface, the second electrode part has a trapezoidal shape in which the width of the lower surface is smaller than the width of the upper surface, and the third electrode part is of the lower surface It has a rectangular shape in which the width and the width of the upper surface are equal.

Meanwhile, a package substrate according to an embodiment includes a circuit board including mounting pads; a connection part disposed on the mounting pad of the circuit board; a chip disposed on the connection portion; and a molding layer for molding the chip, wherein the circuit board includes: an insulating layer including upper and lower surfaces; and a through-electrode penetrating upper and lower surfaces of the insulating layer, wherein the through-electrode is disposed adjacent to the lower surface of the insulating layer and has a first slope such that a width gradually decreases toward the upper surface of the insulating layer. A first electrode part having a; a second electrode part disposed on the first electrode part and having a second slope such that a width thereof gradually increases toward an upper surface of the insulating layer; and a third electrode part disposed between the first electrode part and the second electrode part and having a third inclination different from the first and second inclinations, wherein the third electrode part is among the first electrode parts. The width of the portion closest to the third electrode part is equal to the width of the third electrode part, and the width of the portion closest to the third electrode part among the second electrode parts is equal to the width of the third electrode part. The inclination is perpendicular to the upper or lower surface of the insulating layer, and the chip includes a first chip and a second chip disposed spaced apart from each other in the width direction, and the first chip corresponds to a central processor (CPU) , the second chip corresponds to a graphics processor (GPU).

In the embodiment, when the through electrode is formed on an insulating layer that is a core layer having a predetermined thickness or more (eg, 300 μm or more), the insulating layer is divided into a plurality of regions in the thickness direction. And, in the embodiment, a dense region of glass fibers is included in a central region among a plurality of regions of the insulating layer. Further, in the embodiment, a through hole is formed in the insulating layer including the dense region, and the formed through hole is filled with a conductive material to form a through electrode. Accordingly, in the embodiment, when filling the through hole, it is possible to solve the void problem in which the central region of the through hole is not filled, and thereby improve the physical reliability and electrical reliability of the through electrode.

Accordingly, the central region of the through hole and the through electrode in the embodiment may have a rectangular shape rather than an hourglass shape. Therefore, in the embodiment, compared to the comparative example having an hourglass shape, it is possible to increase the area of the through hole and the through electrode in the central region, thereby maximizing the effect according to the function of the through electrode. For example, when the through electrode functions as a signal shielding function, the signal shielding effect can be further improved. For example, when the through electrode functions to dissipate heat, heat dissipation characteristics may be further improved.

Furthermore, in the embodiment, since a dense region of glass fibers is included in the central region of the insulating layer, a portion of the glass fibers may be exposed in the central region of the through hole. Also, the through electrode in the embodiment may be formed to cover the glass fiber exposed through the through hole. At this time, the exposed glass fiber functions to increase the roughness of the inner wall of the through hole, and thus, bonding force between the insulating layer and the through electrode may be improved during formation of the through electrode. Accordingly, in the embodiment, it is possible to solve a problem in which the through electrode is separated from the insulating layer due to warpage occurring in various use environments of the circuit board, thereby improving physical reliability and electrical reliability of the circuit board. can make it

1A is a diagram for explaining problems of a circuit board according to a first comparative example.
1B is a diagram for explaining problems of the circuit board according to the second comparative example.
2 is a diagram showing a circuit board according to the first embodiment.
3 is a diagram illustrating a circuit board according to a second embodiment.
FIG. 4 is a view for explaining the insulating layer of FIG. 2 .
FIG. 5 is a view for explaining the through electrode formed in FIG. 2 or 3 .
6A is a view for explaining the inclination of the side surfaces of the first electrode part and the second electrode part according to the embodiment.
6B is a view for explaining the inclination of the side of the third electrode part according to the embodiment.
7 is a diagram illustrating a circuit board according to another embodiment.
8 is a view showing a package substrate according to an embodiment.
9 to 14 are diagrams illustrating a manufacturing method of the circuit board shown in FIG. 2 in order of processes.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical idea of the present invention is not limited to some of the described embodiments, but may be implemented in a variety of different forms, and if it is within the scope of the technical idea of the present invention, one or more of the components among the embodiments can be selectively implemented. can be used by combining and substituting.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention, unless explicitly specifically defined and described, can be generally understood by those of ordinary skill in the art to which the present invention belongs. It can be interpreted as meaning, and commonly used terms, such as terms defined in a dictionary, can be interpreted in consideration of contextual meanings of related technologies. In addition, terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In this specification, the singular form may also include the plural form unless otherwise specified in the phrase, and when described as "at least one (or more than one) of A and (and) B and C", A, B, and C are combined. may include one or more of all possible combinations. Also, terms such as first, second, A, B, (a), and (b) may be used to describe components of an embodiment of the present invention.

These terms are only used to distinguish the component from other components, and the term is not limited to the nature, order, or order of the corresponding component. And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected to, combined with, or connected to the other component, but also with the component. It may also include the case of being 'connected', 'combined', or 'connected' due to another component between the other components.

In addition, when it is described as being formed or disposed on the "top (above) or bottom (bottom)" of each component, the top (top) or bottom (bottom) is not only a case where two components are in direct contact with each other, but also one A case in which another component above is formed or disposed between two components is also included. In addition, when expressed as "up (up) or down (down)", it may include the meaning of not only an upward direction but also a downward direction based on one component.

-Comparison Example (Structure of the prior art and its problems)-

1A is a diagram for explaining problems of the circuit board according to the first comparison example, and FIG. 1B is a diagram for explaining problems with the circuit board according to the second comparison example.

Hereinafter, problems of the circuit board according to the comparative example will be described with reference to FIGS. 1A and 1B.

Prior to the description of the comparative example, high density circuit boards are required along with high functionality of electronic devices and high integration of semiconductor devices. Accordingly, the circuit board has a multilayer structure.

The product family to which such a multi-layered circuit board is applied includes FCBGA (Flip Chip Ball Grid Array) or FCCSP (Flip Chip Chip Scale Package). In addition, the circuit board applied to FCBGA or FCCSP may include an insulating layer. The insulating layer may include a core layer, and the core layer has a thickness of 300 μm or more to realize multi-layer build-up, and the core layer includes through-electrodes for conducting circuit patterns of each layer. The through electrode may be formed by filling through holes penetrating the upper and lower surfaces of the core layer with a conductive material. However, when the core layer has a thickness of 300 μm or more, the through hole of the comparative example The process of forming a hole and/or the process of forming a through electrode has the following problems.

As shown in (a) of FIG. 1A, in the first comparative example, an insulating layer 10 to be used as a core layer is prepared. In this case, the thickness of the insulating layer 10 may be 300 μm or more.

Also, in the first comparative example, a through hole may be formed by processing the insulating layer 10 with a laser. At this time, as the insulating layer 10 has a thickness of 300 μm or more, it is difficult to process a through hole only on one side of the insulating layer 10 . Accordingly, in general, when a through hole is formed in an insulating layer 10 such as a core layer using a laser, a process of forming a through hole is performed on the upper and lower surfaces of the insulating layer 10, respectively.

For example, when a through hole is formed in the insulating layer 10 through laser processing, the first hole of the through hole is formed on the upper surface of the insulating layer 10 to correspond to the target hole width and hole depth that the through hole should have. A process of forming a part and forming a second hole part connected to the first hole part of the through hole on the lower surface of the insulating layer 10 is performed.

However, as shown in (b) of FIG. 1A, when the first hole part 11 and the second hole part 12 are formed based on the target hole width, the first hole part 11 and the second hole A non-penetration problem arises in which the parts 12 are not connected to each other.

Accordingly, in the first comparative example, as shown in (c) of FIG. 1A, in order to solve the non-penetration problem, the first hole part and the second hole part have a larger width than the target hole width that the through hole should have. It forms a hall part. However, in this case, the through hole has a larger width w1 than the target hole width. Accordingly, there is a problem in that it is difficult to match the width of the through hole and the through electrode formed by filling the through hole in Comparative Example 1 to a desired target hole width. Furthermore, in Comparative Example 1, as the width of the through hole increases, in the process of filling the inside of the through hole with a conductive material, voids (a phenomenon in which a part of the through hole is not filled) or dimples (through electrodes) It includes plating problems such as dents on the top or bottom of the plate).

Also, as shown in (a) and (b) of FIG. 1B , in the second comparative example, a through hole 20 is formed in the insulating layer 10 using a computer numerical control (CNC) drill instead of a laser. And, in the case of using a CNC drill, the width of the upper and lower surfaces of the through hole 20 has the same width. And, in the second comparative example, a through electrode is formed by filling the through hole 20 with a conductive material. At this time, in the second comparative example, the through hole 20 has a columnar shape in which the upper and lower surfaces have the same width. However, since such a through hole 20 does not include a plating bridge unlike the through hole of FIG. 1A having an hourglass shape, it is difficult to uniformly fill the through hole 20 with a conductive material. there is For example, as shown in (c) of FIG. 1B, as the plating of the first through-electrode 30 formed in the through-hole 20 is completed earlier than the center of the through-hole 20, the plating is completed outside the through-hole 20. There is a problem in that there is an empty space 31 that is not plated. For example, the second through-electrode 40 formed in the through-hole 20 includes a dimple portion 41 having upper and lower surfaces that are not flat but curved (eg, a curved surface concave toward the center). there is In this case, when the dimple portion 41 is included on the surface of the second through electrode 40, the flatness of the substrate surface is reduced or the alignment is reduced when an additional insulating layer is stacked or an additional circuit pattern is formed. there is

In order to solve this problem, in the second comparative example, the inside of the through hole 20 is filled by a hole plugging method. However, the hole plugging method includes a plurality of plating processes and a hole plugging process, and thus the plating process becomes long. In addition, in the hole plugging process, since hole plugging is performed using plate making, there is a problem in that a part of the inside of the through hole is unfilled. At this time, the hole plugging process is a method of filling a part of the through hole with copper and filling the remaining part with a filler. However, the filler is made of a material different from the prepreg constituting the insulating layer 10 and the copper. Accordingly, the circuit board using the hole plugging method has a structure vulnerable to distortion due to a difference in thermal expansion coefficient between the prepreg, the copper, and the filler, and thus cracks easily occur.

Accordingly, in the embodiment, a through electrode having improved electrical and physical reliability can be formed inside the through hole formed in the core layer having a thickness of 300 μm or more. For example, in the embodiment, a circuit board including a through electrode having a novel structure and a package substrate including the same are provided.

-Electronic device-

Prior to the description of the embodiment, a package board having a structure in which a chip is mounted on a circuit board according to the embodiment may be included in an electronic device.

At this time, the electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly, the package substrate includes memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory, a central processor (eg, CPU), a graphic processor (eg, GPU), Application processor chips such as digital signal processors, cryptographic processors, microprocessors and microcontrollers, and logic chips such as analog-to-digital converters and application-specific ICs (ASICs) may be mounted.

In addition, the embodiment provides a package substrate capable of mounting at least two chips of different types on one substrate while reducing the thickness of the package substrate connected to the main board of the electronic device.

At this time, the electronic device includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer. ), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is not limited thereto, and may be any other electronic device that processes data in addition to these.

-circuit board-

2 is a diagram showing a circuit board according to a first embodiment, FIG. 3 is a diagram showing a circuit board according to a second embodiment, FIG. 4 is a diagram for explaining the insulating layer of FIG. 2, and FIG. It is a drawing for explaining the through electrode formed in FIG. 2 or FIG. 3 .

Hereinafter, a circuit board according to an embodiment will be described in detail with reference to FIGS. 2 to 5 .

Referring to FIGS. 2 to 5 , the circuit board may include an insulating layer 110 , a through electrode 120 , a first pattern layer 130 and a second pattern layer 140 .

The circuit board of the embodiment may have a multilayer structure. For example, the circuit board of the embodiment may include a plurality of insulating layers. However, in FIGS. 2 to 5 , a circuit board having a multilayer structure may include a core layer having an insulating layer disposed therein. Also, the penetration electrode 120 according to the embodiment may be formed to pass through the core layer 110 .

For example, the insulating layer 110 may be a core layer. In this embodiment, it is shown that the core layer 110 may have the same configuration as the insulating layer 110, but is not limited thereto, and the insulating layer 110 may further include other components in addition to the core layer 110.

For example, the insulating layer 110 may include prepreg. For example, the insulating layer 110 can improve the warpage of the circuit board by increasing the physical strength of the circuit board.

The prepreg constituting the insulating layer 110 of the embodiment has a structure in which an epoxy resin or the like is impregnated into a fiber layer in the form of a fabric sheet such as a glass fabric woven with glass yarn. can However, the prepreg constituting the insulating layer 110 of the embodiment may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

Specifically, the insulating layer 110 may include a resin and reinforcing fibers disposed in the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to an epoxy resin, and for example, one or more epoxy groups may be included in the molecule, two or more epoxy groups may be included, and, alternatively, four or more epoxy groups may be included. In addition, the resin constituting the insulating layer 110 may include a naphthalene group, and may be, for example, an aromatic amine type, but is not limited thereto. For example, the resin is bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenyl type epoxy resin, aralkyl type epoxy Resins, dicyclopentadiene type epoxy resins, naphthalene type epoxy resins, naphthol type epoxy resins, epoxy resins of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, biphenyl aralkyl type epoxy resins, fluorene type epoxies resins, xanthene-type epoxy resins, triglycidyl isocyanurate, rubber-modified epoxy resins, and phosphorous-type epoxy resins; naphthalene-type epoxy resins, bisphenol A-type epoxy resins, and phenol novolac epoxy resins; , cresol novolak epoxy resins, rubber-modified epoxy resins, and phosphorus-based epoxy resins. In addition, the reinforcing fibers may be glass fibers, carbon fibers, aramid fibers (eg, aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials. can The reinforcing fibers may be arranged to cross each other in a planar direction within the resin.

Meanwhile, glass fibers, carbon fibers, aramid fibers (eg, aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials may be used.

The insulating layer 110 of the embodiment may be divided into a plurality of regions. For example, the insulating layer 110 may be divided into a first region 111 , a second region 112 , and a third region 113 in the thickness direction. To this end, the insulating layer 110 may be divided into a plurality of parts in the thickness direction. However, in the embodiment, when the insulating layer 110 is divided into a plurality of parts, this is only for dividing the insulating layer 110 into a plurality of regions in the thickness direction, and is substantially a single insulating layer. can be configured.

For example, the insulating layer 110 may be divided into at least three regions in a thickness direction. Also, the densities of glass fibers included in the three regions of the insulating layer 110 may be different from each other.

For example, the insulating layer 110 includes a top surface (TS) and a bottom surface (BS). Also, a first pattern layer 130 and a second pattern layer 140 may be disposed on the lower surface BS and the upper surface TS of the insulating layer 110 , respectively. The insulating layer 110 includes a first region 111 adjacent to the lower surface BS of the insulating layer 110 and a second region 112 adjacent to the upper surface TS of the insulating layer 110. , It can be divided into a third area 113 between the first area 111 and the second area 112.

A density of glass fibers in the first region 111 may be different from a density of glass fibers in the third region 113 . Also, the density of glass fibers in the second region 112 may be different from the density of glass fibers in the third region 113 . For example, the density of glass fibers in the third region 113 of the insulating layer 110 may be greater than the density of glass fibers in each of the first region 111 and the second region 112 . there is.

In this case, the thicknesses of the first region 111, the second region 112, and the third region 113 may be different from each other. Accordingly, the weight percent of glass fibers in the first region 111 of the insulating layer 110 and the weight percent of glass fibers in the second region 112, respectively, of the insulating layer 110 3 may be less than the weight percent of glass fibers in region 113.

For example, in the embodiment, as shown in FIG. 2 , the first region 111 of the insulating layer 110 includes the first glass fiber 111-1, and the second region 112 includes the second region 112. 2 glass fibers 112-1 are included, and the third region 113 may include a third glass fiber 113-1. In this case, the weight % of the third glass fiber 113-1 is greater than the weight % of the first glass fiber 111-1 and the weight % of the second glass fiber 112-1, respectively. can

Unlike this, in the embodiment, as shown in FIG. 3 , glass fibers may not be included in the first region 111 and the second region 112 of the insulating layer 110, and the insulating layer 110 Glass fibers may be concentrated or densely included in the third region 113 of .

In conclusion, the insulating layer 110 in the embodiment is divided into a first region 111, a second region 112, and a third region 113 in the thickness direction, respectively. At this time, the third region 113 located in the center ) may include dense regions in which glass fibers are concentrated.

Accordingly, in the embodiment, when the through hole is formed in the insulating layer 110, the slope of the inner wall of the through hole in the insulating layer 110 may be different from each other due to the difference in the density of the glass fibers. For example, in the embodiment, the density of glass fibers may be high in the third region 113 so that the slope of the inner wall of the through hole formed in the third region 113 is substantially vertical. However, the embodiment is not limited thereto, and the through hole formed in the third region 113 may have a rectangular cross section through a method other than the density of the glass fiber.

However, in the embodiment, when glass fibers are included in each of the first region 111, the second region 112, and the third region 113 of the insulating layer 110, the bending characteristics of the circuit board can be further improved. Accordingly, as shown in FIG. 2 , glass fibers may be partially included in the first region 111 and the second region 112 of the insulating layer 110 .

Meanwhile, the insulating layer 110 as described above may be manufactured as shown in FIG. 4 .

For example, in the embodiment, the insulating layer 110 as shown in FIG. 2 or 3 may be formed by stacking a plurality of insulating layers.

To this end, in the embodiment, the first insulating part 110a and the second insulating part 110b of the insulating layer 110 may be prepared.

At this time, the first insulating part 110a has a 1-1 region 110a1 in which glass fibers are disposed adjacent to the lower surface of the first insulating part 110a and an upper surface of the first insulating part 110a. It may include the first-second region 110a2 adjacent to which the glass fiber is disposed.

In addition, the second insulating part 110b has a 2-1 region 110b1 in which glass fibers are disposed adjacent to the lower surface of the second insulating part 110b and an upper surface of the second insulating part 110b. It may include a 2-2 area 110b2 adjacent to which glass fibers are disposed.

Further, in the embodiment, the insulating layer 110 of FIG. 2 may be formed by performing thermal compression in a state in which the second insulating part 110b is disposed on the first insulating part 110a.

For example, the insulating layer 110 may include a first region 111 corresponding to the 1-1 region 110a1 of the first insulating part 110a. Also, the insulating layer 110 may include a second region 112 corresponding to the 2-2 region 110b2 of the second insulating part 110b. Further, the insulating layer 110 includes a third region 113 corresponding to the 1-2 region 110a2 of the first insulating part 110a and the 2-1 region 110b1 of the second insulating part 110b. ) may be included.

Accordingly, the third region 113 of the insulating layer 110 includes the 1-2 regions 110a2 including glass fibers in the first insulating part 110a and the glass fibers in the second insulating part 110b. It may be composed of a 2-1 area (110b1) including. Therefore, glass fibers may be densely formed in the third region 113 of the insulating layer 110 in the embodiment. For example, the insulating layer 110 in the embodiment may include a third region 113 that is a region in which glass fibers are concentrated. Further, the third region 113 includes a first region 111 adjacent to the lower surface BS of the insulating layer 110 and a second region 112 adjacent to the upper surface TS of the insulating layer 110. It can be an in-between area or a central area.

Meanwhile, when glass fibers are also included in the first region 111 and the second region 112 of the insulating layer 110, the density of glass fibers in the third region 113 is 111) and/or at least twice the density of glass fibers in the second region 112. For example, the density of glass fibers in the third region 113 is at least the density of glass fibers in the first region 111 and/or the density of glass fibers in the second region 112. It can be 3 times or more. For example, the density of glass fibers in the third region 113 is at least the density of glass fibers in the first region 111 and/or the density of glass fibers in the second region 112. It can be 5 times or more.

The insulating layer 110 may have a thickness of 300 μm or more. The thickness of the insulating layer 110 may be 350 μm or more. The thickness of the insulating layer 110 may be 400 μm or more. That is, the insulating layer 110 is a core layer, and thus may have a thickness of at least 300 μm or more in order to improve the bending characteristics of the circuit board in a packaging process while increasing the physical rigidity of the circuit board. And, in the embodiment, when the thickness of the insulating layer 110 is 300 μm or more as described above, in order to improve the physical reliability and electrical reliability of the through electrode 120 penetrating the insulating layer 110, the insulating layer 110 is formed in the thickness direction. divided into first to third regions. And, in the embodiment, the glass fibers are concentrated in the third region 113, which is the central region of the insulating layer 110.

However, the embodiment is not limited thereto, and even when the thickness of the insulating layer 110 is less than 300 μm, the insulating layer 110 is divided into three regions, and accordingly, a glass fiber dense region is formed in the center. You may. However, in the embodiment, the effect of forming the through electrode 120 on the insulating layer 110 including the third region 113 in which the glass fibers are dense is that the insulating layer 110 has a thickness of 300 μm or more. is maximized in the case of Accordingly, hereinafter, the insulating layer 110 will be described assuming that it has a thickness of 300 μm or more.

The first region 111 , the second region 112 , and the third region 113 constituting the insulating layer 110 may have different thicknesses. For example, the first region 111 may have a greater thickness than the third region 113 . The first region 111 and the second region 112 may have thicknesses corresponding to each other. However, embodiments are not limited thereto. For example, each of the first region 111 and the second region 112 of the insulating layer 110 may have a smaller thickness than the third region 113 .

The first region 111 of the insulating layer 110 may have a first thickness ranging from 75 μm to 150 μm. For example, the first region 111 may have a first thickness ranging from 80 μm to 130 μm. For example, the first region 111 may have a first thickness ranging from 90 μm to 120 μm. When the thickness of the first region 111 is less than 75 μm, the processability of through-holes in the third region 113 is deteriorated, and accordingly, the through-hole processing time may increase. When the thickness of the first region 111 exceeds 150 μm, the thickness of the third region 113 decreases accordingly, and thus the area of the via hole or the through electrode increases due to the third region 113 Increased effect may be insignificant.

The second region 112 of the insulating layer 110 may have a second thickness corresponding to the first region 111 . For example, the second region 112 may have a second thickness ranging from 75 μm to 150 μm. For example, the second region 112 may have a second thickness ranging from 80 μm to 130 μm. For example, the second region 112 may have a second thickness ranging from 90 μm to 120 μm.

Meanwhile, in an embodiment, the thickness of the third region 113 may be larger or smaller than the thickness of the first region 111 and the thickness of the second region 112 . However, when the thickness of the third region 113 is greater than the thickness of the first region 111 and the thickness of the second region 112, the area of the through hole and the through electrode can be maximized accordingly, Accordingly, hereinafter, the thickness of the third region 113 will be described as greater than the thickness of the first region 111 and the thickness of the second region 112 .

The third region 113 may have a third thickness T3 greater than the first thickness of the first region 111 or the second thickness of the second region 112 . For example, the third region 113 may have a third thickness ranging from 150 μm to 300 μm. For example, the third region 113 may have a third thickness ranging from 165 μm to 280 μm. For example, the third region 113 may have a third thickness ranging from 180 μm to 250 μm. If the thickness of the third region 113 is less than 150 μm, the effect of increasing the area of the through hole or through electrode by the third region 113 may be insignificant. For example, as the area of the via hole or the area of the through electrode in the third region 113 is increased, heat dissipation characteristics by the through electrode may be improved or defects such as voids or dimples in the through electrode may be solved. can However, when the thickness of the third region 113 is reduced, there may be no significant difference in the heat dissipation characteristic improvement or the effect of solving defects compared to the comparative example.

In addition, when the thickness of the third region 113 exceeds 300 μm, laser processability for forming a through hole in the third region 113 is deteriorated, and accordingly, processability may be complicated.

Meanwhile, each thickness of the first region 111, the second region 112, and the third region 113 of the insulating layer 110 may be determined by the total thickness of the core layer.

Further, the thickness of each of the first region 111 and the second region 112 is set to have a range between 35% and 65% of the thickness of the third region 113 . For example, the thickness of each of the first region 111 and the second region 112 is in a range of 38% to 62% of the thickness of the third region 113 . For example, the thickness of each of the first region 111 and the second region 112 is in a range of 40% to 58% of the thickness of the third region 113 . In addition, when the thickness of each of the first region 111 and the second region 112 is out of the range between 35% and 65% of the third region 113, the problems described above may occur. there is.

The circuit board of the embodiment includes a penetration electrode 120 penetrating the insulating layer 110 . For example, the through electrode 120 penetrates the first electrode part 121 passing through the first region 111 of the insulating layer 110 and the second region 112 of the insulating layer 110. and a third electrode part 123 penetrating the third region 113 of the insulating layer 110.

Specifically, the first electrode part 121 is disposed adjacent to the lower surface BS of the insulating layer 110 and has a width gradually decreasing toward the upper surface TS of the insulating layer 110. 1 may have an incline. The first inclination may refer to an inclination of a side surface of the first electrode part 121 with respect to the lower surface BS of the insulating layer 110 . Alternatively, the first inclination may refer to an inclination of the side surface of the first electrode part 121 with respect to the upper surface TS of the insulating layer 110 .

Also, the second electrode part 122 may be disposed on the first electrode part 121 . For example, the second electrode part 122 may be disposed adjacent to the upper surface TS of the insulating layer 110 . The second electrode part 122 may have a second slope such that a width gradually increases toward the upper surface TS of the insulating layer 110 . That is, the second electrode part 122 may have a second inclination different from the first inclination of the first electrode part 121 . The second inclination may refer to an inclination of a side surface of the second electrode part 122 with respect to a lower surface of the insulating layer 110 . Alternatively, the second inclination may refer to an inclination of a side surface of the second electrode part 122 with respect to an upper surface of the insulating layer 110 .

In other words, the first slope of the side surface of the first electrode part 121 with respect to the lower surface BS of the insulating layer 110 is the second electrode part with respect to the lower surface BS of the insulating layer 110. It may be different from the second slope of the side of (122). In addition, the first slope of the side surface of the first electrode part 121 with respect to the upper surface TS of the insulating layer 110 is the second electrode part 122 with respect to the upper surface TS of the insulating layer 110. ) may be different from the second slope of the side. For example, an inclined direction of the first electrode part 121 corresponding to the first inclination may be different from an inclined direction of the second electrode part 122 corresponding to the second inclination.

The third electrode part 123 may be disposed between the first electrode part 121 and the second electrode part 122 . The third electrode part 123 may have a third inclination different from the first inclination of the first electrode part 121 and the second inclination of the second electrode part 122 . The third inclination may refer to an inclination of a side surface of the third electrode part 123 with respect to the lower surface BS of the insulating layer 110 . Alternatively, the third inclination may refer to an inclination of the side surface of the third electrode part 123 with respect to the top surface TS of the insulating layer 110 .

In conclusion, the third slope of the side surface of the third electrode part 123 with respect to the lower surface BS of the insulating layer 110 is the first electrode part with respect to the lower surface BS of the insulating layer 110. It may be different from the first slope of the side surface of (121) and the second slope of the side surface of the second electrode part 122 with respect to the lower surface (BS) of the insulating layer 110. In addition, the third slope of the side surface of the third electrode part 123 with respect to the upper surface TS of the insulating layer 110 is the first electrode part 121 with respect to the upper surface TS of the insulating layer 110. ) may be different from the first slope of the side of the insulating layer 110 and the second slope of the side of the second electrode part 122 with respect to the upper surface TS of the insulating layer 110 . In this case, in one embodiment, the third slope may be perpendicular to the lower surface BS or the upper surface TS of the insulating layer 110 . Also, in another embodiment, the third inclination may have a certain inclination with respect to the lower surface BS or the upper surface of the insulating layer 110 . Further, when the third inclination has a predetermined inclination with respect to the lower or upper surface of the insulating layer 110, the predetermined inclination is different from the first inclination and the second inclination, and the first inclination and the second inclination are different. It may be any one of the angles between.

Accordingly, the side surface of the through electrode 120 of the embodiment may include a plurality of curved portions. For example, the side of the through electrode 120 includes a first curved portion formed at a boundary between the first electrode part 121 and the third electrode part 123, and the second electrode part 122 and the second electrode part 122. A second curved portion formed at the boundary of the third electrode part 123 may be included.

Meanwhile, the first electrode part 121, the second electrode part 122, and the third region 113 of the through electrode 120 as described above may be formed penetrating each region of the insulating layer 110. there is.

For example, the insulating layer 110 may include a through hole TH in which the through electrode 120 is disposed.

Specifically, the first region 111 of the insulating layer 110 may include the first hole part TH1 of the through hole TH in which the first electrode part 121 is disposed. Also, the first hole part TH1 may have a shape corresponding to the first electrode part 121 . For example, the first hole part TH1 may be disposed adjacent to the lower surface of the insulating layer 110 and gradually decrease in width toward the upper surface TS of the insulating layer 110 . For example, an inner wall of the first hole part TH1 may have an inclination corresponding to a first inclination of the first electrode part 121 .

Also, the second region 112 of the insulating layer 110 may include the second hole part TH2 of the through hole TH in which the second electrode part 122 is disposed. Also, the second hole part TH2 may have a shape corresponding to the second electrode part 122 . For example, the second hole part TH2 may be disposed adjacent to the upper surface of the insulating layer 110 and gradually increase in width toward the upper surface TS of the insulating layer 110 . For example, an inner wall of the second hole part TH2 may have an inclination corresponding to the second inclination of the second electrode part 122 .

Also, the third region 113 of the insulating layer 110 may include the third hole part TH3 of the through hole TH in which the third electrode part 123 is disposed. Also, the third hole part TH3 may have a shape corresponding to the third electrode part 123 . For example, the third hole part TH3 is disposed between the first hole part TH1 and the second hole part TH2, and the first hole part TH1 and the second hole part ( TH2) and may have a different slope. For example, an inner wall of the third hole part TH3 may have an inclination corresponding to a third inclination of the third electrode part 123 .

Meanwhile, the first hole part TH1, the second hole part TH2, and the third hole part TH3 form respective electrode parts corresponding to the through electrode 120, and the insulating layer It may be any one of a machining hole, a laser machining hole, and a chemical machining hole formed through (110).

In addition, the first electrode part 121, the second electrode part 122, and the third electrode part 123 are the first hole part TH1, the second hole part TH2, and the third hole part. It may be formed by filling the inside of (TH3) with a conductive material. For example, the insides of the first hole part TH1 , the second hole part TH2 , and the third hole part TH3 may be filled through a plating process. That is, the first hole part TH1 , the second hole part TH2 , and the third hole part TH3 may be formed by any one of mechanical processing, laser processing, and chemical processing. When the through hole is formed by machining, methods such as milling, drilling, and routing may be used, and when the through hole is formed by laser processing, a UV or CO ₂ laser method may be used. When formed by chemical processing, the first region 111 and the second region 112 can be opened using a chemical containing aminosilane, ketones, and the like.

On the other hand, the laser processing is a cutting method that melts and evaporates a part of the material by concentrating optical energy on the surface to take a desired shape, and can easily process complex formations by computer programs, and other methods Even difficult composite materials can be machined. In addition, the processing by the laser can cut a diameter of up to a minimum of 0.005 mm, and has the advantage of a wide range of processable thickness. As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO ₂ laser, or an ultraviolet (UV) laser. The YAG laser is a laser capable of processing both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser capable of processing only the insulating layer.

Accordingly, the first electrode part 121 filled in the first hole part TH1 may have a trapezoidal shape in which the width W1 of the upper surface is smaller than the width W2 of the lower surface, and the second hole part TH2 The second electrode part 122 filled in ) may have a trapezoidal shape in which the width W3 of the upper surface is greater than the width W4 of the lower surface. For example, the first electrode part 121 and the second electrode part 122 may have mutually symmetrical shapes around the third electrode part 123, but are not limited thereto.

Meanwhile, the third hole part TH3 is formed in the third region 113 corresponding to the glass fiber dense region of the insulating layer 110 .

At this time, in the case of forming a through hole in a general core layer, a process of forming grooves on the upper and lower sides of the core layer is performed, and the through hole is formed as the grooves are connected. Here, the conventional core layer has a uniform density of glass fibers over the entire area, and thus the through hole formed in the core layer has an hourglass shape. Unlike this, in the embodiment, the third region 113 of the insulating layer 110 includes a dense region in which glass fibers are concentrated. Accordingly, in the embodiment, a rectangular through hole may be formed in the third region 113 of the insulating layer 110, and thus the overall shape of the through hole or through electrode has at least three inclinations (an hourglass). including two slopes).

Meanwhile, as shown in FIG. 2 , the third region 113 includes a dense region of glass fibers, and is included in the third region 113 in the process of forming the third hole part TH3. At least a portion of the glass fibers may be exposed into the third hole part TH3. Also, the third electrode part 123 filling the third hole part TH3 may be formed to cover the glass fiber exposed into the third hole part TH3. At this time, the exposed glass fibers may function to increase the roughness of the inner wall of the through hole. Based on this, in the embodiment, bonding strength between the insulating layer 110 and the through electrode 120 may be improved.

Meanwhile, the third hole part TH3 has one side connected to the first hole part TH1 and the other side connected to the second hole part TH2. The third hole part TH3 is formed in the third region 113 of the insulating layer 110 in which the glass fibers are concentrated, and thus, the width of the upper surface thereof may be the same as the width of the lower surface thereof.

Furthermore, in the embodiment, the width of the lower surface of the third hole part TH3 may be the same as the width W1 of the upper surface of the first hole part TH1. Also, in the embodiment, the width of the upper surface of the third hole part TH3 may be the same as the width W4 of the lower surface of the second hole part TH2.

For example, the width of the upper surface of the third hole part TH3 may range from 95% to 105% of the width of the lower surface of the third hole part TH3.

Accordingly, in the embodiment, the width of the lower surface of the third hole part TH3 may range from 95% to 105% of the width of the upper surface of the first hole part TH1.

Also, in the embodiment, the width of the upper surface of the third hole part TH3 may be in the range of 95% to 105% of the width of the lower surface of the second hole part TH2.

For example, the width of the third hole part TH3 may be smaller than the width of the part having the largest width in the first hole part TH1. Also, the width of the third hole part TH3 may be the same as that of the smallest part of the first hole part TH1.

For example, the width of the third hole part TH3 may be smaller than that of the part having the largest width in the second hole part TH2. Also, the width of the third hole part TH3 may be the same as that of the smallest part of the second hole part TH2.

Meanwhile, the width of the lower surface of the first hole part TH1 may correspond to the width of the lower surface of the first electrode part 121 . Also, the width of the upper surface of the first hole part TH1 may correspond to the width of the upper surface of the first electrode part 121 .

Also, the width of the upper surface of the second hole part TH2 may correspond to the width of the upper surface of the second electrode part 122 . Also, the width of the lower surface of the second hole part TH2 may correspond to the width of the lower surface of the second electrode part 122 .

Also, the width of the upper surface of the third hole part TH3 may correspond to the width of the upper surface of the third electrode part 123 . Also, the width of the lower surface of the third hole part TH3 may correspond to the width of the lower surface of the third electrode part 123 .

Meanwhile, the first pattern layer 130 is disposed on the lower surface BS of the insulating layer 110 according to the embodiment, and the second pattern layer 140 is disposed on the upper surface TS of the insulating layer 110 . The first pattern layer 130 and the second pattern layer 140 may include at least one pad connected to the through electrode 120 and a trace connected to the pad. For example, the first pattern layer 130 may include a first pad connected to the lower surface of the through electrode 120 (eg, the lower surface of the first electrode part 121). For example, the second pattern layer 140 may include a second pad connected to the top surface of the through electrode 120 (eg, the top surface of the second electrode part 122).

The first pad of the first pattern layer 130 may have a greater width than the first electrode part 121 . For example, the first pad of the first pattern layer 130 may have a greater width than the width W2 of the lower surface of the first electrode part 121 . Accordingly, in the embodiment, the first pad of the first pattern layer 130 covers the lower surface of the first electrode part 121 as a whole and is disposed so that the function of the first pad (for example, signal transmission , heat dissipation or shielding) reliability (eg, signal transfer characteristics, heat dissipation characteristics, shielding characteristics) can be improved.

The second pad of the second pattern layer 140 may have a greater width than the second electrode part 122 . For example, the second pad of the second pattern layer 140 may have a greater width than the width W3 of the upper surface of the second electrode part 122 . Accordingly, in the embodiment, the second pad of the second pattern layer 140 covers the upper surface of the second electrode part 122 as a whole and is disposed so that the function of the second pad (eg, signal transmission , heat dissipation or shielding) reliability (eg, signal transfer characteristics, heat dissipation characteristics, shielding characteristics) can be improved.

The first pattern layer 130 and the second pattern layer 140 are made of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc ( It may be formed of at least one metal material selected from Zn).

In addition, the first pattern layer 130 and the second pattern layer 140 are made of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper ( It may be formed of a paste or solder paste containing at least one metal material selected from Cu) and zinc (Zn). Preferably, the first pattern layer 130 and the second pattern layer 140 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The first pattern layer 130 and the second pattern layer 140 are formed using an additive process, a subtractive process, a modified semi-additive process (MSAP) and SAP (Semi Additive Process) method, etc., and detailed description is omitted here.

As described above, in the embodiment, when the penetration electrode 120 is formed on the insulating layer 110, which is a core layer having a thickness of a certain thickness or more (eg, 300 μm or more), the insulating layer 110 is divided into a plurality of regions. and, accordingly, electrode parts (eg, first to third electrode parts) penetrating the respective regions are formed. Accordingly, in the embodiment, the physical reliability and electrical reliability of the through electrode 120 can be improved by solving the void problem in the center of the through electrode 120 while increasing the area of the through electrode 120. let it be In addition, in the embodiment, the third electrode part 123 disposed in the center among the plurality of electrode parts constituting the through electrode 120 is formed in the glass fiber dense region, and thus has a shape in which the upper and lower surfaces have substantially the same width. have Accordingly, in the embodiment, the area of the through electrode can be increased compared to the through electrode having an hourglass shape in the comparative example, and thus, the effect according to the function of the through electrode can be maximized. For example, when the through electrode functions as a signal shielding function, the signal shielding effect can be further improved. For example, when the through electrode functions to dissipate heat, heat dissipation characteristics may be further improved.

In addition, in the embodiment, the width of the first electrode part 121 and the second electrode part 123, not the third electrode part 123, may be increased, but the first electrode part 121 and the second electrode part 121 may have different widths. When the width of the electrode part 123 increases, the arrangement space of the first pattern layer 130 or the second pattern layer 140 decreases, and thus the density of circuit patterns may decrease, and accordingly, the circuit board The volume in the width direction or the length direction of may increase. In contrast, even if the width of the third electrode part 123 increases in the embodiment, the first pattern layer 130 or the second pattern layer 140 is not affected at all. This means that the third electrode part 123 is disposed at the center of the insulating layer 110, and there is no pattern layer spaced apart from the third electrode part 123 in the longitudinal direction or width direction (horizontal direction in the drawing). because it doesn't

Hereinafter, first to third inclinations of the first electrode part 121 , the second electrode part 122 , and the third electrode part 123 according to the embodiment will be described. At this time, the first hole part TH1, the second hole part TH2, and the third hole part in which the first electrode part 121, the second electrode part 122, and the third electrode part 123 are disposed The inclination of each inner wall of (TH3) may correspond to the first to third inclinations of the first electrode part 121, the second electrode part 122, and the third electrode part 123, respectively.

6A is a view for explaining the inclination of the side surfaces of the first electrode part and the second electrode part according to the embodiment, and FIG. 6B is a view for explaining the inclination of the side surface of the third electrode part according to the embodiment.

Hereinafter, the inclination of each side surface of the first electrode part 121, the second electrode part 122, and the third electrode part 123 will be described with reference to FIGS. 6A and 6B.

The first to third slopes of the side surfaces of the first electrode part 121, the second electrode part 122, and the third electrode part 123 are relative to the top surface TS of the insulating layer 110. It may be an inclination, or alternatively it may be an inclination with respect to the lower surface (BS).

As shown in (a) of FIG. 6A , the side surface of the first electrode part 121 may have a first slope with respect to the upper surface TS of the insulating layer 110 . For example, an interior angle θ1 between the top surface TS of the insulating layer 110 and the side surface of the first electrode part 121 having the first slope may be an acute angle.

Alternatively, as shown in (b) of FIG. 6A, the side surface of the second electrode part 122 may have a second slope different from the first slope with respect to the top surface TS of the insulating layer 110. . For example, an interior angle θ2 between the top surface TS of the insulating layer 110 and the side surface of the second electrode part 122 having the second slope may be an obtuse angle.

Meanwhile, as shown in (c) of FIG. 6A , the side surface of the first electrode part 121 may have a first slope with respect to the lower surface BS of the insulating layer 110 . For example, an interior angle θ3 between the lower surface BS of the insulating layer 110 and the side surface of the first electrode part 121 having the first slope may be an obtuse angle.

Alternatively, as shown in (d) of FIG. 6A, the side surface of the second electrode part 122 may have a second slope different from the first slope with respect to the lower surface BS of the insulating layer 110. . For example, an interior angle θ4 between the lower surface BS of the insulating layer 110 and the side surface of the second electrode part 122 having the second slope may be an obtuse angle.

Meanwhile, as shown in FIG. 6B , the third electrode part 123 has a third inclination different from the first inclination of the first electrode part 121 and the second inclination of the second electrode part 122. can have

The third inclination may refer to an inclination of the side surface of the third electrode part 123 with respect to the upper surface TS of the insulating layer 110, and differently to the lower surface BS of the insulating layer 110. It may mean the slope of the side of the third electrode part 123 for the

Specifically, the side surface of the third electrode part 123 may have a third inclination different from the first and second inclinations with respect to the upper surface TS of the insulating layer 110 . For example, an interior angle θ5 between the top surface TS of the insulating layer 110 and the side surface of the third electrode part 123 having the third slope may be a right angle. For example, an interior angle θ6 between the lower surface BS of the insulating layer 110 and the side surface of the third electrode part 123 having the third inclination may be a right angle. However, the embodiment is not limited thereto, and the third inclination with respect to the side surface of the third electrode part 123 may be different from the first inclination and the second inclination without being perpendicular. For example, the third inclination with respect to the side surface of the third electrode part 123 may be any one of inclinations included in a range between the first inclination and the second inclination.

7 is a diagram illustrating a circuit board according to another embodiment.

The circuit board of FIG. 7 may refer to a circuit board having a multilayer structure including the circuit boards of FIGS. 2 and 3 as core layers.

For example, the circuit board may include the circuit boards of FIGS. 2 and 3 as a core layer.

That is, the circuit board may have a three-layer structure based on the number of insulating layers. However, the embodiment is not limited thereto, and the circuit board may have a two-layer structure, or may have four or more layers.

Also, a circuit board having a multilayer structure may include the insulating layer 110 of FIG. 2 or 3 as the first insulating layer 110 serving as a core layer. And, as described above, the first insulating layer 110 includes the first to third regions 111, 112, and 113, and among them, the third region 113 may include a dense region of glass fibers. there is.

In addition, the circuit board may include a through electrode 120 penetrating the first insulating layer 110 . Also, the penetration electrode 120 may include a first electrode part 121, a second electrode part 122, and a third electrode part 123 penetrating each region of the first insulating layer 110. there is.

In addition, a first pattern layer 130 may be disposed on a lower surface of the first insulating layer 110 , and a second pattern layer 140 may be disposed on an upper surface of the first insulating layer 110 .

In addition, the circuit board may include a second insulating layer 150 disposed under the first insulating layer 110 . In this case, the second insulating layer 150 may refer to a lowermost insulating layer disposed on the lowermost side of the multi-layered circuit board. For example, when the circuit board has four or more layers, at least one insulating layer (not shown) and a pattern layer (not shown) are interposed between the first insulating layer 110 and the second insulating layer 150. This can be further placed.

In addition, the circuit board may include a second through electrode 155 penetrating the second insulating layer 150 and a third pattern layer 160 disposed on a lower surface of the second insulating layer 150 .

In addition, the circuit board may include a third insulating layer 170 disposed on the first insulating layer 110 . The third insulating layer 170 may refer to an uppermost insulating layer disposed on the uppermost side of a multi-layered circuit board. For example, when the circuit board has four or more layers, at least one insulating layer (not shown) and a pattern layer 160 may be formed between the first insulating layer 110 and the third insulating layer 170 . This can be further placed.

In addition, the circuit board may include a third through electrode 175 penetrating the third insulating layer 170 and a fourth pattern layer 180 disposed on the upper surface of the third insulating layer 170. .

In addition, the circuit board may include a first protective layer 190 and a second protective layer 195 . The first protective layer 190 is disposed on the upper surface of the second insulating layer 150 and may include an opening (not shown) exposing a part of the lower surface of the third pattern layer 160 . In addition, the second protective layer 195 is disposed on the upper surface of the third insulating layer 170 and may include an opening (not shown) exposing a part of the upper surface of the fourth pattern layer 180. . The first protective layer 190 and the second protective layer 195 may be solder resists that protect the lower surface of the second insulating layer 150 and the upper surface of the third insulating layer 160, but are limited thereto It is not.

-Package Substrate-

8 is a view showing a package substrate according to an embodiment.

Referring to FIG. 8 , a package substrate according to an exemplary embodiment includes a circuit board of FIG. 7 , at least one chip mounted on the circuit board, and a molding layer for molding the chip and a connection part for connecting the chip or an external board. includes

For example, the package substrate of the embodiment may include the first connector 210 disposed on the fourth pattern layer 180, which is the outermost pattern layer. The cross section of the first connection part 210 may include a circular shape or a semicircular shape. For example, the cross section of the first connector 210 may include a partially or entirely rounded shape. A cross-sectional shape of the first connector 210 may be a flat surface on one side and a curved surface on the other side. The first connector 210 may be a solder ball, but is not limited thereto.

Meanwhile, in the embodiment, the chip 220 disposed on the first connector 210 may be included. The chip 220 may be a processor chip. For example, the chip 220 may be an application processor (AP) chip among a central processor (eg, CPU), a graphic processor (eg, GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller. The terminal 225 of the chip 220 may be connected to the fourth pattern layer 180 through the first connector 210 . For example, the fourth pattern layer 180 may include a mounting pad on which the chip 220 is mounted.

Also, although not shown in the drawing, the package substrate according to the embodiment may further include an additional chip. For example, in an embodiment, at least two chips of a central processor (eg, CPU), a graphic processor (eg, GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller are spaced apart on the circuit board. can be placed separately. For example, the chip 220 in the embodiment may include a central processor chip and a graphic processor chip, but is not limited thereto.

Meanwhile, the plurality of chips may be spaced apart from each other at regular intervals on the circuit board. For example, the spacing between the plurality of chips may be 150 μm or less. For example, the spacing between the plurality of chips may be 120 μm or less. For example, the spacing between the plurality of chips may be 100 μm or less.

Preferably, the distance between the plurality of chips may range from 60 μm to 150 μm. Preferably, the distance between the plurality of chips may range from 70 μm to 120 μm. Preferably, the spacing between the plurality of chips may have a range of 80 μm to 110 μm. If the spacing between the plurality of chips is less than 60 μm, a problem may occur in operation reliability due to mutual interference between the plurality of chips. When the distance between the plurality of chips is greater than 150 μm, signal transmission loss may increase as the distance between the plurality of chips increases. When the spacing between the plurality of chips is greater than 150 μm, the volume of the package substrate may increase.

The package substrate may include a molding layer 230 . The molding layer 230 may be disposed while covering the chip 220 . For example, the molding layer 230 may be EMC (Epoxy Mold Compound) formed to protect the mounted chip 220, but is not limited thereto.

In this case, the molding layer 230 may have a low dielectric constant in order to increase heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding layer 230 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 230 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 230 may be 0.8 to 5. Accordingly, in the embodiment, the molding layer 230 has a low permittivity, so that heat dissipation characteristics for heat generated from the chip 220 can be improved.

Meanwhile, the package substrate may include the second connector 240 disposed on the lowermost side of the circuit board. The second connector 240 may be disposed on a lower surface of the third pattern layer 160 exposed through the first protective layer 190 .

-Manufacturing method-

Hereinafter, a method of manufacturing the circuit board shown in FIG. 2 according to an embodiment will be described in the order of processes.

9 to 14 are diagrams illustrating a manufacturing method of the circuit board shown in FIG. 2 in order of processes.

Referring to FIG. 9 , in the embodiment, an insulating layer 110, which is a basis for manufacturing a circuit board, may be prepared.

Specifically, the insulating layer 110 may include a plurality of regions in a thickness direction. For example, the insulating layer 110 may include a first region 111 adjacent to the lower surface BS, a second region 112 adjacent to the upper surface TS, and a third region 113 therebetween. .

In addition, the insulating layer 110 may have a structure in which glass fibers are concentrated in the third region 113 .

The insulating layer 110 may be manufactured by thermally compressing a plurality of insulating parts. Since this has already been described above with reference to FIG. 5, a detailed description thereof will be omitted.

Meanwhile, a metal layer may be formed on the surface of the insulating layer 110 .

For example, a first metal layer M1 may be formed on the lower surface BS of the insulating layer 110 . In addition, a second metal layer M2 may be formed on the upper surface TS of the insulating layer 110 .

The first metal layer M1 and the second metal layer M2 may be copper foil layers.

Also, the first metal layer M1 and the second metal layer M2 may mean a copper foil layer of CCL (Copper Clad Laminate) in which a copper foil layer is stacked on the insulating layer 110 .

Alternatively, the first metal layer M1 and the second metal layer M2 may be formed by performing electroless plating on the upper surface TS and the lower surface BS of the insulating layer 110 , respectively.

Next, referring to FIG. 10 , in the embodiment, a process of forming a first groove VH1-1 on the upper side of the insulating layer 110 by performing primary laser processing on the upper side of the insulating layer 110. can proceed.

At this time, in the general insulating layer, when the first groove is formed, the first groove has a trapezoidal shape in which the width is narrowed from the upper side to the lower side.

Unlike this, in the embodiment, the first groove VH1 - 1 passes through the second region 112 of the insulating layer 110 and partially penetrates the third region 113 of the insulating layer 110 . It can be formed openly. At this time, in the embodiment, the first groove VH1 - 1 has a trapezoidal shape in the second area 112 and a rectangular shape in the third area 113 .

Next, referring to FIG. 11 , in the embodiment, a process of forming second grooves VH1-2 on the lower side of the insulating layer 110 by performing secondary laser processing on the lower side of the insulating layer 110. can proceed.

At this time, the second groove (VH1-2) may communicate with the first groove (VH1-1), thereby forming one through hole (VH) connected to each other.

Here, the second groove VH1 - 2 may be formed by opening a part of the third region 113 of the insulating layer 110 while penetrating the first region 111 of the insulating layer 110 . can At this time, in the embodiment, the second groove VH1 - 2 has a trapezoidal shape in the first area 111 and a rectangular shape in the third area 113 .

Next, referring to FIG. 12, in an embodiment, seed layers 121-1 and 122-1 are formed on the inner walls of the first metal layer M1, the second metal layer M2, and the through hole VH. process can proceed.

The seed layers 121-1 and 122-1 may be formed by performing a chemical copper plating process.

Next, in the embodiment, a process of forming dry films DF1 and DF2 on the seed layers 121-1 and 122-1 may be performed.

In the embodiment, the dry films DF1 and DF2 are exposed and developed to expose the first pattern layer 130, the second pattern layer 130, and the through electrode 120. can form

Next, referring to FIG. 13, in the embodiment, electrolytic plating is performed using the seed layers 121-1 and 122-1 to fill the openings of the dry films DF1 and DF2. The first pattern layer ( 130), the second pattern layer 140, and the through electrode 120 may be formed.

Accordingly, the through electrode 120 may substantially include seed layers 121-1 and 122-1 and a plating layer formed by performing electrolytic plating using the seed layers 121-1 and 122-1. can

In addition, the first pattern layer 130 and the second pattern layer 140 include the metal layers M1 and M2, the seed layers 121-1 and 122-1, and the seed layers 121-1 and 122-1. 1) may include a plating layer electrolytically plated using.

Next, referring to FIG. 14 , in the embodiment, a process of removing the dry films DF1 and DF2 may be performed.

In the embodiment, an etching process may be performed to remove portions of the seed layers 121-1 and 122-1 and the metal layers M1 and M2.

In the embodiment, when the through electrode is formed on an insulating layer that is a core layer having a predetermined thickness or more (eg, 300 μm or more), the insulating layer is divided into a plurality of regions in the thickness direction. And, in the embodiment, a dense region of glass fibers is included in a central region among a plurality of regions of the insulating layer. Further, in the embodiment, a through hole is formed in the insulating layer including the dense region, and the formed through hole is filled with a conductive material to form a through electrode. Accordingly, in the embodiment, when filling the through hole, it is possible to solve the void problem in which the central region of the through hole is not filled, and thereby improve the physical reliability and electrical reliability of the through electrode.

Accordingly, the central region of the through hole and the through electrode in the embodiment may have a rectangular shape instead of an hourglass shape. Therefore, in the embodiment, compared to the comparative example having an hourglass shape, it is possible to increase the area of the through hole and the through electrode in the central region, thereby maximizing the effect according to the function of the through electrode. For example, when the through electrode functions as a signal shield, the signal shield effect can be further improved. For example, when the through electrode functions to dissipate heat, heat dissipation characteristics may be further improved.

Furthermore, in the embodiment, since a dense region of glass fibers is included in the central region of the insulating layer, a portion of the glass fibers may be exposed in the central region of the through hole. Also, the through electrode in the embodiment may be formed to cover the glass fiber exposed through the through hole. At this time, the exposed glass fiber functions to increase the roughness of the inner wall of the through hole, and thus, bonding force between the insulating layer and the through electrode may be improved during formation of the through electrode. Accordingly, in the embodiment, it is possible to solve a problem in which the through electrode is separated from the insulating layer due to warpage occurring in various use environments of the circuit board, thereby improving physical reliability and electrical reliability of the circuit board. can make it

Features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, and effects illustrated in each embodiment can be combined or modified with respect to other embodiments by those skilled in the art in the field to which the embodiments belong. Therefore, contents related to these combinations and modifications should be construed as being included in the scope of the embodiments.

Although the above has been described centering on the embodiment, this is only an example and does not limit the embodiment, and those skilled in the art in the field to which the embodiment belongs may find various things not exemplified above to the extent that they do not deviate from the essential characteristics of the embodiment. It will be appreciated that variations and applications of branches are possible. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the embodiments set forth in the appended claims.

Claims (15)

An insulating layer including upper and lower surfaces; and
A through electrode penetrating the upper and lower surfaces of the insulating layer,
The through electrode is
a first electrode part disposed adjacent to a lower surface of the insulating layer and having a first slope such that a width gradually decreases toward the upper surface of the insulating layer;
a second electrode part disposed on the first electrode part and having a second slope such that a width thereof gradually increases toward an upper surface of the insulating layer; and
A third electrode part disposed between the first electrode part and the second electrode part and having a third inclination different from the first and second inclinations,
A width of the third electrode part is equal to a width of a region having the smallest width among the first and second electrode parts. An insulating layer including upper and lower surfaces and a through hole penetrating the upper and lower surfaces,
The through hole,
a first hole part disposed adjacent to a lower surface of the insulating layer and having a first slope such that a width gradually decreases toward the upper surface of the insulating layer;
a second hole part disposed on the first hole part and having a second slope such that a width gradually increases toward the upper surface; and
A third hole part disposed between the first hole part and the second hole part and having a third inclination different from the first and second inclinations,
A width of the third hole part is equal to a width of a region having the smallest width among the first and second hole parts. According to claim 2,
The circuit board,
A through electrode penetrating the insulating layer and corresponding to the through hole;
The through electrode is
A first electrode part corresponding to the first hole part;
A second electrode part corresponding to the second hole part;
A circuit board comprising a third electrode part corresponding to the third hole part. According to claim 1 or 3,
The third electrode part has the same width on the upper and lower surfaces,
The width of the lower surface of the third electrode part is equal to the width of the region having the smallest width in the first electrode part,
A width of the upper surface of the third electrode part is equal to a width of a region having a small width in the second electrode part. According to claim 1 or 3,
The insulating layer is
A first region in which the first electrode part is disposed;
A second region in which the second electrode part is disposed;
A third region in which the third electrode part is disposed,
The density of the glass fibers in the third region,
greater than the density of glass fibers in the first and second regions. According to claim 5,
The insulating layer is
A first insulating part and a second insulating part over the first insulating part,
The first insulating part
A 1-1 region adjacent to the lower surface of the insulating layer and a 1-2 region adjacent to the lower surface of the insulating layer,
The second insulating part,
A 2-1 region adjacent to the lower surface of the insulating layer and a 2-2 region adjacent to the upper surface of the insulating layer,
The first region of the insulating layer,
Corresponds to the 1-1 region of the first insulating part,
The second region of the insulating layer corresponds to the 2-1 region of the second insulating part,
The third region of the insulating layer,
Corresponding to the 1-2 region of the first insulating part and the 2-1 region of the second insulating part, the circuit board. According to claim 1 or 3,
a first pad disposed on a lower surface of the insulating layer and connected to the first electrode part; and
Disposed on the upper surface of the insulating layer, including a second pad connected to the second electrode part,
circuit board. According to claim 7,
A width of a portion closest to the first pad of the first electrode part is smaller than a width of the first pad;
The width of the part closest to the second pad of the second electrode part is smaller than the width of the second pad,
circuit board. According to claim 1 or 3,
The width of the upper surface of the third electrode part is
Satisfying the range between 95% and 105% of the width of the lower surface of the third electrode part,
circuit board. According to claim 1 or 3,
The third slope,
Perpendicular to the upper or lower surface of the insulating layer,
circuit board. According to claim 1 or 3,
The first electrode part and the second electrode part,
Having a mutually symmetrical shape around the third electrode part,
circuit board. According to claim 1 or 3,
The first slope and the second slope are inclined in different directions,
circuit board. According to claim 1 or 3,
The insulating layer includes a prepreg containing resin and glass fibers,
circuit board. According to claim 1 or 3,
The first electrode part has a trapezoidal shape in which the width of the lower surface is greater than the width of the upper surface,
The second electrode part has a trapezoidal shape in which the width of the lower surface is smaller than the width of the upper surface,
The third electrode part has a rectangular shape in which the width of the lower surface and the width of the upper surface are the same,
circuit board. a circuit board including mounting pads;
a connection part disposed on the mounting pad of the circuit board;
a chip disposed on the connection portion; and
A molding layer for molding the chip;
The circuit board,
An insulating layer including upper and lower surfaces; and
A through electrode penetrating the upper and lower surfaces of the insulating layer,
The through electrode,
a first electrode part disposed adjacent to a lower surface of the insulating layer and having a first slope such that a width gradually decreases toward the upper surface of the insulating layer;
a second electrode part disposed on the first electrode part and having a second slope such that a width thereof gradually increases toward an upper surface of the insulating layer; and
A third electrode part disposed between the first electrode part and the second electrode part and having a third inclination different from the first and second inclinations,
The width of the part closest to the third electrode part of the first electrode part is the same as the width of the third electrode part,
The width of the part closest to the third electrode part of the second electrode part is the same as the width of the third electrode part,
The third slope is perpendicular to the upper or lower surface of the insulating layer,
The chip includes a first chip and a second chip disposed spaced apart from each other in the width direction;
The first chip corresponds to a central processor (CPU),
The second chip corresponds to a graphics processor (GPU),
package substrate.

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