KR20220129196A - Lateral Type VCSEL Chip, VCSEL Array and Method for Manufacturing thereof Using Transfer - Google Patents

Abstract

Disclosed are a horizontal-type VCSEL chip, a VCSEL array, and a manufacturing method therefor using transcription. According to one aspect of the present embodiment, provided is the VCSEL array that is characterized in comprising: a substrate; an adhesive layer coated on the substrate; a VCSEL chip that is disposed and fixed on the adhesive layer, and oscillates a light or a laser upon receiving power; a polymer coated on the VCSEL chip and the adhesive layer; and an interconnector electrically connected to the VCSEL chip.

Description

Horizontal Type VCSEL Chip, VCSEL Array, and Manufacturing Method Thereof Using Transfer

The present invention relates to a horizontal micro VCSEL, a VCSEL array including the same, and a method for manufacturing a VCSEL array by performing transfer.

The content described in this section merely provides background information for the present embodiment and does not constitute the prior art.

In general, semiconductor laser diodes are a side-emitting laser diode (EEL, Edge Emitting Laser Diode, hereinafter abbreviated as 'EEL') and a vertical resonance type surface emitting laser diode (VCSEL: Vertical Cavity Surface Emitting Laser, hereinafter abbreviated as 'VCSEL'). ) is included. Since the EEL has a resonance structure that is parallel to the stacking surface of the device, it oscillates a laser beam in a direction parallel to the stacked surface, and the VCSEL has a resonance structure that is perpendicular to the stacked surface of the device, so that the laser beam is converted into an element. oscillate in a direction perpendicular to the lamination plane of

VCSEL has a shorter optical gain length than EEL, so it can realize low power, and since high-density integration is possible, it is advantageous for mass production. In addition, the VCSEL can oscillate a laser beam in a single-ended mode (Single Longitudinal Mode) and can be tested on a wafer. Furthermore, since the VCSEL is capable of high-speed modulation and can oscillate a circular beam, coupling with an optical fiber is easy and a two-dimensional surface array is possible.

VCSELs have been mainly used as light sources in optical devices in optical communication, optical interconnection, optical pickup, and the like. However, in recent years, the VCSEL has been extended to a light source in an image forming apparatus such as LiDAR, facial recognition, motion recognition, AR (Augmented Reality), or VR (Virtual Reality).

As such, VCSELs are used in various fields, and there arises a need to appropriately manufacture a VCSEL chip or a VCSEL array depending on the application. Conventionally, only a two-dimensional array using a GaAs substrate on which an epitaxial layer is grown has been used. As such, the two-dimensional array contained the GaAs substrate used for growth of the VCSEL epitaxial layer, and thus the curvature could not be formed. Accordingly, there is considerable inconvenience in constructing a two-dimensional array such as a LiDAR light source that requires curvature.

An embodiment of the present invention has an object to provide a VCSEL chip, a VCSEL array, and a method of manufacturing a VCSEL array in a transfer manner.

According to an aspect of the present invention, a substrate and an adhesive layer coated on the substrate, a VCSEL chip disposed on and fixed on the adhesive layer, receiving power to oscillate light or laser, the VCSEL chip, and a polymer coated on the adhesive layer and an interconnector electrically connected to the VCSEL chip.

According to an aspect of the present invention, the VCSEL chip includes a first reflector including a plurality of DBR (Distributed Bragg Reflector) pairs, a second reflector including a plurality of DBR pairs, the first reflector, and the second A cavity layer located between the reflection units, in which holes generated in any one of the first reflection unit and the second reflection unit and electrons generated in the other one are recombine, the cavity layer, and the first reflection unit or the second reflection unit An oxide film layer that is located between the reflective parts and determines the characteristics of the laser to be output and the diameter of the opening, and a contact layer formed in one DBR pair of the second reflective part and the first reflective part come into contact with the first reflective part to be in contact with the first reflective part The first metal layer through which power can be supplied and the contact layer are in contact with the second metal layer through which power can be supplied to the second reflecting unit, and located at the lower end of the second reflecting unit, in the etching process. An etch-stop layer for preventing damage that may occur on the second reflective part, and a passivation layer for protecting the first reflective part, the second reflective part, the cavity layer, the oxide layer, the contact layer, and the etch-stop layer from the outside. characterized by including.

According to an aspect of the present invention, the second reflector includes more DBR pairs than the first reflector.

According to one aspect of the present invention, the contact layer is characterized in that it has a mesa structure.

According to an aspect of the present invention, the second metal layer is disposed in the mesa structure and is in contact with the contact layer.

According to one aspect of the present invention, the etch stop layer is characterized in that it has a mesa structure.

According to an aspect of the present invention, the passivation layer is characterized in that it is applied to a part or all of the mesa structure of the etch stop layer.

According to one aspect of the present invention, the VCSEL chip is characterized in that it includes one or more output units.

According to one aspect of the present invention, the VCSEL chip is characterized in that it has a cross section of a predetermined shape.

According to one aspect of the present invention, the preset shape is characterized in that it has the same shape even when rotated by a preset angle.

According to one aspect of the present invention, the preset shape is characterized in that it differs according to the number of output units included in the VCSEL chip.

According to an aspect of the present invention, when the VCSEL chip includes a plurality of output units, light or laser of the same or different wavelength is output from each output unit.

According to one aspect of the present invention, in a method of manufacturing a VCSEL array, a first arrangement in which the VCSEL chip of any one of claims 2 to 11 is disposed on the coating layer and the coating process in which an adhesive layer is coated on a substrate A process, a coating process in which a polymer is coated and cured on the VCSEL chip, a removal process of removing the polymer coated on each metal layer of the VCSEL chip, and a first step of disposing an interconnector on each metal layer of the VCSEL chip It provides a method for manufacturing a VCSEL array comprising two batch processes.

As described above, according to one aspect of the present invention, there is an advantage that the VCSEL chip can be manufactured as a VCSEL array by the transfer method.

1 is a cross-sectional view of a VCSEL array according to an embodiment of the present invention.
2 is a cross-sectional view in one direction of a VCSEL chip according to an embodiment of the present invention.
3 is a cross-sectional view in another direction of a VCSEL epitaxy according to an embodiment of the present invention.
4 is a schematic plan view of a VCSEL chip in a VCSEL array according to an embodiment of the present invention.
5 to 10 are flowcharts illustrating a method of manufacturing a VCSEL array according to an embodiment of the present invention.

Since the present invention can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to a specific embodiment, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numerals have been used for like elements.

Terms such as first, second, A, and B may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that no other element is present in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. It should be understood that terms such as “comprise” or “have” in the present application do not preclude the possibility of addition or existence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification in advance. .

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. does not

In addition, each configuration, process, process or method included in each embodiment of the present invention may be shared within a range that does not technically contradict each other.

1 is a cross-sectional view of a VCSEL array according to an embodiment of the present invention.

Referring to FIG. 1 , a VCSEL array 100 according to an embodiment of the present invention includes a substrate 110 , an adhesive layer 120 , a VCSEL chip 130 , a polymer 140 , and interconnectors 150 and 155 . do.

A VCSEL array (Vertical Cavity Surface Emitting Laser Array, 100) refers to an optical device in which a plurality of VCSEL chips 130 are arranged in an array form and vertically output light (or laser) of a predetermined intensity or higher. The VCSEL array 100 includes a plurality of, typically dozens to hundreds of VCSEL chips, in order to output light of a certain age or more. One (optical) output unit may be included in the VCSEL chip, or a plurality of output units may be included. 1 illustrates that one output unit is included in the VCSEL chip, but is not limited thereto.

The substrate 110 supports each of the components in the VCSEL array 100 .

The adhesive layer 120 is coated on the substrate 110 so that the VCSEL chip 130 can be seated on the substrate 110 . The adhesive layer 120 has an adhesive strength sufficient to be fixed after being seated on the substrate 110 . Accordingly, the adhesive layer 120 is coated on the substrate 110 to fix the VCSEL chip 130 seated on its top.

The VCSEL chip 130 receives power and oscillates light or laser. The VCSEL chip 130 is seated on the adhesive layer 120 and oscillates light or laser in the opposite direction to which the substrate 110 is positioned. A single (optical) output unit (Emitter) may be included in the VCSEL chip, or a plurality of output units may be included. In addition, when a plurality of output units are included in the VCSEL chip 130 , all of them may output light of the same wavelength band, or some or all of them may output light of a different wavelength band. A specific structure of the VCSEL chip 130 will be described later with reference to FIGS. 2 to 4 .

The polymer 140 is coated on the adhesive layer 120 and the upper portion of the VCSEL chip 130 (in the direction opposite to the direction in which the substrate is positioned relative to the VCSEL chip) and then cured, to fix the VCSEL chip 130 and to the external environment. prevent exposure to As the polymer 140 is coated on the VCSEL chip 130 , the VCSEL chip 130 may be completely fixed by the adhesive layer 120 and the polymer 140 . In addition, the polymer 140 exposes the upper portion of the VCSEL chip 130 to the outside and may prevent damage or breakage that may occur due to an external environment.

Interconnectors 150 and 155 are electrically connected to the metal layer of the VCSEL chip 130 . The interconnectors 150 and 155 are connected to each metal layer in the VCSEL chip 130 via the polymer 140 . Each metal layer in the VCSEL chip 130 may be exposed to the outside by the interconnectors 150 and 155 , and power may be applied to the VCSEL chip 130 as power is supplied to the interconnectors 150 and 155 . have.

2 is a cross-sectional view in one direction of a VCSEL chip according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view in another direction of a VCSEL epitaxy according to an embodiment of the present invention.

2 and 3 , the VCSEL chip 130 according to an embodiment of the present invention includes a first reflector 210 , an oxide layer 220 , a cavity layer 230 , and a second reflector 240 . , a first contact layer 250 , an etch stop layer 255 , a first metal layer 260 , a second metal layer 270 , and a passivation layer 280 .

The first reflector 210 may be made of a semiconductor material doped with a p-type dopant, and may be made of AlGaAs, which is a semiconductor material including Al. The first reflector 210 includes a plurality of DBR (Distributed Bragg Reflector, or 'Distributed Bragg Reflector') pairs. The DBR pair consists of a High Al Composition Layer comprising a high Al ratio of 85 to 100% and a High Al Composition Layer comprising a low Al ratio of 0 to 20%. A plurality of them are implemented as one pair. The first reflector 210 includes a smaller number of DBR pairs than the second reflector 240 , and has relatively lower reflectivity. Accordingly, the light or laser oscillated from the cavity 230 layer is oscillated in the direction of the first reflector 210 having a low reflectivity due to a relatively small number of pairs.

The ratio of aluminum included in the high aluminum component layer of the first reflective part 210 is relatively lower than that of the second reflective part 240 . Accordingly, the reflectivity of each reflective unit in the VCSEL chip 130 according to an embodiment of the present invention may be maintained while maintaining the same reflectivity, and the overall thickness of the VCSEL chip 130 may be reduced compared to the related art.

The oxide layer 220 undergoes an oxidation process to form an oxidized portion of a certain length, and the length of the oxidized portion determines the characteristics of the laser output and the diameter of the opening. The oxide layer 220 is made of aluminum (Al) having a higher concentration than that of the first and second reflectors 210 and 240 . The higher the aluminum concentration, the higher the rate of oxidation. As the oxide film layer 220 is implemented with a relatively higher aluminum concentration than both of the reflection units 210 and 240 , oxidation can be selectively performed during subsequent oxidation. For example, the oxide layer 220 may be implemented with AlGaAs having an Al ratio of 98% or more, and each of the reflection units 210 and 240 may be implemented with AlGaAs having an Al ratio of 0% to 100%. Although it is illustrated in FIG. 2 that the oxide layer 220 is formed at a position adjacent to the first reflective part 210 , the present invention is not limited thereto, and the oxide layer 220 is formed adjacent to the second reflective part 240 or the first reflective part. It may be formed at both positions adjacent to the 210 and the second reflection unit 240 .

The cavity layer 230 is a layer in which holes generated by the first reflecting unit 210 and electrons generated by the second reflecting unit 240 meet and recombine, and light is generated by recombination of electrons and holes. The cavity layer 230 may include a single quantum well (SQW) structure or a multiple quantum well (MQW) structure having a plurality of quantum well layers. When the multi-quantum well structure is included, the cavity layer 230 has a structure in which well layers (not shown) and barrier layers (not shown) having different energy bands are alternately stacked once or more. The well layer (not shown)/barrier layer (not shown) of the cavity layer 230 may be formed of InGaAs/AlGaAs, InGaAs/GaAs, or GaAs/AlGaAs.

The second reflector 240 may be implemented as an n-type semiconductor layer doped with an n-type dopant, and may be formed of AlGaAs, which is a semiconductor material including Al. The second reflector 240 is also configured of a plurality of DBR pairs. However, as described above, since the first reflector 210 includes a relatively larger number of DBR pairs, the reflectivity is relatively high. Accordingly, the light or laser oscillated from the cavity 230 layer is oscillated in the direction of the first reflector 210 having a low reflectivity due to a relatively small number of pairs.

Meanwhile, the first contact layer 250 is formed on the low aluminum component layer in one DBR pair of the second reflection unit 240 . As the first contact layer 250 is formed in the second reflector 240 , the VCSEL chip 130 may have an intra VCSEL structure. The first contact layer 250 is formed on the low aluminum component layer, but unlike the low aluminum component layer, it may be implemented with a GaAs component. However, these components have a characteristic of partially absorbing the oscillated light or laser. Accordingly, the first contact layer 250 is formed at a position separated from the cavity layer 230 by a predetermined distance. As the first contact layer 250 is separated from the cavity layer 230 by a predetermined distance, the VCSEL chip 130 may have an intra VCSEL structure while minimizing light or laser absorption. Here, the preset distance may be a plurality of pairs (a high aluminum constituent layer and a low aluminum constituent layer), in particular, a position separated by 4 to 5 pairs from the cavity layer 230 . As the first contact layer 250 is formed at a location separated by a predetermined distance from the cavity layer 230 , it may have the above-described characteristics.

The first contact layer 250 has a relatively thick thickness m times the thickness of one DBR pair. Accordingly, the VCSEL chip 130 can have the mesa structure M ₂ while the second reflection unit 240 is connected to the second metal layer 270 . As the first contact layer 250 has a relatively large thickness, etching can occur up to a position 255 of the first contact layer 250 without difficulty. The first reflective layer 210 , the oxide layer 220 , the cavity layer 230 , and the second reflective part 240 are etched to one area of both ends and one area of the first contact layer 250 , and the mesa structure ( M ₂ ). In addition, as etching occurs to one area of the first contact layer 250 and the first contact layer 250 is exposed to the outside, the second metal layer 270 may be disposed in the exposed portion.

The etch stop layer 255 is formed on the lower end of the second reflector 240 (in a direction opposite to the direction in which the first reflector is positioned with respect to the second reflector), and in the process of etching the sacrificial layer 320 , the second reflector ( 240) is protected. Like the first contact layer 250 , the second reflector 240 is made of GaAs and has a preset thickness. As the etch stop layer 255 is formed on the lower end of the second reflector 240 , the second reflector 240 is protected from damage in the process of separating the VCSEL chip 130 grown on the substrate 310 .

The first metal layer 260 is in contact with the first reflective part 210 so that power can be supplied to the first reflective part 210 . The first metal layer 260 may be a p-metal such as titanium (Ti), platinum (Pt), or gold (Au). As the first metal layer 260 is formed on the upper end of the first reflection unit 210 (based on FIG. 2 ), power applied through the electrical connection unit 140 is transmitted to the first reflection unit 210 . .

The second metal layer 270 is in contact with the first contact layer 250 so that power can be supplied to the second reflection unit 240 . As opposed to the first metal layer 260 , the second metal layer 270 may be n-metal. The VCSEL chip 130 has a shape etched in the mesa structure M ₂ from the first reflective part 210 to one position of the first contact layer 250 . By this etching, a portion of the first contact layer 250 is exposed to the outside, and the second metal layer 270 is disposed at the exposed position of the first contact layer 250 . have. As the second metal layer 270 is formed on top of the second reflection unit 240 and the first contact layer 250 (based on FIG. 2 ), power applied from the outside is applied to the second reflection unit 240 . forward to

However, the polarities of the first metal layer 260 and the second metal layer 270 are assuming that (+) power is applied to the interconnector 150 and (-) power is applied to the interconnector 155 . is the polarity of When the polarity of the power applied to each of the interconnectors 150 and 155 is different, the polarity of the first metal layer 260 and the second metal layer 270 may be reversed.

The VCSEL chip 130 has a plurality of mesa structures. Up to one position of the first contact layer 250 is primarily etched into the mesa structure M ₂ , and up to a portion of the etch stop layer 255 is additionally etched into the mesa structure M ₃ . Accordingly, the VCSEL chip 130 has a 3 mesa structure.

The passivation layer 280 is applied to the side surfaces of the remaining components except for a portion of the first metal layer 260 , a portion of the second metal layer 270 , and each metal layer to protect each component from the outside. At this time, as shown in FIG. 2 , the passivation layer 280 may be applied only to the etched portion of the etch stop layer 255 , and may not be applied to the entire etched portion (mesa structure). When the passivation layer 280 is applied as shown in FIG. 2 , the other components 240 and 255 are relatively more exposed to the etchant, but the passivation layer 280 does not have to have a mesa structure, so the application process is relatively can be simplified to On the other hand, unlike FIG. 2 , the passivation layer 280 may be applied to the entire mesa structure M ₃ of the etch stop layer. When the passivation layer 280 is applied with a mesa structure as described above, although it is somewhat complicated in the application process, other components 240 and 255 are exposed to the etching solution while the sacrificial layer 320, which will be described later, is etched by the etching solution. can be minimized. Accordingly, damage to the other components 240 and 255 by the etching solution can be minimized.

The above-described configuration of the VCSEL chip 130 is grown on the substrate 310 , and the sacrificial layer 320 is grown between the configuration of the VCSEL chip 130 and the substrate 310 . The sacrificial layer 320 is etched by the etchant to separate the substrate 310 and the VCSEL chip 130 .

By having such a structure, the VCSEL chip 130 is easily transferred to a substrate.

4 is a schematic plan view of a VCSEL chip in a VCSEL array according to an embodiment of the present invention.

The VCSEL chip has a different shape (cross-section) depending on the number of output units included. However, no matter how many output units are included, the cross-section of the VCSEL chip 130 is implemented in a preset shape. Here, the preset shape means a shape that becomes the same shape even if the predetermined angle is rotated. As such, as the VCSEL chip 130 has a preset shape, even if rotation occurs while the VCSEL chip 130 is transferred to the substrate 110 during the manufacturing process of the VCSEL array, it can be fully seated and operated.

4A to 4E are plan views of the VCSEL chip 130 according to the number of output units included in the VCSEL chip, respectively.

Referring to FIG. 4A , when one output unit is included in the VCSEL chip, the VCSEL chip 130 has a circular cross section. When the VCSEL chip 130 is formed in this way, the VCSEL chip 130 may have the same shape no matter what angle it is rotated.

When two output units are included in the VCSEL chip, the VCSEL chip 130 is formed as shown in FIG. 4B . Two circular mesa (M ₁ ) are formed side by side, and when the two circles are arranged side by side, the second metal layer 270 connects only the contours of each of the two circles (outsides that do not face each other). implemented in the form The mesa (M ₂ ) and the mesa (M ₃ ) are formed to have the same shape as that of the second metal layer 270 . When formed in this way, the VCSEL chip 130 may have the same shape even when rotated by 180 degrees.

When three output units are included in the VCSEL chip, the VCSEL chip 130 is formed as shown in FIG. 4C . When three circular mesa (M ₁ ) are formed adjacent to each other (one of which is adjacent to the other two), the second metal layer 270 has the outline of each of the three circles when the three circles are disposed adjacent to each other. It is implemented in the form of connecting only (outsides of each circle that do not face each other). The mesa (M ₂ ) and the mesa (M ₃ ) are formed to have the same shape as that of the second metal layer 270 . When formed in this way, even if the VCSEL chip 130 rotates 120 degrees, it may have the same shape.

When four output units are included in the VCSEL chip, the VCSEL chip 130 is formed as shown in FIG. 4D. Any one of the four circular mesa (M ₁ ) is formed to be adjacent to the other two, and the second metal layer 270 has the contours of each of the four circles when the four circles are arranged like the mesa (M ₁ ). It is implemented in the form of connecting only (outsides of each circle that do not face each other). The mesa (M ₂ ) and the mesa (M ₃ ) are formed to have the same shape as that of the second metal layer 270 . When the VCSEL chip 130 is formed in this way, it may have the same shape even if it is rotated by 90 degrees.

When five output units are included in the VCSEL chip, the VCSEL chip 130 is formed as shown in FIG. 4E. Of the five circular mesa (M ₁ ), four mesa (M ₁ ) are formed so that any one is adjacent to the other two, and the other one mesa (M _{1 ) of the five circular mesa (M 1 )} is the other four mesa (M ₁ ) It is formed so as to be adjacent to all. In the second metal layer 270 , when five circles are arranged like the mesa (M ₁ ), the contours of each of the four circles formed so that one is adjacent to the other two (outsides where each circle does not face each other) It is implemented in the form of connecting the bays. The mesa (M ₂ ) and the mesa (M ₃ ) are formed to have the same shape as that of the second metal layer 270 . When formed in this way, even if the VCSEL chip 130 rotates 90 degrees, it may have the same shape.

How the VCSEL array is fabricated is shown in Figures 5-10.

5 and 6 , the adhesive layer 120 is coated on the substrate 110 .

Next, as shown in FIG. 7 , the VCSEL chip 130 is disposed on the adhesive layer 120 . The VCSEL chip 130 is disposed on the adhesive layer 120 and fixed. Each VCSEL chip 130 is disposed with an appropriate interval according to the number to be included in the VCSEL array to be manufactured.

Next, as shown in FIG. 8 , the polymer 140 is coated on the adhesive layer 120 and the VCSEL chip 130 and then cured.

Next, as shown in FIG. 9 , the polymers 910 and 920 on the positions of the first metal layer 260 and the second metal layer 270 in the VCSEL chip 130 are removed.

Finally, as shown in FIG. 10 , the interconnectors 150 and 155 are respectively disposed at the positions of the removed polymer, and are electrically connected to the first metal layer 260 and the second metal layer 270 in the VCSEL chip 130 . .

The above description is merely illustrative of the technical idea of this embodiment, and various modifications and variations will be possible without departing from the essential characteristics of the present embodiment by those of ordinary skill in the art to which this embodiment belongs. Accordingly, the present embodiments are intended to explain rather than limit the technical spirit of the present embodiment, and the scope of the technical spirit of the present embodiment is not limited by these embodiments. The protection scope of this embodiment should be interpreted by the claims below, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present embodiment.

100: VCSEL array
110: substrate
120: first electrode
130: VCSEL chip
130: polymer
150, 155: interconnect
210: first reflector
220: oxide layer
230: cavity layer
240: second reflector
250: contact layer
255: etch stop layer
260: first metal layer
270: second metal layer
280: passivation layer
310: substrate
320: sacrificial layer

Claims (12)

Board;
an adhesive layer coated on the substrate;
a VCSEL chip disposed on the adhesive layer and fixed, receiving power to oscillate light or laser;
a polymer coated on the VCSEL chip and the adhesive layer; and
an interconnector electrically connected to the VCSEL chip
VCSEL array comprising a. According to claim 1,
The VCSEL chip,
a first reflector including a plurality of DBR (Distributed Bragg Reflector) pairs;
a second reflector including a plurality of DBR pairs;
a cavity layer positioned between the first reflecting unit and the second reflecting unit, wherein holes generated in any one of the first reflecting unit and the second reflecting unit and electrons generated in the other one are recombine;
an oxide layer positioned between the cavity layer and the first or second reflecting unit to determine characteristics of a laser to be output and a diameter of an opening;
a contact layer formed in one DBR pair of the second reflector;
a first metal layer in contact with the first reflective part so that power can be supplied to the first reflective part;
a second metal layer in contact with the contact layer so that power can be supplied to the second reflection unit;
an etch stop layer positioned at a lower end of the second reflector to prevent damage that may occur to the second reflector during an etching process; and
and a passivation layer for protecting the first reflective part, the second reflective part, the cavity layer, the oxide layer, the contact layer, and the etch stop layer from the outside. 3. The method of claim 2,
The second reflector,
VCSEL array comprising more DBR pairs than the first reflector. 3. The method of claim 2,
The contact layer is
VCSEL array, characterized in that it has a mesa structure. 5. The method of claim 4,
The second metal layer,
A VCSEL array disposed within the mesa structure and in contact with the contact layer. 3. The method of claim 2,
The etch stop layer,
VCSEL array, characterized in that it has a mesa structure 7. The method of claim 6,
The passivation layer,
VCSEL array, characterized in that applied to part or all of the mesa structure of the etch stop layer According to claim 1,
The VCSEL chip,
A VCSEL array comprising one or more outputs. 9. The method of claim 8,
The VCSEL chip,
VCSEL array, characterized in that it has a cross section of a predetermined shape. 10. The method of claim 9,
The preset shape is
VCSEL array, characterized in that it has the same shape even if it is rotated by a preset angle. 10. The method of claim 9,
When the VCSEL chip includes a plurality of output units, a VCSEL array, characterized in that light or laser of the same or different wavelength is output from each output unit. A method of manufacturing a VCSEL array, comprising:
A coating process in which an adhesive layer is coated on a substrate;
A first arrangement process in which the VCSEL chip of any one of claims 2 to 11 is disposed on the coating layer;
A coating process in which a polymer is coated and cured on the VCSEL chip;
a removal process of removing the polymer coated on each metal layer of the VCSEL chip; and
A second arrangement process of disposing an interconnector on each metal layer of the VCSEL chip
VCSEL array manufacturing method comprising a.

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