KR102422873B1 - VCSEL Chip, VCSEL Array and Method for Manufacturing thereof - Google Patents

Abstract

Disclosed are a VCSEL chip, a VCSEL array, and a manufacturing method thereof. According to one aspect of the present embodiment, provided is a VCSEL chip comprising: a first reflection unit including a plurality of distributed Bragg reflector (DBR) pairs; a second reflection unit including a plurality of DBR pairs; a cavity layer which is positioned between the first reflection unit and the second reflection unit and in which holes generated from one between the first reflection unit and the second reflection unit and electrons generated from the remaining one are combined again; an oxide film layer positioned between the cavity layer and the first reflection unit or the second reflection unit to determine the characteristics of the laser to be output and the diameter of an opening; a contact layer formed by coming in contact with the second reflection unit in a direction away from the first reflection unit; a first metal layer coming in contact with the first reflection unit so as to supply power to the first reflection unit; a second metal layer formed on the contact layer so as to supply power to the second reflection unit; and a passivation layer protecting the first reflection unit, the second reflection unit, the cavity layer, the oxide film layer, and a portion of the contact layer from the outside. The VCSEL chip can be transferred in a self-assembly manner.

Description

VCSEL chip, VCSEL array and manufacturing method thereof

The present invention relates to a flip-chip type micro VCSEL, a VCSEL array including the same, and a method for manufacturing the VCSEL array.

The content described in this section merely provides background information for the present embodiment and does not constitute the prior art.

In general, semiconductor laser diodes are a side-emitting laser diode (EEL, Edge Emitting Laser Diode, hereinafter abbreviated as 'EEL') and a vertical resonance type surface emitting laser diode (VCSEL: Vertical Cavity Surface Emitting Laser, hereinafter abbreviated as 'VCSEL'). ) is included. Since the EEL has a resonance structure that is parallel to the stacking surface of the device, it oscillates a laser beam in a direction parallel to the stacked surface, and the VCSEL has a resonance structure that is perpendicular to the stacked surface of the device, so that the laser beam is converted into an element. oscillate in the direction perpendicular to the lamination plane of

VCSEL has a shorter optical gain length than EEL, so it can realize low power, and since high-density integration is possible, it is advantageous for mass production. In addition, the VCSEL can oscillate a laser beam in a single-ended mode (Single Longitudinal Mode) and can be tested on a wafer. Furthermore, since the VCSEL is capable of high-speed modulation and can oscillate a circular beam, coupling with an optical fiber is easy and a two-dimensional surface array is possible.

VCSELs have been mainly used as light sources in optical devices in optical communication, optical interconnection, optical pickup, and the like. However, in recent years, the VCSEL has been extended to a light source in an image forming apparatus such as LiDAR, facial recognition, motion recognition, AR (Augmented Reality), or VR (Virtual Reality).

As such, VCSELs are used in various fields, and there arises a need to appropriately manufacture a VCSEL chip or a VCSEL array depending on the application. Conventionally, only a two-dimensional array using a GaAs substrate on which an epitaxial layer is grown has been used. As such, the two-dimensional array contained the GaAs substrate used for growth of the VCSEL epitaxial layer, and thus the curvature could not be formed. Therefore, it is true that there were considerable difficulties in constructing a two-dimensional array such as a LiDAR light source that requires curvature. Recently, a method of direct transfer is used in transferring a VCSEL to a specific substrate (eg, a flexible substrate), but mass transfer is difficult and the process and investment cost are considerable, so there is an inconvenience of lowering mass productivity.

An embodiment of the present invention has an object to provide a VCSEL chip that can be transferred in a self-assembled manner and a VCSEL array manufactured accordingly.

According to an aspect of the present invention, a first reflector including a plurality of DBR (Distributed Bragg Reflector) pairs, a second reflector including a plurality of DBR (Distributed Bragg Reflector) pairs, the first reflector, and the first reflector A cavity layer located between the two reflecting units, in which holes generated in any one of the first reflecting unit and the second reflecting unit and electrons generated in the other are recombine, the cavity layer, and the first reflecting unit or the second reflecting unit An oxide film layer positioned between the two reflecting units and determining the characteristics of the laser to be output and the diameter of the opening, a contact layer formed in contact with the second reflecting unit in a direction away from the first reflecting unit, and the first reflecting unit A second metal layer and the first reflection formed on the first metal layer and the contact layer to be in contact with the first reflective part so that power can be supplied to the first reflective part so that power can be supplied to the second reflective part. It provides a VCSEL chip comprising a passivation layer for protecting a part, the second reflection part, the cavity layer, the oxide layer, and a part of the contact layer from the outside.

According to one aspect of the present invention, the DBR pair is characterized in that it comprises a high aluminum constituent layer comprising a relatively higher proportion of aluminum and a low aluminum constituent layer comprising a relatively small proportion of aluminum.

According to an aspect of the present invention, the first reflector includes a larger number of DBR pairs than the second reflector.

According to one aspect of the present invention, the contact layer is characterized in that a predetermined area is etched.

According to one aspect of the present invention, the passivation layer is characterized in that it is applied only to the etched surface of the contact layer.

According to one aspect of the present invention, the passivation layer is characterized in that it is applied to all of the etched area of the contact layer.

According to one aspect of the present invention, a plurality of substrates, the first electrode disposed on the substrate, and the VCSEL chip of any one of claims 1 to 6 have the same shape and are spaced apart by the width of the VCSEL chip. 6. The VCSEL chip of any one of claims 1 to 5, wherein a plurality of dams and a plurality of dams are arranged in the shape of an interval within the interval formed by the dam, and disposed between the VCSEL chip and the first electrode within the interval formed by the dam. It provides a VCSEL array comprising a plurality of electrical connection portions electrically connecting the two and an interconnector electrically connecting the second metal layer of each VCSEL chip to each other.

According to one aspect of the present invention, it is characterized in that the AR (Anti Reflection) coating layer is applied to the far end of the substrate and the VCSEL chip.

According to one aspect of the present invention, the AR coating layer is characterized in that it is disposed between the second metal layer.

According to one aspect of the present invention, it is characterized in that the polymer is coated and cured with a gap occurring between the VCSEL chip and the dam.

According to one aspect of the present invention, in a method of manufacturing a VCSEL array, a first arrangement process in which a first electrode is disposed on a substrate and a VCSEL of any one of claims 1 to 6 on the first electrode A second arrangement process in which dams having the same shape as the chip are disposed with an interval as much as the width of the VCSEL chip, a third arrangement process in which an electrical connection part is disposed between the intervals of each dam, and the VCSEL chip is assembled on the electrical connection part An assembly process, a curing process in which a polymer is coated and cured on the dam, a removal process to remove the polymer coated on the top of the VCSEL chip, an application process of applying an anti-reflection (AR) coating layer to the top of the VCSEL chip, and each It provides a method for manufacturing a VCSEL array, comprising a fourth arrangement process of disposing an interconnector between VCSEL chips, wherein the second metal layer is disposed together with the AR coating layer on top of the VCSEL chip during the coating process .

According to an aspect of the present invention, the polymer is coated with a gap generated between the VCSEL chip and the dam to be cured.

According to an aspect of the present invention, the interconnector electrically connects the second metal layers of each VCSEL chip to each other.

As described above, according to one aspect of the present invention, when the VCSEL array is manufactured, there is an advantage that the VCSEL chip can be transferred in a self-assembled manner.

1 is a cross-sectional view of a VCSEL array according to an embodiment of the present invention.
2 is a cross-sectional view in one direction of a VCSEL chip according to an embodiment of the present invention.
3 is a cross-sectional view in another direction of a VCSEL epitaxy according to an embodiment of the present invention.
4 is a diagram illustrating a process of growing a dam on the first electrode according to an embodiment of the present invention.
5 is a diagram illustrating a process of assembling a VCSEL chip between dams according to an embodiment of the present invention.
6 is a diagram illustrating a process of coating a polymer on a dam and a VCSEL chip according to an embodiment of the present invention.
7 is a view showing a process of removing the polymer coated on the top of the VCSEL chip according to an embodiment of the present invention.
8 is a diagram illustrating a process of performing AR coating on the VCSEL chip according to an embodiment of the present invention.
9 is a diagram illustrating a process of interconnecting electrodes between VCSEL chips according to an embodiment of the present invention.

Since the present invention can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to a specific embodiment, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numerals have been used for like elements.

Terms such as first, second, A, and B may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that no other element is present in the middle.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. It should be understood that terms such as “comprise” or “have” in the present application do not preclude the possibility of addition or existence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification in advance. .

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. does not

In addition, each configuration, process, process or method included in each embodiment of the present invention may be shared within a range that does not technically contradict each other.

1 is a cross-sectional view of a VCSEL array according to an embodiment of the present invention.

Referring to FIG. 1 , a VCSEL array 100 according to an embodiment of the present invention includes a substrate 110 , a first electrode 120 , a dam 130 , an electrical connection unit 140 , a VCSEL chip 150 , and a polymer. 160 and an interconnector 170 .

A VCSEL array (Vertical Cavity Surface Emitting Laser Array, 100) refers to an optical device in which a plurality of VCSEL chips 150 are arranged in an array form and vertically output light (or laser) having a predetermined intensity or higher. The VCSEL array 100 includes a plurality of, typically several tens to hundreds of VCSEL chips 150 to output light of a certain age or more.

The substrate 110 supports each of the components in the VCSEL array 100 .

The first electrode 120 is disposed on the substrate 110 , and is electrically connected to the electrical connection unit 140 to supply power to each VCSEL chip 150 . The first electrode 120 is disposed on the substrate 110 , and is disposed to be electrically connected to each electrical connection unit 140 connected to each VCSEL chip 150 disposed on the substrate 110 . Accordingly, the first electrode 120 receives power from the outside and transmits it to the VCSEL chip 150 through each electrical connection unit 140 .

The dam 130 is implemented in the same shape as the VCSEL chip 150 , and the VCSEL chip 150 is disposed and fixed on the first electrode 120 . The dam 130 has the same shape as the VCSEL chip 150 and is spaced apart by the width of the VCSEL chip 150 . Since the dam 130 having the same shape as the VCSEL chip 150 is spaced apart by the above-described distance, a gap having a shape symmetrical to the dam is formed between a specific dam and a dam adjacent thereto. The VCSEL chip 150 is disposed between the dams in a shape symmetrical to the dams. Since the dam 130 is implemented in the same shape as the VCSEL chip 150 and is spaced apart by an interval of the VCSEL chip 150 , the VCSEL chip 150 may be fixed between the dams 130 .

The electrical connection unit 140 electrically connects the first electrode 120 and the VCSEL chip 150 . The electrical connection unit 140 is disposed at the lowermost end of the space between the dam 130 and the dam 130 , and contacts both the first electrode 120 and the VCSEL chip 150 . The electrical connection part 140 is implemented with a material having excellent electrical conductivity, and transmits a current flowing therein. The electrical connection unit 140 may be implemented and disposed in the form of a solder ball, or may be implemented and disposed with an eutectic metal (eg, AuSn or InSn, etc.) by deposition. However, the present invention is not limited thereto, and any configuration that electrically connects the both 120 and 150 may be substituted.

The VCSEL chip 150 receives power and oscillates light or laser. The VCSEL chip 150 is disposed in the space between the dams 130 and oscillates light or laser in the opposite direction where the substrate 110 is located. A specific structure of the VCSEL chip 150 will be described later with reference to FIGS. 2 and 3 .

The polymer 160 is applied to the upper portion of the dam 130 (in the direction opposite to the direction in which the substrate is positioned with respect to the VCSEL chip) to completely fix the VCSEL chip 150 . Even if the dam 130 and the VCSEL chip 150 have the same shape, tolerances are inevitable because they are not cast in the same mold. Accordingly, even if the VCSEL chip 150 is seated between the dam 130 implemented in the same shape as the VCSEL chip 150 , the VCSEL chip 150 may be separated due to such a tolerance. In order to prevent this, the polymer 160 is applied and cured on the upper portion of the dam 130 , thereby preventing the VCSEL chip 150 from detaching.

The interconnector 170 connects electrodes of the adjacent VCSEL chip 150 . The polymer 160 is removed from the top of the VCSEL chip 150 and the electrode is exposed to the outside. The interconnector 170 electrically connects each of the VCSEL chips 150 by connecting the electrodes exposed as described above. Accordingly, power of one polarity is applied to the first electrode 120 from the outside, and power of a different polarity is applied to each electrode from the outside through the interconnector 170 . Accordingly, the VCSEL chip 150 may receive power to oscillate light or laser.

2 is a cross-sectional view in one direction of a VCSEL chip according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view in another direction of a VCSEL epitaxy according to an embodiment of the present invention.

2 and 3 , the VCSEL chip 150 according to an embodiment of the present invention includes a first reflector 210 , an oxide layer 220 , a cavity layer 230 , and a second reflector 240 . , a contact layer 250 , a first metal layer 260 , and a passivation layer 270 .

The first reflector 210 may be made of a semiconductor material doped with a p-type dopant, and may be made of AlGaAs, which is a semiconductor material including Al. The first reflector 210 includes a plurality of DBR (Distributed Bragg Reflector, or 'Distributed Bragg Reflector') pairs. The DBR pair consists of a High Al Composition Layer comprising a high Al ratio of 85 to 100% and a High Al Composition Layer comprising a low Al ratio of 0 to 20%. A plurality of them are implemented as one pair. The first reflector 210 includes a larger number of DBR pairs than the second reflector 240 , and has relatively higher reflectivity. Accordingly, the light or laser oscillated from the cavity 230 layer is oscillated in the direction of the second reflector 240 having a low reflectivity due to a relatively small number of pairs.

The ratio of aluminum included in the high aluminum component layer of the first reflective part 210 is relatively higher than that of the second reflective part 240 . Accordingly, the reflectivity of each reflective unit in the VCSEL chip 150 according to an embodiment of the present invention may be maintained, and the overall thickness of the VCSEL chip 150 may be reduced compared to the related art.

The oxide layer 220 undergoes an oxidation process to form an oxidized portion of a certain length, and the length of the oxidized portion determines the characteristics of the laser output and the diameter of the opening. The oxide layer 220 is made of aluminum (Al) having a higher concentration than that of the first and second reflectors 210 and 240 . The higher the aluminum concentration, the higher the rate of oxidation. As the oxide film layer 220 is implemented with a relatively higher aluminum concentration than both of the reflection units 210 and 240 , oxidation can be selectively performed during subsequent oxidation. For example, the oxide layer 220 may be implemented with AlGaAs having an Al ratio of 98% or more, and each of the reflection units 210 and 240 may be implemented with AlGaAs having an Al ratio of 0% to 100%. Although it is illustrated in FIG. 2 that the oxide layer 220 is formed at a position adjacent to the first reflective part 210 , the present invention is not limited thereto, and the oxide layer 220 is formed adjacent to the second reflective part 240 or the first reflective part. It may be formed at both positions adjacent to the 210 and the second reflection unit 240 .

The cavity layer 230 is a layer in which holes generated by the first reflecting unit 210 and electrons generated by the second reflecting unit 240 meet and recombine, and light is generated by recombination of electrons and holes. The cavity layer 230 may include a single quantum well (SQW) structure or a multiple quantum well (MQW) structure having a plurality of quantum well layers. When a multi-quantum well structure is included, the cavity layer 230 has a structure in which well layers (not shown) and barrier layers (not shown) having different energy bands are alternately stacked once or more. The well layer (not shown)/barrier layer (not shown) of the cavity layer 230 may be formed of InGaAs/AlGaAs, InGaAs/GaAs, or GaAs/AlGaAs.

The second reflector 240 may be implemented as an n-type semiconductor layer doped with an n-type dopant, and may be formed of AlGaAs, which is a semiconductor material including Al. The second reflector 240 is also configured of a plurality of DBR pairs. However, as described above, since the first reflector 210 includes a relatively smaller number of DBR pairs, the reflectivity is relatively low. Accordingly, the light or laser oscillated from the cavity 230 layer is oscillated in the direction of the second reflector 240 having a low reflectivity due to a relatively small number of pairs.

The contact layer 250 is formed under the second reflection unit 240 , and supplies power transmitted from the outside to the second reflection unit 240 . Unlike the DBR pair of the second reflector 240 , the contact layer 250 is made of GaAs and has a relatively thick thickness m times the thickness of one DBR pair. Accordingly, the etching can occur up to one position 255 of the contact layer 250 without difficulty. Etching is performed to one area of both ends of the first reflective layer 210 , the oxide layer 220 , the cavity layer 230 and the second reflective part 240 and one area of the contact layer 250 , and the passivation layer 270 . Even the etched portion of the contact layer 250 may be smoothly formed.

The first metal layer 260 is in contact with the first reflective part 210 so that power can be supplied to the first reflective part 210 . The first metal layer 260 may be a p-metal such as titanium (Ti), platinum (Pt), or gold (Au). As the first metal layer 260 is formed on top of the first metal layer 260 (based on FIG. 2 ), power applied through the electrical connection unit 140 is transmitted to the first reflection unit 210 . .

However, the polarity of the first metal layer 260 is the polarity when it is assumed that a (+) power is applied to the first electrode 120 . When the polarity of the power applied to the first electrode 120 is different, the polarity of the first metal layer 260 may be reversed.

The passivation layer 270 is applied to a portion of the first metal layer 260 and the contact layer 250 and side surfaces of the remaining components except for the first metal layer 260 and the contact layer 250 to protect each component from the outside. In this case, the passivation layer 270 has a mesa structure as shown in FIG. 2A and may be applied to the entire etched portion of the contact layer 250 . When the passivation layer 270 is applied with a mesa structure as described above, although it is somewhat complicated during the application process, other components 240 and 250 are exposed to the etching solution while the sacrificial layer 320, which will be described later, is etched by the etching solution. can be minimized. Accordingly, damage to the other components 240 and 250 by the etching solution can be minimized. Meanwhile, as shown in FIG. 2B , the passivation layer 270 may be applied only to the etched portion of the contact layer 250 and not the entire etched portion. As such, when the passivation layer 270 is applied, the other components 240 and 250 are relatively more exposed to the etchant, but since the passivation layer 270 does not have to have a mesa structure, the application process is relatively can be simplified.

The above-described configuration of the VCSEL chip 150 is grown on the substrate 310 , and the sacrificial layer 320 is grown between the configuration of the VCSEL chip 150 and the substrate 310 . The sacrificial layer 320 is etched by the etchant to separate the substrate 310 and the VCSEL chip 150 .

By having such a structure, the VCSEL chip 150 is easily transferred to a substrate in a self-assembly manner. How the VCSEL chip 150 is transferred to the substrate 110 is illustrated in FIGS. 4 to 9 .

4 is a diagram illustrating a process of growing a dam on the first electrode according to an embodiment of the present invention.

The first electrode 120 is disposed on the substrate 110 , and the dam 130 is disposed on the first electrode 120 . As described above, the dam 130 is implemented in the same shape as the VCSEL chip 150 and is spaced apart from the VCSEL chip 150 by an interval. Between a specific dam and an adjacent dam, there is a gap of a shape symmetrical to the dam.

5 is a diagram illustrating a process of assembling a VCSEL chip between dams according to an embodiment of the present invention.

Between the gaps of each dam, a VCSEL chip 150 is disposed. Since the dam 130 is spaced apart by the interval of the VCSEL chip 150 , the VCSEL chip 150 may be transferred and disposed between the intervals of the dam 130 in a self-assembled form.

The electrical connection unit 140 is first disposed in the space where the VCSEL chip 150 is to be disposed, and electrically connects the VCSEL chip 150 and the first electrode 120 .

6 is a diagram illustrating a process of coating a polymer on a dam and a VCSEL chip according to an embodiment of the present invention.

When the VCSEL chip 150 is transferred, a gap 510 occurs between the dam 130 and the VCSEL chip 150 . Although the dam 130 is manufactured to have the same shape as the VCSEL chip 150 , fine tolerances may occur because it is not manufactured in the same process. In addition, since the electrical connection unit 140 is disposed in the space where the VCSEL chip 150 is to be disposed, a gap 510 between the two occurs even under the influence of the electrical connection unit 140 . Such a gap may induce deviation in the height direction of the VCSELC chip 150 disposed between the dams 130 . That is, the gap 510 must be filled to prevent the complete fixation of the VCSEL chip 150 .

In order to fill the gap 510, the polymer 160 is coated on the top of the dam 130 and then cured. As the polymer 160 is injected into the gap 510 and cured, it fills the gap 510 and completely fixes the VCSEL chip 150 to prevent separation.

7 is a view showing a process of removing the polymer coated on the top of the VCSEL chip according to an embodiment of the present invention.

The polymer 160 is coated over a certain height to sufficiently fill the gap 510 . Accordingly, the polymer 160 may be coated up to the upper portion of the VCSEL chip 150 (in the direction of the upper portion and the second reflector in FIG. 7 ). If the polymer 160 is also coated in the corresponding position, it interferes with the complete laser output from the VCSEL chip 150 .

Accordingly, the polymer 710 coated on the VCSEL chip 150 is removed, and the polymer 720 coated in the gap between the VCSEL chips 150 is not removed.

8 is a diagram illustrating a process of performing AR coating on the VCSEL chip according to an embodiment of the present invention.

An anti-reflection (AR) coating layer 810 is applied on the VCSEL chip 150 from which the polymer 160 is removed, and a second metal layer 820 is disposed.

The AR coating layer 810 is applied on the top of the VCSEL chip 150, so that most of the laser can be irradiated out of the chip while minimizing the laser reflected into the chip. The AR coating layer 820 is not applied over the entire area of the VCSEL chip 150 and the contact layer 250 but is applied only to a certain area.

The second metal layer 820 is disposed on the remaining area of the VCSEL chip 150 on which the AR coating layer 810 is not applied. That is, the AR coating layer 810 is positioned between the second metal layers 820 . The second metal layer 820 contacts the contact layer 250 so that power can be supplied to the second reflector 240 through the contact layer 250 . Since the second metal layer 820 is exposed to the outside on the contact layer 250 , the interconnector 170 easily (electrically) connects the second metal layers 820 in each VCSEL chip 150 . can The VCSEL chip 150 may form a VCSEL array with a simple structure.

9 is a diagram illustrating a process of interconnecting electrodes between VCSEL chips according to an embodiment of the present invention.

An interconnector 170 connecting the second metal layer 820 in each VCSEL chip 150 is disposed. The interconnector 170 is disposed between each VCSEL chip 150 in contact with the second metal layer 820 of each VCSEL chip 150 . Accordingly, the interconnector 170 connects all of the electrodes between the VCSEL chips 150 , and the VCSEL array 100 is finally manufactured.

In the VCSEL chip 150 , as the contact layer 250 having a thickness m times the thickness of one DBR pair is disposed at the bottom, the etching of the contact layer 250 can be easily performed, and interconnecting between each VCSEL chip is performed. and the VCSEL array 100 can be easily manufactured.

The above description is merely illustrative of the technical idea of this embodiment, and a person skilled in the art to which this embodiment belongs may make various modifications and variations without departing from the essential characteristics of the present embodiment. Accordingly, the present embodiments are intended to explain rather than limit the technical spirit of the present embodiment, and the scope of the technical spirit of the present embodiment is not limited by these embodiments. The protection scope of this embodiment should be interpreted by the claims below, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present embodiment.

100: VCSEL array
110: substrate
120: first electrode
130: dam
135: step
140: electrical connection
150: VCSEL chip
160: polymer
170: interconnect
210: first reflector
220: oxide layer
230: cavity layer
240: second reflector
250: contact layer
260: first metal layer
270: passivation layer
310: substrate
320: sacrificial layer
510: play
810: AR coating layer
820: second metal layer

Claims (13)

In a VCSEL array,
First and second reflectors including a plurality of DBR (Distributed Bragg Reflector) pairs;
a cavity layer located between the first reflecting unit and the second reflecting unit, in which holes generated in any one of the first reflecting unit and the second reflecting unit and electrons generated in the other are recombine;
an oxide layer positioned between the cavity layer and the first or second reflecting unit to determine the characteristics of the laser to be output and the diameter of the opening;
a contact layer formed in contact with the second reflective part in a direction far from the first reflective part;
A first metal layer in contact with the first reflective part to supply power to the first reflective part and a second metal layer formed on the contact layer to supply power to the second reflective part , and
a VCSEL chip comprising a passivation layer protecting a portion of the first reflective part, the second reflective part, the cavity layer, the oxide layer, and the contact layer from outside;
Board;
a first electrode disposed on the substrate;
a plurality of dams having the same shape as the VCSEL chip and spaced apart by a width of the VCSEL chip;
The VCSEL chips are disposed in the shape of a gap within the gap formed by the plurality of dams, and are disposed between the VCSEL chip and the first electrode within the gap formed by the plurality of dams to electrically connect both of them. connection; and
A VCSEL array comprising; an interconnector electrically connecting the second metal layers of each VCSEL chip to each other. According to claim 1,
The DBR pair is
A VCSEL array comprising a high aluminum constituent layer comprising a relatively higher proportion of aluminum and a low aluminum constituent layer comprising a relatively lower proportion of aluminum. According to claim 1,
The first reflector,
VCSEL array comprising a larger number of DBR pairs than the second reflector. According to claim 1,
The contact layer is
A VCSEL array, characterized in that a predetermined area is etched. 5. The method of claim 4,
The passivation layer,
VCSEL array, characterized in that applied only to the etched side of the contact layer. 5. The method of claim 4,
The passivation layer,
VCSEL array, characterized in that applied to all of the etched area of the contact layer. delete According to claim 1,
VCSEL array, characterized in that the AR (Anti Reflection) coating layer is applied to the far end of the substrate and the VCSEL chip. 9. The method of claim 8,
The AR coating layer,
VCSEL array, characterized in that disposed between the second metal layer. According to claim 1,
VCSEL array, characterized in that the polymer is coated and cured with a gap that occurs between the VCSEL chip and the dam. A method of manufacturing a VCSEL array, comprising:
a first arrangement process in which a first electrode is disposed on a substrate;
a second arrangement process in which dams having the same shape as the VCSEL chip of any one of claims 1 to 6 are disposed on the first electrode at intervals as much as the width of the VCSEL chip;
a third arrangement process in which electrical connections are arranged between the intervals of each dam;
an assembly process in which the VCSEL chip is assembled on the electrical connection part;
a curing process in which a polymer is coated on the dam and cured;
A removal process of removing the polymer coated on the top of the VCSEL chip;
an application process of applying an anti-reflection (AR) coating layer on the top of the VCSEL chip; and
a fourth arrangement process of disposing an interconnector between each VCSEL chip;
The second metal layer is a VCSEL array manufacturing method, characterized in that disposed together with the AR coating layer on the top of the VCSEL chip in the coating process. 12. The method of claim 11,
The polymer is
VCSEL array manufacturing method, characterized in that the coating is cured with a gap generated between the VCSEL chip and the dam. 12. The method of claim 11,
The interconnector is
A method of manufacturing a VCSEL array, characterized in that the second metal layers of each VCSEL chip are electrically connected to each other.

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