KR20220115765A - Display apparatus and method of driving the same - Google Patents

Abstract

A display device includes a display panel, a driving control part, a gate driving part, an emission driving part and a data driving part. The display panel includes a pixel including a driving switching element and a light emitting element. The driving control part determines a driving frequency varying depending on input image data or a driving mode. The gate driving part outputs a gate signal and a bias control signal to the pixel. The emission driving part outputs an emission signal. The data driving part outputs a data voltage to the pixel. In a lighting frame, the bias control signal for applying a bias voltage to the driving switching element has a first width, and, in a holding frame, the bias control signal has a second width different from the first width. Therefore, the present invention is capable of improving the display quality of the display panel.

Description

Display device and its driving method {DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME}

The present invention relates to a display device and a driving method thereof, and more particularly, to a display device and a driving method thereof for removing a luminance difference due to a bias deviation between a writing frame and a holding frame during variable frequency driving.

In general, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes: a gate driver providing a gate signal to the plurality of gate lines; a data driver providing a data voltage to the data lines; an emission driver providing an emission signal to the emission lines; and a driving controller for controlling the gate driver, the data driver, and the emission driver.

In order to realistically express game images and movie images, high-resolution and high-frequency driving is required. In addition, when supporting game images and movie images, high frequency driving and variable frequency driving are required to reduce power consumption. In variable frequency driving, the display panel may have a writing frame in which a data voltage is written to a pixel and a holding frame in which a conventional data voltage is maintained without writing a data voltage to the pixel.

At this time, the degree of bias of the writing frame and the degree of bias of the holding frame may be different from each other, so that the luminance of the image of the writing frame and the luminance of the image of the holding frame may have a difference. Due to the luminance difference, the display quality of the display panel may be deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device capable of improving display quality by removing a difference in luminance between a writing frame and a holding frame during variable frequency driving.

Another object of the present invention is to provide a method of driving the display device.

A display device according to an exemplary embodiment of the present invention includes a display panel, a driving control unit, a gate driving unit, an emission driving unit, and a data driving unit. The display panel includes a pixel including a driving switching device and a light emitting device. The driving control unit determines a variable driving frequency according to input image data or a driving mode. The gate driver outputs a gate signal and a bias control signal to the pixel. The emission driver outputs an emission signal to the pixel. The data driver outputs a data voltage to the pixel. In a writing frame, the bias control signal for applying a bias voltage to the driving switching element has a first width, and in a holding frame, the bias control signal has a second width different from the first width.

In an embodiment of the present invention, the second width may be greater than the first width.

In an embodiment of the present invention, when the driving frequency is a normal frequency, the display panel may have only the writing frame. When the driving frequency is a low frequency driving frequency smaller than the normal frequency, the display panel may include the writing frame and the holding frame.

In one embodiment of the present invention, the pixel comprises a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node, a control electrode; A second pixel switching element including an input electrode to which a data voltage is applied and an output electrode connected to a fourth node, a control electrode, an input electrode connected to the first node, and an output electrode connected to the third node A fourth pixel switching element including a third pixel switching element, a control electrode, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node, a control electrode, an input electrode to which a reference voltage is applied, and the fourth node A sixth pixel switching element including a fifth pixel switching element including an output electrode connected to, a control electrode, an input electrode connected to the third node, and an output electrode connected to an anode electrode of the light emitting element, the control electrode, the A seventh pixel switching element including an input electrode to which an initialization voltage is applied and an output electrode connected to the anode electrode of the light emitting element, a control electrode, an input electrode to which the bias voltage is applied, and an output electrode connected to the second node An eighth pixel switching element including A light emitting device including the anode electrode connected to and a cathode electrode to which a low power supply voltage is applied, a first capacitor including a first electrode to which the high power supply voltage is applied, and a second electrode connected to the fourth node, and the second electrode It may include a second capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node.

In an embodiment of the present invention, the bias control signal may be applied to the control electrode of the eighth pixel switching element.

In an embodiment of the present invention, the bias control signal may be applied to the control electrode of the seventh pixel switching element.

In an embodiment of the present invention, a first gate signal may be applied to the control electrode of the second pixel switching element.

In an embodiment of the present invention, a second gate signal may be applied to the control electrode of the fourth pixel switching element. A third gate signal may be applied to the control electrode of the third pixel switching element and the control electrode of the fifth pixel switching element.

In an embodiment of the present invention, a first emission signal may be applied to the control electrode of the ninth pixel switching element. A second emission signal may be applied to the control electrode of the sixth pixel switching element.

In an embodiment of the present invention, the display device may further include a power voltage generator that generates a high power voltage, a low power voltage, an initialization voltage, a reference voltage, and the bias voltage and outputs the generated voltage to the pixel.

In one embodiment of the present invention, the bias voltage of the holding frame may be greater than the bias voltage of the writing frame.

In one embodiment of the present invention, the pixel comprises a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node, a control electrode; a second pixel switching element including an input electrode to which the data voltage is applied and an output electrode connected to a fourth node, a control electrode, an input electrode connected to the first node, and an output electrode connected to the third node a fourth pixel switching element including a third pixel switching element, a control electrode, an input electrode to which a reference voltage is applied, and an output electrode connected to the fourth node, a control electrode, an input electrode to which a high power voltage is applied, and the second pixel switching element A sixth pixel switching element comprising a fifth pixel switching element including an output electrode connected to the second node, a control electrode, an input electrode connected to the third node, and an output electrode connected to an anode electrode of the light emitting element, a control electrode , a seventh pixel switching element including an input electrode to which an initialization voltage is applied and an output electrode connected to the anode electrode of the light emitting element, a control electrode, an input electrode to which the bias voltage is applied, and an output connected to the second node An eighth pixel switching element including an electrode, a light emitting element including the anode electrode connected to the seventh pixel switching element and a cathode electrode to which a low power voltage is applied, the first electrode to which the high power voltage is applied, and the first electrode and a first capacitor including a second electrode connected to the first node, and a second capacitor including a first electrode connected to the third node and a second electrode connected to the fourth node.

In an embodiment of the present invention, the bias control signal may be applied to the control electrode of the eighth pixel switching element.

In an embodiment of the present invention, a first gate signal may be applied to the control electrode of the second pixel switching element. A second gate signal may be applied to the control electrode of the third pixel switching element.

In an embodiment of the present invention, a third gate signal may be applied to the control electrode of the fourth pixel switching element. A fourth gate signal may be applied to the control electrode of the seventh pixel switching element.

The fourth gate signal may be the same as the third gate signal applied to the next horizontal line.

A display device according to an embodiment of the present invention includes a display panel, a driving controller, a gate driver, an emission driver, a data driver, and a power supply voltage generator. The display panel includes a pixel including a driving switching device and a light emitting device. The driving control unit determines a variable driving frequency according to input image data or a driving mode. The gate driver outputs a gate signal and a bias control signal to the pixel. The emission driver outputs an emission signal to the pixel. The data driver outputs a data voltage to the pixel. The power supply voltage generator generates a bias voltage. The bias voltage of the writing frame is different from the bias voltage of the holding frame.

In an embodiment of the present invention, when the driving frequency is a normal frequency, the display panel may have only the writing frame. When the driving frequency is a low frequency driving frequency smaller than the normal frequency, the display panel may include the writing frame and the holding frame.

In one embodiment of the present invention, the bias voltage of the holding frame may be greater than the bias voltage of the writing frame.

In one embodiment of the present invention, the width of the bias control signal for applying the bias voltage to the driving switching element in the holding frame may be the same as the width of the bias control signal in the writing frame.

A method of driving a display device according to an embodiment of the present invention for realizing another object of the present invention includes determining a driving frequency that varies according to input image data or a driving mode; outputting a gate signal and a bias control signal; outputting an emission signal to the pixel; and outputting a data voltage to the pixel. In a writing frame, the bias control signal for applying a bias voltage to the driving switching element may have a first width, and in a holding frame, the bias control signal may have a second width different from the first width.

According to the display device and the driving method thereof, the width of the bias control signal of the writing frame and the width of the bias control signal of the holding frame are set to be different from each other when the variable frequency is driven, or the bias voltage of the writing frame and the bias of the holding frame are set differently. By setting the voltages to be different from each other, it is possible to remove the deviation between the bias degree of the writing frame and the bias degree of the holding frame when the variable frequency is driven.

Accordingly, the display quality of the display panel can be improved by removing the difference between the luminance of the image of the writing frame and the luminance of the image of the holding frame during the variable frequency driving.

In addition, power consumption of the display device may be reduced by performing a variable frequency driving operation in which deterioration of the display quality does not occur.

1 is a block diagram illustrating a display device according to an exemplary embodiment.
FIG. 2 is a circuit diagram illustrating a pixel of the display panel of FIG. 1 .
3 is a timing diagram illustrating input signals and node signals applied to the pixel of FIG. 2 .
4 is a circuit diagram illustrating an operation of the pixel of FIG. 2 in a first section.
FIG. 5 is a circuit diagram illustrating an operation in a second section of the pixel of FIG. 2 .
FIG. 6 is a circuit diagram illustrating operations in a third section and a fifth section of the pixel of FIG. 2 .
FIG. 7 is a circuit diagram illustrating operations of a fourth section and a sixth section of the pixel of FIG. 2 .
8 is a circuit diagram illustrating an operation of a seventh section of the pixel of FIG. 2 .
9 is a circuit diagram illustrating an operation of an eighth section of the pixel of FIG. 2 .
10 is a circuit diagram illustrating an operation of the pixel of FIG. 2 in a ninth section.
11 is a timing diagram illustrating input signals applied to the pixel of FIG. 2 in a writing frame.
12 is a timing diagram illustrating input signals applied to the pixel of FIG. 2 in a holding frame.
13 is a timing diagram illustrating an operation of the display device of FIG. 1 in a writing frame and a holding frame.
14 is a timing diagram illustrating an operation of a display device according to an exemplary embodiment in a writing frame and a holding frame.
15 is a timing diagram illustrating an operation of a display device according to an exemplary embodiment in a writing frame and a holding frame.
16 is a circuit diagram illustrating a pixel of a display panel of a display device according to an exemplary embodiment.
17 is a timing diagram illustrating input signals and node signals applied to the pixel of FIG. 16 .
18 is a timing diagram illustrating input signals applied to the pixel of FIG. 16 in a writing frame.
19 is a timing diagram illustrating input signals applied to the pixel of FIG. 16 in a holding frame.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram illustrating a display device according to an exemplary embodiment.

Referring to FIG. 1 , the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200 , a gate driver 300 , a gamma reference voltage generator 400 , a data driver 500 , and an emission driver 600 . The display panel driver further includes a power voltage generator 700 .

The display panel 100 includes a display unit for displaying an image and a peripheral unit disposed adjacent to the display unit.

The display panel 100 includes a plurality of gate lines GWL, GIL, and GCL, a plurality of bias lines EBL, a plurality of data lines DL, a plurality of emission lines EL1 and EL2 and and a plurality of pixels electrically connected to each of the gate lines GWL, GIL, and GCL, the bias lines EBL, the data lines DL, and the emission lines EL1 and EL2. The gate lines GWL, GIL, GCL and the bias lines EBL extend in a first direction D1 , and the data lines DL extend in a second direction crossing the first direction D1 . It extends in the direction D2, and the emission lines EL1 and EL2 extend in the first direction D1.

The driving controller 200 receives input image data IMG and an input control signal CONT from an external device (not shown). For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

The driving control unit 200 includes a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a second control signal CONT1 based on the input image data IMG and the input control signal CONT. 4 The control signal CONT4 and the data signal DATA are generated.

The driving controller 200 generates the first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and outputs it to the gate driver 300 . The first control signal CONT1 may include a vertical start signal and a gate clock signal.

The driving controller 200 generates the second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT and outputs the generated second control signal CONT2 to the data driver 500 . The second control signal CONT2 may include a horizontal start signal and a load signal.

The driving controller 200 generates a data signal DATA based on the input image data IMG. The driving control unit 200 outputs the data signal DATA to the data driving unit 500 .

The driving controller 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT to generate the gamma reference voltage generator ( 400) is printed.

The driving control unit 200 generates the fourth control signal CONT4 for controlling the operation of the emission driving unit 600 based on the input control signal CONT and outputs it to the emission driving unit 600 . do.

In the present embodiment, the driving controller 200 may determine a driving frequency that varies according to the input image data IMG or a driving mode. For example, when the input image data IMG is a still image, the driving controller 200 may determine the driving frequency as a relatively low frequency. For example, when the driving mode is a gaming mode, the driving controller 200 may determine to vary the driving frequency of the input image data IMG.

For example, when the driving frequency is a normal frequency, the display panel 100 may have only the writing frame. For example, the normal frequency may be the same as the input frequency of the input image data IMG.

For example, when the driving frequency is a low frequency driving frequency smaller than the normal frequency, the display panel 100 may include the writing frame and the holding frame. A data voltage may be written in the pixels of the display panel 100 in the writing frame. The data voltage may not be written to the pixels of the display panel 100 and the previously written data voltage may be maintained in the holding frame.

The gate driver 300 generates gate signals for driving the gate lines GWL, GIL, and GCL in response to the first control signal CONT1 received from the driving controller 200 . The gate driver 300 may output the gate signals to the gate lines GWL, GIL, and GCL. For example, the gate driver 300 may be mounted on the peripheral portion of the display panel 100 . For example, the gate driver 300 may be integrated in the peripheral portion of the display panel 100 .

In the present embodiment, the gate driver 300 generates bias signals for driving the bias lines EBL in response to the first control signal CONT1 received from the driving controller 200 . The gate driver 300 may output the bias signals to the bias lines EBL.

The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200 . The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500 . The gamma reference voltage VGREF has a value corresponding to each data signal DATA.

For example, the gamma reference voltage generator 400 may be disposed in the driving controller 200 or in the data driver 500 .

The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200 , and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400 . receive input. The data driver 500 converts the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

The emission driver 600 generates emission signals for driving the emission lines EL1 and EL2 in response to the fourth control signal CONT4 received from the driving controller 200 . The emission driver 600 may output the emission signals to the emission lines EL1 and EL2 .

The power supply voltage generator 700 may generate a high power supply voltage ELVDD, a low power supply voltage ELVSS, an initialization voltage VINT, a reference voltage VREF, and a bias voltage VBIAS. The power supply voltage generator 700 generates the high power supply voltage ELVDD, the low power supply voltage ELVSS, the initialization voltage VINT, the reference voltage VREF, and the bias voltage VBIAS to the display panel ( 100) of pixels.

FIG. 2 is a circuit diagram illustrating a pixel of the display panel 100 of FIG. 1 . 3 is a timing diagram illustrating input signals applied to the pixel of FIG. 2 .

1 to 3 , the display panel 100 includes a plurality of pixels, and each of the pixels includes a driving switching device T1 and an organic light emitting device EE.

The pixel includes a first pixel switching element (T1) including a control electrode connected to a first node (G), an input electrode connected to a second node (S), and an output electrode connected to a third node (D); A second pixel switching element T2 including a control electrode, an input electrode to which the data voltage VDATA is applied, and an output electrode connected to the fourth node A, a control electrode, and a control electrode connected to the first node G A third pixel switching element T3 including an input electrode and an output electrode connected to the third node D, a control electrode, an input electrode to which an initialization voltage VINT is applied, and the first node G are connected A fifth pixel switching element including a fourth pixel switching element T4 including an output electrode of T5), a sixth pixel switching element T6 including a control electrode, an input electrode connected to the third node D, and an output electrode connected to an anode electrode of the light emitting element EE, a control electrode, and the initialization voltage A seventh pixel switching element T7 including an input electrode to which VINT is applied and an output electrode connected to the anode electrode of the light emitting element EE, a control electrode, and an input electrode to which the bias voltage VBIAS is applied and an eighth pixel switching element T8 including an output electrode connected to the second node S, a control electrode, an input electrode to which the high power voltage ELVDD is applied, and the second node S connected to the second node S A light emitting element (EE) including a ninth pixel switching element (T9) including an output electrode, the anode electrode connected to the output electrode of the seventh pixel switching element (T7), and a cathode electrode to which a low power voltage is applied , a first capacitor CST including a first electrode to which the high power voltage is applied and a second electrode connected to the fourth node A, and a first electrode connected to the fourth node A and the A second capacitor (C) including a second electrode connected to the first node (G) PR) may be included.

A first gate signal GW may be applied to the control electrode of the second pixel switching element T2 . A third gate signal GC may be applied to the control electrode of the third pixel switching element T3 . A second gate signal GI may be applied to the control electrode of the fourth pixel switching element T4 . The third gate signal GC may be applied to the control electrode of the fifth pixel switching element T5 . A second emission signal EM2 may be applied to the control electrode of the sixth pixel switching element T6 . The bias control signal EB may be applied to the control electrode of the seventh pixel switching element T7 . The bias control signal EB may be applied to the control electrode of the eighth pixel switching element T8. A first emission signal EM1 may be applied to the control electrode of the ninth pixel switching element T9 .

For example, the first to ninth pixel switching elements T1 to T9 may be P-type thin film transistors. A control electrode of the first to ninth pixel switching elements T1 to T9 is a gate electrode, an input electrode of the first to ninth pixel switching elements T1 to T9 is a source electrode, and the first to ninth pixel switching elements are switched. The output electrode of the devices T1 to T9 may be a drain electrode.

Referring to FIG. 3 , in the first, third and fifth sections DR1 , DR3 , and DR5 , the first emission signal EM1 has a low level and the second emission signal EM2 has a high level. The second gate signal GI has a low level, the third gate signal GC has a high level, the first gate signal GW has a high level, and the bias control signal EB ) may have a high level. Also, the signal T1 GATE of the gate electrode of the first pixel switching element T1 may have a low level.

Here, the low level means an activation level, and the high level means a deactivation level.

In the second, fourth and sixth sections DR2, DR4, and DR6, the first emission signal EM1 has a low level, the second emission signal EM2 has a high level, and the second emission signal EM2 has a high level. The gate signal GI has a high level, the third gate signal GC has a low level, the first gate signal GW has a high level, and the bias control signal EB has a high level. can have Also, the signal T1 GATE of the gate electrode of the first pixel switching element T1 may have a high level.

In the seventh section DR7 , the first emission signal EM1 has a high level, the second emission signal EM2 has a high level, and the second gate signal GI has a high level. , the third gate signal GC may have a high level, the first gate signal GW may have a low pulse, and the bias control signal EB may have a high level. Also, the signal T1 GATE of the gate electrode of the first pixel switching element T1 may have a high level.

In the eighth section DR8, the first emission signal EM1 has a high level, the second emission signal EM2 has a high level, and the second gate signal GI has a high level. , the third gate signal GC may have a high level, the first gate signal GW may have a high level, and the bias control signal EB may have a low pulse. Also, the signal T1 GATE of the gate electrode of the first pixel switching element T1 may have a high level.

In the ninth section DR9, the first emission signal EM1 has a low level, the second emission signal EM2 has a low level, and the second gate signal GI has a high level. , the third gate signal GC may have a high level, the first gate signal GW may have a high level, and the bias control signal EB may have a high level. Also, the signal T1 GATE of the gate electrode of the first pixel switching element T1 may have a high level.

4 is a circuit diagram illustrating an operation of the pixel of FIG. 2 in a first section. FIG. 5 is a circuit diagram illustrating an operation in a second section of the pixel of FIG. 2 . FIG. 6 is a circuit diagram illustrating operations in a third section and a fifth section of the pixel of FIG. 2 . FIG. 7 is a circuit diagram illustrating operations of a fourth section and a sixth section of the pixel of FIG. 2 . 8 is a circuit diagram illustrating an operation of a seventh section of the pixel of FIG. 2 . 9 is a circuit diagram illustrating an operation of an eighth section of the pixel of FIG. 2 . 10 is a circuit diagram illustrating an operation of the pixel of FIG. 2 in a ninth section.

Referring to FIG. 4 , in the first period DR1 , the fourth pixel switching element T4 and the ninth pixel switching element T9 are turned on. A previous data voltage is written in the fourth node A. The initialization voltage VINT is applied to the first node G through the fourth pixel switching element T4. The high power voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. The first period DR1 may be referred to as a first initialization stage because the initialization voltage VINT is applied to the first node G.

Referring to FIG. 5 , in the second period DR2 , the third pixel switching element T3 , the fifth pixel switching element T5 , and the ninth pixel switching element T9 are turned on. The reference voltage VREF is applied to the fourth node A through the fifth pixel switching element T5. That is, the voltage of the fourth node A is changed from the previous data voltage to the reference voltage VREF. ELVDD-Vth is applied to the first node G through a path formed along the ninth pixel switching element T9 , the first pixel switching element T1 , and the third pixel switching element T3 . Here, Vth is the threshold voltage of the first pixel switching element T1. The high power voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. Since ELVDD-Vth is applied to the first node G in the second section DR2, it may be referred to as a first threshold compensation step. However, in this case, the voltage change at the fourth node (A) may affect the Vth compensation of the first node (G), which may be referred to as an incomplete threshold compensation step.

Referring to FIG. 6 , in the third period DR3 and the fifth period DR5 , the fourth pixel switching element T4 and the ninth pixel switching element T9 are turned on. The reference voltage VREF is applied to the fourth node A. The initialization voltage VINT is applied to the first node G through the fourth pixel switching element T4. The high power voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. Since the initialization voltage VINT is applied to the first node G in the third period DR3 and the fifth period DR5, it may be referred to as a second initialization phase and a third initialization phase.

Referring to FIG. 7 , in the fourth period DR4 and the sixth period DR6 , the third pixel switching element T3 , the fifth pixel switching element T5 , and the ninth pixel switching element T9 . is turned on The reference voltage VREF is applied to the fourth node A through the fifth pixel switching element T5. ELVDD-Vth is applied to the first node G through a path formed along the ninth pixel switching element T9 , the first pixel switching element T1 , and the third pixel switching element T3 . Here, Vth is the threshold voltage of the first pixel switching element T1. The high power voltage ELVDD is applied to the second node S through the ninth pixel switching element T9. Since ELVDD-Vth is applied to the first node G in the fourth period DR4 and the sixth period DR6 , it may be referred to as a second threshold compensating stage and a third threshold compensating stage. However, in this case, since the fourth node (A) is in a stable state with the reference voltage (VREF), it does not affect the Vth compensation of the first node (G), which can be called a complete threshold compensation step. can

In this embodiment, the initialization step is performed three times (DR1, DR3, DR5) and the threshold compensation step is performed three times (DR2, DR4, DR6), but the present invention is not limited thereto. , the initialization step may be performed more or less than three times, and the threshold compensation step may be performed more or less than three times.

Referring to FIG. 8 , in the seventh period DR7 , the second pixel switching element T2 is turned on. The data voltage VDATA is applied to the fourth node A through the second pixel switching element T2. ELVDD Vth + VDATA VREF may be applied to the first node G by coupling of the second capacitor CPR. The seventh period DR7 may be referred to as a data writing stage because ELVDD Vth + VDATA VREF is applied to the first node G.

Referring to FIG. 9 , in the eighth period DR8 , the seventh pixel switching element T7 and the eighth pixel switching element T8 are turned on. The data voltage VDATA is written in the fourth node A. ELVDD Vth + VDATA VREF is applied to the first node G by the coupling of the second capacitor CPR. The bias voltage VBIAS is applied to the second node S by the eighth pixel switching element T8. Also, the anode electrode of the light emitting device EE is initialized to the initialization voltage VINT by the seventh pixel switching device T7. The eighth period DR8 may be referred to as a bias stage because the bias voltage VBIAS is applied to the input electrode of the first pixel switching element T1 by the eighth pixel switching element T8.

Referring to FIG. 10 , the first pixel switching element T1 , the sixth pixel switching element T6 , and the ninth pixel switching element T9 are turned on in the ninth period DR9 . The data voltage VDATA is written in the fourth node A. ELVDD Vth + VDATA VREF is applied to the first node G by the coupling of the second capacitor CPR. The high power voltage ELVDD is applied to the second node S by the ninth pixel switching element T9. In the ninth section DR9, the light emitting element EE emits light along a path formed by the first, sixth, and ninth pixel switching elements T1, T6, and T9, and thus may be referred to as a light emitting stage. In this case, the drain-source current of the first pixel switching element T1 may be expressed as Equation 1 below.

[Formula 1]

Here, u is the mobility of the first pixel switching element T1, Cox is the capacitance per unit area of the first pixel switching element T1, and W/L is the mobility of the first pixel switching element T1. It can represent the ratio of width to length.

11 is a timing diagram illustrating input signals applied to the pixel of FIG. 2 in a writing frame. 12 is a timing diagram illustrating input signals applied to the pixel of FIG. 2 in a holding frame.

1 to 12 , as shown in FIG. 11 , in the lighting frame, the pixel may emit light through the process described with reference to FIGS. 4 to 10 . That is, in the writing frame, the first gate signal GW, the second gate signal GI, and the third gate signal GC have activation levels, and the pixel is subjected to the initialization step and the threshold compensation. step, the biasing step, and the light emitting step are sequentially performed.

On the other hand, as shown in FIG. 12 , in the holding frame, the initialization step, the threshold compensation step, the data writing step, etc. are omitted from the processes described with reference to FIGS. 4 to 10 , and the bias step and the light emission step are omitted. is performed

In the writing frame, in the initialization step, the initialization voltage VINT is applied to the first node G and the high power supply voltage ELVDD is applied to the second node S, even in the initialization step. A bias may be primarily applied to the first pixel switching element T1 . Also, in the writing frame, in the biasing step, the first pixel switching device T1 may be secondarily biased using the bias voltage VBIAS by the eighth pixel switching device T8.

On the other hand, since the initialization step is omitted in the holding frame, a bias is not primarily applied to the first pixel switching device T1, and in the biasing step, the first pixel switching device T8 causes the first pixel switching device T8. Only bias using the bias voltage VBIAS may be performed in the pixel switching device T1.

The deviation of the degree of bias between the writing frame and the holding frame may be expressed as a difference in luminance of images of the writing frame and the holding frame. Accordingly, the display quality of the display panel 100 may be deteriorated due to the difference in luminance.

In this embodiment, the bias control signal EB for applying a bias voltage to the driving switching element in a writing frame has a first width WW, and in a holding frame, the bias control signal EB is the first The second width WH may be different from the width WW. In the holding frame, an insufficient degree of bias needs to be increased, so that the second width WH may be set to be larger than the first width WW.

Also, in this embodiment, the bias voltage VBIAS of the writing frame may be the same as the bias voltage VBIAS of the holding frame. That is, in the present embodiment, the power supply voltage generator 700 may generate the bias voltage VBIAS having a constant level regardless of the writing frame and the holding frame.

13 is a timing diagram illustrating an operation of the display device of FIG. 1 in a writing frame and a holding frame.

1 to 13 , in FIG. 13 , the first frame is a 240 Hz frame, and 240 Hz may be a normal frequency. When the driving frequency is the normal frequency, the display panel 100 may have only a writing frame.

Since the first frame is a writing frame, in the initialization step, a bias is primarily performed on the first pixel switching element T1 using the initialization voltage VINT and the high power supply voltage ELVDD, In the biasing step, a second bias using the bias voltage VBIAS is additionally performed on the first pixel switching device T1 by the eighth pixel switching device T8.

The second to fifth frames may be frames representing 60 Hz. 60 Hz may be a low frequency driving frequency smaller than the normal frequency.

The second frame is a writing frame, and the third to fifth frames are holding frames. Since the second frame is a writing frame, in the initialization step, a bias is primarily performed on the first pixel switching element T1 using the initialization voltage VINT and the high power supply voltage ELVDD, In the biasing step, a second bias using the bias voltage VBIAS is additionally performed on the first pixel switching device T1 by the eighth pixel switching device T8. On the other hand, since the third to fifth frames are holding frames, since the initialization step is omitted, the bias voltage VBIAS is applied to the first pixel switching device T1 by the eighth pixel switching device T8 in the biasing step. ) is only used for biasing.

In the writing frame, the bias control signal EB for applying a bias voltage to the driving switching element has a first width WW, and in the holding frame, the bias control signal EB has the first width WW. Since it has the larger second width WH, it is possible to compensate for the lack of the degree of bias in the holding frame.

The sixth frame exemplifies a case of a 240 Hz frame, and 240 Hz may be a normal frequency.

According to the present embodiment, when the variable frequency is driven, the width of the bias control signal of the writing frame and the width of the bias control signal of the holding frame are set to be different from each other, or the bias voltage of the writing frame and the bias voltage of the holding frame are set to be different from each other. By setting it, it is possible to remove the deviation between the bias degree of the writing frame and the bias degree of the holding frame when the variable frequency is driven.

Accordingly, the display quality of the display panel can be improved by removing the difference between the luminance of the image of the writing frame and the luminance of the image of the holding frame during the variable frequency driving.

In addition, power consumption of the display device may be reduced by performing a variable frequency driving operation in which deterioration of the display quality does not occur.

14 is a timing diagram illustrating an operation of a display device according to an exemplary embodiment in a writing frame and a holding frame.

The display device and the driving method of the display device according to the present exemplary embodiment are substantially the same as the display device and the driving method of the display device of FIGS. 1 to 13 except for a method of compensating for a lack of bias, and thus have the same or similar configuration. The same reference numerals are used for elements, and overlapping descriptions are omitted.

Referring to FIG. 14 , in the present embodiment, the bias control signal EB for applying a bias voltage to the driving switching element in a writing frame has a first width WW, and in the holding frame, the bias control signal ( EB) may have a second width WW equal to the first width WW. Instead, the bias voltage VBIAS2 of the holding frame may be set to be greater than the bias voltage VBIAS1 of the writing frame because the holding frame needs to increase the insufficient degree of bias.

14 exemplifies a case in which the first frame is a 240 Hz frame, and 240 Hz may be a normal frequency. When the driving frequency is the normal frequency, the display panel 100 may have only a writing frame.

The second to fifth frames may be frames representing 60 Hz. 60 Hz may be a low frequency driving frequency smaller than the normal frequency.

The second frame is a writing frame, and the third to fifth frames are holding frames. Since the second frame is a writing frame, in the initialization step, a bias is primarily performed on the first pixel switching element T1 using the initialization voltage VINT and the high power supply voltage ELVDD, In the biasing step, a second bias using the bias voltage VBIAS is additionally performed on the first pixel switching device T1 by the eighth pixel switching device T8. On the other hand, since the third to fifth frames are holding frames, since the initialization step is omitted, the bias voltage VBIAS is applied to the first pixel switching device T1 by the eighth pixel switching device T8 in the biasing step. ) is only used for biasing.

In the writing frame, the bias control signal EB for applying a bias voltage to the driving switching element has a first width WW, and in the holding frame, the bias control signal EB has the first width WW. has On the other hand, the bias voltage VBIAS2 of the holding frame may be set to be greater than the bias voltage VBIAS1 of the writing frame.

The sixth frame exemplifies a case of a 240 Hz frame, and 240 Hz may be a normal frequency.

According to the present embodiment, when the variable frequency is driven, the width of the bias control signal of the writing frame and the width of the bias control signal of the holding frame are set to be different from each other, or the bias voltage of the writing frame and the bias voltage of the holding frame are set to be different from each other. By setting it, it is possible to remove the deviation between the bias degree of the writing frame and the bias degree of the holding frame when the variable frequency is driven.

Accordingly, the display quality of the display panel can be improved by removing the difference between the luminance of the image of the writing frame and the luminance of the image of the holding frame during the variable frequency driving.

In addition, power consumption of the display device may be reduced by performing a variable frequency driving operation in which deterioration of the display quality does not occur.

15 is a timing diagram illustrating an operation of a display device according to an exemplary embodiment in a writing frame and a holding frame.

The display device and the driving method of the display device according to the present exemplary embodiment are substantially the same as the display device and the driving method of the display device of FIGS. 1 to 13 except for a method of compensating for a lack of bias, and thus have the same or similar configuration. The same reference numerals are used for elements, and overlapping descriptions are omitted.

15 , in the present embodiment, the bias control signal EB for applying a bias voltage to the driving switching element in a writing frame has a first width WW, and in the holding frame, the bias control signal ( EB) may have a second width WH different from the first width WW. In the holding frame, an insufficient degree of bias needs to be increased, so that the second width WH may be set to be larger than the first width WW.

In addition, the bias voltage VBIAS2 of the holding frame may be set to be greater than the bias voltage VBIAS1 of the writing frame because the holding frame needs to increase the degree of bias that is insufficient.

15 exemplifies a case in which the first frame is a 240 Hz frame, and 240 Hz may be a normal frequency. When the driving frequency is the normal frequency, the display panel 100 may have only a writing frame.

The second to fifth frames may be frames representing 60 Hz. 60 Hz may be a low frequency driving frequency smaller than the normal frequency.

The second frame is a writing frame, and the third to fifth frames are holding frames. Since the second frame is a writing frame, in the initialization step, a bias is primarily performed on the first pixel switching element T1 using the initialization voltage VINT and the high power supply voltage ELVDD, In the biasing step, a second bias using the bias voltage VBIAS is additionally performed on the first pixel switching device T1 by the eighth pixel switching device T8. On the other hand, since the third to fifth frames are holding frames, since the initialization step is omitted, the bias voltage VBIAS is applied to the first pixel switching device T1 by the eighth pixel switching device T8 in the biasing step. ) is only used for biasing.

In the writing frame, the bias control signal EB for applying a bias voltage to the driving switching element has a first width WW, and in the holding frame, the bias control signal EB has the first width WW. Since it has the larger second width WH, it is possible to compensate for the lack of the degree of bias in the holding frame.

Also, the bias voltage VBIAS2 of the holding frame may be set to be greater than the bias voltage VBIAS1 of the writing frame.

The sixth frame exemplifies a case of a 240 Hz frame, and 240 Hz may be a normal frequency.

According to the present embodiment, when the variable frequency is driven, the width of the bias control signal of the writing frame and the width of the bias control signal of the holding frame are set to be different from each other, or the bias voltage of the writing frame and the bias voltage of the holding frame are set to be different from each other. By setting it, it is possible to remove the deviation between the bias degree of the writing frame and the bias degree of the holding frame when the variable frequency is driven.

Accordingly, the display quality of the display panel can be improved by removing the difference between the luminance of the image of the writing frame and the luminance of the image of the holding frame during the variable frequency driving.

In addition, power consumption of the display device may be reduced by performing a variable frequency driving operation in which deterioration of the display quality does not occur.

16 is a circuit diagram illustrating a pixel of a display panel of a display device according to an exemplary embodiment. 17 is a timing diagram illustrating input signals and node signals applied to the pixel of FIG. 16 . 18 is a timing diagram illustrating input signals applied to the pixel of FIG. 16 in a writing frame. 19 is a timing diagram illustrating input signals applied to the pixel of FIG. 16 in a holding frame.

The display device and the driving method of the display device according to the present exemplary embodiment are substantially the same as the display device and the driving method of the display device of FIGS. 1 to 13 , except for the structure of the pixel of the display panel. For the same reference numerals are used, and overlapping descriptions are omitted.

16 to 19 , the pixel includes a control electrode connected to a first node (G), an input electrode connected to a second node (S), and an output electrode connected to a third node (D) A second pixel switching element T2 including a first pixel switching element T1 , a control electrode, an input electrode to which the data voltage is applied, and an output electrode connected to a fourth node N4 , a control electrode, and the first A third pixel switching element T3 including an input electrode connected to the node G and an output electrode connected to the third node D, a control electrode, an input electrode to which a reference voltage is applied, and the fourth node ( A fifth pixel switching including a fourth pixel switching element T4 including an output electrode connected to N4 , a control electrode, an input electrode to which a high power voltage is applied, and an output electrode connected to the second node S A sixth pixel switching element T6 including an element T5, a control electrode, an input electrode connected to the third node D, and an output electrode connected to an anode electrode of the light emitting element EE, a control electrode, and initialization A seventh pixel switching element T7 including an input electrode to which a voltage is applied and an output electrode connected to the anode electrode of the light emitting element EE, a control electrode, an input electrode to which the bias voltage is applied, and the second node A light emitting device including an eighth pixel switching element T8 including an output electrode connected to (S), the anode electrode connected to the seventh pixel switching element T7, and a cathode electrode to which a low power voltage is applied ( EE), a first capacitor CST including a first electrode to which the high power voltage is applied, and a second electrode connected to the first node G, and a first electrode connected to the third node D and a second capacitor CPR including a second electrode connected to the fourth node N4 .

For example, the bias control signal EB2(N) may be applied to the control electrode of the eighth pixel switching element T8. A first gate signal GW(N) may be applied to the control electrode of the second pixel switching element T2 . A second gate signal GC(N) may be applied to the control electrode of the third pixel switching element T3 . For example, a third gate signal EB1(N) may be applied to the control electrode of the fourth pixel switching element T4 . For example, a fourth gate signal EB1 (N+1) may be applied to the control electrode of the seventh pixel switching element T7 . Here, the fourth gate signal EB1(N) may be the same as the third gate signal EB1(N+1) applied to the next horizontal line.

17 , the pixel may perform an initialization step and a data writing step in the first period DRA. In the first period DRA, the data voltage VDATA may be written to the pixel.

The pixel may be biased in the second period DRB. In the second period DRB, the bias voltage VBIAS may be written to the pixel.

The pixel may emit light in the third period DRC. In the third period DRC, the light emitting device EE emits light in response to the data voltage VDATA.

18 and 19 , in the present embodiment, the bias control signal EB2 for applying the bias voltage VBIAS to the driving switching element in the writing frame has a first width WW, and the holding frame The bias control signal EB2 may have a second width WH different from the first width WW. In the holding frame, an insufficient degree of bias needs to be increased, so that the second width WH may be set to be larger than the first width WW.

Also, in this embodiment, the bias voltage VBIAS of the writing frame may be the same as the bias voltage VBIAS of the holding frame. That is, in the present embodiment, the power supply voltage generator 700 may generate the bias voltage VBIAS having a constant level regardless of the writing frame and the holding frame.

According to the present embodiment, when the variable frequency is driven, the width of the bias control signal of the writing frame and the width of the bias control signal of the holding frame are set to be different from each other, or the bias voltage of the writing frame and the bias voltage of the holding frame are set to be different from each other. By setting it, it is possible to remove the deviation between the bias degree of the writing frame and the bias degree of the holding frame when the variable frequency is driven.

Accordingly, the display quality of the display panel can be improved by removing the difference between the luminance of the image of the writing frame and the luminance of the image of the holding frame during the variable frequency driving.

In addition, power consumption of the display device may be reduced by performing a variable frequency driving operation that does not cause deterioration of the display quality.

According to the display device and the driving method thereof according to the present invention described above, the display quality of the display panel can be improved by removing the difference between the luminance of the image of the writing frame and the luminance of the image of the holding frame.

Although it has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. will be able

100: display panel 200: driving control unit
300: gate driver 400: gamma reference voltage generator
500: data driver 600: emission driver
700: power supply voltage generator

Claims (20)

a display panel including a pixel including a driving switching device and a light emitting device;
a driving control unit configured to determine a variable driving frequency according to input image data or a driving mode;
a gate driver outputting a gate signal and a bias control signal to the pixel;
an emission driver outputting an emission signal to the pixel; and
and a data driver outputting a data voltage to the pixel;
In a writing frame, the bias control signal for applying a bias voltage to the driving switching element has a first width, and in a holding frame, the bias control signal has a second width different from the first width. . The display device of claim 1 , wherein the second width is greater than the first width. The display panel of claim 1 , wherein when the driving frequency is a normal frequency, the display panel has only the writing frame,
When the driving frequency is a low frequency driving frequency that is smaller than the normal frequency, the display panel includes the writing frame and the holding frame. The method of claim 1, wherein the pixel is
a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node;
a second pixel switching element including a control electrode, an input electrode to which a data voltage is applied, and an output electrode connected to a fourth node;
a third pixel switching element including a control electrode, an input electrode connected to the first node, and an output electrode connected to the third node;
a fourth pixel switching element including a control electrode, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node;
a fifth pixel switching element including a control electrode, an input electrode to which a reference voltage is applied, and an output electrode connected to the fourth node;
a sixth pixel switching element including a control electrode, an input electrode connected to the third node, and an output electrode connected to an anode electrode of the light emitting element;
a seventh pixel switching element including a control electrode, an input electrode to which the initialization voltage is applied, and an output electrode connected to the anode electrode of the light emitting element;
an eighth pixel switching element including a control electrode, an input electrode to which the bias voltage is applied, and an output electrode connected to the second node;
a ninth pixel switching element including a control electrode, an input electrode to which a high power voltage is applied, and an output electrode connected to the second node;
a light emitting device including the anode electrode connected to the output electrode of the seventh pixel switching device and a cathode electrode to which a low power voltage is applied;
a first capacitor including a first electrode to which the high power voltage is applied and a second electrode connected to the fourth node; and
and a second capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node. The display device of claim 4 , wherein the bias control signal is applied to the control electrode of the eighth pixel switching element. The display device of claim 5 , wherein the bias control signal is applied to the control electrode of the seventh pixel switching element. The display device of claim 4 , wherein a first gate signal is applied to the control electrode of the second pixel switching element. 8. The method of claim 7, wherein a second gate signal is applied to the control electrode of the fourth pixel switching element;
A third gate signal is applied to the control electrode of the third pixel switching element and the control electrode of the fifth pixel switching element. 5. The method of claim 4, wherein a first emission signal is applied to the control electrode of the ninth pixel switching element;
A second emission signal is applied to the control electrode of the sixth pixel switching element. The display device of claim 1 , further comprising a power voltage generator that generates a high power voltage, a low power voltage, an initialization voltage, a reference voltage, and the bias voltage and outputs the generated voltage to the pixel. The display device of claim 10 , wherein the bias voltage of the holding frame is greater than the bias voltage of the writing frame. The method of claim 1, wherein the pixel is
a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node;
a second pixel switching element including a control electrode, an input electrode to which the data voltage is applied, and an output electrode connected to a fourth node;
a third pixel switching element including a control electrode, an input electrode connected to the first node, and an output electrode connected to the third node;
a fourth pixel switching element including a control electrode, an input electrode to which a reference voltage is applied, and an output electrode connected to the fourth node;
a fifth pixel switching element including a control electrode, an input electrode to which a high power voltage is applied, and an output electrode connected to the second node;
a sixth pixel switching element including a control electrode, an input electrode connected to the third node, and an output electrode connected to an anode electrode of the light emitting element;
a seventh pixel switching element including a control electrode, an input electrode to which an initialization voltage is applied, and an output electrode connected to the anode electrode of the light emitting element;
an eighth pixel switching element including a control electrode, an input electrode to which the bias voltage is applied, and an output electrode connected to the second node;
a light emitting device including the anode electrode connected to the seventh pixel switching device and a cathode electrode to which a low power voltage is applied;
a first capacitor including a first electrode to which the high power voltage is applied and a second electrode connected to the first node; and
and a second capacitor including a first electrode connected to the third node and a second electrode connected to the fourth node. The display device of claim 12 , wherein the bias control signal is applied to the control electrode of the eighth pixel switching element. 14. The method of claim 13, wherein a first gate signal is applied to the control electrode of the second pixel switching element;
A second gate signal is applied to the control electrode of the third pixel switching element. 15. The method of claim 14, wherein a third gate signal is applied to the control electrode of the fourth pixel switching element,
a fourth gate signal is applied to the control electrode of the seventh pixel switching element;
and the fourth gate signal is the same as the third gate signal applied to a next horizontal line. a display panel including a pixel including a driving switching device and a light emitting device;
a driving control unit configured to determine a variable driving frequency according to input image data or a driving mode;
a gate driver outputting a gate signal and a bias control signal to the pixel;
an emission driver outputting an emission signal to the pixel;
a data driver outputting a data voltage to the pixel; and
A power supply voltage generator for generating a bias voltage,
and the bias voltage of the writing frame is different from the bias voltage of the holding frame. The method of claim 16 , wherein when the driving frequency is a normal frequency, the display panel has only the writing frame,
When the driving frequency is a low frequency driving frequency that is smaller than the normal frequency, the display panel includes the writing frame and the holding frame. The display device of claim 16 , wherein the bias voltage of the holding frame is greater than the bias voltage of the writing frame. The display device of claim 18 , wherein a width of the bias control signal for applying the bias voltage to the driving switching element in the holding frame is the same as a width of the bias control signal in the writing frame. determining a variable driving frequency according to input image data or a driving mode;
outputting a gate signal and a bias control signal to a pixel including a driving switching device and a light emitting device;
outputting an emission signal to the pixel; and
outputting a data voltage to the pixel;
In a writing frame, the bias control signal for applying a bias voltage to the driving switching element has a first width, and in a holding frame, the bias control signal has a second width different from the first width. of the driving method.

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