KR20220097116A - Electroluminescence Display Device - Google Patents

Abstract

The present invention relates to an electroluminescence display device. According to an embodiment of the present invention, the electroluminescence display device comprises: a display panel including a plurality of pixels and a plurality of readout lines connected to the pixels; and a sensing circuit sensing a driving current of the pixels through a plurality of sensing channels connected to the readout lines. The sensing circuit includes: two or more high-input processing stages sensing and amplifying the driving current and converting the amplification results from analog to digital; switches for parallel access which parallelly connect the high-input processing stages to different sensing channels in a first segment; and switches for serial access which serially connect the high-input processing stages to each other in a second segment next to the first segment. The present invention aims to provide an electroluminescence display device which is capable of minimizing sensing errors and maximizing sensing ability.

Description

Electroluminescence Display Device

This specification relates to an electroluminescent display device.

The electroluminescent display is divided into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. Each pixel of the electroluminescent display device includes a light emitting element that emits light by itself, and the luminance is adjusted by controlling the amount of light emitted by the light emitting element with a data voltage according to the gray level of image data.

The threshold voltage (or operating point voltage) of the light emitting device may vary in pixels according to process deviation and/or the lapse of driving time. If there is a deviation in driving characteristics between pixels, the pixel current contributing to light emission in the pixels is inevitably different even when the same data voltage is applied. This deviation of the pixel current causes luminance non-uniformity and deteriorates image quality.

In the electroluminescent display device, various attempts have been made to compensate for the deviation in driving characteristics between pixels, but the chip size of the data driver with a built-in sensing circuit increases, and the accuracy of sensing is not sufficient due to an error for each sensing channel, resulting in uniform luminance. There are limits to securing gender.

Accordingly, the embodiment disclosed in the present specification is to solve the above-described problems, and provides an electroluminescent display device capable of reducing a mounting area of a sensing circuit in a data driver and minimizing a sensing error.

An electroluminescent display device according to an embodiment of the present specification includes: a display panel having a plurality of pixels and a plurality of lead-out lines connected to the pixels; and a sensing circuit configured to sense the driving current of the pixels through a plurality of sensing channels connected to the read-out lines. The sensing circuit may include: at least two or more high-input processing stages for sensing and amplifying the driving current and converting the amplification result into analog-to-digital; In a first section, a mux circuit connecting the high-input processing stages to different sensing channels in parallel; and a cascading circuit connecting the high-input processing stages in series with each other in a second section following the first section.

This embodiment has the following effects.

The electroluminescent display device according to the embodiment of the present specification includes a current-voltage conversion circuit that converts a current flowing from a sensing channel into a voltage in the pipeline ADC, thereby reducing the area occupied by the sensing circuit in the data driver and power consumption can reduce The sensing circuit of this embodiment shares a current sensing scheme through parallel sensing and serial amplification in the pipeline ADC, thereby minimizing sensing error and maximizing sensing capability.

Effects according to the present specification are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram illustrating an electroluminescent display device according to an exemplary embodiment of the present specification.
2 is a diagram illustrating an example in which a sensing channel of a sensing circuit is connected to a pixel of a display panel through a lead-out line.
3 is a block diagram schematically illustrating a sensing circuit.
4A is a diagram illustrating an example in which two high-input processing stages are connected in parallel to ten sensing channels in a sensing circuit.
FIG. 4B is a diagram illustrating operation timings of the MUX circuit, switches for parallel connection, and switches for series connection included in FIG. 4A .
5A is a diagram illustrating an example in which three high-input processing stages are connected in parallel to nine sensing channels in a sensing circuit.
FIG. 5B is a diagram illustrating operation timings of the MUX circuit, switches for parallel connection, and switches for series connection included in FIG. 5A .
6 is a diagram illustrating a detailed configuration of the high-input processing stages shown in FIGS. 4A and 4B .
FIG. 7 is a diagram of driving waveforms for the high-input processing stages of FIG. 6 .
8A to 8C are diagrams illustrating an operation process of an MDAC included in the high-input processing stages of FIG. 6 .
9 is a driving waveform diagram for the MDAC of FIGS. 8A to 8C.
FIG. 10 is a view showing operating states of high-input processing stages in section DX1 of FIG. 7 .
FIG. 11 is a view showing operation states of high-input processing stages in the DX2 section of FIG. 7 .
12A is a diagram illustrating input/output of a first high-input processing stage in a section DX2 of FIG. 7 .
12B is a diagram illustrating input/output of a second high-input processing stage in a section DX2 of FIG. 7 .
FIG. 13 is a view showing operating states of high-input processing stages in the DY section of FIG. 7 .
14A is a diagram illustrating input/output of a first high-input processing stage in a section DY of FIG. 7 .
14B is a diagram illustrating input/output of a second high-input processing stage in the DY section of FIG. 7 .
15 is a diagram illustrating one output of a sensing circuit.
16 is a diagram illustrating an example of error correction of a sensing circuit.
17 is a diagram illustrating a configuration of a low-input processing stage.
18 is a driving timing diagram for the low input processing stage of FIG. 17 .

Advantages and features of the present specification, and a method for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present specification to be complete, and common knowledge in the technical field to which this specification belongs It is provided to fully inform those who have the scope of the invention, and the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and thus the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

The first, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

1 is a block diagram illustrating an electroluminescent display device according to an exemplary embodiment of the present specification. 2 is a diagram illustrating an example in which a sensing channel of a sensing circuit is connected to a pixel of a display panel through a readout line.

Referring to FIG. 1 , an electroluminescent display device according to an exemplary embodiment of the present specification includes a display panel 10 , a timing controller 11 , a data driver 12 , and a gate driver 13 .

In the display panel 10 , a plurality of data lines 14A, a plurality of readout lines 14B, and a plurality of gate lines 15 cross each other, and pixels PXL are formed in a matrix in each crossed area. are arranged in a shape to constitute a pixel array.

Two or more pixels PXL connected to different data lines 14A may share the same readout line 14B and the same gate line 15 . For example, the R pixel for red display, the W pixel for the white display, the G pixel for the green display, and the B pixel for the blue display connected to the same gate line 15 next to each other are horizontally adjacent to each other on one lead-out line 14B. can be commonly connected to. According to the reference voltage line sharing structure, since the structure of the pixel array is simplified, it is easy to secure an aperture ratio of the display panel and it is easy to secure a process margin. Under the reference voltage line sharing structure, a plurality of data lines 14A may be disposed between adjacent readout lines 14B.

The R pixel, W pixel, G pixel, and B pixel may constitute one unit pixel. In a unit pixel, red, white, green, and blue images may be combined with each other to implement various colors according to a grayscale ratio (or a light emission ratio). The unit pixel may include an R pixel, a G pixel, and a B pixel.

Each of the pixels PXL receives the high potential pixel voltage EVDD and the low potential pixel voltage EVSS through a power supply line PWL connected to a power generation circuit (not shown). The pixel PXL of the present specification may have a circuit structure suitable for sensing deterioration of the driving device and/or the light emitting device according to the lapse of driving time and/or environmental conditions such as panel temperature.

The timing controller 11 may implement a sensing mode for sensing driving and a display mode for driving a display according to a predetermined control sequence. Here, the sensing driving is driving to sense the driving characteristics of the driving element and/or the light emitting element (hereinafter referred to as driving characteristics of the pixel) and updating the compensation value accordingly, and the display driving is to compensate the input image data DATA. This is a driving operation for reproducing the display image by writing the corrected image data CDATA in which the value is reflected on the display panel 10 . Under the control of the timing controller 11, the sensing driving may be performed in the booting period before the display driving starts, in the vertical blank period during the display driving, or in the power-off period after the display driving is finished. . The booting period refers to the period from when the system power is applied until the screen is turned on. The power-off period refers to the period from when the screen is turned off until the system power is turned off. The vertical blank section is located between the vertical active sections in which the corrected image data CDATA is written on the display panel 10 .

Meanwhile, the sensing driving may be performed in a state in which only the screen of the display device is turned off while the system power is being applied, for example, in a standby mode, a sleep mode, a low power mode, and the like. The timing controller 11 may detect a standby mode, a sleep mode, a low power mode, etc. according to a predetermined control process, and may control general operations for sensing driving.

The timing controller 11 controls the operation timing of the gate driver 13 and the data timing control signal DDC for controlling the operation timing of the data driver 12 based on the timing signals TSIG input from the host system. A gate timing control signal GDC for controlling may be generated. The timing controller 11 may generate the timing control signals DDC and GDC for driving the display and the timing control signals DDC and GDC for driving the sensing differently.

The gate timing control signal GDC includes a gate start pulse, a gate shift clock, and the like. A gate start pulse is applied to the gate stage that produces the first output to control that gate stage. The gate shift clock is a clock signal input to the gate stages and is a clock signal for shifting the gate start pulse.

The data timing control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the data driver 12 . The source sampling clock is a clock signal that controls the sampling timing of data based on a rising or falling edge. The source output enable signal controls the output timing of the data driver 12 .

The timing controller 11 may include a compensation circuit and a memory.

The compensation circuit receives sensing result data SDATA representing driving characteristics of a pixel from the data driver 12 during sensing driving. The compensation circuit calculates a compensation value capable of compensating for a luminance deviation according to a change in driving characteristics of a pixel based on the sensing result data SDATA, and stores the compensation value in a memory. The compensation value stored in the memory may be updated whenever a sensing operation is performed.

Meanwhile, the sensing driving may be performed in a time division manner in units of pixel lines and in units of colors (RWGB). For example, the sensing driving is performed sequentially or out-of-sequentially by one pixel line by one pixel line by targeting only all pixels of the first color included in the pixel array, and then performing one pixel by targeting only all pixels of the second color It is done line by line in a sequential or non-sequential manner. Also, the sensing driving may be performed on the pixels of the third and fourth colors in the same manner. The compensation value calculation operation may be performed after sensing of all color pixels PXL of the pixel array is completed. Here, each of the pixel lines does not mean a physical signal line, but an aggregate of horizontally adjacent pixels PXL.

The compensation circuit may correct the input image data DATA based on the compensation value read from the memory when the display is driven, and supply the corrected image data CDATA to the data driver 12 . A luminance deviation due to a change in driving characteristics of a pixel may be compensated for by the corrected image data CDATA.

The data driver 12 includes at least one or more source driver integrated circuits. The source driver IC may include a voltage generating circuit connected to each data line 14A and a sensing circuit 121 as shown in FIG. 2 .

The voltage generating circuit converts the corrected image data CDATA into a data voltage for display according to the data timing control signal DDC applied from the timing controller 11 when driving the display, and supplies the converted image data CDATA to the data lines 14A. Meanwhile, the voltage generation circuit may generate a data voltage for sensing according to the data timing control signal DDC applied from the timing controller 11 during sensing driving and supply it to the data lines 14A.

The data voltage for sensing may include an on-level data voltage capable of turning on the driving device and an off-level data voltage capable of driving the driving device off. The on-level data voltage is a voltage applied to the gate electrode of the driving device during sensing driving to turn on the driving device (ie, a voltage that generates the flow of pixel current), and the off-level data voltage is the gate electrode of the driving device during sensing driving. It is a voltage applied to to turn off the driving element (ie, a voltage that blocks the flow of pixel current). The on-level data voltage may be set to have different sizes in the R (red), G (green), B (blue), and W (white) pixels in consideration of the different driving characteristics of the driving device/light emitting device for each color. , but not limited thereto.

The on-level data voltage is applied to the sensing pixel within one unit pixel, and the off-level data voltage is applied to the non-sensing pixels sharing the readout line 14B with the sensing pixel within the one unit pixel. For example, in FIG. 2 , when the R pixel is sensed and the W, G, and B pixels are not sensed, the on-level data voltage is applied to the driving element of the R pixel, and the off-level data voltage is the W, G, and B pixels. It may be applied to a driving element of each of the pixels.

The sensing circuit 121 senses the driving current of the pixels PXL through the plurality of sensing channels SCH connected to the read-out lines 14B. The sensing circuit 121 is implemented as a pipeline analog to digital converter (ADC). Since a current-voltage conversion circuit that converts a current flowing in from the sensing channel SCH into a voltage is included in the pipeline ADC, the area occupied by the sensing circuit 121 in the data driver 12 is reduced and power consumption is reduced. can The sensing circuit 121 may minimize a sensing error and maximize sensing capability by using a pipeline ADC that shares a current sensing scheme through parallel sensing and serial amplification processes.

The gate driver 13 may generate a sensing gate signal (or scan signal) based on the gate control signal GDC during sensing driving and then sequentially or non-sequentially supply the sensing gate signal (or scan signal) to the gate lines 15 . The sensing gate signal is a sensing scan signal synchronized with the sensing data voltage. The pixel lines L1 to Ln may be sensed and driven sequentially or non-sequentially by the sensing gate signal and the sensing data voltage.

The gate driver 13 may generate a display gate signal (or scan signal) based on the gate control signal GDC when driving the display, and then sequentially supply the generated gate signal (or scan signal) to the gate lines 15 . The display gate signal is a display scan signal synchronized with the display data voltage. The pixel lines L1 to Ln may be sequentially display driven by the display gate signal and the display data voltage.

3 is a block diagram schematically illustrating the sensing circuit 121 .

Referring to FIG. 3 , the sensing circuit 121 includes M (M is a natural number greater than or equal to 2) high-input processing stages (HST1 to HSTm, HSTG), and N (N is a natural number greater than M) sensing channels (SCH) MUX circuits (MUX) and switches for parallel connection connecting M high input processing stages (HSTG) in parallel to each other, and switches for serial connection connecting M high input processing stages (HSTG) in series with each other include The mux circuit MUX is connected between the sensing channels SCH and the switches for parallel connection, and serves to selectively connect the sensing channels SCH to the switches for parallel connection. Since the number of the high-input processing stages HST1 to HSTm and HSTG is reduced by the mux circuit MUX and the switches for parallel connection than the number of the sensing channels SCH, the size of the sensing circuit 121 and Manufacturing cost can be reduced. Meanwhile, according to the embodiment shown in FIG. 6 , the mux circuit MUX may be omitted.

The sensing circuit 121 includes a plurality of low-input processing stages LSTG1 to LSTGi that are serially connected to the M high-input processing stages HSTG to receive the output of the previous stage, and the high-input processing stages HSTG. The device may further include an error correction unit configured to output digital sensing result data SDATA by correcting the outputs and outputs of the low-input processing stages LSTG1 to LSTGi.

In the first section, the sensing circuit 121 connects the M high-input processing stages HSTG to different sensing channels SCH through the mux circuit MUX and parallel connection switches in parallel to generate sensing channels. Simultaneously sense driving currents flowing from (SCH). In the second section following the first section, the sensing circuit 121 connects the high-input processing stages (HSTG) in series with each other through switches for serial connection, so that the pipeline ADC (Analog to Digital Converter) and other new concept It can act as an ADC. Since the M high-input processing stages HSTG transmit and receive output signals in a cascading manner, a sensing error is remarkably reduced, and a separate scaler circuit is not required in the sensing circuit 121 . Accordingly, there is an advantage in that the mounting area of the sensing circuit 121 is greatly reduced.

4A to 5B are diagrams for schematically explaining a configuration and operation examples of the sensing circuit 121 .

4A is a diagram illustrating an example in which two high-input processing stages are connected in parallel to ten sensing channels in a sensing circuit. FIG. 4B is a diagram illustrating operation timings of the MUX circuit, switches for parallel connection, and switches for series connection included in FIG. 4A .

Referring to FIG. 4A , the mux circuit MUX includes first to tenth mux switches SM1 to SM10 respectively connected to the first to tenth sensing channels SCH1 to SCH10. Among the first to tenth mux switches SM1 to SM10, the first, 3, 5, 7, and 9 mux switches SM1, SM3, SM5, SM7, SM9 connect the first parallel connection switch SA1. connected to the first high-input processing stage HST1 through the It is connected to the second high-input processing stage HST2. The first switch for parallel connection (SA1) and the second switch for parallel connection (SA2) constitute the switches for parallel connection (SRY1). A first serial connection switch SB1 is connected between the first high-input processing stage HST1 and the second high-input processing stage HST2, and the second high-input processing stage HST2 and the first low-input processing stage A second serial connection switch SB2 is connected between the LSTG1. The first switch for serial connection (SB1) and the second switch for serial connection (SB2) constitute the switches for serial connection (SRY2).

The sensing circuit of FIG. 4A may sequentially process driving currents corresponding to ten sensing channels through the first to fifth sensing periods PED1 to PED5 as shown in FIG. 4B . In each of the first to fifth sensing periods PED1 to PED5 , two sensing channels may be simultaneously connected to the sensing circuit.

At the first timing of the first sensing period PED1 , the first and second mux switches SM1 and SM2 and the first and second parallel connection switches SA1 and SA2 are simultaneously turned on and then turned off. In this case, the first and second high-input processing stages HST1 and HST2 simultaneously sense first and second driving currents flowing from the first and second sensing channels SCH1 and SCH2, respectively. Subsequently, at the second timing of the first sensing period PED1 , the first and second series connection switches SB1 and SB2 are simultaneously turned on and then turned off, followed by a third timing of the first sensing period PED1 . is turned off after the second switch for serial connection (SB2) is turned on. Then, each of the first and second high-input processing stages HST1 and HST2 simultaneously amplifies the sensed result, and applies the amplified result to the plurality of low-input processing stages LSTG1 to LSTGi through a cascading method. ), the digital sensing result data SDATA corresponding to the first and second driving currents may be output.

At the first timing of the second sensing period PED2 , the third and fourth mux switches SM3 and SM4 and the first and second parallel connection switches SA1 and SA2 are simultaneously turned on and then turned off. Then, the first and second high-input processing stages HST1 and HST2 simultaneously sense the third and fourth driving currents flowing in from the third and fourth sensing channels SCH3 and SCH4, respectively. Subsequently, at the second timing of the second sensing period PED2 , the first and second series connection switches SB1 and SB2 are simultaneously turned on and then turned off, followed by a third timing of the second sensing period PED2 . is turned off after the second switch for serial connection (SB2) is turned on. Then, each of the first and second high-input processing stages HST1 and HST2 simultaneously amplifies the sensed result, and applies the amplified result to the plurality of low-input processing stages LSTG1 to LSTGi through a cascading method. ), digital sensing result data SDATA corresponding to the third and fourth driving currents may be output.

In the same way, after the ninth and tenth mux switches SM9 and SM10 and the first and second parallel connection switches SA1 and SA2 are simultaneously turned on at the first timing of the fifth sensing period PED5 turns off Then, the first and second high input processing stages HST1 and HST2 simultaneously sense the ninth and tenth driving currents flowing from the ninth and tenth sensing channels SCH9 and SCH10, respectively. Subsequently, at the second timing of the fifth sensing period PED5 , the first and second series connection switches SB1 and SB2 are simultaneously turned on and then turned off, followed by a third timing of the fifth sensing period PED5 . is turned off after the second switch for serial connection (SB2) is turned on. Then, each of the first and second high-input processing stages HST1 and HST2 simultaneously amplifies the sensed result, and applies the amplified result to the plurality of low-input processing stages LSTG1 to LSTGi through a cascading method. ), the digital sensing result data SDATA corresponding to the ninth and tenth driving currents may be output.

5A is a diagram illustrating an example in which three high-input processing stages are connected in parallel to nine sensing channels in a sensing circuit. FIG. 5B is a diagram illustrating operation timings of the MUX circuit, switches for parallel connection, and switches for series connection included in FIG. 5A .

Referring to FIG. 5A , the mux circuit MUX includes first to ninth mux switches SM1 to SM9 respectively connected to the first to ninth sensing channels SCH1 to SCH9. Among the first to ninth mux switches SM1 to SM9, the first, fourth, and seventh mux switches SM1, SM4, and SM7 are connected to the first high-input processing stage ( HST1), and the second, fifth, and eighth mux switches SM2, SM5, and SM8 are connected to the second high-input processing stage HST2 through the second parallel connection switch SA2, and the third, The 6 and 9 mux switches SM3, SM6, and SM9 are connected to the third high input processing stage HST3 through the third parallel connection switch SA3. The first switch SA1 for parallel connection, the second switch SA2 for parallel connection, and the third switch SA3 for parallel connection constitute the switches SRY1 for parallel connection. A first serial connection switch SB1 is connected between the first high-input processing stage HST1 and the second high-input processing stage HST2, and the second high-input processing stage HST2 and the third high-input processing stage A second serial connection switch SB2 is connected between HST3, and a third serial connection switch SB3 is connected between the third high input processing stage HST3 and the first low input processing stages LSTG1. connected The first switch for serial connection SB1 , the second switch for serial connection SB2 , and the third switch for serial connection SB3 constitute the switches for serial connection SRY2 .

The sensing circuit of FIG. 5A may sequentially process driving currents corresponding to the nine sensing channels through the first to third sensing periods PED1 to PED3 as shown in FIG. 5B . In each of the first to third sensing periods PED1 to PED3 , three sensing channels may be simultaneously connected to the sensing circuit.

At the first timing of the first sensing period PED1 , the first to third mux switches SM1 to SM3 and the first to third parallel connection switches SA1 to SA3 are simultaneously turned on and then turned off. In this case, the first to third high input processing stages HST1 to HST3 simultaneously sense first to third driving currents flowing from the first to third sensing channels SCH1 to SCH3 , respectively. Subsequently, at the second timing of the first sensing period PED1 , the first to third series connection switches SB1 to SB3 are simultaneously turned on and then turned off, and then, at the third timing of the first sensing period PED1 . is turned off after the second and third switches for serial connection SB2 and SB3 are turned on, and then turned off after the third switch for serial connection SB3 is turned on at the fourth timing of the first sensing period PED1 do. Then, each of the first to third high-input processing stages HST1 to HST3 simultaneously amplifies the sensed result, and cascading the amplified result to the plurality of low-input processing stages LSTG1 to LSTGi. ), the digital sensing result data SDATA corresponding to the first to third driving currents may be output.

At the first timing of the second sensing period PED2 , the fourth to sixth mux switches SM4 to SM6 and the first to third parallel connection switches SA1 to SA3 are simultaneously turned on and then turned off. In this case, the first to third high input processing stages HST1 to HST3 simultaneously sense fourth to sixth driving currents flowing from the fourth to sixth sensing channels SCH4 to SCH6, respectively. Subsequently, at the second timing of the second sensing period PED2 , the first to third series connection switches SB1 to SB3 are simultaneously turned on and then turned off, and then, at the third timing of the second sensing period PED2 . In , the second and third switches SB2 and SB3 for series connection are turned off after being turned on, and then, at the fourth timing of the second sensing period PED2, after the third switch for series connection SB3 is turned on, they are turned off. do. Then, each of the first to third high-input processing stages HST1 to HST3 simultaneously amplifies the sensed result, and cascading the amplified result to the plurality of low-input processing stages LSTG1 to LSTGi. ), the digital sensing result data SDATA corresponding to the fourth to sixth driving currents may be output.

At the first timing of the third sensing period PED3 , the seventh to ninth mux switches SM7 to SM9 and the first to third parallel connection switches SA1 to SA3 are simultaneously turned on and then turned off. In this case, the first to third high input processing stages HST1 to HST3 simultaneously sense seventh to ninth driving currents flowing from the seventh to ninth sensing channels SCH7 to SCH9, respectively. Subsequently, at the second timing of the third sensing period PED3 , the first to third series connection switches SB1 to SB3 are simultaneously turned on and then turned off, and then, at the third timing of the third sensing period PED3 . In , the second and third switches for series connection SB2 and SB3 are turned off after being turned on, and then, at the fourth timing of the third sensing period PED3, after the third switch for series connection SB3 is turned on, they are turned off. do. Then, each of the first to third high-input processing stages HST1 to HST3 simultaneously amplifies the sensed result, and cascading the amplified result to the plurality of low-input processing stages LSTG1 to LSTGi. ), the digital sensing result data SDATA corresponding to the seventh to ninth driving currents may be output.

6 is a diagram illustrating a detailed configuration of the first and second high input processing stages HST1 and HST2 illustrated in FIGS. 4A and 4B . And, FIG. 7 is a driving waveform diagram for the high-input processing stages of FIG. 6 . 6 and 7 , the configuration and operation timing of the MUX circuit are omitted.

6 and 7 , the first and second high-input processing stages HST1 and HST2 simultaneously sense the driving current in the first period DX, and use the sensed result in the second period DY. is amplified at the same time, and the additively amplified result is sequentially output in the second section DY. In FIG. 6 , SA1 and SA2 indicate the aforementioned switches for parallel connection SRY1 , and SB1 and SB2 indicate the aforementioned switches for serial connection SRY2 .

The first high-input processing stage HST1 includes a first sensing & amplifier circuit MDAC1, a first analog-to-digital conversion circuit SADC1, a first digital-to-analog conversion circuit DAC1, a first latch circuit LL1, and a first output latch LAT1.

The first sensing & amplification circuit MDAC1 is connected to the first sensing channel SCH1 through SA1, receives a first driving current from the first sensing channel SCH1, senses and amplifies the first driving current, 1 Create an analog output (Vout1). The first sensing & amplifier circuit MDAC1 includes a first amplifier AMP1 having an inverting input terminal (-) connected to SA1, a non-inverting input terminal (+) to which a reference voltage Vref is input, and an output terminal; 1 The first feedback capacitor CFB1 and the first reset switch RST1 connected in parallel between the inverting input terminal (-) and the output terminal of the first amplifier AMP1, and the output terminal and the first node of the first amplifier AMP1 A switch S11 connected between (N1), a first sampling capacitor (CSM1) having one electrode connected to the switch S11 through a first node (N1) and the other electrode connected to a second node (N2), a first sampling capacitor The switch S12 connected between the other electrode (ie, the second node N2) of CSM1 and the input terminal of the reference voltage Vref, the inverting input terminal (-) of the first amplifier AMP1 and the first sampling capacitor A switch S13 connected between the other electrode (ie, second node N2) of CSM1 and one electrode (ie, first node N1) of the first sampling capacitor CSM1 and a first digital-to-analog conversion and a switch S14 connected between the circuit DAC1.

The first digital-to-analog conversion circuit DAC1 is connected to the first node N1 through a switch S14 while the amplification operation is performed in the first sensing & amplification circuit MDAC1, and the input of the first sensing channel SCH1 A set voltage (eg, any one of 0.75V, 0V, and -0.75V) corresponding to the voltage is supplied to the first node N1 . Accordingly, the first analog output Vout1, which is an amplified value for the first driving current, becomes (first sensing channel SCH1 input voltage + set voltage)*CSM1/CFB1. The first digital-to-analog conversion circuit DAC1 selectively outputs a set voltage (eg, any one of 0.75V, 0V, -0.75V) a first digital-analog switch DAS1, a first digital-analog switch ( and a first latch logic LL1 for controlling the operation of the DAS1 .

The first analog-to-digital conversion circuit SADC1 converts the first analog output Vout1 of the first sensing & amplifier circuit MDAC1 into a digital sensing value. The first analog-to-digital conversion circuit SADC1 includes a first operation circuit X1 for outputting a first operation result by comparing the first analog output Vout1 with (+) 1/4 Vref, and a first analog output ( and a second arithmetic circuit Y1 that compares Vout1) with (-) 1/4 Vref and outputs a second arithmetic result.

The first latch circuit LL1 supplies the digital sensed value input from the first analog-to-digital conversion circuit SADC1 to the first output latch LAT1 . The first output latch LAT1 outputs the digital sensed value to the outside.

The second high-input processing stage HST2 includes a second sensing and amplification circuit MDAC2, a second analog-to-digital conversion circuit SADC2, a second digital-to-analog conversion circuit DAC2, a second latch circuit LL2, and a second output latch LAT2.

The second sensing & amplification circuit MDAC2 is connected to the second sensing channel SCH2 through SA2, receives a second driving current from the second sensing channel SCH2, senses and amplifies the second driving current, and 2 Create an analog output (Vout2). The second sensing & amplification circuit MDAC2 includes a second amplifier AMP2 having an inverting input terminal (-) connected to SA2, a non-inverting input terminal (+) to which a reference voltage Vref is input, and an output terminal; 2 The second feedback capacitor CFB2 and the second reset switch RST2 connected in parallel between the inverting input terminal (-) and the output terminal of the second amplifier AMP2, and the output terminal and the third node of the second amplifier AMP2 A switch S21 connected between (N3), a second sampling capacitor (CSM2) having one electrode connected to the switch S21 through a third node (N3) and the other electrode connected to a fourth node (N4), and a second sampling capacitor The switch S22 connected between the other electrode (ie, the fourth node N4) of CSM2 and the input terminal of the reference voltage Vref, the inverting input terminal (-) of the second amplifier AMP2 and the second sampling capacitor A switch S23 connected between the other electrode (ie, the fourth node N4) of the CSM2 and the one electrode (ie, the third node N3) of the second sampling capacitor CSM2 and a second digital-analog conversion a switch S24 connected between the circuit DAC2, and a switch S25 connected between the output terminal of the second amplifier AMP2 and the second analog-to-digital conversion circuit SADC2.

The second digital-to-analog conversion circuit DAC2 is connected to the third node N3 through the switch S24 while the amplification operation is performed in the second sensing & amplification circuit MDAC2, and the input of the second sensing channel SCH2 A set voltage corresponding to the voltage (eg, any one of 0.75V, 0V, and -0.75V) is supplied to the third node N3 . Accordingly, the second analog output Vout2, which is an amplified value of the second driving current, becomes (second sensing channel SCH2 input voltage+set voltage)*CSM1/CFB1. The second digital-analog conversion circuit DAC2 selectively outputs a set voltage (eg, any one of 0.75V, 0V, -0.75V) a second digital-analog switch DAS2, a second digital-analog switch ( and a second latch logic LL2 that controls the operation of the DAS2 .

The second analog-to-digital conversion circuit SADC2 changes the first analog output Vout1 of the first sensing & amplifier circuit MDAC1 to a digital sensing value, and then, when the switch S25 is turned on, the second sensing & amplifier circuit ( The second analog output Vout2 of MDAC2 is changed to a digital sensing value. The second analog-to-digital conversion circuit SADC2 compares the first and second analog outputs Vout1 and Vout2 with (+) 1/4 Vref, respectively, and outputs a third operation result by comparing them with a third operation circuit X2 and , and a fourth operation circuit Y2 for outputting a fourth operation result by comparing the first and second analog outputs Vout1 and Vout2 with (-) 1/4 Vref, respectively.

The second latch circuit LL2 supplies the digital sensed value input from the second analog-to-digital conversion circuit SADC2 to the second output latch LAT2 . The second output latch LAT2 outputs the digital sensed value to the outside.

Referring to FIG. 7 , during a first period DX in which the control pulse Psam has an on level, SA1 and SA2 maintain an on state. The first section DX includes a reset section DX1 and a sampling section DX2. At a first timing within the reset period DX1, the control pulse P11 and the control pulse P12 have an on level. RST1 is turned on by the on-level control pulse P11, and RST2 is turned on by the on-level control pulse P12. At a second timing (here, the second timing is later than the first timing) within the sampling period DX2, the control pulse P21 and the control pulse P22 have an on level. S11 and S12 are turned on by the on-level control pulse P21, and S21, S22, and S25 are turned on by the on-level control pulse P22.

Referring to FIG. 7 , the control pulse P31 and the control pulse P32 have an on level at the third timing (here, the third timing is later than the second timing) within the second period DY. S13, S14, and SB1 are turned on by the on-level control pulse P31, and S23, S23, and SB2 are turned on by the on-level control pulse P32.

Referring to FIG. 7 , the control pulse P12 has the on level again at the fourth timing (here, the fourth timing is later than the third timing) within the second period DY. RST2 is turned on again by the on-level control pulse P12.

Referring to FIG. 7 , the control pulse P22 has the on level again at the fifth timing (here, the fifth timing is later than the fourth timing) within the second period DY. S21, S22, and S25 are turned on again by the on-level control pulse P22.

Referring to FIG. 7 , at the sixth timing (here, the sixth timing is later than the fifth timing) within the second period DY, the control pulse P32 has the on level again. S23, S23, and SB2 are turned on again by the on-level control pulse P32.

8A to 8C are diagrams illustrating an operation process of an MDAC included in the high-input processing stages of FIG. 6 . And, FIG. 9 is a driving waveform diagram for the MDAC of FIGS. 8A to 8C.

8A and 9 , the switch SA is turned on in response to the control pulse Фsam in the reset section DX1 and the switch RST is turned on in response to the control pulse Ф1. As a result, the input terminals (-, +) and output terminals of the sensing channel SCH, the amplifier AMP are reset to the reference voltage Vref. In the reset section DX1, the analog output Vout of the amplifier AMP becomes the reference voltage Vref.

8B and 9 , the switch SA maintains an on state in response to the control pulse Фsam within the sampling period DX2, and the switches S1 and S2 are turned on in response to the control pulse Ф2. As a result, the driving current flowing in from the sensing channel SCH is stored in the feedback capacitor CFB, and the analog output Vout of the amplifier AMP is lower than the reference voltage Vref by “Vref-VФ2”.

8C and 9 , the switches S3 and S4 are turned on in response to the control pulse Ф3 within the amplification period DY. As a result, due to the capacitance distribution operation between the feedback capacitor CFB and the sampling capacitor CSM, the analog output Vout of the amplifier AMP is “(Vref-VФ2)*(CSM/CFB)” compared to “VФ2” It is amplified by lowering it by as much as

FIG. 10 is a diagram illustrating operating states of first and second high input processing stages HST1 and HST2 in section DX1 of FIG. 7 .

7 and 10, the switches SA1 and SA2 are turned on in response to the control pulse Psam within the reset section DX1, and the switch RST1 is turned on in response to the control pulse P11, and the control pulse P12 In response, switch RST2 turns on. As a result, the first and second high input processing stages HST1 and HST2 are reset.

FIG. 11 is a diagram illustrating operating states of first and second high-input processing stages HST1 and HST2 in section DX2 of FIG. 7 . 12A is a diagram illustrating input/output of the first high input processing stage HST1 in the section DX2 of FIG. 7 . And, FIG. 12B is a diagram showing the input/output of the second high input processing stage HST2 in the section DX2 of FIG. 7 .

7 and 11 , in response to the control pulse Psam within the sampling period DX2, the switches SA1 and SA2 maintain an on state, and in response to the control pulse P21, the switches S11 and S12 are turned on , the switches S21 and S22 are turned on in response to the control pulse P22.

As a result, a digital output as shown in FIG. 12A is generated in the first high-input processing stage HST1 and a digital output as shown in FIG. 12B is generated in the second high-input processing stage HST2.

In FIG. 12A , the bar graph on the left represents a 1.5-bit output with respect to the current input value. This bar graph divides the 00, 01, and 10 digital output ranges based on -1/4Vref (-0.375V, Y1 and Y2 references) and 1.4Vref (0.375V, X1 and X2 references). In FIG. 12A , the residual graph on the right makes it possible to predict the output of the value passed to the next stage after the output of the input value. In the residual graph, “00,01,10,11” located on the right side is the next stage prediction values, and “00,01,10” located on the bottom side is the current stage output values.

When the sensing voltage value obtained from the first sensing channel SCH1 of the first high input processing stage HST1 of FIG. 11 is -0.4V, the value output through the first output latch LAT1 is "00" as shown in the bar graph. " will be displayed. And, after being output through the first output latch LAT1, a value output from the diaphragm stage indicates a position of -0.4V on the horizontal axis in the residual graph.

When the sensing voltage value obtained from the second sensing channel SCH2 of the second high input processing stage HST2 of FIG. 11 is -0.1V, the value output through the second output latch LAT2 is “01” as shown in the bar graph. " will be displayed. And, after being output through the second output latch LAT2, the value output from the diaphragm stage indicates a position of -0.1V on the horizontal axis in the residual graph.

FIG. 13 is a diagram illustrating operating states of first and second high input processing stages HST1 and HST2 in the DY section of FIG. 7 . 14A is a diagram illustrating input/output of the first high-input processing stage HST1 in the DY section of FIG. 7 . And, FIG. 14B is a diagram illustrating input/output of the second high input processing stage HST2 in the DY section of FIG. 7 .

7 and 13 , the switches S13, S14, and SB1 are turned on in response to the control pulse P31 in the amplification period DY, and the switches S23, S24, and SB2 are turned on in response to the control pulse P32. become a state

The first digital-analog switch DAS1 selects 0.75V through the output value “00” (refer to FIG. 12A ) of the first high-input processing stage HST1, and the first analog output Vout1 uses the first processing formula changed to 0.7V. Here, the first processing equation is "Vout1 = (CSM/CFB)*(previous stage value + previous stage DAS selection value)", and CSM1/CFB1 may be 2. In other words, the first analog output Vout1 may be changed to 0.7V through the first processing equation, Vout1=(2)*(-0.4+0.75). The changed first analog output Vout1 is applied to the second analog-to-digital conversion circuit SADC2 of the second high input processing stage HST2.

In the left bar graph of FIG. 14A , 0.7V indicates a digital output corresponding to “10”, and the point marked at -0.4V on the horizontal axis of the left residual graph is Vout1 “10” section on the right at the intersection with the residual graph is the corresponding value.

The second digital-analog switch DAS2 selects 0V through the output value “01” (refer to FIG. 12B ) of the second high-input processing stage HST2, and the second analog output Vout2 is output through the second processing equation It is changed to -0.2V. Here, the second processing equation is "Vout2 = (CSM/CFB)*(previous stage value + previous stage DAS selection value)", and CSM1/CFB1 may be 2. In other words, the second analog output Vout2 may be changed to -0.2V through the second processing equation, Vout2=(2)*(-0.1+0). The modified second analog output Vout2 is applied to the analog-to-digital conversion circuit of the low input processing stage.

In the left bar graph of FIG. 14B, -0.2V indicates a digital output corresponding to "01", and the point marked at -0.1V on the horizontal axis of the left residual graph is Vout2 "01" section on the right at the intersection with the residual graph is a value corresponding to

15 is a diagram illustrating one output of a sensing circuit. And, FIG. 16 is a diagram showing an example of error correction of a sensing circuit.

Referring to FIG. 15 , assuming that the digital sensing result data SDATA output to the sensing circuit 121 is 10 bits, the sensing circuit 121 includes two high-input processing stages HST1 and HST2 and It may include a plurality of low-input processing stages LSTG1 to LSTG8.

The high-input and low-input processing stages are interconnected in a cascade manner. The high input processing stages HST1 and HST2 are in charge of the upper bit area of the digital sensing result data SDATA, and the low input processing stages LSTG1 to LSTG8 are in charge of the lower bit area of the digital sensing result data SDATA. do.

The value sampled in the first high input processing stage HST1 is a 10-bit value after passing through the first and second high input processing stages HST1 and HST2 and the plurality of low input processing stages LSTG1 to LSTG7. generated as a digital output. Similarly, the value sampled in the second high-input processing stage HST2 is generated as a 10-bit digital output after passing through the second high-input processing stage HST2 and the plurality of low-input processing stages LSTG1 to LSTG8 do.

15 illustrates an output value of each processing stage when -0.4V is sampled in the first high-input processing stage HST1 as an example. Each processing stage determines an output value according to the processing equation illustrated in FIG. 13 , and outputs a digital value that matches each section “00, 01, 10”.

16 shows that values obtained through 9 processing stages are output as final 10 bits through an error correction unit. Values output as 1.5-bits from each processing stage are listed as shown in FIG. 16 and then output as the final bit through the addition of the lower bit of each stage and the upper bit of the next stage.

The error correction unit receives the outputs D1 to D9 of the high and low input processing stages, and corrects the sensing error based on the outputs D1 to D9, thereby minimizing the sensing error. The error correction unit outputs digital sensing result data SDATA in which the sensing error is corrected.

17 is a diagram illustrating a configuration of a low-input processing stage. And, FIG. 18 is a driving timing diagram for the low input processing stage of FIG. 17 .

Referring to FIG. 17 , the low-input processing stage is serially connected to the previous stage (high-input or low-input processing stage), and the residual value after processing in the previous stage is calculated by the formula Vout = (CSM/CFB)*(previous stage value) + It receives and processes it through the previous stage DAS selection value).

The low-input processing stage may include a sensing and amplification circuit (MDAC) for sensing and amplifying the output of the previous stage, and an analog-to-digital conversion circuit (SADC) for digitally converting the output of the previous stage.

The sensing & amplification circuit (MDAC) and the analog-to-digital conversion circuit (SADC) have a difference in that they are composed of relatively low-voltage devices compared to the corresponding components of the high-input processing stage, but in terms of generating a series of ADC outputs It can be seen that substantially the same operation is performed.

The sensing & amplification circuit (MDAC) includes a digital-to-analog conversion circuit (DAC) connected to the output terminal of the analog-to-digital conversion circuit (SADC), and a non-inverting input terminal to which an inverting input terminal (-) and a base voltage (GND) are input. An amplifier AMP having a positive (+) and an output terminal, a first capacitor CFB connected between an inverting input terminal (-) of the amplifier AMP and a first node Na, and the output of the previous stage are input The first switch T21 connected between the input terminal IN and the first node Na, the second switch T22 connected between the input terminal IN and the second node Nb, and the second node The second capacitor (CSAM) connected between (Nb) and the inverting input terminal (-) of the amplifier (AMP), and the second capacitor (CSAM) connected between the inverting input terminal (-) of the amplifier (AMP) and the input terminal of the base voltage (GND) 3 switch T23, a fourth switch T31 connected between the first node Na and the output terminal, and a fifth switch T32 connected between the second node Nb and the digital-to-analog converter circuit DAC ) is included.

18 , the first, second, and third switches T21, T22, and T23 maintain an on state according to the first control signal CT1, and the fourth and fifth switches T31 and T32 maintains an on state according to the second control signal CT2. Here, the first control signal CT1 and the second control signal CT2 are turned on/off in reverse. In order to increase the stability and reliability of operation, the on-level section of the first control signal CT1 is wider than the off-level section of the second control signal CT2, and the on-level section of the second control signal CT2 has the first control It may be wider than the off-level section of the signal CT1 .

17 and 18, the low-input processing stage also outputs 1.5-bit output from the analog-to-digital conversion circuit (SADC) to D<0> D<1> for the output value received from the previous stage, and the remaining remaining after processing Values are passed to the next stage through the formula Vout = (CSM/CFB)* (stage value + stage's DAS selection value).

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driver 13: gate driver
14A: data line 14B: readout line
121: sensing circuit

Claims (14)

a display panel including a plurality of pixels and a plurality of lead-out lines connected to the pixels; and
a sensing circuit for sensing the driving current of the pixels through a plurality of sensing channels connected to the read-out lines;
The sensing circuit is
at least two or more high-input processing stages for sensing and amplifying the driving current and converting the amplification result into analog-to-digital;
In a first section, switches for parallel connection connecting the high-input processing stages to different sensing channels in parallel; and
In a second section following the first section, the electroluminescent display device includes switches for serial connection connecting the high-input processing stages to each other in series. The method of claim 1,
The high-input processing stages are
The electroluminescent display device simultaneously senses the driving current in the first section, amplifies the sensed result in the second section, and sequentially outputs the amplified result in the second section. The method of claim 1,
Each of the high-input processing stages,
a sensing & amplification circuit for sensing and amplifying the driving current;
an analog-to-digital conversion circuit connected to an output terminal of the sensing & amplification circuit; and
An electroluminescent display including a digital-to-analog conversion circuit connected to the sensing & amplification circuit and the analog-to-digital conversion circuit. 4. The method of claim 3,
The sensing & amplification circuit is
an amplifier having an inverting input terminal connected to any one of the switches for parallel connection, a non-inverting input terminal to which a reference voltage is input, and the output terminal;
a first capacitor and a reset switch connected in parallel between the inverting input terminal and the output terminal of the amplifier;
a first switch coupled to the output terminal of the amplifier;
a second capacitor having one electrode connected to the first switch;
a second switch connected between the second electrode of the second capacitor and the input terminal of the reference voltage;
a third switch connected between the inverting input terminal of the amplifier and the other electrode of the second capacitor; and
and a fourth switch connected between one electrode of the second capacitor and the digital-analog conversion circuit. 5. The method of claim 4,
The operation period of the sensing & amplification circuit includes a reset period, a sampling period following the reset period, and an amplification period following the sampling period. 6. The method of claim 5,
The switches for parallel connection maintain an on state in the reset section and the sampling section,
The first switch and the second switch maintain an on state in the sampling period,
The third switch, the fourth switch, and the series connection switches maintain an on state in the amplification section. The method of claim 1,
a plurality of low-input processing stages connected in series to the high-input processing stages to receive an output of the previous stage; and
The electroluminescent display device further comprising an error correction unit for outputting digital sensing result data by correcting outputs of the high input processing stages and outputs of the low input processing stages. 8. The method of claim 7,
Each of the low-input processing stages,
a sensing & amplification circuit for sensing and amplifying the output of the previous stage; and
An electroluminescent display device including an analog-to-digital conversion circuit for digitally converting the output of the previous stage. 9. The method of claim 8,
The sensing & amplification circuit is
a digital-to-analog conversion circuit connected to an output terminal of the analog-to-digital conversion circuit;
an amplifier having an inverting input terminal, a non-inverting input terminal to which a base voltage is input, and an output terminal;
a first capacitor coupled between the inverting input terminal of the amplifier and a first node;
a first switch connected between an input terminal to which an output of the previous stage is input and the first node;
a second switch connected between the input terminal and a second node;
a second capacitor coupled between the second node and the inverting input terminal of the amplifier;
a third switch connected between the inverting input terminal of the amplifier and the input terminal of the base voltage;
a fourth switch connected between the first node and the output terminal; and
and a fifth switch connected between the second node and the digital-analog conversion circuit. 10. The method of claim 9,
The first, second and third switches maintain an on state according to a first control signal,
The fourth and fifth switches maintain an on state according to a second control signal,
The first control signal and the second control signal are turned on/off in opposite directions. 11. The method of claim 10,
An on-level section of the first control signal is wider than an off-level section of the second control signal,
An on-level section of the second control signal is wider than an off-level section of the first control signal. The method of claim 1,
The electroluminescent display device further comprising a mux circuit connected between the sensing channels and the switches for parallel connection, and selectively connecting the sensing channels to the switches for parallel connection. 13. The method of claim 12,
The mux circuit includes a plurality of mux switches respectively connected to the sensing channels,
The number of the MUX switches is less than the number of the switches for parallel connection. 14. The method of claim 13,
The mux switches include a mux switch of a first group and a mux switch of a second group operating at different timings,
In the first sensing section, the mux switch of the first group and the switches for parallel connection are turned on and off at the same time,
In a second sensing section following the first sensing section, the mux switch of the second group and the switches for parallel connection are turned on and off at the same time.

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