KR20220050512A - Electroluminescence Display Device - Google Patents

Abstract

In accordance with an embodiment of the present invention, an electroluminescence display device includes: a display panel (10) including a sensing pixel (PX1), a non-sensing pixel (PX3), an on-driving data line (DL1) connected to the sensing pixel (PX1), a floating driving data line (DL3) connected to the non-sensing pixel (PX3), a reference voltage line (RL) connected to the sensing pixel (PX1) and the non-sensing pixel (PX3), and a feedback capacitor (CPS) connected between the reference voltage line (RL) and the floating driving data line (DL3); and a data driver (20) in which an integrator amplifier (AMP) having a first input terminal (-) connected to the reference voltage line (RL) and having a second input terminal (+) connected to an integrator reference voltage (CVref), and a reset switch (RST) connected between an output terminal and a first input terminal of the integrator amplifier are mounted. In a sensing mode for sensing a pixel current flowing in the sensing pixel (PX1), the feedback capacitor (CPS) is connected between the output terminal and the first input terminal of the integrator amplifier. Therefore, the present invention is capable of improving the accuracy and reliability of sensing.

Description

Electroluminescence Display Device

This specification relates to an electroluminescent display device.

The electroluminescent display is divided into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. Each pixel of the electroluminescent display device includes a light emitting element that emits light by itself, and the luminance is adjusted by controlling the amount of light emitted by the light emitting element with a data voltage according to the gray level of image data.

The threshold voltage (or operating point voltage) of the light emitting device may vary in pixels according to process deviation and/or the lapse of driving time. If there is a deviation in driving characteristics between pixels, the pixel current contributing to light emission in the pixels is inevitably different even when the same data voltage is applied. This deviation of the pixel current causes luminance non-uniformity and deteriorates image quality.

In the electroluminescent display device, various attempts have been made to compensate for the deviation in driving characteristics between pixels, but the chip size of the data driver with a built-in sensing circuit increases, and the sensing accuracy is insufficient due to noise to ensure luminance uniformity there is a limit to

Accordingly, the embodiment disclosed in the present specification is to solve the above-described problem, and provides an electroluminescent display device capable of reducing a mounting area of a sensing circuit in a data driver and minimizing the effect of sensing noise.

The electroluminescent display device according to an embodiment of the present invention includes a sensing pixel PX1, a non-sensing pixel PX3, an on-drive data line DL1 connected to the sensing pixel PX1, and a non-sensing pixel PX3 connected to A floating driving data line DL3, a reference voltage line RL connected to the sensing pixel PX1 and the non-sensing pixel PX3, and a reference voltage line RL connected between the floating driving data line DL3 a display panel 10 having a feedback capacitor (CPS); and an integrator amplifier (AMP) having a first input terminal (−) connected to the reference voltage line (RL) and a second input terminal (+) connected to an integrator reference voltage (CVref), a first input terminal of the integrator amplifier and and a data driver 20 having a reset switch RST connected between output terminals mounted thereon, and in a sensing mode for sensing a pixel current flowing through the sensing pixel PX1, the first input terminal of the integrator amplifier and The feedback capacitor CPS is connected between the output terminals.

This embodiment has the following effects.

The electroluminescent display device according to the embodiment of the present specification uses a parasitic capacitor formed between the reference voltage line and the floating driving data line as a feedback capacitor of the current integrator. Since the feedback capacitor is formed on the display panel instead of being mounted in the data driver, the size and mounting area of the sensing circuit may be reduced.

In the present specification, since the capacity of the feedback capacitor can be increased without increasing the size of the sensing circuit, the influence of sensing noise can be minimized and the accuracy and reliability of sensing can be improved.

In addition, the electroluminescent display device according to the embodiment of the present specification sets the first reference voltage applied to the floating driving data line to be lower than the integrator reference voltage applied to the reference voltage line, thereby causing abnormal conduction of non-sensing pixels in the sensing period. (that is, generation of abnormal pixel current) can be prevented.

In addition, in the electroluminescent display device according to the embodiment of the present specification, panel noise is commonly input to the first input terminal and the second input terminal of the integrator amplifier to be canceled inside the integrator amplifier, so that the sensory result is distorted due to panel noise This phenomenon can be prevented in advance and the accuracy of sensing can be improved.

Effects according to the present specification are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram illustrating an electroluminescent display device according to an exemplary embodiment of the present specification.
2 is a diagram illustrating an example of connection of one unit pixel sharing a reference voltage line.
3 is a diagram showing an example of a configuration of a pixel array and a source driver IC.
4 is a diagram illustrating an example of a configuration of one unit pixel and a sensing circuit according to an embodiment of the present specification.
FIG. 5 is an equivalent circuit diagram of one pixel included in one unit pixel of FIG. 4 .
6 is a diagram illustrating a connection configuration between one unit pixel and a data driver according to the first embodiment of the present specification.
FIG. 7 is a driving waveform diagram of the components shown in FIG. 6 .
FIG. 8A is a diagram illustrating operation states of corresponding components in the initialization section of FIG. 7 .
FIG. 8B is a diagram illustrating operation states of corresponding components in the sensing section of FIG. 7 .
9 is a diagram illustrating a connection configuration of one unit pixel and a data driver according to a second embodiment of the present specification.
FIG. 10 is a driving waveform diagram of the components shown in FIG. 9 .
FIG. 11A is a diagram illustrating operation states of corresponding components in the initialization section of FIG. 10 .
FIG. 11B is a diagram illustrating operation states of corresponding components in the sensing section of FIG. 10 .
12 is a diagram illustrating a connection configuration between one unit pixel and a data driver according to a third embodiment of the present specification.
13 is a driving waveform diagram of the components shown in FIG. 12 .
FIG. 14A is a diagram illustrating operation states of corresponding components in the initialization section of FIG. 13 .
FIG. 14B is a view showing operating states of corresponding components in the sensing section of FIG. 13 .

Advantages and features of the present specification, and a method for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present specification to be complete, and common knowledge in the technical field to which this specification belongs It is provided to fully inform those who have the scope of the invention, and the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and thus the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

The first, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

In the present specification, the pixel circuit formed on the substrate of the display panel may be implemented as a TFT having an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure or as a TFT having a p-type MOSFET structure. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type TFT, since electrons flow from the source to the drain, the direction of the current flows from the drain to the source. In contrast, in the case of a p-type TFT (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed according to the applied voltage.

Meanwhile, in the present specification, the semiconductor layer of the TFT may be implemented with at least one of an oxide device, an amorphous silicon device, and a polysilicon device.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

1 is a block diagram illustrating an electroluminescent display device according to an exemplary embodiment of the present specification. 2 is a diagram illustrating an example of connection of one unit pixel sharing a reference voltage line. And, FIG. 3 is a diagram showing a configuration example of a pixel array and a source driver IC.

1 to 3 , an electroluminescent display device according to an exemplary embodiment of the present specification includes a display panel 10 , a timing controller 11 , a data driver 12 , a gate driver 13 , and a memory 16 . , a compensation circuit 20 , and a power generation circuit 30 .

In the display panel 10 , a plurality of data lines 14A, a plurality of reference voltage lines 14B, and a plurality of gate lines 15 cross each other, and pixels PXL are matrixed in each crossed area. are arranged in a shape to constitute a pixel array.

Two or more pixels PXL connected to different data lines 14A may share the same reference voltage line 14B and the same gate line 15 . For example, as shown in FIG. 2 , an R pixel for a red display, a W pixel for a white display, a G pixel for a green display, and a B pixel for a blue display, which are horizontally adjacent to each other and connected to the same gate line 15 are one reference. It may be commonly connected to the voltage line 14B. According to the reference voltage line sharing structure, since the structure of the pixel array is simplified, it is easy to secure an aperture ratio of the display panel and it is easy to secure a process margin. Under the reference voltage line sharing structure, a plurality of data lines 14A may be disposed between adjacent reference voltage lines 14B. The reference voltage line 14B may include a main part ML and a branch part BL. The main part ML may be positioned parallel to the data line 14A, and the branch part BL may be positioned to cross the data line 14A. A parasitic capacitor CP may be formed by the intersection between the branch portion BL and the data line 14A. The parasitic capacitor CP is connected between the inverting input terminal and the output terminal of the current integrator in the sensing mode for sensing the driving characteristic of the pixel PXL, thereby serving as a feedback capacitor to store the pixel current flowing in the sensing pixel. can do. Meanwhile, the reference voltage line 14B also serves to supply the reference voltage to the pixels PXL in the display mode and the sensing mode.

The R pixel, the W pixel, the G pixel, and the B pixel may constitute one unit pixel as shown in FIG. 2 . In a unit pixel, red, white, green, and blue images may be combined with each other to implement various colors according to a grayscale ratio (or a light emission ratio). The unit pixel may include an R pixel, a G pixel, and a B pixel.

Each of the pixels PXL receives the high-potential pixel voltage EVDD and the low-potential pixel voltage EVSS from the power generation circuit 30 . The pixel PXL of the present specification may have a circuit structure suitable for accurately sensing deterioration of the driving device and/or the light emitting device according to the lapse of driving time and/or environmental conditions such as panel temperature.

The timing controller 11 may implement a sensing mode for sensing driving and a display mode for driving a display according to a predetermined control sequence. Here, the sensing driving is driving for sensing the operating point voltage (or threshold voltage) of the light emitting device and updating the compensation value accordingly, and the display driving is the display panel 10 by providing the corrected image data CDATA reflecting the compensation value. It is a drive that reproduces the displayed image by writing. Under the control of the timing controller 11 , sensing driving may be performed in a booting period before display driving starts, or in a power-off period after display driving is finished. The booting period refers to the period from when the system power is applied until the screen is turned on. The power-off period refers to the period from when the screen is turned off until the system power is turned off.

Meanwhile, the sensing driving may be performed in a state in which only the screen of the display device is turned off while the system power is being applied, for example, in a standby mode, a sleep mode, a low power mode, and the like. The timing controller 11 may detect a standby mode, a sleep mode, a low power mode, etc. according to a predetermined sensing process, and may control general operations for sensing driving.

The timing controller 11 is a data driver based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE input from the host system. The data timing control signal DDC for controlling the operation timing of 12 ) and the gate timing control signal GDC for controlling the operation timing of the gate driver 13 may be generated. The timing controller 11 may generate the timing control signals DDC and GDC for driving the display and the timing control signals DDC and GDC for driving the sensing differently.

The gate timing control signal GDC includes a gate start pulse, a gate shift clock, and the like. A gate start pulse is applied to the gate stage that produces the first output to control that gate stage. The gate shift clock is a clock signal input to the gate stages and is a clock signal for shifting the gate start pulse.

The data timing control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the data driver 12 . The source sampling clock is a clock signal that controls the sampling timing of data based on a rising or falling edge. The source output enable signal controls the output timing of the data driver 12 .

The timing controller 11 may include a compensation circuit 20 .

The compensation circuit 20 receives the sensing result data SDATA for the operating point voltage of the light emitting device from the sensing circuit SU during sensing driving. The compensation circuit 20 calculates a compensation value capable of compensating for a luminance deviation due to a process deviation or deterioration (ie, shift of the operating point voltage) of the light emitting device and/or the driving device based on the sensing result data SDATA. and this compensation value is stored in the memory 16 . The compensation value stored in the memory 16 may be updated whenever a sensing operation is performed.

Meanwhile, the sensing driving may be performed in a time division manner in units of pixel lines L1 to Ln and in units of colors RWGB. For example, the sensing driving is performed sequentially or out-of-sequentially by one pixel line by one pixel line by targeting only all pixels of the first color included in the pixel array, and then performing one pixel by targeting only all pixels of the second color It is done line by line in a sequential or non-sequential manner. Also, the sensing driving may be performed on the pixels of the third and fourth colors in the same manner. The compensation value calculation operation may be performed after sensing of all color pixels PXL of the pixel array is completed. Here, each of the pixel lines L1 to Ln does not mean a physical signal line, but an aggregate of horizontally adjacent pixels PXL.

The compensation circuit 20 may correct the data DATA of the input image based on the compensation value read from the memory 16 when driving the display, and supply the corrected image data CDATA to the data driver 12 . A luminance deviation due to a difference in characteristics of a light emitting device and/or a driving device may be compensated for by the corrected image data CDATA.

The data driver 12 includes at least one source driver integrated circuit (SDIC). The source driver IC (SDIC) includes a digital-to-analog converter (hereinafter, DAC) connected to each data line 14A, a sensing circuit SU connected to each reference voltage line 14B, and outputs of a plurality of sensing circuits SU It may include a multiplexer (MUX) for time division output, and an analog-to-digital converter (hereinafter, ADC) connected to the multiplexer (MUX) to generate sensing result data (SDATA).

The DAC converts the corrected image data CDATA into a data voltage for display according to the data timing control signal DDC applied from the timing controller 11 when the display is driven, and supplies the converted image data CDATA to the data lines 14A. Meanwhile, the DAC of the data driver IC SDIC may generate a data voltage for sensing according to the data timing control signal DDC applied from the timing controller 11 during sensing driving and supply it to the data lines 14A.

The data voltage for sensing may include an on-level data voltage capable of turning on the driving device and an off-level data voltage capable of driving the driving device off. The on-level data voltage is applied to the gate electrode of the driving device during sensing driving to turn on the driving device (ie, a voltage that generates pixel current), and the off-level data voltage is applied to the gate electrode of the driving device during sensing driving. This is the voltage that turns off the driving element (ie, the voltage that blocks the pixel current). The on-level data voltage may be set to have different sizes in the R (red), G (green), B (blue), and W (white) pixels in consideration of the different driving characteristics of the driving device/light emitting device for each color. , but not limited thereto.

The on-level data voltage is applied to the sensing pixel within one unit pixel, and the off-level data voltage is applied to the non-sensing pixels sharing the reference voltage line 14B with the sensing pixel within the one unit pixel. For example, in FIG. 2 , when the R pixel is sensed and the W, G, and B pixels are not sensed, the on-level data voltage is applied to the driving element of the R pixel, and the off-level data voltage is the W, G, and B pixels. It may be applied to a driving element of each of the pixels.

Each sensing circuit SU may be connected to the reference voltage line 14B and selectively connected to the ADC through a multiplexer MUX. Each sensing circuit SU includes an integrator amplifier and a reset switch. Each sensing circuit SU may be further connected to a parasitic capacitor CP formed in the pixel array to operate as a current integrator during sensing driving. During sensing driving, the parasitic capacitor CP functions as a feedback capacitor for accumulating a pixel current of a sensing pixel. Since the feedback capacitor is not embedded in the source driver integrated circuit SDIC but is located in the pixel array, there is an advantage in that the mounting area of the sensing circuit SU is reduced. The ADC may convert the sensing output voltage output from each sensing circuit SU into sensing result data SDATA and output it to the compensation circuit 20 .

The gate driver 13 may generate a sensing gate signal (or scan signal) based on the gate control signal GDC during sensing driving and then sequentially or non-sequentially supply the sensing gate signal (or scan signal) to the gate lines 15 . The sensing gate signal is a sensing scan signal synchronized with the sensing data voltage. The pixel lines L1 to Ln may be sensed and driven sequentially or non-sequentially by the sensing gate signal and the sensing data voltage.

The gate driver 13 may generate a display gate signal (or scan signal) based on the gate control signal GDC when driving the display, and then sequentially supply the generated gate signal (or scan signal) to the gate lines 15 . The display gate signal is a display scan signal synchronized with the display data voltage. The pixel lines L1 to Ln may be sequentially display driven by the display gate signal and the display data voltage.

In the present specification, a sensing driving sequence for detecting a pixel current that varies depending on driving characteristics of the driving element and/or the light emitting element may be independently performed for each R, W, G, and B pixel. For example, in the sensing driving sequence of the present invention, R pixels are sensed in a line-sequential/non-sequential manner for all pixel lines of the display panel 10 , and then W pixels are sensed in a line-sequential/out-of-sequential manner, followed by G After the pixels are sensed in a line-sequential/out-of-order method, the B pixels may be sensed in a line-sequential/out-of-order method. The sensing order according to these colors may be set differently.

The power generation circuit 30 generates a high potential pixel voltage EVDD and a low potential pixel voltage EVSS to be supplied to each pixel PXL. The power generation circuit 30 may generate a gate-on voltage and a gate-off voltage necessary for the operation of the gate driver 13 , and supply the generated gate-on voltage and gate-off voltage to the gate driver 13 . A gate signal for sensing or display swings between a gate-on voltage (ie, an on level) and a gate-off voltage (ie, an off level).

4 is a diagram illustrating an example of a configuration of one unit pixel and a sensing circuit according to an embodiment of the present specification.

Referring to FIG. 4 , one unit pixel according to an exemplary embodiment of the present specification is located in the display panel 10 . One unit pixel includes a first pixel PX1 connected to a first data line DL1 and a gate line 15 , a second pixel PX2 connected to a second data line DL2 and a gate line 15 , and a third It includes a third pixel PX3 connected to the data line DL3 and the gate line 15 , and a fourth pixel PX4 connected to the fourth data line DL4 and the gate line 15 . The first to fourth pixels PX1 to PX4 share the reference voltage line RL, and may be R, W, G, and B pixels of FIG. 3 , respectively. Parasitic capacitors CP formed by crossing the reference voltage line RL and the first to fourth data lines DL1 to DL4 are positioned on the display panel 10 .

The data driver 12 includes first to fourth voltage generators DAC1 to DAC4 respectively connected to the first to fourth data lines DL1 to DL4, an integrator amplifier AMP connected to the reference voltage line RL, It may include a reset switch RST and a sampling circuit SH.

In the sensing mode, any one of the first to fourth pixels PX1 to PX4 becomes a sensing pixel, and the remaining pixels excluding the sensing pixel become non-sensing pixels. Data lines connected to the sensing pixels become on-driving data lines, some of the data lines connected to the non-sensing pixels become off-driving data lines, and the rest of the data lines connected to the non-sensing pixels become floating driving data lines. The on-drive data line receives an on-level data voltage from a voltage generator connected thereto, and the off-drive data line receives an off-level data voltage from a voltage generator connected thereto.

During sensing driving, the floating driving data line is disconnected from the voltage generator. The parasitic capacitor CP between the floating driving data line and the reference voltage line RL becomes a feedback capacitor of the current integrator. Accordingly, not only the reference voltage line RL but also the floating driving data line functions as a sensing path for the pixel current.

Since the off-level data voltage is charged in the off-drive data line during sensing driving, it cannot function as a sensing path. Accordingly, the parasitic capacitor CP between the off-driving data line and the reference voltage line RL cannot be a feedback capacitor of the current integrator.

The integrator amplifier AMP has a first input terminal (-), a second input terminal (+), and an output terminal. The first input terminal (-) of the integrator amplifier (AMP) is connected to the reference voltage line (RL), the second input terminal (+) is connected to the input terminal of the integrator reference voltage (CVref), and the output terminal is connected to the sampling circuit ( SH) is connected. A reset switch RST is connected between the first input terminal (-) and the output terminal of the integrator amplifier AMP. In addition, the integrator amplifier AMP is further connected to the feedback capacitor of the display panel 10 to operate as a current integrator. The sampling circuit SH samples the output of the current integrator according to the sampling signal SAM.

FIG. 5 is an equivalent circuit diagram of one pixel included in one unit pixel of FIG. 4 .

Referring to FIG. 5 , one pixel may have a circuit structure suitable for sensing deterioration of a driving device and/or a light emitting device. The pixel according to the present embodiment includes a data line 14A to which a display data voltage Vdata or sensing data voltage Von, Voff is supplied, and a display scan signal SCAN or sensing scan signal SCAN. It is connected to the supplied gate line 15 . Von is the on-level data voltage described with reference to FIG. 4 and Voff is the off-level data voltage described with reference to FIG. 4 .

The pixel according to the present exemplary embodiment may include a light emitting element EL, a driving element DT, a storage capacitor Cst, a first switch transistor ST1, and a second switch transistor ST2. The driving element DT may be implemented as a driving transistor. In the present embodiment, the driving transistor DT and the switch transistors ST1 and ST2 may be implemented as n-type thin film transistors (hereinafter referred to as TFTs), but is not limited thereto and may be implemented as p-type TFTs. . In addition, the semiconductor layer of TFTs constituting the pixel may include amorphous silicon, polysilicon, or oxide.

The light emitting element EL emits light according to the pixel current. The light emitting element EL includes an anode electrode connected to the source node N2, a cathode electrode connected to the input terminal of the low-potential pixel voltage EVSS, and an organic or inorganic compound layer positioned between the anode electrode and the cathode electrode. . The organic or inorganic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection). layer, EIL). When the anode voltage Vs applied to the anode electrode becomes higher than the operating point voltage Vx compared to the low-potential pixel voltage EVSS applied to the cathode electrode, the light emitting element EL is turned on. When the light emitting element EL is turned on, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL are moved to the light emitting layer EML to form excitons, and as a result, the light emitting layer EML emits light. will occur

The operating point voltage Vx of the light emitting device EL may vary in pixels due to a difference in the equivalent resistance of the light emitting device EL due to process variation or deterioration variation. Accordingly, by sensing the voltage of the source node N2 through the pixel current, the change in the operating point voltage of the pixel can be detected.

The driving transistor DT includes a gate connected to the gate node N1 , a source connected to the source node N2 , and a drain connected to the input terminal of the high potential pixel voltage EVDD. The driving transistor DT generates a pixel current according to a gate-source voltage. The pixel current may be generated with a magnitude proportional to the square of the gate-source voltage.

The threshold voltage and electron mobility of the driving transistor DT may vary in pixels due to a process deviation, deterioration deviation, temperature, or the like. Accordingly, when the voltage of the source node N2 is sensed through the pixel current, a change in driving characteristics of the driving transistor DT included in the pixel can be detected.

The storage capacitor Cst is connected between the gate node N1 and the source node N2 to maintain the gate-source voltage of the driving transistor DT.

The first switch transistor ST1 connects the data line 14A and the gate node N1 according to the sensing scan signal SCAN to apply the sensing data voltage charged in the data line 14A to the gate node N1 . accredit to The data voltage for sensing may be an on-level data voltage Von or an off-level data voltage Voff. The first switch transistor ST1 has a gate connected to the gate line 15 , a first electrode (either source/drain) connected to the data line 14A, and a second electrode connected to the gate node N1 . (the other one of source/drain).

The second switch transistor ST2 turns on/off the current flow (ie, electrical connection) between the source node N2 and the reference voltage line 14B according to the sensing scan signal SCAN. The second switch transistor ST2 includes a gate connected to the gate line 15 , a first electrode connected to the reference voltage line 14B, and a second electrode connected to the source node N2 .

The sensing circuit SU is connected to the pixel through a reference voltage line 14B.

Hereinafter, various embodiments relating to a connection configuration between a single unit pixel and a data driver for reducing the size and mounting area of the sensing circuit SU will be described.

[First embodiment]

6 is a diagram illustrating a connection configuration between one unit pixel and a data driver according to the first embodiment of the present specification. FIG. 7 is a driving waveform diagram of the components shown in FIG. 6 . FIG. 8A is a diagram illustrating operation states of corresponding components in the initialization section of FIG. 7 . And, FIG. 8B is a diagram showing operating states of corresponding components in the sensing section of FIG. 7 .

6 to 8B , the first pixel PX1 provided in the display panel 10 is a sensing pixel, and the second to fourth pixels PX2 , PX3 , and PX4 are non-sensing pixels.

The sensing pixel PX1 is connected to the on driving data line DL1. The on-drive data line DL1 is connected to a corresponding voltage generator (hereinafter, DAC1 ), receives the on-level data voltage Von from the DAC1 and transmits it to the sensing pixel PX1 . A pixel current Ipix corresponding to the on-level data voltage Von flows through the sensing pixel PX1. In contrast, no pixel current flows to the non-sensing pixels.

Among the non-sensing pixels, the second and fourth pixels PX2 and PX4 are respectively connected to the off driving data lines DL2 and DL4. The off-driving data line DL2 is connected to a corresponding voltage generator (hereinafter, DAC2), receives the off-level data voltage Voff from the DAC2, and transmits it to the non-sensing pixel PX2. The off-driving data line DL4 is connected to a corresponding voltage generator (hereinafter, DAC4 ), receives the off-level data voltage Voff from DAC2 and transmits it to the non-sensing pixel PX4 .

Among the non-sensing pixels, the third pixel PX3 is connected to the floating driving data line DL3. The floating driving data line DL3 is not connected to a corresponding voltage generator (hereinafter, DAC3). In the present embodiment, the floating driving data line DL3 is only disconnected from the DAC3, and may be connected to another circuit, for example, an output terminal of the integrator amplifier AMP. Therefore, it should be noted that the “floating driving data line DL3” is not maintained in a “floating state” in the dictionary meaning.

A reference voltage line RL commonly connected to the sensing pixel PX1 and the non-sensing pixels PX2 , PX3 , and PX4 is positioned. A parasitic capacitor CP is formed between the reference voltage line RL and the on-drive data line DL1 and between the reference voltage line RL and each of the off-drive data lines DL2 and DL4. In addition, a feedback capacitor CPS is formed between the reference voltage line RL and the floating driving data line DL3. Since the feedback capacitor CPS is formed on the display panel 10 instead of being mounted in the data driver 12 , the size and mounting area of the sensing circuit can be reduced. Moreover, since the capacity of the feedback capacitor CPS can be increased without increasing the size of the sensing circuit according to the first embodiment, the effect of sensing noise can be minimized and the accuracy and reliability of sensing can be increased.

The relative positions of the sensing pixel and the non-sensing pixel, and accordingly, the relative positions of the on driving data line, the off driving data line, and the floating driving data line may be changed.

The data driver 12 includes data channels DCH connected to the data lines DL1 to DL4 and a sensing channel SCH connected to the reference voltage line RL. The sensing channel SCH is connected to the integrator amplifier AMP and the reset switch RST through the sensing switch SIO.

The data driver 12 includes DAC1 corresponding to the on driving data line DL1, DAC2 corresponding to the off driving data line DL2, DAC3 corresponding to the floating driving data line DL3, and the off driving data line DL4. The corresponding DAC4 is mounted. DAC1 is connected to the on-drive data line DL1 through the switch P2 and the data channel DCH. The on-drive data line DL1 is not connected to the output terminal of the integrator amplifier AMP by the switch P1 driven off. DAC2 is connected to the off-drive data line DL2 through the switch P2' and the data channel DCH. The off-driving data line DL2 is not connected to the output terminal of the integrator amplifier AMP by the off-driven switch P1'. DAC4 is connected to the off-drive data line DL4 through the switch P2” and the data channel DCH. The off-driving data line DL4 is not connected to the output terminal of the integrator amplifier AMP by the off-driven switch P1”. DAC3 is not connected to the floating driving data line DL3 by the switch P2S driven off. On the other hand, the floating driving data line DL3 is connected to the output terminal of the integrator amplifier AMP through the data channel DCH and the switch P1S.

7 , the sensing mode includes an initialization period XY1 and a sensing period XY2.

The switches P1S, P2, P2', P2” and the sensing switch SIO maintain an ON state in the initialization period XY1 and the sensing period XY2. On the other hand, the switches P2S, P1, P1', P1" maintain an off state in the initialization period XY1 and the sensing period XY2. The reset switch RST maintains an on state in the initialization period XY1 and maintains an off state in the sensing period XY2.

As shown in FIG. 8A , in the initialization period XY1 , the on-driving data line DL1 is charged with the on-level data voltage Von, and the off-driving data lines DL2 and DL4 are charged with the off-level data voltage Voff. is charged The on-level data voltage Von charged in the on-driving data line DL1 is applied to the gate node (N1 of FIG. 5 ) of the sensing pixel PX1 in synchronization with the on-level sensing scan signal SCAN. The off-level data voltage Voff charged in the off-driving data lines DL2 and DL4 is synchronized with the on-level sensing scan signal SCAN at the gate nodes of the non-sensing pixels PX2 and PX4 (FIG. 5). of N1) is applied.

In the initialization period XY1, the first and second input terminals (+, -) of the integrator amplifier AMP achieve an equipotential with the integrator reference voltage CVref. Also, the output terminal of the integrator amplifier AMP is initialized to the integrator reference voltage CVref through the reset switch RST.

In the initialization period XY1 , the floating driving data line DL3 and the reference voltage line RL are charged with the integrator reference voltage CVref. The integrator reference voltage CVref charged in the floating driving data line DL3 is applied to the gate node (N1 of FIG. 5 ) of the non-sensing pixel PX3 in synchronization with the on-level sensing scan signal SCAN, and the reference The integrator reference voltage CVref charged in the voltage line RL is applied to the source node (N2 of FIG. 5 ) of all the pixels PX1 to PX4 in synchronization with the on-level sensing scan signal SCAN.

As shown in FIG. 8B , in the sensing period XY2 , the pixel current Ipix flowing through the sensing pixel PX1 is applied to one electrode of the feedback capacitor CPS through the reference voltage line RL. At this time, the other electrode of the feedback capacitor CPS is connected to the output terminal of the integrator amplifier AMP through the floating driving data line DL3 and the switch P1S, and the integrator output voltage CI_OUT is the pixel current Ipix. As it accumulates in the electrode, it decreases from the integrator reference voltage CVref. The falling slope of the integrator output voltage CI_OUT depends on the size of the pixel current Ipix. In other words, the deviation of the pixel current Ipix appears as a difference in the integrator output voltage CI_OUT sampled at the same time in the sensing period XY2 . The difference in the integrator output voltage CI_OUT is a result of reflecting the driving characteristic deviation between pixels.

[Second embodiment]

9 is a diagram illustrating a connection configuration of one unit pixel and a data driver according to a second embodiment of the present specification. FIG. 10 is a driving waveform diagram of the components shown in FIG. 9 . FIG. 11A is a diagram illustrating operation states of corresponding components in the initialization section of FIG. 10 . And, FIG. 11B is a diagram showing operating states of corresponding components in the sensing section of FIG. 10 .

The second embodiment according to FIGS. 9 to 11B includes all of the effects or advantages according to the first embodiment described above. Furthermore, the second embodiment has an additional effect of resolving the “negative Vth” problem of the non-sensing pixel PX3 connected to the floating driving data line DL3. The “Nagative Vth” problem means that when the threshold voltage Vth of the driving element included in the non-sensing pixel PX3 is shifted in the negative direction, an abnormal pixel current flows to the non-sensing pixel PX3, and this abnormal pixel current This means that the sensing result is distorted by In the second embodiment, by setting the voltage applied to the floating driving data line DL3 to be lower than the integrator reference voltage CVref applied to the reference voltage line RL, the non-sensing pixel PX3 in the sensing period XY2 is Abnormal conduction (ie, generation of abnormal pixel current) can be prevented.

Hereinafter, the second embodiment will be specifically described.

9 to 11B , the first pixel PX1 provided in the display panel 10 is a sensing pixel, and the second to fourth pixels PX2 , PX3 , and PX4 are non-sensing pixels.

The sensing pixel PX1 is connected to the on driving data line DL1. The on-drive data line DL1 is connected to a corresponding voltage generator (hereinafter, DAC1 ), receives the on-level data voltage Von from the DAC1 and transmits it to the sensing pixel PX1 . A pixel current Ipix corresponding to the on-level data voltage Von flows through the sensing pixel PX1. In contrast, pixel current should not flow to non-sensing pixels.

Among the non-sensing pixels, the second and fourth pixels PX2 and PX4 are respectively connected to the off driving data lines DL2 and DL4. The off-driving data line DL2 is connected to a corresponding voltage generator (hereinafter, DAC2), receives the off-level data voltage Voff from the DAC2, and transmits it to the non-sensing pixel PX2. The off-driving data line DL4 is connected to a corresponding voltage generator (hereinafter, DAC4 ), receives the off-level data voltage Voff from DAC2 and transmits it to the non-sensing pixel PX4 .

Among the non-sensing pixels, the third pixel PX3 is connected to the floating driving data line DL3. The floating driving data line DL3 is not connected to a corresponding voltage generator (hereinafter, DAC3). In the present embodiment, the floating driving data line DL3 is only disconnected from the DAC3 and may be connected to another circuit, for example, an output node NO to which the integrator output voltage CI_OUT is applied. Therefore, it should be noted that the “floating driving data line DL3” is not maintained in a “floating state” in the dictionary meaning. The floating driving data line DL3 is further connected to the input terminal of the first reference voltage DVref through the switch SWRS so that the “Nagative Vth” problem of the non-sensing pixel PX3 does not occur. The first reference voltage DVref is set lower than the integrator reference voltage CVref to lower the gate-source voltage of the driving device included in the non-sensing pixel PX3 in the initialization period XY1 to less than the threshold voltage Vth. do The difference voltage ΔV between the first reference voltage DVref and the integrator reference voltage CVref is lower than the threshold voltage of the driving element included in the non-sensing pixel PX3 . Accordingly, the driving element included in the non-sensing pixel PX3 does not conduct even if the threshold voltage Vth thereof is shifted in the negative direction.

Meanwhile, the switch SWR for receiving the first reference voltage DVref is also connected to each of the on driving data line DL1 and the off driving data lines DL2 and DL4, but the switch SWR maintains an off state in the sensing mode. do.

A reference voltage line RL commonly connected to the sensing pixel PX1 and the non-sensing pixels PX2 , PX3 , and PX4 is positioned on the display panel 10 . A parasitic capacitor CP is formed between the reference voltage line RL and the on-drive data line DL1 and between the reference voltage line RL and each of the off-drive data lines DL2 and DL4. In addition, a feedback capacitor CPS is formed between the reference voltage line RL and the floating driving data line DL3. Since the feedback capacitor CPS is formed on the display panel 10 instead of being mounted in the data driver 12 , the size and mounting area of the sensing circuit are reduced. Furthermore, since the second embodiment can increase the capacity of the feedback capacitor CPS without increasing the size of the sensing circuit, the effect of sensing noise can be minimized and the accuracy and reliability of sensing can be increased.

The relative positions of the sensing pixel and the non-sensing pixel, and accordingly, the relative positions of the on driving data line, the off driving data line, and the floating driving data line may be changed.

The data driver 12 includes data channels DCH connected to the data lines DL1 to DL4 and a sensing channel SCH connected to the reference voltage line RL. The sensing channel SCH is connected to the integrator amplifier AMP and the reset switch RST through the sensing switch SIO. The output terminal of the integrator amplifier AMP is connected to the output node NO through the output switch SWO.

The data driver 12 includes DAC1 corresponding to the on driving data line DL1, DAC2 corresponding to the off driving data line DL2, DAC3 corresponding to the floating driving data line DL3, and the off driving data line DL4. The corresponding DAC4 is mounted. DAC1 is connected to the on-drive data line DL1 through the switch P2 and the data channel DCH. The on-driving data line DL1 is not connected to the output node NO by the off-driven switch P1. DAC2 is connected to the off-drive data line DL2 through the switch P2' and the data channel DCH. The off-driving data line DL2 is not connected to the output node NO by the off-driven switch P1'. DAC4 is connected to the off-drive data line DL4 through the switch P2” and the data channel DCH. The off-driving data line DL4 is not connected to the output node NO by the off-driven switch P1”. DAC3 is not connected to the floating driving data line DL3 by the switch P2S driven off. On the other hand, the floating driving data line DL3 is connected to the output node NO through the data channel DCH and the switch P1S.

10 , the sensing mode includes an initialization period XY1 and a sensing period XY2.

The switches P1S, P2, P2', P2” and the sensing switch SIO maintain an ON state in the initialization period XY1 and the sensing period XY2. On the other hand, the switches P2S, P1, P1', P1" maintain an off state in the initialization period XY1 and the sensing period XY2. The reset switch RST and the switch SWRS maintain an on state in the initialization period XY1 and maintain an off state in the sensing period XY2. The output switch SWO maintains an off state in the initialization period XY1 and maintains an on state in the sensing period XY2.

11A , in the initialization period XY1 , the on-driving data line DL1 is charged with the on-level data voltage Von, and the off-driving data lines DL2 and DL4 are charged with the off-level data voltage Voff. is charged The on-level data voltage Von charged in the on-driving data line DL1 is applied to the gate node (N1 of FIG. 5 ) of the sensing pixel PX1 in synchronization with the on-level sensing scan signal SCAN. The off-level data voltage Voff charged in the off-driving data lines DL2 and DL4 is synchronized with the on-level sensing scan signal SCAN at the gate nodes of the non-sensing pixels PX2 and PX4 (FIG. 5). of N1) is applied.

In the initialization period XY1, the first and second input terminals (+, -) of the integrator amplifier AMP achieve an equipotential with the integrator reference voltage CVref. Also, the output terminal of the integrator amplifier AMP is initialized to the integrator reference voltage CVref through the reset switch RST.

In the initialization period XY1, the reference voltage line RL is charged with the integrator reference voltage CVref, while the floating driving data line DL3 is charged with the first reference voltage DVref lower than the integrator reference voltage CVref. is charged Since the first reference voltage DVref charged in the floating driving data line DL3 is applied to the output node NO through the switch P1S, the output node NO is initialized to the first reference voltage DVref. The first reference voltage DVref charged in the floating driving data line DL3 is applied to the gate node (N1 of FIG. 5 ) of the non-sensing pixel PX3 in synchronization with the on-level sensing scan signal SCAN, The integrator reference voltage CVref charged in the reference voltage line RL is applied to the source nodes (N2 of FIG. 5 ) of all the pixels PX1 to PX4 in synchronization with the on-level sensing scan signal SCAN.

As shown in FIG. 11B , in the sensing period XY2 , the pixel current Ipix flowing through the sensing pixel PX1 is applied to one electrode of the feedback capacitor CPS through the reference voltage line RL. In this case, the other electrode of the feedback capacitor CPS is connected to the output node NO through the floating driving data line DL3 and the switch P1S. And, the output node NO is connected to the output terminal of the integrator amplifier AMP through the output switch SWO. Accordingly, the integrator output voltage CI_OUT decreases from the first reference voltage DVref as the pixel current Ipix is accumulated in the one electrode. The falling slope of the integrator output voltage CI_OUT depends on the size of the pixel current Ipix. In other words, the deviation of the pixel current Ipix appears as a difference in the integrator output voltage CI_OUT sampled at the same time in the sensing period XY2 . The difference in the integrator output voltage CI_OUT is a result of reflecting the driving characteristic deviation between pixels.

[Third embodiment]

12 is a diagram illustrating a connection configuration between one unit pixel and a data driver according to a third embodiment of the present specification. 13 is a driving waveform diagram of the components shown in FIG. 12 . FIG. 14A is a diagram illustrating operation states of corresponding components in the initialization section of FIG. 13 . And, FIG. 14B is a diagram showing operating states of corresponding components in the sensing section of FIG. 13 .

The third embodiment according to FIGS. 12 to 14B includes all of the effects or advantages according to the first embodiment described above. Furthermore, the third embodiment has an additional effect of removing the panel noise component included in the sensed value. In the third embodiment, when the first input terminal (-) of the integrator amplifier AMP is connected to the feedback capacitor CPS through the reference voltage line RL, the second input terminal (+) of the integrator amplifier AMP is also It is connected to the first floating driving data line DL4. Panel noise may be mixed in the pixel current Ipix accumulated in the feedback capacitor CPS through the reference voltage line RL. Since such panel noise is commonly input to the first input terminal (-) and the second input terminal (+) of the integrator amplifier AMP, it may be canceled inside the integrator amplifier AMP.

Hereinafter, the third embodiment will be specifically described.

12 to 14B , the first pixel PX1 provided in the display panel 10 is a sensing pixel, and the second to fourth pixels PX2 , PX3 , and PX4 are non-sensing pixels.

The sensing pixel PX1 is connected to the on driving data line DL1. The on-drive data line DL1 is connected to a corresponding voltage generator (hereinafter, DAC1 ), receives the on-level data voltage Von from the DAC1 and transmits it to the sensing pixel PX1 . A pixel current Ipix corresponding to the on-level data voltage Von flows through the sensing pixel PX1. In contrast, no pixel current flows to the non-sensing pixels.

Among the non-sensing pixels, the second pixel PX2 is connected to the off driving data lines DL2, respectively. The off-driving data line DL2 is connected to a corresponding voltage generator (hereinafter, DAC2), receives the off-level data voltage Voff from the DAC2, and transmits it to the non-sensing pixel PX2.

Among the non-sensing pixels, the third pixel PX3 is connected to the floating driving data line DL3. The floating driving data line DL3 is not connected to a corresponding voltage generator (hereinafter, DAC3). In addition, the fourth pixel PX4 is connected to the first floating driving data line DL4 . The first floating driving data line DL4 is not connected to a corresponding voltage generator (hereinafter, DAC4).

In the present embodiment, the floating driving data line DL3 is only disconnected from the DAC3 and may be connected to another circuit, for example, an output terminal of the integrator amplifier AMP to which the integrator output voltage CI_OUT is applied. In addition, the first floating driving data line DL4 is only disconnected from the DAC4, and may be connected to the second input terminal (+) of the integrator amplifier AMP through another circuit, for example, the switch Q1S. Accordingly, it should be noted that the “floating driving data line DL3 and the first floating driving data line DL4” are not maintained in a “floating state” in the dictionary meaning.

A reference voltage line RL commonly connected to the sensing pixel PX1 and the non-sensing pixels PX2 , PX3 , and PX4 is positioned on the display panel 10 . Between the reference voltage line RL and the on driving data line DL1 , between the reference voltage line RL and the off driving data line DL2 , and between the reference voltage line RL and the first floating driving data line DL4 A parasitic capacitor CP is formed in the In addition, a feedback capacitor CPS is formed between the reference voltage line RL and the floating driving data line DL3. Since the feedback capacitor CPS is formed on the display panel 10 instead of being mounted in the data driver 12 , the size and mounting area of the sensing circuit are reduced. Moreover, since the third embodiment can increase the capacitance of the feedback capacitor CPS without increasing the size of the sensing circuit, the effect of sensing noise can be minimized and the accuracy and reliability of sensing can be increased.

The relative positions of the sensing pixel and the non-sensing pixel, and accordingly, the relative positions of the on driving data line, the off driving data line, the floating driving data line, and the first floating driving data line may be changed.

The data driver 12 includes data channels DCH connected to the data lines DL1 to DL4 and a sensing channel SCH connected to the reference voltage line RL. The sensing channel SCH is connected to the integrator amplifier AMP and the reset switch RST through the sensing switch SIO.

The data driver 12 includes DAC1 corresponding to the on driving data line DL1, DAC2 corresponding to the off driving data line DL2, DAC3 corresponding to the floating driving data line DL3, and a first floating driving data line DL4. DAC4 corresponding to ) is mounted. DAC1 is connected to the on-drive data line DL1 through the switch P2 and the data channel DCH. The on-drive data line DL1 is not connected to the output terminal of the integrator amplifier AMP by the switch P1 driven off. DAC2 is connected to the off-drive data line DL2 through the switch P2' and the data channel DCH. The off-driving data line DL2 is not connected to the output terminal of the integrator amplifier AMP by the off-driven switch P1'. DAC3 is not connected to the floating driving data line DL3 by the switch P2S driven off. On the other hand, the floating driving data line DL3 is connected to the output terminal of the integrator amplifier AMP through the data channel DCH and the switch P1S. DAC4 is not connected to the first floating driving data line DL4 by the switch P2″ driven off. Also, the first floating driving data line DL4 is not connected to the output terminal of the integrator amplifier AMP by the off-driven switch P1”.

The switch Q1 is connected between the second input terminal (+) of the integrator amplifier (AMP) and the off-driving data line (DL2), and the second input terminal (+) of the integrator amplifier (AMP) and the first floating driving data line ( DL4), the switch Q1S is connected. In sensing mode, switch Q1S remains on, while switch Q1 remains off.

13 , the sensing mode includes an initialization period XY1 and a sensing period XY2.

The switches P1S, P2, P2', the sensing switch SIO, and the switch Q1S maintain an ON state in the initialization period XY1 and the sensing period XY2. On the other hand, the switches P2S, P1, P1', P1”, P2” and the switch Q1 maintain an off state in the initialization period XY1 and the sensing period XY2. The reset switch RST maintains an on state in the initialization period XY1 and maintains an off state in the sensing period XY2.

14A , in the initialization period XY1 , the on-driving data line DL1 is charged with the on-level data voltage Von, and the off-driving data line DL2 is charged with the off-level data voltage Voff. The on-level data voltage Von charged in the on-driving data line DL1 is applied to the gate node (N1 of FIG. 5 ) of the sensing pixel PX1 in synchronization with the on-level sensing scan signal SCAN. The off-level data voltage Voff charged in the off-driving data line DL2 is applied to the gate node (N1 of FIG. 5 ) of the non-sensing pixel PX2 in synchronization with the on-level sensing scan signal SCAN.

In the initialization period XY1, the first and second input terminals (+, -) of the integrator amplifier AMP achieve an equipotential with the integrator reference voltage CVref. Also, the output terminal of the integrator amplifier AMP is initialized to the integrator reference voltage CVref through the reset switch RST.

In the initialization period XY1 , the reference voltage line RL, the floating driving data line DL3 , and the first floating driving data line DL4 are charged with the integrator reference voltage CVref. Since the integrator reference voltage CVref charged in the reference voltage line RL is applied to the output terminal of the integrator amplifier AMP through the reset switch RST, the output terminal is initialized to the integrator reference voltage CVref. The integrator reference voltage CVref charged in the floating driving data line DL3 is applied to the gate node (N1 of FIG. 5 ) of the non-sensing pixel PX3 in synchronization with the on-level sensing scan signal SCAN, The integrator reference voltage CVref charged in the first floating driving data line DL4 is applied to the gate node (N1 of FIG. 5 ) of the non-sensing pixel PX4 in synchronization with the on-level sensing scan signal SCAN. In addition, the integrator reference voltage CVref charged in the reference voltage line RL is applied to the source nodes (N2 in FIG. 5 ) of all the pixels PX1 to PX4 in synchronization with the on-level sensing scan signal SCAN. do.

As shown in FIG. 14B , in the sensing period XY2 , the pixel current Ipix flowing through the sensing pixel PX1 is applied to one electrode of the feedback capacitor CPS through the reference voltage line RL. At this time, the other electrode of the feedback capacitor CPS is connected to the output terminal of the integrator amplifier AMP through the floating driving data line DL3 and the switch P1S. Accordingly, the integrator output voltage CI_OUT decreases from the integrator reference voltage CVref as the pixel current Ipix is accumulated in the one electrode. The falling slope of the integrator output voltage CI_OUT depends on the size of the pixel current Ipix. In other words, the deviation of the pixel current Ipix appears as a difference in the integrator output voltage CI_OUT sampled at the same time in the sensing period XY2 . The difference in the integrator output voltage CI_OUT is a result of reflecting the driving characteristic deviation between pixels.

Meanwhile, in the sensing section XY2, the reference voltage line RL is connected to the first input terminal (-) of the integrator amplifier AMP through the sensing switch SIO, and the first floating driving data line DL4 is It is connected to the second input terminal (+) of the integrator amplifier (AMP) through the switch Q1S. A panel noise current having a similar or substantially the same magnitude may flow through the reference voltage line RL and the first floating driving data line DL4 . The panel noise current may include an off-state current generated abnormally in an off-driven driving device. Since the panel noise current is commonly input to the first input terminal (-) and the second input terminal (+) of the integrator amplifier AMP, it can be canceled inside the integrator amplifier AMP. When the panel noise current is canceled, it is possible to prevent the panel noise component from being mixed into the integrator output voltage CI_OUT, and as a result, the accuracy of sensing is increased.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: data driver 13: gate driver
14A: data line 14B: reference voltage line
15: gate line 20: compensation circuit
SU: sensing circuit 30: power generation circuit

Claims (15)

A sensing pixel PX1, a non-sensing pixel PX3, an on-driving data line DL1 connected to the sensing pixel PX1, a floating driving data line DL3 connected to the non-sensing pixel PX3, the sensing pixel ( A display panel 10 including a reference voltage line RL connected to PX1 and the non-sensing pixel PX3 and a feedback capacitor CPS connected between the reference voltage line RL and the floating driving data line DL3 ); and
An integrator amplifier (AMP) having a first input terminal (-) connected to the reference voltage line (RL) and a second input terminal (+) connected to an integrator reference voltage (CVref), a first input terminal and an output of the integrator amplifier and a data driver 20 on which a reset switch (RST) connected between terminals is mounted,
In a sensing mode for sensing a pixel current flowing in the sensing pixel PX1 , the feedback capacitor CPS is connected between the first input terminal and the output terminal of the integrator amplifier. The method of claim 1,
The feedback capacitor CPS is a parasitic capacitor formed by the intersection of the reference voltage line RL and the floating driving data line DL3. The method of claim 1,
The data driver 20,
a first voltage generator DAC1 corresponding to the on-drive data line DL1;
a second voltage generator DAC3 corresponding to the floating driving data line DL3;
a switch P1 connected between the on-drive data line DL1 and the output terminal of the integrator amplifier;
a switch P2 connected between an output terminal of the first voltage generator DAC1 and the on-drive data line DL1;
a switch P1S connected between the floating driving data line DL3 and the output terminal of the integrator amplifier; and
The electroluminescent display device further comprising a switch P2S connected between the output terminal of the second voltage generator (DAC3) and the floating driving data line (DL3). 4. The method of claim 3,
The sensing mode includes an initialization section and a sensing section,
The switch P2 and the switch P1S maintain an on state in the initialization period and the sensing period,
The switch P1 and the switch P2S maintain an off state in the initialization period and the sensing period,
The reset switch RST maintains an on state in the initialization period and maintains an off state in the sensing period. 4. The method of claim 3,
In the initialization section,
An on-level data voltage Von is supplied from the first voltage generator DAC1 to the on-drive data line DL1,
The integrator reference voltage CVref is supplied from the integrator amplifier AMP to the reference voltage line RL, the floating driving data line DL3, and an output terminal of the integrator amplifier. 4. The method of claim 3,
In the sensing section,
The integrator output voltage CI_OUT applied to the output terminal of the integrator amplifier AMP is lowered from the integrator reference voltage CVref. The method of claim 1,
The data driver 20,
a first voltage generator DAC1 corresponding to the on-drive data line DL1;
a second voltage generator DAC3 corresponding to the floating driving data line DL3;
a switch SWRS that applies a first reference voltage DVref lower than the integrator reference voltage CVref to the floating driving data line DL3;
an output switch (SWO) connected between the output terminal of the integrator amplifier and an output node (NO);
a switch P1 connected between the on-drive data line DL1 and the output node NO;
a switch P2 connected between an output terminal of the first voltage generator DAC and the on-drive data line DL1;
a switch P1S connected between the floating driving data line DL3 and the output node NO; and
and a switch P2S connected between the output terminal of the second voltage generator (DAC) and the floating driving data line (DL3). 8. The method of claim 7,
The difference voltage ΔV between the first reference voltage DVref and the integrator reference voltage CVref is lower than a threshold voltage of a driving element included in the non-sensing pixel PX3. 8. The method of claim 7,
The sensing mode includes an initialization section and a sensing section,
The switch P2 and the switch P1S maintain an on state in the initialization period and the sensing period,
The switch P1 and the switch P2S maintain an off state in the initialization period and the sensing period,
The reset switch RST maintains an on state in the initialization period and maintains an off state in the sensing period,
The output switch SWO maintains an off state in the initialization period and maintains an on state in the sensing period. 10. The method of claim 9,
In the initialization section,
An on-level data voltage Von is supplied from the first voltage generator DAC1 to the on-drive data line DL1,
The integrator reference voltage CVref is supplied from the integrator amplifier AMP to the reference voltage line RL,
The first reference voltage DVref is supplied to the floating driving data line DL3 and the output node NO. 10. The method of claim 9,
In the sensing section,
The integrator output voltage CI_OUT applied to the output node NO is lowered from the first reference voltage DVref. The method of claim 1,
The display panel 10 is
A first non-sensing pixel PX4 further connected to the reference voltage line RL, and a first floating driving data line DL4 connected to the first non-sensing pixel PX4,
The data driver 20,
a first voltage generator DAC1 corresponding to the on-drive data line DL1;
a second voltage generator DAC3 corresponding to the floating driving data line DL3;
a third voltage generator DAC4 corresponding to the first floating driving data line DL4;
a switch P1 connected between the on-drive data line DL1 and the output terminal of the integrator amplifier;
a switch P2 connected between an output terminal of the first voltage generator DAC1 and the on-drive data line DL1;
a switch P1S connected between the floating driving data line DL3 and the output terminal of the integrator amplifier;
a switch P2S connected between an output terminal of the second voltage generator DAC3 and the floating driving data line DL3;
a switch P1" connected between the first floating driving data line DL4 and the output terminal of the integrator amplifier;
a switch P2″ connected between the output terminal of the third voltage generator (DAC4) and the first floating driving data line (DL4); and
and a switch Q1S connected between the second input terminal (+) of the integrator amplifier (AMP) and the first floating driving data line (DL4). 13. The method of claim 12,
The sensing mode includes an initialization section and a sensing section,
The switch P2, the switch P1S, and the switch Q1S maintain an on state in the initialization period and the sensing period,
The switch P1 and the switch P2S and the switch P1” and the switch P2” maintain an off state in the initialization period and the sensing period,
The reset switch RST maintains an on state in the initialization period and maintains an off state in the sensing period. 13. The method of claim 12,
In the initialization section,
An on-level data voltage Von is supplied from the first voltage generator DAC1 to the on-drive data line DL1,
The integrator reference voltage CVref from the integrator amplifier AMP is provided to the reference voltage line RL, the floating driving data line DL3, the first floating driving data line DL4, and the output terminals of the integrator amplifier. Supplied electroluminescent display. 13. The method of claim 12,
In the sensing section,
The integrator output voltage CI_OUT applied to the output terminal of the integrator amplifier AMP is lowered from the integrator reference voltage CVref.

Images