KR20220032466A - An analog-to-digital converter, an electronic device comprising the same, and an operating method of the analog-to-digital converter - Google Patents

Abstract

Disclosed are an analog-to-digital converter (ADC) to reduce burden of designing a quantizer of an ADC, an operation method thereof, and an electronic device including the same. According to the present invention, the ADC comprises: a first stage including a plurality of channels, sequentially sampling a first analog signal on the basis of time interleaving to generate a first sampling signal, and performing analog-to-digital conversion on the basis of the first sampling signal to generate a first digital signal and first residual signal corresponding to the first analog signal; an amplifier amplifying the first residual signal; and a second stage including a plurality of channels, sequentially sampling the amplified first residual signal on the basis of time interleaving to generate a second sampling signal, and performing analog-to-digital conversion on the basis of the second sampling signal to generate a second digital signal and second residual signal corresponding to the first analog signal, wherein the first stage can include an odd number of channels.

Description

Analog-to-digital converter, electronic device including analog-to-digital converter, and method of operation of analog-to-digital converter

The present disclosure relates to a time interleaving pipeline bandpass noise shaping SAR analog-to-digital converter, an electronic device including the analog-to-digital converter, and a method of operating the analog-to-digital converter.

An analog-to-digital converter (ADC) may convert an analog signal represented by continuous values into a digital signal represented by discrete values (eg, an integer number of bit strings). The ADC may include a Delta-Sigma ADC, a Successive Approximatin Register (SAR) ADC, and the like. In order to ensure high resolution and fast operation speed, a time interleaving ADC including a plurality of ADC channels connected in parallel, a pipelined ADC including a plurality of ADC stages connected in series, etc. are used. .

In order to implement a resonator having a high Q-factor, the bandpass ADC may include a plurality of Operational Transconductance Amplifiers (OTAs) or one OTA having high power consumption. Accordingly, the implementation difficulty of the ADC may increase, the area occupied by the ADC may increase, and power consumed by the ADC may increase.

An object of the present disclosure is to provide an analog-to-digital converter, an electronic device including the analog-to-digital converter, and a method of operating the analog-to-digital converter.

An analog converter according to some embodiments of the present disclosure includes: a plurality of channels, and generates a first sampling signal by sequentially sampling a first analog signal based on time interleaving, and an analog signal based on the first sampling signal - a first stage for generating a first digital signal and a first residual signal corresponding to the first analog signal by performing digital conversion; an amplifier for amplifying the first residual signal; and a plurality of channels, generating a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving, and performing analog-to-digital conversion based on the second sampling signal to perform the second sampling signal. A second stage generating a second digital signal corresponding to one analog signal and a second residual signal, wherein the first stage may include an odd number of channels.

An electronic device according to some embodiments of the present disclosure may include: a processor; and an analog-to-digital converter, and a communication device configured to communicate with an external device under the control of the processor, wherein the analog-to-digital converter includes: a plurality of channels; generating a first sampling signal by sequentially sampling based on first stage; an amplifier for amplifying the first residual signal; and a plurality of channels, generating a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving, and performing analog-to-digital conversion based on the second sampling signal to perform the second sampling signal. a second stage generating a second digital signal corresponding to one analog signal and a second residual signal, wherein the first stage includes an odd number of channels and the second stage includes an even number of channels there is.

A method of operating an analog-to-digital converter including a first stage and a second stage each including a plurality of channels, and an interstage amplifier according to some embodiments of the present disclosure includes: by the first stage, a first analog generating a first sampled signal by sequentially sampling the signal based on time interleaving; generating, by the first stage, a first digital signal and a first residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the first sampling signal; amplifying the first residual signal by the interstage amplifier; generating, by the second stage, a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving; and generating, by the second stage, a second digital signal corresponding to the first analog signal and a second residual signal by performing analog-to-digital conversion based on the second sampling signal, wherein the second The first stage may include an odd number of channels and the second stage may include an even number of channels.

According to some embodiments of the present disclosure, a time-interleaving-based bandpass noise shaping SAR analog-to-digital converter of a pipeline structure that can implement a simple and high Q-factor resonator by including one OTA may be provided. . Accordingly, power consumption of the analog-to-digital converter may be reduced. As both the time interleaving structure and the pipeline structure are included, the analog-to-digital converter can operate at high speed, have high resolution, and cope with a wide bandwidth. Also, the design burden of the quantizer of the analog-to-digital converter can be reduced.

1 is a block diagram of an analog-to-digital converter (ADC) according to some embodiments of the present disclosure.
2 is a block diagram of an ADC according to some embodiments of the present disclosure.
3 is a timing diagram illustrating an operation of the ADC of FIG. 2 according to some embodiments of the present disclosure;
4 is a block diagram of an ADC according to some embodiments of the present disclosure.
5 illustrates a noise transfer function corresponding to an ADC according to some embodiments of the present disclosure.
6A and 6B illustrate interleaving spurs caused by mismatch between channels of a time interleaving bandpass ADC, according to some embodiments of the present disclosure.
7A and 7B illustrate interleaving spurs and quantization noise generated in-band of a time interleaving ADC according to some embodiments of the present disclosure.
8 is a block diagram of an electronic device according to some embodiments of the present disclosure.
9 is a flowchart illustrating an operation method of an ADC according to some embodiments of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described clearly and in detail to the extent that those of ordinary skill in the art can easily practice the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In describing the present disclosure, in order to facilitate an overall understanding, like reference numerals are used for similar components in the drawings, and duplicate descriptions for similar components are omitted.

1 is a block diagram of an analog-to-digital converter (ADC) 100 according to some embodiments of the present disclosure. Referring to FIG. 1 , the ADC 100 may include a plurality of stages 110 to 1n0 connected in series; n is a natural number), an interstage amplifier (eg, 101 ), and a loop filter 102 . there is. The input signal Vin, which is an analog signal, may be converted into a digital signal through a plurality of stages 110 to 1n0; n is a natural number. For convenience of illustration, the plurality of stages 110 to 1n0 is illustrated as including a plurality of channels and an adder, but is not limited thereto. For example, each of the plurality of stages 110 to 1n0 may further include a block for performing a sampling and hold operation.

In some embodiments, the ADC 100 may be implemented as an ADC in which a pipelined structure and a time interleaving structure are combined. For example, the ADC 100 may be implemented as a pipeline structure including a plurality of stages 110 to 1n0, where each stage may be implemented as a time interleaving structure including a plurality of channels connected in parallel. can Each of the plurality of channels may include one or more ADCs implemented substantially the same and operating substantially the same. The plurality of stages may sequentially perform analog-to-digital conversion from the most significant bit to the least significant bit. Each of the plurality of channels may sequentially (eg, time interleaving) convert an analog signal into a digital signal.

For example, in the illustrated embodiment, each of the plurality of stages 110 to 1n0 may include one or more channels. The first stage 110 may include a plurality of channels 111 and an adder 112 connected in parallel. Each of the plurality of channels 111 may be implemented substantially the same. For example, each of the plurality of channels 111 may include one or more ADCs having substantially the same performance. In some embodiments, each of the plurality of channels 111 may include one or more Successive Approximation Register (SAR) ADCs. Accordingly, the ADC 100 may operate at low power.

Each of the plurality of channels 111 may convert an analog signal into a digital signal based on time interleaving. For example, during the first time, the first channel CH11 of the first stage 110 converts the input signal Vin into a digital signal and converts the residual signal (Residual Signal; or residual voltage, Error Signal) into a digital signal. ), the error voltage) may be transmitted to the adder 112 . The residual signal may be a signal corresponding to a difference between an analog signal and a digital signal remaining after converting the input signal Vin into a digital signal. Thereafter, for a second time, the second channel CH12 of the first stage 110 may convert the input signal Vin into a digital signal, and transmit the residual signal to the adder 112 . Thereafter, for a third time period, the third channel CH13 of the first stage 110 may convert the input signal Vin into a digital signal, and transmit the residual signal to the adder 112 .

The adder 112 may perform an addition operation (or a subtraction operation) on the signal filtered from the loop filter 102 and the residual signal received from any one of the plurality of channels 111 . Accordingly, noise shaping may be performed on the residual signal transferred from the first stage 110 to the second stage 120 . For example, quantization noise of a residual signal in a specific frequency band may be reduced. The adder 112 may transmit the operation result to the amplifier 101 .

The amplifier 101 may amplify the residual signal transmitted from the first stage 110 and transmit it to the second stage 120 . In a similar manner to the first stage 110 , the second stage 120 converts the analog signal output from the amplifier 101 into a digital signal based on time interleaving, and converts the residual signal into a third stage (not shown). can be transmitted as For example, the first stage 110 may perform analog-to-digital conversion on the most significant bit (MSB), and the second stage 120 may perform analog-to-digital conversion on the second most significant bit. can

In a similar manner to the first stage 110 , the nth stage 1n0 may convert an analog signal transferred from the n−1th stage (not shown) through an inter-channel amplifier into a digital signal based on time interleaving. . The nth stage 1n0 may transmit the residual signal to the loop filter 102 .

The loop filter 102 may filter the residual signal generated from the nth stage 1n0. While passing through the loop filter 102 , the first frequency band component of the residual signal generated from the nth stage 1n0 may be filtered (or reduced). For example, the loop filter 102 may reduce quantization noise of a desired frequency band of the residual signal. The loop filter 102 may transmit the filtered signal to the adders (eg, 112 ) of the plurality of stages 110 to 1n0 . Accordingly, the analog signal with reduced quantization noise of a specific frequency band may be fed back to the plurality of stages 110 to 1n0.

In some embodiments, the loop filter 102 may be implemented as a lowpass filter. In such embodiments, the high frequency component of the residual signal may be filtered by the loop filter 102 . For example, the high frequency quantization noise of the residual signal may be reduced by the loop filter 102 . The filtered residual signal may be transmitted to adders (eg, 112) of the plurality of stages 110 to 1n0. As the high-frequency component-filtered residual signal is fed back to the plurality of stages 110 to 1n0, quantization noise in the in-band may be reduced. For example, the ADC 100 may reduce quantization noise of a specific frequency band. Consequently, the ADC 100 may operate as a bandpass ADC.

2 is a block diagram of an ADC 200 according to some embodiments of the present disclosure. Referring to FIG. 2 , the ADC 200 may include a first stage 210 , a second stage 220 , and amplifiers 201 and 202 . The ADC 200 may be implemented as a pipelined time interleaving ADC, including two stages 210 and 220 , each of which includes two or more channels. Accordingly, it is possible to provide an ADC that operates at a high speed, has a high resolution, achieves a wide bandwidth, and can be simply implemented. In some embodiments, each of channels 211 , 212 , 213 , 221 , 222 may include one or more SAR ADCs. Accordingly, the ADC 200 may operate with low power.

In some embodiments, the first stage 210 may include an odd number of channels and the second stage 220 may include an even number of channels. For example, in the illustrated embodiment, the first stage 210 may include three channels 211 , 212 , 213 , and the second stage 220 may include two channels 221 , 222 . ), but the present disclosure is not limited thereto. As the first stage 210 includes an odd number of channels, the occurrence of interleaving spurs within the used band may be prevented. The generation of interleaving spurs will be specifically described below with reference to FIGS. 6A and 6B .

The first stage 210 may include three channels 211 , 212 , and 213 . The channels 211 , 212 , and 213 may sequentially convert the input signal Vin into a digital signal. For example, the input signal Vin may be sampled by channel 211 and converted to a digital signal, then sampled by channel 212 and converted to a digital signal, followed by channel 213 . may be sampled by and converted into a digital signal, and then may be sampled again by the channel 211 and converted into a digital signal.

For example, during a first time period (eg, between a first time period Φ1,a and a second time period Φ1,b), the input signal Vin may be sampled by the channel 211 . . During a second period of time (eg, between the second time .phi.1,b and the third time .phi.1,c), the channel 211 performs analog-to-digital conversion on the sampled input signal Vin. By doing so, the digital signal D1,a can be output. During a third time period (eg, between the third time period Φ1,c and the fourth time period), the channel 211 converts the residual signal Vres1,a into the amplifier 201 as the residual signal Vres1,in. , and the amplifier 201 may amplify the residual signal Vres1,in.

While the input signal Vin is converted into a digital signal by the channel 211 (eg, during a second time period), the input signal Vin may be sampled by the channel 212 . Thereafter, during the third time period, the channel 212 may output the digital signals D1 and b by performing analog-to-digital conversion on the input signal Vin. During a fourth time period following the third time period, the channel 212 may pass the residual signal Vres1,b to the amplifier 201 as the residual signal Vres1,in, and the amplifier 201 The signal (Vres1,in) can be amplified.

While the input signal Vin is converted into a digital signal by the channel 212 (eg, during a third time period), the input signal Vin may be sampled by the channel 213 . Thereafter, during the fourth time period, the channel 213 may output the digital signals D1,c by performing analog-to-digital conversion on the sampled input signal Vin. During a fifth time period following the fourth time period, the channel 213 may pass the residual signal Vres1,c to the amplifier 201 as the residual signal Vres1,in, and the amplifier 201 The signal (Vres1,in) can be amplified.

While the input signal Vin is converted into a digital signal by the channel 213 (eg, during a fourth time period), the input signal Vin may be sampled. Thereafter, during a fifth time period, the channel 211 may perform analog-to-digital conversion on the sampled input signal Vin. As a result, the channels 211 , 212 , and 213 of the first stage 210 may alternately sample the input signal Vin and convert it into a digital signal.

The amplifier 201 may include a first input for receiving the residual signal Vres1,in generated from the first stage 210 and a second input connected to an output of the amplifier 202 . The amplifier 201 may amplify the residual signal Vres1,in and the output signal of the amplifier 202 . The amplifier 201 may provide the amplified signal as an input signal Vin2 to the second stage 220 .

The amplifier 202 may include an input terminal for receiving the residual signal Vres2,in from the second stage 220 and an output terminal connected to the second input terminal of the amplifier 201 . The amplifier 202 may amplify the magnitude of the residual signal Vres2,in by '1/G' times. For example, the amplifier 202 may reduce the magnitude of the residual signal Vres2,in, and provide the reduced signal to the amplifier 201 .

The second stage 220 may include channels 221 and 222 . In a manner similar to the first stage 210 , the channels 221 and 222 may sequentially convert the input signal Vin2 into a digital signal.

For example, the input signal Vin2 output from the amplifier 201 may be sampled during the sixth time period (eg, between time Φ2,a and time Φ2,b). During the seventh time period following the sixth time period, the channel 221 may output the digital signal D2,a by performing analog-to-digital conversion on the sampled input signal Vin2. Channel 221 may pass the residual signal (Vres2,a) as residual signal (Vres2,in) to amplifier 202, which amplifier 202 multiplies the residual signal (Vres2,in) by '1/G' It can be amplified and transmitted to the amplifier 201 .

While the input signal Vin2 is converted into a digital signal by the channel 221 (eg, during the seventh time period), the input signal Vin2 may be sampled by the channel 222 . Thereafter, during an eighth time period following the seventh time period, the channel 222 may output the digital signals D2 and b by performing analog-to-digital conversion on the sampled input signal Vin2. Channel 222 may pass the residual signal (Vres2,b) as residual signal (Vres2,in) to amplifier 202, which amplifier 202 multiplies the residual signal (Vres2,in) by '1/G' It can be amplified and transmitted to the amplifier 201 .

During the eighth time period, the channel 221 may sample the input signal Vin2, and then, during a ninth time period following the eighth time period, analog-to-digital conversion on the sampled input signal Vin2. can be done As a result, the channels 221 and 222 of the second stage 210 may alternately sample the input signal Vin2 and convert it into a digital signal.

The residual signal Vres2,in output from the second stage 220 may be fed back to the second stage 220 through the amplifier 202 and the amplifier 201 . Accordingly, noise shaping may be performed. For example, the quantization noise of the input signal Vin2 within the band used by the ADC 200 may be reduced. Accordingly, the ADC 200 may operate as a bandpass ADC.

3 is a timing diagram illustrating an operation of the ADC 200 of FIG. 2 according to some embodiments of the present disclosure. 2 and 3, the operation of the ADC 200 will be described in detail.

The channels 211 , 212 , and 213 of the first stage 210 may generate a sampling signal by sequentially sampling the input signal Vin, which is an analog signal, based on time interleaving (in the illustrated embodiment, Corresponds to 'S/H1'). For example, the channels 211 , 212 , and 213 of the first stage may sequentially perform a sample and hold operation on the input signal Vin.

The channels 211 , 212 , and 213 of the first stage 210 may sequentially sample the input signal Vin based on a preset sampling period. In the illustrated embodiment, the sampling periods are n-3 th period, n-2 th period, n-1 th period, n th period, n+1 th period, n+2 th period, etc. according to the passage of time. may be referred to separately.

The channels 211 , 212 , and 213 of the first stage 210 may perform digital conversion based on the generated sampling signal (corresponding to 'Convs' in the illustrated embodiment). For example, the channels 211 , 212 , and 213 of the first stage 210 may perform digital conversion on the most significant bit (MSB). The channels 211, 212, and 213 of the first stage 210 are digital signals D1,a, D1,b, D1,c and residual signals Vres1,a, Vres1,b corresponding to the most significant bit. , Vres1,c) can be output respectively.

The residual signals Vres1,a, Vres1,b, and Vres1,c may be alternately amplified (corresponding to 'Amp' in the illustrated embodiment). For example, the residual signals Vres1,a, Vres1,b, and Vres1,c may be alternately amplified by the interstage amplifier 201 according to a preset period. In some embodiments, the preset period may correspond to the above-described sampling period.

In the illustrated embodiment, in the n-3 th cycle of the first stage, the channel 211 of the first stage 210 may perform sampling on the input signal Vin ('S/H1(#n) -3)'). While digital conversion is performed by the channel 211 ('Convs'), in the n-2 th cycle, the channel 212 may perform sampling on the input signal Vin ('S/H1(#) n-2)'). While the residual signal Vres1,a generated by channel 211 is amplified ('Amp'), channel 212 can perform a digital conversion ('Convs'), and channel 213 is: In the n-1 th cycle, sampling may be performed on the input signal Vin ('S/H1(#n-1)'). In a similar manner, the channel 211 may perform sampling on the input signal Vin again in the n-th period. In other words, the channels 211 , 212 , and 213 may alternately sample the input signal Vin, perform digital conversion based on the sampled analog signal, and amplify the residual signal.

The residual signals Vres1,a/Vres1,b/Vres1,c generated from the first stage 210 may be transmitted to the second stage 220 . For example, the channel 211 of the first stage 210 may transmit the residual signal Vres1,a to the second stage 210 after digital conversion is performed based on the sampled signal.

The channels 221 and 222 of the second stage 220 sequentially sample the residual signals Vres1,a/Vres1,b/Vres1,c output from the first stage 210, which are analog signals, based on time interleaving. , it is possible to generate a sampling signal ('S/H2'). For example, the channels 211 , 212 , and 213 of the first stage may sequentially perform a sample and hold operation on the input signal Vin.

The channels 221 and 222 of the second stage 220 have a residual signal 'Vres1', for example, Vres1,a, Vres1,b sequentially output from the first stage 210 based on a preset sampling period. , or Vres1,c) (corresponding to 'S/H2' in the illustrated embodiment). In the illustrated embodiment, the sampling periods are n-3 th period, n-2 th period, n-1 th period, n th period, n+1 th period, n+2 th period, etc. according to the passage of time. may be referred to separately.

In some embodiments, the amplifying operation 'Amp' by the first stage 210 and the sampling operation 'S/H2' by the second stage 220 may be synchronized. For example, an operation of amplifying the residual signal 'Vres1' output from the first stage 210 and a sampling operation of the amplified residual signal 'Vres1' may be performed substantially simultaneously. In the illustrated embodiment, the arrow 'STG Vres1' from the first stage to the second stage indicates that the residual signal 'Vres1' is amplified by the interstage amplifier 201, and the channel of the second stage 220 It may indicate that it is transmitted to any one of the ones 221 and 222 and is sampled. The channels 211, 212, and 213 of the first stage 210 transmit the amplified residual signal 'Vres1' to any one of the channels 221 and 222 of the second stage 220 in a preset period (eg, For example, it may be transmitted alternately according to the sampling period).

The channels 221 and 222 of the second stage 220 may perform digital conversion based on the generated sampling signal (corresponding to 'Convs' in the illustrated embodiment). For example, the channels 221 and 222 of the second stage 220 may perform digital conversion on a least significant bit (LSB). The channels 221 and 222 of the second stage 220 may output digital signals D2,a, D2,b and residual signals Vres2,a, Vres2,b corresponding to the least significant bit, respectively. Unlike the channels 211 , 212 , and 213 of the first stage 210 , the channels 221 and 222 of the second stage 220 perform an amplification operation (eg, an operation corresponding to 'Amp'). may not perform.

In the illustrated embodiment, in the n-3 th period of the second stage, the channel 221 of the second stage 220 is the residual signal Vres1,a output from the channel 211 of the first stage 210 . Sampling can be performed for ('S/H2(#n-3)'). While digital conversion is performed by the channel 221 ('Convs'), in the n-2 th cycle, the channel 222 is the residual signal Vres1,b output from the channel 212 of the first stage 210 ) can be sampled ('S/H2(#n-2)'). The channel 221 may provide the residual signal Vres2,a back to the channel 221 after digital conversion is performed. For example, the residual signal Vres2,a may be provided back to the channel 221 through the amplifier 201 . While digital conversion is performed by the channel 222 ('Convs'), in the n-1 th cycle, the channel 221 is the residual signal Vres1,c output from the channel 213 of the first stage 210 ) and the residual signal Vres2,a generated from the channel 221 ('S/H2(#n-1)').

In some embodiments, the residual signal Vres2,a output from the channel 221 of the second stage 220 may be delayed for a predetermined period and then provided to the channel 221 again. For example, in the n-1 th cycle, the residual signal Vres2,a may be reflected in the sampling and hold operation of the channel 221 (S/H2(#n-1)). Thereafter, in the n+1th cycle after two sampling cycles, the residual signal Vres2,a may be reflected again in the sampling and hold operation of the channel 221 (S/H2(#n+1)) . Accordingly, the error due to the LSB conversion performed by the channel 221 is fed back to the channel 221, and the intermediate frequency IF of the ADC 200 is for the sampling rate Fs, Equation 1 may be satisfied.

In other words, the intermediate frequency IF may be 1/4 times the sampling rate Fs. Consequently, ADC 200 may be implemented as a bandpass noise shaping ADC.

4 is a block diagram of an ADC 200 according to some embodiments of the present disclosure. 2 to 4 , the ADC 200 may further include a comparator 203 , an amplifier 204 , adders 205 and 214 , a subtractor 215 , and a block 206 . For convenience of description, some components (eg, SAR ADC, or channels 211 to 213, 221, 222, etc.) of the ADC 200, some components that perform a sampling operation and some components that perform analog-to-digital conversion are omitted.

In some embodiments, the adder 214 and the subtractor 215 may be included in the first stage 210 . For example, each of the channels 211 to 213 of the first stage 210 may include an adder corresponding to the adder 214 and a subtractor corresponding to the subtractor 215 . As another example, the channels 211 to 213 of the first stage 210 may sequentially (or alternately) share the adder 214 and the subtractor 215 .

The input signal Vin(z) may be converted into a digital signal D1(z) by the first stage 210 . For example, the input signal Vin(z) may correspond to the input signal Vin of FIG. 2 . The adder 214 may calculate the sum of the input signal Vin(z) and the quantization noise Q1(z) generated by the first stage 210 . The quantization noise Q1(z) may be generated from analog-to-digital conversion performed by the first stage 210 . The adder 214 may output the calculated sum as a digital signal D1(z). The digital signal D1(z) may be any one of the digital signals D1,a to D1,c). For example, when analog-to-digital conversion is performed by the channel 211 , the adder 214 calculates the sum of the input signal Vin applied to the channel 211 and the quantization noise generated by the channel 211 . operation, and the calculated sum may be output as a digital signal D1,a.

The subtractor 215 may calculate a difference between the input signal Vin(z) and an operation result of the adder 214 . The operation result of the subtractor 215 may be provided to the amplifier 201 as a residual signal Vres1(z). The residual signal Vres1(z) may be any one of the residual signals Vres1,a to Vres1,c. For example, when analog-to-digital conversion is performed by the channel 211, the subtractor 215 calculates the difference between the input signal Vin and the digital signal D1,a applied to the channel 211, Then, the calculated difference may be transferred to the amplifier 201 as the residual signal Vres1,a.

The amplifier 201 may include a subtractor 201a and amplifiers 201b and 201c. The amplifier 201 may include two input terminals ('2-Input AMP'). The amplifier 201 is configured to substantially simultaneously amplify the residual signal Vres1(z) output from the first stage 210 and the residual signal Vres2(z) outputted from the second stage 220 delayed twice. can

For example, the amplifier 201 may have a first input that receives the residual signal Vres1(z) from the first stage 210 and the residual signal Vres2(z) from the second stage 220 via block 206 . )) may include a second input terminal for receiving. By going through block 206 , the residual signal Vres2(z) output from the second stage 220 may be delayed twice (eg, by two sampling periods) and input to the amplifier 201 . There is ('z ^-2 '). The residual signal Vres2(z) may be any one of the residual signals Vres2,a, Vres2,b. The delayed residual signal Vres2(z) may be amplified by a factor of '1/G' by the amplifier 201c. Accordingly, the magnitude of the delayed residual signal Vres2(z) may be reduced.

The amplifier 201c may correspond to the amplifier 202 of FIG. 2 . For example, the residual signal Vres2,a generated by the channel 221 of the second stage 220 is delayed by two sampling periods (eg, by going through block 206 ), and then the amplifier 201c ) can be amplified by '1/G' times. Unlike the embodiment shown in FIG. 4 , similar to the amplifier 202 of FIG. 2 , the amplifier 201c may not be included in the interstage amplifier 201 .

The subtractor 201a of the amplifier 201 may calculate the difference between the residual signal Vres1(z) output from the first stage 210 and the output signal of the amplifier 201c. The amplifier 201b may amplify the operation result of the subtractor 201a. For example, the amplifier 201b may amplify the operation result of the subtractor by 'G'. The amplifier 201b may transmit the amplified signal to the comparator 203 .

In some embodiments, the amplifier 201 may be implemented as an Operational Transconductance Amplifier (OTA). Through the amplifier 201 , a high Q-factor resonator may be implemented in the ADC 200 having a pipeline structure. In other words, since only one OTA (eg, amplifier 201 ) is included in ADC 200 , it may be possible for a resonator having a high Q-factor to be implemented in the bandpass ADC 200 . Accordingly, the area of the ADC 200 may be reduced, the implementation difficulty of the ADC 200 may be reduced, and the power efficiency of the ADC 200 may be improved.

The comparator 203 may include adders 203a and 203b, an amplifier 203c, and a subtractor 203d. The comparator 203 may include two input terminals ('2-Input CMP'). For example, the comparator 203 has a first input that receives the amplified signal from the amplifier 201b of the amplifier 201 and a second that receives the twice delayed residual signal Vres2(z) from the block 206 . It may include an input terminal.

In some embodiments, the comparator 203 may be included in the second stage 220 . For example, each of the channels 221 and 222 of the second stage 220 may include a comparator 203 . As another example, the channels 221 , 222 of the second stage 220 may sequentially (or alternately) share the comparator 203 .

The residual signal Vres2(z) delayed twice via block 206 is attenuated by a predetermined ratio, and the analog-to-digital conversion of the second stage 220 (or the digital generated by the second stage 220 ) may be reflected in signal D2(z), for example the residual signal Vres2(z) delayed twice via block 206 is amplified by a '3/4' time by amplifier 203c, Then, it may be transmitted to the adder 203a. The adder 203a may calculate the sum of the output signal of the amplifier 203c and the output signal of the amplifier 201b. The adder 203b may operate the adder 203a. The sum of the result and the quantization noise Q2(z) generated by the second stage 220 can be calculated. The quantization noise Q2(z) is analog-digital performed by the second stage 220 . The result of the operation of the adder 203b may be transmitted as a digital signal D2(z) to the amplifier 204. The digital signal D2(z) is performed by the second stage It may be the result of analog-to-digital conversion.

The digital signal D2(z) may be any one of the digital signals D2,a, D2,b. For example, when analog-to-digital conversion is performed by the channel 221 , the adder 203b calculates the sum of the operation result of the adder 201a and the quantization noise generated by the channel 221 , and the operation The resulting sum can be output as a digital signal (D2,a).

The operation result of the adder 203b may also be transmitted to the subtractor 203d. The subtractor 203d may calculate a difference between the signal output from the amplifier 201 and the operation result of the adder 203b. The adder 203d may transmit the operation result to the block 206 as the residual signal Vres2(z) of the second stage 220 .

The amplifier 204 may amplify the digital signal D2(z) by '1/G' times. The amplifier 204 may pass the amplified signal to the adder 205 . The adder 205 is the sum of the digital signal D1(z) generated from the first stage 210 and the digital signal D2(z) generated from the second stage 220 amplified by '1/G' times. can be calculated. The adder 205 may output the operation result as an output digital signal Dout(z). The output digital signal Dout(z) may be a result of analog-to-digital conversion for the input signal Vin(z) performed by the ADC 200 .

5 illustrates a noise transfer function NTF(z) corresponding to the ADC 200 according to some embodiments of the present disclosure. 1 to 5 , the noise transfer function NTF(z) may have two poles and two zero points.

In the embodiment shown in FIG. 4 , the residual signal Vres2(z) of the second stage 220 may be input back to the amplifier 201 through the block 206 . Accordingly, as the analog-to-digital conversion error is fed back, the ADC 200 may be implemented as a noise shaping ADC having an error-feedback structure. The noise transfer function NTF _EF (z) by error feedback may satisfy Equation (2).

Referring to Equation 2, the noise transfer function NTF _EF (z) may have two zero points. Accordingly, the intermediate frequency IF of the ADC 200 may satisfy Equation 1 (ie, the intermediate frequency IF may be 1/4 times the sampling rate Fs).

4 , the residual signal Vres2(z) of the second stage 220 is delayed twice by block 206 and amplified by '3/4' times by amplifier 203c and , and may be input to the adder 203a again. Accordingly, the residual signal Vres2(z) may be input to the comparator 203 again through a feed-forward path. The feed-forward noise transfer function NTF _FF (z) may satisfy Equation (3).

Referring to Equation 3, the noise transfer function NTF _FF (z) may have two poles. Accordingly, quantization noise within a band used by the ADC 200 may be effectively reduced.

Referring to Equations 2 and 3, the noise transfer function NTF(z) of the ADC 200 may satisfy Equation 4.

Referring to Equation 4, the intermediate frequency IF of the ADC 200 may be 1/4 times the sampling rate Fs, and quantization noise within the used band of the ADC 200 may be effectively reduced. Accordingly, the ADC 200 may be implemented as a bandpass NS ADC, and the performance of the ADC 200 may be improved.

6A and 6B illustrate interleaving spurs caused by mismatch between channels of a time interleaving bandpass ADC, according to some embodiments of the present disclosure. More specifically, in a time interleaving bandpass ADC in which the center frequency IF is 1/4 times the sampling rate Fs, FIG. 6A shows an input signal ('Signal') and interleaving spurs of the time interleaving bandpass ADC including an even number of channels. The Power Spectrum Density (PSD) is shown. 6B shows the Power Spectrum Density (PSD) of the input signal and interleaving spurs of a bandpass ADC comprising an odd number of channels.

Performances of a plurality of channels included in one time interleaving ADC may not be completely identical. In this case, interleaving spurs may occur due to mismatch between channels. Interleaving spurs due to, for example, offset mismatch due to offset difference between channels, gain mismatch due to gain difference, timing mismatch due to time skew, and bandwidth mismatch due to bandwidth difference between channels, etc. can occur Due to the interleaving spurs, the resolution of the time interleaving ADC may be degraded.

Referring to FIG. 6A , interleaving spurs of a time interleaving bandpass ADC including an even number of channels may exist within a used band. Due to this, the resolution of the time interleaving bandpass ADC may be deteriorated. On the other hand, referring to FIG. 6B , interleaving spurs of a time interleaving bandpass ADC including an odd number of channels may exist outside the use band. For example, in an ADC having a narrow bandwidth around the center frequency IF, interleaving spurs may not be formed within the used band.

In some embodiments, the ADC 200 may include a first stage including an odd number of channels and a second stage including an even number of channels. For example, in the embodiment shown in FIG. 2 , the first stage 210 may include three channels 211 , 212 , and 213 . Accordingly, the interleaving spurs of the first stage 210 may not be formed within the use band without a separate complicated calibration. As a result, the time interleaving bandpass ADC 200 having improved accuracy while having a fast sampling rate and a simple structure can be provided.

Since the second stage 220 includes two channels 221 and 222 , interleaving spurs may occur within the used band. However, quantization of the second stage 220 is performed based on the residual signal Vres1,a/Vres1,b/Vres1,c remaining after analog-to-digital conversion of the upper bit is performed by the first stage 210 Therefore, the size of the interleaving spurs of the second stage 220 may be relatively small. Accordingly, the interleaving spurs of the second stage 220 may not affect the resolution of the ADC 200 .

7A and 7B illustrate interleaving spurs and quantization noise generated in-band of a time interleaving noise shaping ADC, according to some embodiments of the present disclosure. More specifically, FIG. 7A shows the Power Spectrum Density (PSD) of the input signal ('Signal'), interleaving spurs, and quantization noise of a time interleaved lowpass noise shaping ADC. FIG. 7B shows the Power Spectrum Density (PSD) of the input signal, interleaving spurs, and quantization noise of the ADC of the time interleaving bandpass noise shaping ADC 200 of FIG. 2 .

In the embodiment shown in FIG. 7A , the use band of the ADC may be located in a relatively low frequency band. The quantization noise of the ADC is low in the low frequency band, and may become larger as the frequency increases. And the intermediate frequency IF may be lower than the point where it is 1/4 times the sampling rate Fs. Interleaving spurs generated from the ADC of FIG. 7A may be located around the intermediate frequency band, and as a result, it may be difficult to implement a bandpass characteristic in which the intermediate frequency IF satisfies 1/4 times the sampling rate Fs.

On the other hand, in the embodiment shown in FIG. 7B , interleaving spurs may not exist within the band used by the ADC 200 . Noise shaping may be performed on the quantization noise within the use band, and accordingly, the quantization noise within the use band may be reduced. The ADC 200 may have a band-pass characteristic.

8 is a block diagram of an electronic device 300 according to some embodiments of the present disclosure. Referring to FIG. 8 , the electronic device 300 may include a processor 310 , a random access memory (RAM) 320 , a storage device 330 , and a communication device 340 . In some embodiments, the electronic device 300 may include a mobile device such as a smart phone or a tablet PC.

The processor 310 may function as a central processing unit of the electronic device 300 . For example, the processor 310 may control the operation of the electronic device 300 by executing software, firmware, program codes, or instructions loaded into the memory 320 .

The memory 320 may store data and program codes to be processed or to be processed by the processor 310 . For example, the memory 320 may store data and program codes provided from a user or an external device. Software, firmware, program codes, or instructions for controlling the electronic device 300 by the processor 310 may be loaded into the memory 320 . Data stored in the storage device 330 may be loaded into the memory 320 under the control of the processor 310 . The memory 320 may be a main memory device of the electronic device 300 . The memory 320 may include dynamic random access memory (DRAM) or static RAM (SRAM).

The storage device 330 may store data generated by the processor 310 for long-term storage, a file to be driven by the processor 310 , or various codes that may be executed by the processor 310 . The storage device 330 may function as an auxiliary storage device of the electronic device 300 . The storage device 330 may include a flash memory or the like. Unlike the drawings, the storage device 330 may be implemented as an external device of the electronic device 300 .

The communication device 340 may communicate with an external device of the electronic device 300 . For example, under the control of the processor 310 , the communication device 340 may transmit data to, and receive data from, an external device based on various wired or wireless protocols.

In some embodiments, the communication device 340 may include a receiver including the ADC 200 to receive a radio frequency (RF) signal from the outside. For example, the receiver may be used for 5 ^th generation (5G) communication or 6 ^th generation (6G) communication. In these embodiments, the ADC 200 may have high resolution, may operate with low power, and may occupy a small area in the receiver. Since the ADC 200 may be implemented as a time interleaving pipeline noise shaping SAR ADC in which the first stage 210 includes an odd number of channels, the ADC 200 may operate at a high speed while maintaining high resolution.

Also, in these embodiments, the ADC 200 may have a bandpass characteristic. Accordingly, it is possible to prevent wastage of resources by performing only digital conversion of a desired bandwidth, and the use thereof may not be limited to a low frequency band. For example, the receiver including the ADC 200 may process signals of a relatively high frequency band compared to a receiver including the low-pass ADC.

9 is a flowchart illustrating an operation method of the ADC 200 according to some embodiments of the present disclosure. 2 and 9 , the ADC 200 may perform steps S100 to S300 .

In step S100 , the first stage 210 of the ADC 200 may generate a first digital signal and a first residual signal from the first analog signal based on time interleaving. For example, the channels 211 to 213 of the first stage 210 may generate the first sampling signal by sequentially sampling the first analog signal based on time interleaving. The channels 211 to 213 may generate a first digital signal and a first residual signal corresponding to the first analog signal by sequentially performing analog-to-digital conversion based on the first sampling signal. For example, the first digital signal may correspond to a most significant bit (MSB) corresponding to the first analog signal. The first residual signal may correspond to a difference between the first analog signal and the first digital signal.

In step S200 , the interstage amplifier 201 of the ADC 200 may amplify the first residual signal. For example, the interstage amplifier 201 receives the first residual signal and the second residual signal generated by the second stage 220 in response to the second analog signal input two periods before the first analog signal. can receive The interstage amplifier 201 may amplify the first residual signal based on the second residual signal generated by the second stage 220 in response to the second analog signal. The interstage amplifier 201 may transfer the amplified first residual signal to the second stage 220 .

In step S300 , the second stage 220 of the ADC 200 may generate a second digital signal and a second residual signal from the amplified first residual signal based on time interleaving. For example, the channels 221 and 222 of the second stage 220 may generate the second sampling signal by sampling the sequentially amplified first residual signal based on time interleaving. The channels 221 and 222 may sequentially generate a second digital signal and a second residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the second sampling signal. For example, the second digital signal may correspond to the least significant bit LSB corresponding to the first analog signal. The second residual signal may correspond to a difference between the amplified first residual signal and the second digital signal.

The above are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments and should be defined by the claims and equivalents of the present invention as well as the claims to be described later.

100, 200: ADC (Analog-Digital Converter)
300: electronic device

Claims (20)

It includes a plurality of channels, generates a first sampling signal by sequentially sampling the first analog signal based on time interleaving, and performs analog-to-digital conversion on the first analog signal based on the first sampling signal. a first stage for generating a corresponding first digital signal and a first residual signal;
an amplifier for amplifying the first residual signal; and
It includes a plurality of channels, generates a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving, and performs analog-to-digital conversion based on the second sampling signal to generate the first a second stage for generating a second digital signal corresponding to the analog signal and a second residual signal;
wherein the first stage includes an odd number of channels. The method of claim 1,
wherein the second stage includes an even number of channels. The method of claim 1,
and each of the plurality of channels of the first stage and the plurality of channels of the second stage includes a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The method of claim 1,
wherein the amplifier is shared by a plurality of channels of a first stage and alternately amplifies the first residual signal sequentially generated from each of the plurality of channels according to a first period. 5. The method of claim 4,
wherein the amplifier receives the first residual signal and the second residual signal generated by the second stage in response to a second analog signal input two periods before the first analog signal. 6. The method of claim 5,
an analog-to-digital converter having a bandpass characteristic based on the second residual signal generated by the second stage in response to the second analog signal. 6. The method of claim 5,
the second residual signal generated by the second stage in response to the second analog signal is attenuated by a first ratio, and
and the second stage performs the analog-to-digital conversion further based on the attenuated second residual signal. 6. The method of claim 5,
wherein the first stage comprises a first channel, a second channel, and a third channel;
While the sampling of the first analog signal is performed for the nth period in the first channel, amplification of the sampling signal corresponding to the n-2th period is performed in the second channel, and the amplification of the sampling signal corresponding to the n-2th period is performed in the third channel An analog-to-digital converter in which analog-to-digital conversion of a sampling signal corresponding to an n-1 period is performed. 6. The method of claim 5,
The second stage includes a first channel and a second channel,
An analog-to-digital converter for performing analog-to-digital conversion of a sampling signal corresponding to an n−1th period in the second channel while sampling of the first residual signal is performed for an nth period in the first channel. The method of claim 1,
Each of the plurality of channels of the first stage sequentially transfers the first residual signal corresponding to the first sampling signal to the second stage. processor; and
A communication device comprising an analog-to-digital converter and, under the control of the processor, performing communication with an external device,
The analog-to-digital converter comprises:
It includes a plurality of channels, generates a first sampling signal by sequentially sampling the first analog signal based on time interleaving, and performs analog-to-digital conversion on the first analog signal based on the first sampling signal. a first stage for generating a corresponding first digital signal and a first residual signal;
an amplifier for amplifying the first residual signal; and
It includes a plurality of channels, generates a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving, and performs analog-to-digital conversion based on the second sampling signal to generate the first a second stage for generating a second digital signal corresponding to the analog signal and a second residual signal, and
The first stage includes an odd number of channels and the second stage includes an even number of channels. 12. The method of claim 11,
Each of the plurality of channels of the first stage and the plurality of channels of the second stage includes a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). 12. The method of claim 11,
The amplifier is shared by a plurality of channels of the first stage and alternately amplifies the first residual signal sequentially generated from each of the plurality of channels according to a first period. 14. The method of claim 13,
wherein the amplifier receives the first residual signal and the second residual signal generated by the second stage in response to a second analog signal input two periods before the first analog signal. 15. The method of claim 14,
The analog-to-digital converter has a bandpass characteristic based on the second residual signal generated by the second stage in response to the second analog signal. 15. The method of claim 14,
the second residual signal generated by the second stage in response to the second analog signal is attenuated by a first ratio, and
and the second stage performs the analog-to-digital conversion further based on the attenuated second residual signal. A method of operating an analog-to-digital converter comprising a first stage and a second stage each comprising a plurality of channels, and an inter-stage amplifier:
generating, by the first stage, a first sampling signal by sequentially sampling a first analog signal based on time interleaving;
generating, by the first stage, a first digital signal and a first residual signal corresponding to the first analog signal by performing analog-to-digital conversion based on the first sampling signal;
amplifying the first residual signal by the interstage amplifier;
generating, by the second stage, a second sampling signal by sequentially sampling the amplified first residual signal based on time interleaving; and
generating, by the second stage, a second digital signal corresponding to the first analog signal and a second residual signal by performing analog-to-digital conversion based on the second sampling signal,
wherein the first stage includes an odd number of channels and the second stage includes an even number of channels. 18. The method of claim 17,
Each of the plurality of channels of the first stage and the plurality of channels of the second stage includes a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). 18. The method of claim 17,
The step of amplifying the first residual signal includes the first residual signal and the second residual signal generated by the second stage in response to a second analog signal input two periods before the first analog signal. A method of operating an analog-to-digital converter comprising the step of receiving. 20. The method of claim 19,
Based on the second residual signal generated by the second stage in response to the second analog signal, the analog-to-digital converter has a bandpass characteristic.

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