KR20220012269A - Method for predicting electrical properties of semiconductor devices - Google Patents

Abstract

Predict the electrical characteristics of the semiconductor device from the process list. The electrical characteristics of the semiconductor device are predicted using the feature calculation unit and the characteristic prediction unit. The feature-quantity calculator has a first learning model and a second learning model, and the feature predictor has a third learning model. The first learning model has a step of learning a process list for producing a semiconductor element, and a step of generating a first feature quantity. The second learning model has the steps of learning the electrical characteristics of the semiconductor device generated according to the process list, and generating the second characteristic quantity. The third learning model has a step of performing multimodal learning using the first and second feature variables, and a step of outputting values of variables used in calculation formulas of semiconductor device characteristics. In addition, the first to third learning models each have different neural networks.

Description

Method for predicting electrical properties of semiconductor devices

One aspect of the present invention relates to a method for learning a multimodal learning model using any one or a plurality of process recipes, electrical characteristics, and image data. In addition, one aspect of the present invention relates to a method of predicting electrical characteristics of a semiconductor device using a multimodal learned model using any one or a plurality of process recipes, electrical characteristics, and image data. One embodiment of the present invention relates to a method for predicting electrical characteristics of a semiconductor device using a computer.

In addition, in this specification etc., a semiconductor element refers to the element which can function by using semiconductor characteristics. A semiconductor element, such as a transistor, a diode, a light emitting element, or a light receiving element, is mentioned as an example. Further, as another example of the semiconductor element, a passive element formed by using a conductive film or an insulating film, such as a capacitor, a resistance element, an inductor, or the like is mentioned. Moreover, as another example of a semiconductor element, the semiconductor device provided with the circuit which has a semiconductor element or a passive element is mentioned.

In recent years, in fields using artificial intelligence (AI), robots, or energy fields that deal with high power such as power ICs, new semiconductor devices have been developed to solve problems such as increase in computational amount or increase in power consumption. is being developed While the integrated circuits required in the market or the semiconductor devices used in the integrated circuits are becoming more complex, it is required to quickly realize an integrated circuit having a new function. However, in the development of a semiconductor device, the knowledge, know-how, or experience of a skilled technician is required for process design, device design, or circuit design.

In recent years, it is known to use a genetic algorithm to adjust the parameters of a physical model of a transistor. Patent Document 1 discloses a parameter adjusting device using a genetic algorithm to adjust parameters of a physical model of a transistor.

Japanese Patent Laid-Open No. 2005-38216

In the development of a semiconductor element, process design, device design, and circuit design are required. As an example, a semiconductor device is formed by combining a plurality of process processes. A semiconductor device has a problem in that electrical characteristics change when the order of process processes is changed. In addition, semiconductor devices have a problem in that electrical characteristics change when manufacturing devices or process conditions are different even if the process is the same.

In addition, there is a problem in that the semiconductor device has different electrical characteristics as miniaturization proceeds even when it is formed using the same process, other devices having the same function, and the same conditions. As an example, the cause may be the film thickness precision or processing precision of the manufacturing apparatus, and the cause may be the change of the physical model due to miniaturization. There is a problem that time for various experiments or evaluation is required to pursue the cause.

As described above, factors that can affect the electrical properties of semiconductor devices, such as the sequence of the process steps, manufacturing apparatus, process conditions, miniaturization, film thickness precision, and processing precision, are numerous and accurately measure the electrical properties of semiconductor devices. It was very difficult to predict.

In view of the above problems, one of the objects of one embodiment of the present invention is to provide a simple method for predicting electrical characteristics of a semiconductor device. Alternatively, one aspect of the present invention is to provide a simple method for predicting electrical characteristics of a semiconductor device using a computer. Alternatively, in one embodiment of the present invention, one of the problems is to learn a process list of a semiconductor element and to provide a neural network that outputs a first characteristic quantity. Alternatively, one aspect of the present invention is to provide a neural network that learns the electrical characteristics of a semiconductor device generated according to the process list of the semiconductor device and outputs a second characteristic quantity. Alternatively, one aspect of the present invention is to learn a cross-sectional schematic diagram or cross-sectional observation image of a semiconductor element generated according to the process list of the semiconductor element, and to provide a neural network for outputting a third characteristic quantity as one of the tasks. Alternatively, one aspect of the present invention is to provide a neural network that performs multi-modal learning using the first to third feature quantities as one of the problems. Alternatively, according to one aspect of the present invention, one of the problems is that a neural network performing multimodal learning outputs a value of a variable used in a calculation formula representing an electrical characteristic of a semiconductor device.

In addition, the description of these subjects does not impede the existence of other subjects. In addition, one embodiment of the present invention does not need to solve all of these problems. In addition, subjects other than these will become apparent by itself in the description of the specification, drawings, claims, etc., and other subjects can be extracted from the description of the specification, drawings, claims, and the like.

One embodiment of the present invention is a method for predicting electrical characteristics of a semiconductor device having a characteristic quantity calculating unit and a characteristic predicting unit. The feature-quantity calculator has a first learning model and a second learning model, and the feature predictor has a third learning model. The first learning model has a step of learning a process list for producing a semiconductor device. Also, the first learning model has a step of generating a first feature quantity. The second learning model has a step of learning the electrical characteristics of the semiconductor device generated according to the process list. The second learning model also has a step of generating a second feature quantity. The third learning model has a step of multimodal learning using the first and second feature quantities. Also, the third learning model is a method for predicting electrical characteristics of a semiconductor device, including outputting a value of a variable used in a calculation formula representing the electrical characteristics of the semiconductor device.

In the above configuration, the feature amount calculating unit has a fourth learning model. The fourth learning model has a step of learning the cross-sectional schematic diagram generated using the process list. Also, the fourth learning model has a step of generating the third feature quantity. The third learning model has a step of performing multimodal learning using the first feature, the second feature, and the third feature. A method for predicting electrical characteristics of a semiconductor device is preferable, in which the third learning model outputs values of variables used in a calculation formula representing electrical characteristics of the semiconductor device.

In the above configuration, the first learning model has a first neural network, and the second learning model has a second neural network. A method for predicting electrical characteristics of a semiconductor device, which includes updating a weighting coefficient of a second neural network by a first characteristic quantity generated by a first neural network is preferable.

In the above configuration, when the process list for inference is given to the first learning model, and the value of the voltage applied to the terminal of the semiconductor element is given to the second learning model, the second learning model determines the value of the current according to the value of the voltage. A method for predicting electrical characteristics of a semiconductor device having a step of outputting a value is preferable.

In the above configuration, when the process list for inference is given to the first learning model and the value of the voltage applied to the terminal of the semiconductor element is given to the second learning model, the third learning model is a formula for calculating the electrical characteristics of the semiconductor element A method for predicting electrical characteristics of a semiconductor device having a step of outputting a value of a variable used for .

In the above configuration, a method for predicting electrical characteristics of a semiconductor element in which the semiconductor element is a transistor is preferable. In addition, the transistor preferably includes a metal oxide in the semiconductor layer.

One embodiment of the present invention can provide a simple method for predicting electrical characteristics of a semiconductor device. Alternatively, one embodiment of the present invention may provide a simple method for predicting electrical characteristics of a semiconductor device using a computer. Alternatively, one embodiment of the present invention may include a neural network that learns a process list of a semiconductor device and outputs a first feature. Alternatively, one embodiment of the present invention may include a neural network that learns electrical characteristics of a semiconductor device generated according to the process list of the semiconductor device and outputs a second characteristic quantity. Alternatively, one embodiment of the present invention may include a neural network that learns a cross-sectional schematic diagram or a cross-sectional image of a semiconductor device generated according to the process list of the semiconductor device and outputs a third feature. Alternatively, one embodiment of the present invention may be equipped with a neural network that performs multimodal learning using the first to third feature quantities. Alternatively, according to one embodiment of the present invention, a neural network performing multi-modal learning may output a value of a variable used in a calculation expression representing an electrical characteristic of a semiconductor device.

In addition, the effect of one embodiment of this invention is not limited to the effect enumerated above. The effects listed above do not prevent the existence of other effects. Also, other effects are effects described below and not mentioned in this section. Effects not mentioned in this item can be derived from descriptions such as the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Also, one embodiment of the present invention has at least one of the effects and/or other effects listed above. Accordingly, one embodiment of the present invention may not have the effects enumerated above in some cases.

1 is a view for explaining a method of predicting electrical characteristics of a semiconductor device.
2(A), (B), (C), and (D) are tables for explaining the process list.
3A and 3B are diagrams for explaining a process list. 3C is a diagram for explaining a neural network for learning a process list.
4A and 4B are diagrams for explaining electrical characteristics of a semiconductor element. 4C is a diagram for explaining a neural network for learning electrical characteristics.
5 is a view for explaining a method of predicting electrical characteristics of a semiconductor device.
Fig. 6A is a diagram for explaining a neural network for learning image data. 6B is a diagram for explaining a schematic cross-sectional view of a semiconductor element. 6C is a view for explaining a cross-sectional observation image of a semiconductor device.
7 is a view for explaining a method of predicting electrical characteristics of a semiconductor device.
8 is a view for explaining a method of predicting electrical characteristics of a semiconductor device.
Fig. 9 is a diagram for explaining a computer operating a program.

EMBODIMENT OF THE INVENTION It demonstrates in detail using drawing about embodiment. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, this invention is limited to the description of the following embodiment, and is not interpreted.

In addition, in the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same parts or parts having the same function, and a repetitive description thereof will be omitted. In addition, when referring to parts having the same function, the hatch pattern is made the same, and there are cases in which no particular sign is attached.

In addition, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. in order to facilitate understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, scope, etc. disclosed in the drawings.

In addition, it should be noted that the ordinal numbers 'first', 'second', and 'third' used in this specification are added to avoid confusion of components, and are not limited to numbers.

(Embodiment)

In one embodiment of the present invention, a method for predicting electrical characteristics of a semiconductor element will be described. As an example, in the method of predicting electrical characteristics of a semiconductor device, a feature calculating unit and a characteristic predicting unit are used. The feature-quantity calculator has a first learning model and a second learning model, and the feature predictor has a third learning model. Also, the first learning model has a first neural network, the second learning model has a second neural network, and the third learning model has a third neural network. In addition, it is preferable that the first to third neural networks are different from each other.

First, a learning method for predicting electrical characteristics of a semiconductor element will be described.

As an example, a case in which the first learning model learns a list of steps for producing a semiconductor element will be described. The first learning model updates the weighting coefficients of the first neural network by being given a list of processes for generating a semiconductor device. That is, the first neural network is a neural network that learns the process list as training data. Hereinafter, as an example, the semiconductor device will be described with a transistor. In addition, the semiconductor element is not limited to a transistor. A transistor is an example, and a diode, a thermistor, a gyro sensor, an acceleration sensor, a light emitting element, a light receiving element, etc. may be sufficient as a semiconductor element. In addition, the semiconductor device may include a resistive device or a capacitive device.

In addition, the above-described process list is information in which a plurality of processes required for forming a transistor are combined. Next, one process item described in the process list will be described. The process item preferably includes at least a process ID, an apparatus ID, and a condition. In addition, the process includes at least one or more of a film forming process, a cleaning process, a resist coating process, an exposure process, a developing process, a processing process, a baking process, a peeling process, and a doping process. In addition, the conditions include setting conditions of each device, and the like.

In addition, the process content indicated by each process ID may be performed by an apparatus having a different function. For example, in a film-forming process, MOCVD (metal organic chemical vapor deposition method), CVD (chemical vapor deposition method), a sputtering method, etc. are used. Accordingly, the information given to the first learning model can manage the two-dimensional information as one-dimensional information by representing the process ID and the device ID as one code. By using codes to indicate process IDs and device IDs, the amount of computation is reduced by reducing learning items. In addition, the code generation method will be described in detail with reference to FIG. 2 .

In addition, the first learning model generates the first feature quantity by the first neural network trained according to the process list.

In one embodiment of the present invention, in parallel with the learning of the first learning model, the second learning model learns the electrical characteristics of the transistor generated by the first model. More specifically, the second learning model learns the electrical characteristics of the transistors generated according to the process list given to the first learning model. The second learning model updates the weighting coefficients of the second neural network given the electrical characteristics of the transistor. That is, the second neural network is a neural network that learns the electrical characteristics of the transistor as training data. For example, as the electrical characteristics of the transistor, an Id-Vgs characteristic for evaluating a temperature characteristic or a threshold voltage of the transistor, and an Id-Vds characteristic for evaluating a saturation characteristic of the transistor can be used.

The drain current Id represents the magnitude of the current flowing through the drain terminal when a voltage is applied to the gate terminal, the drain terminal, and the source terminal of the transistor. Also, the Id-Vgs characteristic indicates a change in the drain current Id when the voltage applied to the gate terminal of the transistor is changed. Also, the Id-Vds characteristic indicates a change in the value Id of the drain current when the voltage applied to the drain terminal of the transistor is changed.

In addition, the second learning model generates the second characteristic quantity by the second neural network that has learned the electrical characteristics of the transistors generated according to the process list.

Then, the third learning model performs multimodal learning using the first and second feature quantities. The third learning model updates the weighting coefficients of the third neural network by giving the first and second feature quantities. That is, the third neural network is a neural network that learns a process list and electrical characteristics of transistors corresponding to the process list as training data.

In addition, multimodal learning uses information of different formats, such as a first feature quantity generated from a process list for generating a semiconductor device and a second feature quantity generated from electrical characteristics of a semiconductor device generated according to the process list means to learn As an example, a neural network using a feature quantity generated from a plurality of pieces of information having different formats as input information may be referred to as a neural network having a multimodal interface. In one embodiment of the present invention, the third neural network corresponds to a neural network having a multimodal interface.

As an example, the third learning model outputs a value of a variable used in a calculation expression representing an electrical characteristic of a transistor. That is, the value of this variable is a value predicted by the method for predicting electrical characteristics of a semiconductor element.

As an example, a gradual channel approximation equation of the transistor is used as a calculation equation representing the electrical characteristics of the transistor. Equation (1) shows the electrical characteristics in the saturation region of the transistor. Equation (2) shows the electrical characteristics in the linear region of the transistor.

[Equation 1]

[Equation 2]

Variables predicted by the method for predicting electrical characteristics of transistors include drain current Id used in equation (1) or equation (2), field effect mobility μFE, unit area capacitance Cox of the gate insulating film, channel length L, channel width W , or the threshold voltage Vth. In addition, it is preferable that speculation data to be described later is given to the gate voltage Vg applied to the gate terminal or the drain voltage Vd applied to the drain terminal. In addition, the 3rd learning model may output all the values of the said variable, and may output any one or a plurality of the values of the said variable.

Since the method for predicting electrical characteristics of a semiconductor device uses supervised learning, a reward is given to the first to third neural networks based on the output result of the third learning model. As an example, the first to third neural networks update the weighting coefficients so as to approximate the result calculated from Equation (1) or Equation (2) based on the electrical characteristics of the transistor.

The feature quantity calculating unit further has a fourth learning model. The fourth learning model learns a cross-sectional schematic diagram of a transistor to be generated using the process list. Alternatively, the fourth learning model learns a cross-sectional SEM image of the transistor generated using the process list. The fourth learning model generates the third feature quantity by learning the cross-sectional schematic diagram or cross-sectional SEM image of the transistor. When the fourth learning model generates the third feature, it is preferable that in parallel with this, the first learning model generates the first feature and the second learning model generates the second feature.

Accordingly, the third learning model performs multimodal learning using the first feature, the second feature, and the third feature. Accordingly, the third learning model outputs the values of variables used in the calculation formula representing the electrical characteristics of the transistor.

Also, the first characteristic quantity updates the weighting coefficient of the second neural network. The first feature amount corresponds to the output of the first learning model that learned the process list. That is, the first characteristic quantity is related to the electrical characteristics of the transistor generated according to the process list.

Next, a method for performing inference using a method of predicting electrical characteristics of a transistor will be described. When the process list for inference is given to the first learning model and the value of the voltage applied to the terminal of the semiconductor element is given to the second learning model, the third learning model is the variable used in the calculation formula representing the electrical characteristics of the transistor. print the value

Also, a description will be given of a method for performing inference using a method for predicting electrical characteristics of a transistor in the case where the first characteristic quantity updates the weighting coefficient of the second neural network. The first learning model is given a list of processes for inference, and the second learning model is given the values of voltages applied to the terminals (gate terminal, drain terminal, and source terminal) of the transistor. The second learning model outputs the value of the current flowing through the drain terminal as the predicted value according to the value of the voltage.

Next, a method for predicting electrical characteristics of a semiconductor device will be described with reference to FIGS. 1 to 8 . Further, a case in which a transistor is used as a semiconductor element will be described.

The method for predicting electrical characteristics of a transistor described in FIG. 1 includes a feature calculating unit 110 and a characteristic predicting unit 120 . The feature quantity calculating unit 110 includes a learning model 210 and a learning model 220 , and the characteristic predicting unit 120 has a learning model 230 .

In addition, the learning model 210 has a neural network 211 and a neural network 212 . In addition, the neural network 211 and the neural network 212 will be described in detail with reference to FIG. 3C .

The learning model 220 has a neural network 221 and an activation function 222 . The neural network 221 preferably has an input layer, an intermediate layer, and an output layer. In addition, the neural network 221 will be described in detail with reference to FIG. 4C .

The learning model 230 has a neural network including a connected layer 231 , a fully connected layer 232 , and a fully connected layer 233 . Also, the connection layer 231 has a multimodal interface. In FIG. 1 , the connection layer 231 connects the first characteristic quantity generated from the process list and the second characteristic quantity generated from the electrical characteristics of the transistor generated according to the process list, thereby providing an output to the fully connected layer 232 . create data

The fully connected layer 233 outputs predicted values of electrical characteristics (eg, drain current) to the output terminals OUT_1 to OUT_w. Values of variables in Equation (1) or Equation (2) correspond to the output terminals OUT_1 to OUT_w. As another example, when the semiconductor device is a resistive device or a capacitive device, the value of the variable output from the fully connected layer 233 is preferably obtained using an equation for calculating a value of resistance or an equation for calculating the size of a capacitor do. In addition, w is an integer of 1 or more.

2(A) to (D) are tables for explaining a process list given to the learning model 210 .

FIG. 2A is a table for explaining the process items of the minimum unit included in the process list. In addition, the process list is composed of a plurality of process items. Process items include process ID, device ID, and device setting conditions. In addition, although not shown in FIG. 2A, which part of each process item forms a transistor may be described. Examples of process items included in the process list include process ID, device ID, condition, and formation part. The formation part includes an oxide film, an electrode (gate, source, or drain, etc.), a semiconductor layer, and the like. In an actual semiconductor element formation process, in addition to the above, there are a plurality of processes such as formation of a contact and formation of a wiring.

2B is an example of a table explaining process items of a semiconductor device. The process ID includes a film forming process, a cleaning process, a resist coating process, an exposure process, a developing process, a processing process 1, a processing process 2, a baking process, a peeling process, a doping process, and the like. It is preferable that the apparatus used in each process be assigned to the apparatus ID. Moreover, it is preferable that the setting conditions of an apparatus are items set for the apparatus used in each process. Even if the process is the same, when the device IDs are different, different setting conditions may be given to each device.

The device ID used in the process can be set as follows. For example, film forming process: CVD1, cleaning process: WAS1, resist application process: REG1, exposure process: PAT1, developing process: DEV1, machining process 1: ETC1, machining process 2: CMP1, baking process: OVN1, peeling process: PER1, doping process: set as DOP1 and the like. It is preferable that the process ID is always managed in association with the device ID. In addition, the process ID can be combined with the device ID to represent a single code. As an example, when the process ID is a film forming process and the apparatus ID is CVD1, the code is 0011. However, the given code is managed as a unique number. In addition, the condition set in each device has a plurality of setting items. In addition, j, k, m, n, p, r, s, t, u, and v in FIG. 2B are integers of 1 or more.

FIG. 2C is a table for explaining that the code is changed when the equipment used is different even if the process items are the same. As an example, even if the process IDs are all the same in the film forming process, there are cases where the apparatus uses the CVD method for film formation and the apparatus uses the sputtering method (device ID: SPT1) for film formation. Also in the case of using the CVD method, there are a case of an apparatus that forms a film using plasma (device ID: CVD1), a case of an apparatus that forms a film using heat (device ID: CVD2), and the like. Also, as another example, in the case of having a plurality of identical devices, different codes may be used for each device. As an example, when a factory has a plurality of apparatuses for forming a film using plasma, even if the apparatus has the same function, the film quality of the film formed may be different, so management of the unit numbers is required. For example, the electrical characteristics of a transistor are sometimes affected by the device ID in the process list.

FIG. 2D is a table for explaining process items included in the process list given to the learning model 210 . As an example, code: 0011 indicating the film forming process will be described. Code: 0011 means process ID: film-forming process, device ID: CVD1. Also, as shown in FIG. 2C , the film-forming conditions given in code: 0011 are film thickness, temperature, pressure, electric power, gas 1, and flow rate of gas 1, and the like. More specifically, the film formation conditions given in Code: 0011 are: film thickness: 5 nm, temperature: 500°C, pressure: 200 Pa, electric power: 150 W, gas 1: SiH, and flow rate of gas 1: 2000 sccm. Moreover, it is preferable that different conditions can be set for each apparatus as a process item.

3A and 3B are diagrams for explaining a part of the process list. 3C is a diagram for explaining a neural network for learning a process list.

As an example, the process of processing the film formed by the film-forming process is demonstrated using a part of the process list shown in FIG.3(A). First, a film designated by the film forming process is formed. Description of the film-forming conditions and the like is omitted for ease of explanation. In addition, the apparatus used in the film-forming process is set to apparatus ID: CVD1 based on code: 0011. In addition, in the process to be described later, the drawings (FIG. 2B, etc.) are referred to, and description of each condition of each process is omitted.

Next, in a resist application process, a photoresist is apply|coated on the said film|membrane formed. Next, in the exposure step, the mask pattern of the film is transferred to the photoresist. Next, in the developing step, the photoresist other than the transferred mask pattern is removed using a developer to form a photoresist mask pattern. Moreover, the process of baking a photoresist may be included in the developing process. Next, in the processing step 1, the film is processed using the mask pattern formed on the photoresist. Next, in a peeling process, a photoresist is peeled.

In FIG.3(B), unlike FIG.3(A), the washing|cleaning process is added after the film-forming process, and the baking process is added after the peeling process. As an example, by adding a cleaning process after the film forming process, impurities remaining on the formed film are removed, or the unevenness of the upper formation surface of the film is made uniform. In addition, by adding a baking process after the peeling process, impurities (such as an organic solvent or moisture) remaining on the film to be processed are removed, or when the film is baked, the reaction of elements contained in the film is accelerated and the film quality can be changed. In addition, when the film is baked, the density of the film increases and the film quality can be hardened.

In FIG. 3B , since a process not shown in FIG. 3A is added, the film formed in the film forming process has different characteristics. Accordingly, the process list affects the electrical characteristics of transistors produced according to the process list.

3C is a diagram for explaining the learning model 210 for learning the process list as learning data. The learning model 210 has a neural network 211 and a neural network 212 .

The neural network 211 is provided with process items in order of process according to the process list. As shown in (D) of FIG. 2, process items are indicated by a single code for the process and the device name used in the process. Each code is given a plurality of conditions set on the device being used. Each condition is given in the form of a number or a number assigned a unit. In addition, the neural network 211 may be given a file in which a plurality of process items are described in process order.

As an example, it is preferable that the neural network 211 vectorize the process items using Word2Vec (W2V). Also, Word2VecGloVe (Global Vectors for Word Representation) and Bag-of-words can be used to vectorize text data. Vectorizing text data can be said in other words to transform it into a distributed representation. A variance representation can also be translated into an embedding representation (feature vector or embedding vector).

In one embodiment of the present invention, the condition of the process item is treated not as a sentence but as a set of words. Therefore, it is preferable to treat the process list as a set of words. As an example, the neural network 211 has an input layer 211a, a hidden layer 211b, and a hidden layer 211c. The neural network 211 outputs a feature vector generated from the process list. In addition, a plurality of the feature vectors may be output, or they may be aggregated into one. Hereinafter, a case in which the neural network 211 outputs a plurality of feature vectors will be described. In addition, the hidden layer may be a single layer or a plurality of layers.

Next, the neural network 212 is given a plurality of feature vectors generated by the neural network 211 . As the neural network 212, it is preferable to use a deep averaging network (DAN). As an example, the neural network 212 has an AGGREGATE layer 212a, a fully connected layer 212b, and a fully connected layer 212c. The AGGREGATE layer 212a may treat a plurality of feature vectors output by the neural network 211 as a whole.

The fully connected layer 212b and the fully connected layer 212c preferably have a sigmoid function, a step function, or a ramp function (Rectifield Linear Unit) as activation functions. Nonlinear activation functions are effective for feature vectorizing complex training data. Therefore, the neural network 212 may average the feature vectors of process items constituting the process list and aggregate them into one feature vector. The aggregated feature vector is given to the learning model 230 . Also, the fully connected layer may be one or multiple layers.

4(A) or (B) is a diagram for explaining electrical characteristics of a transistor generated according to a process list used by the learning model 210 for learning. FIG. 4C is a diagram for explaining a neural network for learning electrical characteristics of a transistor.

4A is a view showing Id-Vds characteristics used to evaluate the saturation characteristics of a transistor. The Id-Vds characteristic represents the current flowing in the drain terminal when a voltage is applied to the gate terminal, the drain terminal, and the source terminal of the transistor. That is, the Id-Vds characteristic is the value Id of the drain current when the voltage applied to the drain terminal of the transistor is changed. 4A is a diagram plotting drain current Id when potentials A1 to A10 are applied to the drain terminal of the transistor when a fixed potential is applied to the gate terminal of the transistor.

4B is a diagram illustrating Id-Vgs characteristics used to evaluate the linear characteristics of a transistor. The Id-Vgs characteristic indicates the current flowing through the drain terminal when a voltage is applied to the gate terminal, the drain terminal, and the source terminal of the transistor. That is, the Id-Vgs characteristic is the value Id of the drain current when the voltage applied to the gate terminal of the transistor is changed. FIG. 4B is a diagram plotting the drain current Id when potentials A1 to A10 are applied to the gate terminal of the transistor when a fixed potential is applied to the drain terminal of the transistor.

FIG. 4C is a diagram for explaining the neural network 221 for learning the electrical characteristics of a transistor using the data of FIG. 4A or 4B. As an example, the neural network 221 is given an input layer with a voltage Vd applied to the drain terminal of the transistor, a voltage Vg applied to the gate terminal of the transistor, and a voltage Vs applied to the source terminal of the transistor. In the case of the above-mentioned conditions, the current Id flowing through the drain terminal of the transistor may be given.

In the neural network 221 as an example, the input layer has neurons X1 to neurons X4, the hidden layer has neurons Y1 to neurons Y10, and the output layer has neurons Z1. Neuron Z1 features vectorized electrical properties, and an activation function 222 outputs a predicted value. The number of neurons in the hidden layer is preferably the same as the number of plots given as training data. Alternatively, it is more preferable that the number of neurons in the hidden layer is larger than the number of plots given as training data. When the number of neurons in the hidden layer is greater than the number of plots given as training data, the learning model 220 learns the electrical characteristics of the transistor in detail. Neuron Z1 also has the function of an activation function 222 .

As an example, a method in which the neural network 221 learns the electrical characteristics of the transistor will be described. First, neuron X1 is given a voltage Vd applied to the drain terminal of the transistor, neuron X2 is given a voltage Vg applied to the gate terminal of the transistor, neuron X3 is given a voltage Vs applied to the source terminal of the transistor, Neuron X4 is given a drain current Id flowing through the drain terminal of the transistor. At this time, the drain current Id is given as training data. The weighting coefficient of the hidden layer is updated so that the output of the neuron Z1 or the output of the activation function 222 approaches the drain current Id. In addition, when the drain current Id is not given as the learning data, learning is performed so that the output of the neuron Z1 or the output of the activation function 222 approaches the drain current Id.

In addition, although the example in which the electrical characteristics of a transistor are given sequentially according to a plot point has been described in FIG. 4(C), all plot points may be given to the neural network 221 at the same time. As a result, the neural network 221 can process calculations at high speed, which is effective in shortening the development period of the semiconductor device.

In addition, it is preferable that the learning model 220 learns in parallel with the learning model 210 . The process list given to the learning model 210 is highly related to the electrical characteristics given to the learning model 220 . Therefore, in learning to predict the electrical characteristics of the transistor, it is effective to learn the learning model 220 and the learning model 210 in parallel.

Next, the characteristic prediction unit 120 will be described. The characteristic prediction unit 120 will be described with reference to FIG. 1 . The characteristic predictor 120 has a learning model 230 . The learning model 230 is a neural network having a connected layer 231 , a fully connected layer 232 , and a fully connected layer 233 . Also, the fully connected layer may be one or multiple layers. The connection layer 231 connects feature vectors output by different learning models (learning model 210, learning model 220), and uses the connected feature vector as one feature vector. That is, by providing the connection layer 231 , the characteristic prediction unit 120 functions as a neural network including a multimodal interface.

The fully connected layer 233 outputs predicted values of electrical characteristics to the output terminals OUT_1 to OUT_w. Further, in one embodiment of the present invention, as the predicted value of the electrical characteristic as the output, the field effect mobility μFE in the above formula (1) or (2), the unit area capacitance of the gate insulating film Cox, the channel length L, the channel width W, Alternatively, the threshold voltage Vth or the like is significant. It is also preferable to output a drain voltage Vd or a gate voltage Vg or the like. In addition, the value of each variable calculated from the electrical characteristics of the transistor may be given to the connection layer 231 as training data. The learning model 230 updates the weight coefficients given the training data.

FIG. 5 is a view for explaining a method of predicting electrical characteristics of a semiconductor device different from that of FIG. 1 . In Fig. 5, the feature amount calculating unit 110A is provided. The feature-quantity extracting unit 110A is different from the feature-quantity calculating unit 110 shown in FIG. 1 in that it has a learning model 240 . The learning model 240 is a neural network that learns image data. In addition, the image data that the learning model 240 learns is a cross-sectional schematic diagram of a transistor formed according to a process list, a cross-sectional observation image obtained using a scanning electron microscope (SEM), or the like.

In addition, the connection layer 231A of the characteristic prediction unit 120 includes a feature vector generated from the process list, a feature vector generated from electrical characteristics of a transistor generated according to the process list, and a schematic cross-sectional diagram or cross-sectional observation of an actual device. By concatenating the feature vectors generated from the image, output data given to the fully connected layer 232 is generated.

6A is a diagram for explaining the learning model 240 in detail. The learning model 240 has a convolutional neural network 241 and a fully connected layer 242 . The convolutional neural network 241 has a convolutional layer 241a to a convolutional layer 241e. The number of convolutional layers is not limited, and may be an integer of 1 or more. Also, in FIG. 6A , as an example, a case having five convolutional layers is shown. The fully connected layer 242 has a fully connected layer 242a to a fully connected layer 242c. Therefore, the learning model 240 may be called a Convolutional Neural Network (CNN).

When the feature-quantity calculator 110A has the learning model 240 , prediction of the electrical characteristics of the semiconductor device using three different feature vectors becomes easy. As an example of image data to be trained, in FIG. 6B , a schematic cross-sectional diagram of a transistor generated according to a process list given to the learning model 210 is shown. Also, in FIG. 6C , a cross-sectional observation image of a transistor generated according to a process list given to the learning model 210 is shown. In addition, as the learning model 240 for learning the cross-sectional schematic diagram of the transistor, a learning model different from the learning model for learning the cross-sectional observation image of the transistor may be used.

As an example, FIG. 6B shows a semiconductor layer, a gate oxide film, and a gate electrode, and FIG. 6C shows a semiconductor layer, a gate oxide film, and a gate electrode corresponding to FIG. 6C. Since the gate oxide film of a transistor is a thin film, it may be difficult to recognize in a cross-sectional observation image. However, there are cases where the thin film, which is easily misdetected, is also described so as to be recognizable in the schematic cross-sectional diagram. Therefore, by learning the cross-sectional schematic diagram, the cross-sectional observation image can be learned more accurately. Accordingly, the process list is improved in relation to the electrical characteristics of the transistor and the actual cross-sectional observation image. Accordingly, the prediction of the electrical characteristics of the semiconductor device becomes easy.

6B and 6C show examples of transistors having a metal oxide in a semiconductor layer. However, the method for predicting electrical characteristics of a semiconductor device according to one embodiment of the present invention can be applied to a transistor including silicon in a semiconductor layer. Alternatively, it may be applied to a transistor including a compound semiconductor or an oxide semiconductor. Also, the semiconductor device is not limited to a transistor. The method for predicting electrical characteristics of a semiconductor device according to one embodiment of the present invention can also be applied to a resistive device, a capacitive device, a diode, a thermistor, a gyro sensor, an acceleration sensor, a light emitting device, or a light receiving device.

FIG. 7 is a view for explaining a method of predicting electrical characteristics of a semiconductor device different from that of FIG. 1 . In FIG. 7 , the feature amount calculating unit 110B is provided. The feature-quantity calculator 110B is different in that the output of the learning model 210 updates the weight coefficient of the neural network 221 . By reflecting the feature vector of the process list in the weight coefficient of the neural network 221 , the neural network 221 may improve the prediction of the electrical characteristics of the transistor.

In FIG. 7 , a method of predicting electrical characteristics of a transistor using a method of predicting electrical characteristics of a semiconductor device will be described. In addition, in the case of predicting the electrical characteristics of the transistor, it is preferable that the learning of the learning model 210 , the learning model 220 , and the learning model 230 is completed. First, the neural network 211 is given a process list of a new configuration as inference data 1 . In addition, the neural network 221 is given, as inference data 2, a drain voltage applied to the drain terminal of the transistor, a gate voltage applied to the gate terminal of the transistor, a source voltage applied to the source terminal of the transistor, and the like.

The feature prediction unit 120 predicts the value of each variable in Equation (1) or (2) by using the feature vector generated by the speculation data 1 and the feature vector generated by the speculation data 2 . Also, the activation function 222 may output a speculation result 1 based on the speculation data 2 . As the inference result 1, the drain current Id can be predicted from the drain voltage applied to the drain terminal of the transistor, the gate voltage applied to the gate terminal of the transistor, the source voltage applied to the source terminal of the transistor, and the like.

FIG. 8 is a view for explaining a method of predicting electrical characteristics of a semiconductor device different from that of FIG. 5 . In FIG. 8 , the feature amount calculating unit 110C is provided. The feature-quantity calculator 110C is different from the feature-quantity calculator 110A shown in FIG. 5 in that the output of the learning model 210 updates the weighting coefficient of the neural network 221 .

In FIG. 8 , a method of predicting electrical characteristics of a transistor using a method of predicting electrical characteristics of a semiconductor device will be described. In addition, in the case of predicting the electrical characteristics of the transistor, it is preferable that learning of the learning model 210 , the learning model 220 , the learning model 230 , and the learning model 240 is completed. First, the neural network 211 is given a process list of a new configuration as inference data 1 . In addition, the neural network 221 is given, as inference data 2, a drain voltage applied to the drain terminal of the transistor, a gate voltage applied to the gate terminal of the transistor, a source voltage applied to the source terminal of the transistor, and the like. Also, the neural network 241 is given a cross-sectional schematic diagram or a cross-sectional observation image of a new configuration as inference data 3 .

The feature prediction unit 120 uses the feature vector generated by the inference data 1, the feature vector generated by the inference data 2, and the feature vector generated by the inference data 3, using the above Equation (1) or Equation ( Predict the value of each variable in 2). Also, the activation function 222 may output a speculation result 1 based on the speculation data 2 . As the inference result 1, the drain current Id can be predicted from the drain voltage applied to the drain terminal of the transistor, the gate voltage applied to the gate terminal of the transistor, the source voltage applied to the source terminal of the transistor, and the like.

The fully connected layer 233 of FIG. 7 or 8 outputs predicted values of electrical characteristics to the output terminals OUT_1 to OUT_w. As an example, in one embodiment of the present invention, the field effect mobility μFE in the formula (1) or (2), the unit area capacitance Cox of the gate insulating film, the channel length L, the channel width W, or the threshold voltage Vth, etc. considerable

Fig. 9 is a diagram for explaining a computer operating a program. The computer 10 connects the database 21 , the remote computer 22 , or the remote computer 23 through a network. The computer 10 has an arithmetic unit 11 , a memory 12 , an input/output interface 13 , a communication device 14 , and a storage 15 . The computer 10 is electrically connected to the display device 16a and the keyboard 16b through the input/output interface 13 . In addition, the computer 10 is electrically connected to the network interface 17 through the communication device 14, and the network interface 17 is connected to the database 21, the remote computer 22, and the remote computer 23 through the network. electrically connected.

Here, the network includes a local area network (LAN) or the Internet. In addition, in the above network, communication by any one or both of wired and wireless can be used. In addition, when wireless communication is used in the above network, in addition to short-distance communication means such as Wi-Fi (registered trademark) and Bluetooth (registered trademark), communication means conforming to the 3rd generation mobile communication system (3G), LTE (referred to as 3.9G) Various communication means, such as a communication means compliant with the 4th generation mobile communication system (4G), or a 5th generation mobile communication system (5G) compliant communication means, can be used.

In the method of predicting electrical characteristics of a semiconductor device according to one embodiment of the present invention, the electrical characteristics of the semiconductor device are predicted using the computer 10 . The program of the computer 10 is stored in the memory 12 or the storage 15 . The program uses the computing device 11 to create a learning model. The program may be displayed on the display device through the input/output interface 13 . With respect to the program displayed on the display device 16a, the user can provide learning data, such as a process list, electrical characteristics, cross-sectional schematic diagram, or cross-sectional observation image, from the keyboard. The display device 16a converts the electrical properties of the semiconductor device predicted by the method for predicting the electrical properties of the semiconductor device into numbers, equations, or graphs and displays them.

Also, the program can be used on the remote computer 22 or the remote computer 23 through a network. Alternatively, the database 21 , the remote computer 22 , or a program stored in the memory or storage of the remote computer 23 may be used to operate the computer 10 . The remote computer 22 may be a portable terminal such as a portable information terminal, a tablet computer, or a notebook type computer. In the case of a portable information terminal or a portable terminal, communication may be performed using wireless communication.

Accordingly, one embodiment of the present invention can provide a method for predicting electrical characteristics of a semiconductor device using a computer. In the method for predicting electrical characteristics of semiconductor devices, multi-modal learning is performed by giving a process list, electrical characteristics of a semiconductor device generated according to the process list, or a cross-sectional schematic diagram or cross-sectional observation image of a semiconductor device generated according to the process list as learning data. can In addition, in the method for predicting electrical characteristics of semiconductor devices, a new process list, conditions of voltage applied to the semiconductor device, cross-sectional schematic diagram, or cross-sectional observation image are given as inference data, thereby representing the electrical properties or electrical properties of the semiconductor device. value can be predicted. As an example, when a new process is added to the process list, the electrical characteristics of the transistor can be easily predicted. Therefore, according to the method for predicting electrical characteristics of a semiconductor device according to one embodiment of the present invention, it is possible to reduce the number of experiments for confirmation in the development of a semiconductor device, and to effectively utilize information from past experiments.

This embodiment can be implemented by combining a part of them suitably.

OUT_w: output terminal, OUT_1: output terminal, 10: computer, 11: arithmetic unit, 12: memory, 13: input/output interface, 14: communication device, 15: storage, 16a: display device, 16b: keyboard, 17: network interface , 21: database, 22: remote computer, 23: remote computer, 110: feature calculator, 110A: feature calculator, 110B: feature calculator, 110C: feature calculator, 120: feature Prediction unit, 210: learning model, 211: neural network, 211a: input layer, 211b: hidden layer, 211c: hidden layer, 212: neural network, 212a: AGGREGATE layer, 212b: fully connected layer, 212c: fully connected layer , 220: learning model, 221: neural network, 230: learning model, 231: connected layer, 231A: connected layer, 232: fully connected layer, 233: fully connected layer, 240: learning model, 241: neural network, 241a: convolutional layer, 241e: convolutional layer, 242: fully connected layer, 242a: fully connected layer, 242c: fully connected layer

Claims (7)

A method for predicting electrical characteristics of a semiconductor device having a feature calculating unit and a characteristic predicting unit, the method comprising:
The feature quantity calculation unit has a first learning model and a second learning model,
The characteristic prediction unit has a third learning model,
The first learning model has a step of learning a process list for producing the semiconductor device,
The second learning model has the step of learning the electrical characteristics of the semiconductor device generated according to the process list,
the first learning model generating a first feature quantity,
wherein the second learning model generates a second feature quantity,
and the third learning model performs multimodal learning using the first feature and the second feature,
and outputting, by the third learning model, a value of a variable used in a calculation expression representing the electrical characteristic of the semiconductor device. The method of claim 1,
The feature quantity calculation unit has a fourth learning model,
The fourth learning model has a step of learning a cross-sectional schematic diagram generated using the process list,
wherein the fourth learning model generates a third feature quantity,
The third learning model has a step of multimodal learning using the first feature, the second feature, and the third feature,
and outputting, by the third learning model, a value of the variable used in a calculation expression representing the electrical characteristic of the semiconductor device. 3. The method of claim 1 or 2,
The first learning model has a first neural network,
The second learning model has a second neural network,
and updating a weighting coefficient of the second neural network by the first feature amount generated by the first neural network. 4. The method according to any one of claims 1 to 3,
When a process list for inference is given to the first learning model, and a value of a voltage applied to a terminal of the semiconductor device is given to the second learning model, the second learning model determines the value of the current according to the value of the voltage. A method for predicting electrical characteristics of a semiconductor device, comprising the step of outputting a value. 4. The method according to any one of claims 1 to 3,
When a process list for inference is given to the first learning model, and a value of a voltage applied to a terminal of the semiconductor element is given to the second learning model, the third learning model is a formula for calculating electrical characteristics of the semiconductor element A method of predicting electrical characteristics of a semiconductor device, comprising the step of outputting a value of a variable used for . 6. The method according to any one of claims 1 to 5,
The method for predicting electrical characteristics of a semiconductor device, wherein the semiconductor device is a transistor. 7. The method of claim 6,
The transistor comprises a metal oxide in the semiconductor layer, the electrical characteristics prediction method of a semiconductor device.

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