KR20220003823A - Display device - Google Patents

Abstract

The present invention relates to a display device for realizing a high resolution. The present invention can realize a high resolution by having a storage capacitor overlapping a thin film transistor. A storage electrode included in the storage capacitor has a hollow region so that current uniformity can be improved while properly maintaining the capacity of the storage capacitor. Since the storage electrode is disposed between a gate electrode and a signal line, signal interference can be minimized.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device capable of realizing high resolution.

A video display device that implements various information on a screen is a key technology in the information and communication era, and is developing in the direction of thinner, lighter, portable and high-performance. Accordingly, flat panel display devices capable of reducing weight and volume, which are disadvantages of cathode ray tubes (CRTs), are in the spotlight.

Examples of flat panel display devices include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display. Device:ED), etc.

The flat panel display implements an image through a plurality of sub-pixels arranged in a matrix form. Each of the plurality of sub-pixels includes a pixel driving circuit including at least one transistor and a storage capacitor.

Recently, as the resolution of a display device increases, the size of each sub-pixel should be reduced. However, since a separate area occupied by the storage capacitor must be provided in each sub-pixel, there is a limitation in realizing a high-resolution display device.

SUMMARY OF THE INVENTION The present invention is to solve the above problems, and the present invention is to provide a display device capable of realizing high resolution.

In order to achieve the above object, a display device according to the present invention includes: a first thin film transistor disposed on a substrate and including an active layer, a gate electrode, and source and drain electrodes; and a capacitor overlapping the first thin film transistor, wherein the capacitor includes a storage electrode having a hollow region to surround an outer region of a channel region of the active layer.

Here, the hollow region of the storage electrode and the storage electrode overlap the gate electrode.

In addition, the hollow region of the storage electrode has a circular, elliptical, or rectangular shape.

In this case, the storage electrode having the rectangular hollow region is parallel to the length direction of the active layer, the first and second electrode patterns facing each other with the hollow region interposed therebetween, and the width direction of the active layer The third and fourth electrode patterns are parallel to each other and face each other with the hollow region interposed therebetween.

The present invention further includes a signal line disposed on the substrate, wherein the storage electrode is disposed between the signal line and the gate electrode.

In addition, the storage electrode is disposed between each of the source and drain electrodes and the gate electrode.

a second thin film transistor connected to the first thin film transistor and having a channel width smaller than a channel width of the first thin film transistor; It further includes a light emitting element connected to the first thin film transistor.

The present invention further includes a gate driver disposed on the substrate and including the first thin film transistor and the capacitor.

In this case, the thin film transistor is disposed in an active region in which an image is implemented, or in an active region and an inactive region in which the image is not implemented.

In the present invention, since there is no separate space occupied by the storage capacitor by providing the storage capacitor overlapping the thin film transistor, high resolution implementation is facilitated.

Also, according to the present invention, since the storage electrode included in the storage capacitor has a hollow region, the capacity of the storage capacitor may be properly maintained and current uniformity may be improved.

In addition, since the storage electrode having the hollow region of the present invention is disposed between the gate electrode and the signal line, signal interference between the gate electrode and the signal line can be minimized.

1 is a block diagram illustrating a display device according to the present invention.
FIG. 2 is a plan view illustrating a thin film transistor included in each sub-pixel shown in FIG. 1 .
3 is a cross-sectional view showing the thin film transistor taken along the line "I-I'" in FIG.
4 is a plan view for explaining the storage electrode shown in FIG. 2 in detail.
FIG. 5 is a cross-sectional view illustrating an arrangement relationship between the first gate electrode, the storage electrode, and the signal line illustrated in FIG. 4 .
6 is a cross-sectional view illustrating an organic light emitting diode display to which the thin film transistor shown in FIG. 4 is applied.
7 is a plan view illustrating the switching transistor shown in FIG. 6 .
8 is a cross-sectional view showing the thin film transistor taken along the line "II-II'" in FIG. 3 and the switching transistor taken along the line "III-III'" in FIG. 7;
9A is a plan view showing the thin film transistor of the comparative example, and FIGS. 9B and 9C are views showing the characteristics of the thin film transistor of the comparative example.
10A is a plan view showing the thin film transistor of the present invention, and FIGS. 10B and 10C are views showing the characteristics of the thin film transistor of the present invention.
11 is a circuit diagram illustrating the gate driver illustrated in FIG. 1 .

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a display device according to the present invention.

The display device illustrated in FIG. 1 includes a display panel 10 and a panel driver driving the display panel 10 . The panel driver includes a data driver 20 , gate drivers 40A and 40B, and a timing controller 30 .

The timing controller 30 generates data control signals and gate control signals for controlling driving timings of the data driver 20 and the gate drivers 40A and 40B, respectively, and generates the data driver 20 and the gate drivers 40A and 40B. supplied with The timing controller 30 processes image data and supplies it to the data driver 20 .

The data driver 20 is controlled by a data control signal supplied from the timing controller 30 , and converts the image data supplied from the timing controller 30 into an analog data signal to form a data line DL of the display panel 10 . supplied with

The gate drivers 40A and 40B are implemented as a gate in panel (GIP) circuit that is directly formed in the form of a thin film transistor on the inactive regions RNA and LNA on the display panel 10 . The gate drivers 40A and 40B are disposed in the non-display area NA of at least one of the left and right sides of the display panel 10 .

The gate drivers 40A and 40B output the gate signal while shifting the level of the gate voltage in response to the gate control signal supplied from the timing controller 30 . The gate drivers 40A and 40B output gate signals through the gate lines GL.

The display panel 10 includes an active area AA realizing a screen on which an input image is displayed, and an inactive area NA positioned at at least one side of the active area AA.

The inactive area NA is an area in which an input image is not displayed, in which the sub-pixels SP are not disposed and signal lines and the gate drivers 40A and 40B are disposed.

In the active area AA, the sub-pixels SP connected to the data lines DL and the gate lines GL that cross each other are arranged in a matrix form. The sub-pixels SP include at least one thin film transistor and a storage capacitor electrically connected to the thin film transistor.

At least one thin film transistor 140 includes a first active layer 144 , a first gate electrode 142 , a first source electrode 146 , and a first drain electrode 148 as shown in FIGS. 2 and 3 . to provide

The first active layer 144 is formed on the buffer layer 110 to overlap the first gate electrode 142 to form a channel region 144C between the first source and first drain electrodes 146 and 148 . In addition, the first active layer 144 is formed to not overlap the first gate electrode 142 and includes a conductive source region 144S and a drain region 144D. The first active layer 144 is formed of at least one of an oxide semiconductor, polysilicon, and amorphous silicon.

The buffer layer 110 disposed under the first active layer 144 delays diffusion of moisture and/or oxygen penetrating into the substrate 101 . The buffer layer 110 is formed as a single layer or multiple layers using at least one of silicon nitride (SiNx) and silicon oxide (SiOx).

The first gate electrode 142 overlaps the channel region 144C of the first active layer 144 with the gate insulating layer 112 interposed therebetween.

The first source electrode 146 is disposed on the third interlayer insulating layer 118 . The first source electrode 156 has a source region ( 144S).

The first drain electrode 148 is disposed on the third interlayer insulating layer 118 . The first drain electrode 148 has a drain region ( 144D).

Meanwhile, although the structure in which the second and third interlayer insulating layers 116 and 118 are disposed between each of the first source and first drain electrodes 146 and 148 and the storage electrode 152 has been described as an example, in addition to the first source and the first Any one of the second and third interlayer insulating layers 116 and 118 or three or more interlayer insulating layers may be disposed between each of the drain electrodes 146 and 148 and the storage electrode 152 .

The storage capacitor Cst is formed by overlapping the first gate electrode 142 and the storage electrode 152 with the first interlayer insulating layer 114 interposed therebetween. Since the storage capacitor Cst overlaps the thin film transistor 140 , a separate space occupied by the storage capacitor Cst becomes unnecessary, thereby realizing high resolution and high definition.

The storage electrode 152 is formed in a frame shape having a hollow region 150 in a circle, oval, or square shape to surround an outer region of the channel region 144C of the first active layer 144 .

For example, as shown in FIG. 4 , the storage electrode 152 having the rectangular hollow region 150 includes first and second first and second electrodes parallel to the length direction of the channel region 144C of the first active layer 144 . The electrode patterns 152a and 152b and third and fourth electrode patterns 152c and 152d parallel to the channel width direction of the first active layer 144 are provided.

The first electrode pattern 152a overlaps the upper surface of the channel region 144C of the first active layer 144 . The second electrode pattern 152b faces the first electrode pattern 152a with the hollow region 150 interposed therebetween, and overlaps the lower surface of the channel region 144C of the first active layer 144 . The third electrode pattern 152c overlaps the boundary between the drain region 144D and the channel region 144C of the first active layer 144 . The fourth electrode pattern 152d faces the third electrode pattern 152c with the hollow region 150 interposed therebetween, and forms a boundary between the source region 144S and the channel region 144C of the first active layer 144 . overlap

The hollow region 150 of the storage electrode 152 is formed to expose a portion of the first interlayer insulating layer 114 disposed on the first gate electrode 142 , and thus overlaps the first gate electrode 142 . . Accordingly, the overlapping area of the storage electrode 152 with the hollow region 150 with the first gate electrode 142 is reduced compared to the storage electrode without the hollow region.

In this case, the storage capacitor of the comparative example in which the storage electrode having no hollow region overlaps with the first gate electrode has an excessive capacity value, and thus the charging characteristic is deteriorated. On the other hand, the storage capacitor Cst of the present invention, which is formed by overlapping the storage electrode 152 having the hollow region 150 and the first gate electrode 142 , has an appropriate capacitance value, so that it is possible to secure stable charging characteristics. have.

In addition, the storage electrode 152 is disposed between each of the first source and first drain electrodes 146 and 148 and the first gate electrode 142 , and includes the first source and first drain electrodes 146 and 148 , respectively, and the first The electric field between the gate electrodes 142 is shielded. Accordingly, the storage electrode 152 may prevent a voltage swing phenomenon caused by the parasitic capacitor formed between each of the first source and first drain electrodes 146 and 148 and the first gate electrode 142 . In addition, as shown in FIG. 5 , the storage electrode 152 includes a signal line (eg, a data line (DL)) 154 disposed around the thin film transistor 140 , and a first gate electrode 142 . It is disposed therebetween to shield an electric field between the signal line 154 and the first gate electrode 152 . Accordingly, the storage electrode 152 may prevent a voltage swing phenomenon caused by the parasitic capacitor Cp formed between the signal line 154 and the first gate electrode 152 .

As such, the storage electrode 152 is disposed between the signal line 154, the first source and first drain electrodes 146 and 148, respectively, and the first gate electrode 142, the signal line 154, the first source and the An interaction between each of the first drain electrodes 146 and 148 and the first gate electrode 142 may be blocked. Accordingly, the present invention can minimize signal interference between the signal line 154 , each of the first source and first drain electrodes 146 and 148 , and the first gate electrode 142 , thereby improving reliability.

Meanwhile, the thin film transistor 140 shown in FIG. 3 overlapping the storage capacitor Cst may be applied to the driving thin film transistor TD of the organic light emitting diode display as shown in FIG. 6 .

The organic light emitting diode display shown in FIG. 6 includes a light emitting device 130 , at least one driving transistor TD and at least one switching transistor TS electrically connected to the light emitting device 130 , and a driving transistor TD ) and a storage capacitor (Cst) that overlaps.

The light emitting device 130 includes an anode electrode 132 , a cathode electrode 136 , and a light emitting stack 134 formed between the anode electrode 132 and the cathode electrode 136 .

The anode electrode 132 is independently disposed on the planarization layer 158 for each sub-pixel. The anode electrode 132 is disposed on the planarization layer 158 to overlap not only the light emitting area provided by the bank 138 but also at least one of the driving and switching transistors TD and TS, thereby increasing the light emitting area. The bank 138 is formed to expose the anode electrode 132 to provide a light emitting region. The bank 138 is formed in the active area with an opaque material (eg, black) to prevent light interference between adjacent sub-pixels, or is inactive to overlap the active area AA as well as the gate drivers 40A and 40B. It is formed in the area NA. In this case, the bank 138 includes a light blocking material made of at least one of a color pigment, organic black, and carbon.

The light-emitting stack 134 is formed by stacking a hole-related layer, an organic light-emitting layer, and an electron-related layer on the anode electrode 132 in the order or in the reverse order.

The cathode electrode 136 is formed on the upper surface and the side surface of the light emitting stack 134 to face the anode electrode 132 with the light emitting stack 134 interposed therebetween. The cathode electrode 136 is formed to be shared by all sub-pixels disposed in the active region.

The switching transistor TS switches a data voltage written to each of the sub-pixels SP located in the active area AA. As shown in FIG. 6 , the switching transistor TS includes a second active layer 164 , a second gate electrode 162 , a second source electrode 166 , and a second drain electrode 168 .

The second active layer 164 is formed to overlap the second gate electrode 162 on the buffer layer 110 to form a channel between the second source and second drain electrodes 166 and 168 . The second active layer 654 has a channel width smaller than that of the first active layer 144 shown in FIG. 2 . The second active layer 164 is formed of at least one of an oxide semiconductor, polysilicon, and amorphous silicon.

Meanwhile, in FIG. 6 , a structure in which the first and second active layers 144 and 164 are disposed on the same plane has been described as an example, but in addition, the first and second active layers 144 and 164 may be disposed on different planes. . For example, when the first active layer 144 is formed of an oxide semiconductor and the second active layer 164 is formed of polysilicon, the first active layer 144 is formed above the second active layer 164 . may be placed.

The second gate electrode 162 is electrically connected to the gate line GL and overlaps the channel of the second active layer 164 with the gate insulating layer 112 interposed therebetween.

The second source electrode 166 is disposed on the third interlayer insulating layer 118 to be electrically connected to the data line DL. The second source electrode 166 is in contact with the second active layer 164 exposed through the second source contact hole 120S penetrating the gate insulating layer 112 and the first to third interlayer insulating layers 114 , 116 , and 118 .

The second drain electrode 168 is disposed on the third interlayer insulating layer 118 to be electrically connected to the first gate electrode 142 of the driving transistor TD. The second drain electrode 168 is in contact with the first active layer 164 exposed through the second drain contact hole 120D penetrating the gate insulating layer 112 and the first to third interlayer insulating layers 114 , 116 , and 118 .

The driving transistor TD operates so that a driving current flows between the high voltage (VDD) supply line and the low voltage (VSS) supply line according to the data voltage stored in the storage capacitor Cst. The driving transistor TD has the same components as the thin film transistor 140 shown in FIGS. 2 and 3 . That is, the driving transistor TD includes a first gate electrode 142 connected to the second drain electrode 168 of the switching transistor TS, a first source electrode 146 connected to a high voltage (VDD) supply line, and , a drain electrode 148 connected to the light emitting device 130 , and a first active layer 144 forming a channel between the first source and first drain electrodes 146 and 148 .

The channel width WD of the first active layer 144 of the driving transistor TD is the channel width WS of the second active layer 164 of the switching transistor TS as shown in FIGS. 7 and 8 . formed more widely. Since the amount of current is proportional to the channel width, the driving transistor TD may increase the amount of current flowing through the channel region 144C of the first active layer 144 larger than that of the switching transistor TS. Accordingly, it is possible to have a more advantageous structure for switching a high current supplied to the light emitting device 130 through the driving transistor TD.

9A and 10A are plan views showing the thin film transistor of the comparative example and the present invention, FIGS. 9B and 9C are views showing the characteristics of the thin film transistor of the comparative example, and FIGS. 10B and 10C are the characteristics of the thin film transistor of the present invention It is a drawing showing

The thin film transistor of the comparative example shown in FIG. 9A includes a first active layer 44 , a first gate electrode 42 , first source and first drain electrodes 46 and 48 , and a first gate electrode 42 . is overlapped with the storage electrode 52 to form a storage capacitor. In this case, the storage electrode 52 is disposed to be biased toward one side of the channel region 44C of the first active layer 44 without a hollow region. That is, the storage electrode 52 is disposed to overlap the upper outer region of the channel region 44C and not overlap the lower outer region of the channel region 44C.

In this case, the drain voltage V versus drain current Ia1 characteristic in the upper region of the channel region 44C illustrated in FIG. 9B is the drain voltage versus the drain voltage in the lower region of the channel region 44C illustrated in FIG. 9C . It is different from the current (Ib1) characteristic. The thin film transistor overlapping the storage electrode 52 of this comparative example cannot ensure uniformity of current density. Accordingly, when the thin film transistor overlapping the storage electrode 52 of the comparative example is applied to the driving transistor TD, the intensity of the driving current supplied to the light emitting device through the driving transistor TD becomes non-uniform, so that the luminance characteristics of the light emitting device cannot be reliably secured.

On the other hand, the storage electrode 152 having the hollow region 150 of the present invention shown in FIG. 10A is formed to surround the outer region of the channel region 144C of the first active layer 144 .

In this case, the characteristic of the drain current Ia2 versus the drain voltage V in the upper region of the channel region 144C shown in FIG. 10B is the drain voltage V in the lower region of the channel region 144C shown in FIG. 10C . ) compared to the drain current (Ib2), there is almost no difference. The thin film transistor overlapping the storage electrode 152 of the present invention may ensure uniformity of current density. Accordingly, when the thin film transistor overlapping the storage electrode 152 of the present invention is applied to the driving transistor TD, the intensity of the driving current supplied to the light emitting device 130 through the driving transistor TD becomes uniform to emit light. The luminance characteristic of the device 130 may be stably secured.

Meanwhile, although a structure in which the storage electrode 152 is applied to the driving transistor TD disposed in the active area AA has been described as an example, the present invention may also be applied to a transistor disposed in the inactive area NA. For example, a scan transistor and a circuit capacitor included in the gate drivers 40A and 40B implemented as a GIP circuit in the non-active area NA may be formed in an overlapping structure.

Specifically, as shown in FIG. 11 , the gate drivers 40A and 40B include a plurality of scan transistors T1 to T9 and scan capacitors Con, CQ, and CQB. Meanwhile, the gate drivers 40A and 40B are not limited to the structure shown in FIG. 11 and may be variously changed.

The first scan transistor T1 is an output buffer whose operation is controlled according to the potential of the node Q3 . The first scan transistor T1 outputs the scan signal SRO of the high-level gate voltage VGH to the node N when the node Q3 is activated with the high-level gate voltage VGH. The second scan transistor T2 is an output buffer whose operation is controlled according to the potential of the node QB. The second scan transistor T2 outputs the scan signal SRO of the low-level gate voltage VGL to the node N when the node QB is activated with the low-level gate voltage VGL. The third scan transistor T3 is switched according to the start signal VST to supply the high-level gate voltage VGH to the node Q2 . The fourth scan transistor T4 is switched according to the previous carry signal Q(n-1) to apply the low-level gate voltage VGL to the node Q1. The fifth scan transistor T5 is switched according to the voltage of the node Q1 to supply the second clock signal CLK2 to the node QB. The sixth scan transistor T6 is switched according to the voltage of the node Q2 to supply the high-level gate voltage VGH to the node QB. The seventh scan transistor T7 is an auxiliary transistor that is always turned on by the high-level gate voltage VGH. The scan transistor T7 maintains the voltages of the nodes Q2 and Q3 substantially the same. The eighth scan transistor T8 is switched according to the voltage of the node QB to apply the low-level gate voltage VGL to the node Q2. The ninth scan transistor T9 is switched according to the first clock signal CLK1 to apply the low-level gate voltage VGL to the node Q1 . The first scan capacitor Con is a coupling capacitor connected between the input terminal of the second clock signal CLK2 and the node Q1, and the second scan capacitor CQ is connected between the node Q3 and the node N. connected to store the voltage of the node Q3, and the third scan capacitor CQB is connected between the node QB and the input terminal of the low-level gate voltage VGL to store the voltage of the node QB.

At this time, the electrode included in at least one of the first to third scan capacitors Con, CQ, and CQB is any one of the plurality of scan transistors T1 to T9 like the storage electrode 152 shown in FIG. 2 . has a second hollow region to surround the outer region of the channel region.

Meanwhile, although the organic light emitting diode display has been described as an example in the present invention, it can be applied to other electronic devices including transistors and capacitors.

1 is a plan view showing a touch display device according to the present invention.

The touch display device illustrated in FIG. 1 includes a plurality of touch electrodes 150 and T11 to T76 and touch lines 160 connected to each of the plurality of touch electrodes 150 .

Since each of the plurality of touch electrodes 150 includes a capacitance formed in the touch electrodes 150 itself, it is used as a self-capacitance type touch sensor for detecting a change in capacitance due to a user's touch. do. In the self-capacitance sensing method using the touch electrode 150 , when a driving signal supplied through the touch line 160 is applied to the touch electrode 150 , electric charges Q are accumulated in the touch sensor. At this time, when a user's finger or a conductive object comes into contact with the touch electrode 150 , a parasitic capacitance is additionally connected to the self-capacitance sensor to change the capacitance value. Accordingly, the capacitance value is different between the touch sensor touched by the finger and the touch sensor not touched by the finger, so that the touch may be determined.

The above description is merely illustrative of the present invention, and various modifications may be made by those of ordinary skill in the art to which the present invention pertains without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be construed by the following claims, and all technologies within the scope equivalent thereto should be construed as being included in the scope of the present invention.

10: display panel 20: data driver
30: timing controller 40A, 40B: gate driver
101: substrate 110: buffer layer
112: gate insulating film 114, 116, 118: interlayer insulating film
130: light emitting element 132: anode electrode
134: light emitting layer 136: cathode electrode
142,162: gate electrode 144,164: active layer
146,166: source electrode 148,168: drain electrode
150: hollow region 152: storage electrode
158: planarization layer

Claims (16)

a first thin film transistor disposed on a substrate and including an active layer, a gate electrode, and source and drain electrodes;
and a capacitor overlapping the first thin film transistor;
the capacitor is
and a storage electrode having a hollow region to surround an outer region of the channel region of the active layer. The method of claim 1,
The hollow region of the storage electrode and the storage electrode overlap the gate electrode. The method of claim 1,
The hollow region of the storage electrode has a circular shape, an oval shape, or a rectangular shape. The method of claim 1,
The storage electrode is
first and second electrode patterns parallel to the longitudinal direction of the active layer and facing each other with the hollow region interposed therebetween;
A display device comprising third and fourth electrode patterns parallel to the width direction of the active layer and facing each other with the hollow region interposed therebetween. The method of claim 1,
Further comprising a signal line disposed on the substrate,
The storage electrode is
a display device disposed between the signal line and the gate electrode. The method of claim 1,
The storage electrode is
The display device is disposed between each of the source and drain electrodes and the gate electrode. The method of claim 1,
a second thin film transistor connected to the first thin film transistor and having a channel width smaller than a channel width of the first thin film transistor;
The display device further comprising a light emitting element connected to the first thin film transistor. The method of claim 1,
The display device further comprising a gate driver disposed on the substrate and including the first thin film transistor and the capacitor. The method of claim 1,
The first thin film transistor is disposed in an active region in which an image is displayed, or in an active region and an inactive region in which the image is not implemented. a switching transistor disposed on the substrate;
a driving transistor connected to the switching transistor and including an active layer, a gate electrode, and source and drain electrodes;
a light emitting element connected to the driving transistor;
a storage capacitor overlapping the driving transistor;
The storage capacitor is
and a storage electrode having a hollow region to surround an outer region of the channel region of the active layer. 11. The method of claim 10,
The hollow region of the storage electrode and the storage electrode overlap the gate electrode. 11. The method of claim 10,
The storage electrode is
first and second electrode patterns parallel to the longitudinal direction of the active layer and facing each other with the hollow region interposed therebetween;
A display device comprising third and fourth electrode patterns parallel to the width direction of the active layer and facing each other with the hollow region interposed therebetween. 11. The method of claim 10,
Further comprising a signal line electrically connected to any one of the switching transistor and the driving transistor,
The storage electrode is
a display device disposed between the signal line and the gate electrode. 14. The method of claim 13,
The storage electrode is
The display device is disposed between each of the source and drain electrodes and the gate electrode. 11. The method of claim 10,
A channel width of the switching transistor is narrower than a channel width of the driving transistor. 11. The method of claim 10,
It is disposed on the substrate and further includes a gate driver including a plurality of scan transistors and a plurality of scan capacitors,
An electrode included in at least one of the plurality of scan capacitors has a second hollow region to surround an outer region of a channel region of any one of the plurality of scan transistors.

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