KR20220000079A - Sense amplification device - Google Patents

Abstract

The disclosure provides a sense amplification device for sensing (reading) data of bit lines. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier.

Description

Sense amplifier device {SENSE AMPLIFICATION DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a signal amplification circuit, and more particularly, to a sense amplifier device.

1 is a circuit block schematic diagram of a memory cell array in a dynamic random access memory (DRAM) 100 . The memory cell array of the DRAM 100 includes a plurality of sub-arrays 110 to 140 . Each of the sub-arrays 110 to 140 includes a plurality of bit-lines (BL0 and BL1), a plurality of word-lines (not shown), and a plurality of memory cells (not shown). does not have). According to design requirements, these sub-arrays 110 to 140 may be well-known memory cells or other memory cells, and thus will not be described in detail here.

The DRAM 100 shown in FIG. 1 further includes a plurality of sense amplifiers (SA). The bit lines of the two sub-arrays share one sense amplifier. Each of these sense amplifiers is a differential signal amplifier. That is, each of these sense amplifiers has a differential pair. The first terminal and the second terminal of the differential pair are respectively connected to one bit line of a different sub-array. For example, the first terminal of the differential pair of the sense amplifier 150 is connected to the bit line BL0 of the sub-array 110 , and the second terminal of the differential pair of the sense amplifier 150 is connected to the sub-array ( 120 is connected to the bit line BL1.

The first terminal and the second terminal of the differential pair of the sense amplifier 150 shown in FIG. 1 have the same bit line capacitance, and the load capacitance is matched for high-precision differential sensing. On one side of the edge sub-array (eg, the sub-array 110 or 140 ), there is no sense amplifier because load capacity matching cannot be performed. The edge sub-array 110 or 140 includes a dummy bit-line (shown by a broken line) and a plurality of dummy memory cells (not shown) connected to the dummy bit-line. In general, the dummy memory cell is a memory cell that does not require idling. Accordingly, half of the memory cells of the edge sub-array are unavailable.

로 나타낼 수 있다.FIG. 2 shows the sense amplifier 150, the bit line BL0, and the bit line BL1 shown in FIG. 3 is a schematic diagram of waveforms of the word line WL, the control signal CSP, the control signal CSN, the data SN, the bit line BL0, and the bit line BL1 shown in FIG. 2 . 3 , the horizontal axis represents time, and the vertical axis represents the signal level. Reference is made to Figures 2 and 3 . The first power supply terminal of the sense amplifier 150 shown in FIG. 2 receives the control signal CSP, and the second power supply terminal of the sense amplifier 150 receives the control signal CSN. The capacitor C _BL shown in FIG. 2 represents the parasitic capacitance of the bit line BL0 and the bit line BL1. The memory cell MC shown in FIG. 2 represents one of a plurality of memory cells connected to the bit line BL1 in the sub array 120 . The memory cell MC represents an equivalent circuit, and includes a switch SW and a storage element C _SN . The first terminal of the switch SW is connected to the bit line BL1. The second terminal of the switch SW is connected to the _{storage element C SN .} A control terminal of the switch SW is connected to one word line WL among a plurality of word lines in the sub-array 120 . When the word line WL turns on the switch SW, the sense amplifier 150 senses the data SN of the memory cell MC by the bit line BL1. read) and amplifies the level of the data SN. The detection signal (level difference between the bit line BL0 and the bit line BL1) is,

can be expressed as

The sense amplifier 150 includes an NMOS pair and a PMOS pair. Depending on the deviation of the process, a V _th mismatch occurs between the paired transistors in the sense amplifier 150 . If the detection signal dV _SIG is not greater than V _th mismatch, the sense amplifier 150 may not accurately detect the _{detection signal dV SIG .} However, when the process is scaled down, the capacity of the cell storage node (CSN) decreases, and the sensing signal dV _SIG becomes small. Further, as the number of sense amplifiers on a chip increases, the V _th mismatch also increases statistically. Thus, as the process shrinks, the sense signal margin decreases.

It should be noted that the content of the paragraph of "Prior Art" is intended to facilitate understanding of the present invention. The contents (or all contents) disclosed in the paragraph of "prior art" may not be well-known techniques known to those of ordinary skill in the technical field to which the present invention belongs. The content disclosed in the paragraph of "Prior Art" does not indicate that the content is already known to a person having ordinary knowledge in the technical field to which the present invention pertains before the filing of the present invention.

The present invention provides a sense amplifier device for sensing (reading out) data of a bit line.

In one embodiment of the present invention, the above-described sense amplifier device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. The input terminal of the first sense amplifier is connected to the first bit line. The input terminal of the second sense amplifier is connected to the second bit line. The third sense amplifier has a differential input pair and a differential output pair, a first input terminal of the differential input pair is connected to an output terminal of the first sense amplifier, and a second input terminal of the differential input pair is , connected to the output terminal of the second sense amplifier, the first output terminal of the differential output pair is connected to the input terminal of the first sense amplifier, the second output terminal of the differential output pair is connected to the input terminal of the second sense amplifier is connected to

As described above, the first sense amplifier and/or the second sense amplifier according to the embodiment of the present invention can amplify a small signal on the bit line. The above-described third sense amplifier may receive the amplified differential signal. Accordingly, this sense amplifier device can sense (read) the data of the bit line.

In order to make it easier to understand the above and other objects, features, and advantages of the present invention, some embodiments in accordance with the drawings will be described below.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included so that the principle of this invention may be further understood, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.
1 is a schematic diagram of a circuit block of a memory cell array in a DRAM.
[Fig. 2] The sense amplifier and bit line shown in Fig. 1 are shown.
Fig. 3 is a schematic diagram of waveforms of word lines, control signals, data, and bit lines shown in Fig. 2;
[Fig. 4] Fig. 4 is a circuit block schematic diagram of a sense amplifier device according to an embodiment of the present invention.
[Fig. 5] Fig. 5 is a circuit schematic diagram of a sense amplifier according to an embodiment of the present invention.
[FIG. 6] It is a sequence schematic diagram explaining the signal shown in FIG. 5 according to one embodiment of the present invention.
7 is a circuit schematic diagram of a sense amplifier according to another embodiment of the present invention.
[FIG. 8] It is a sequence schematic diagram explaining the signal shown in FIG. 7 according to one embodiment of the present invention.
[Fig. 9] A schematic diagram of a voltage generating circuit according to another embodiment of the present invention.
[Fig. 10] It is a circuit schematic diagram for explaining the sense amplifier shown in Fig. 4 according to still another embodiment of the present invention.
[FIG. 11] It is a sequence schematic diagram explaining the signal shown in FIG. 10 according to one embodiment of the present invention.
[Fig. 12] It is a circuit schematic diagram for explaining the sense amplifier shown in Fig. 4 according to still another embodiment of the present invention.
[FIG. 13] It is a sequence schematic diagram explaining the signal shown in FIG. 12 according to one embodiment of the present invention.

The phrase "connection (connection)" used in the entirety of the specification (including claims) of the present application may refer to any direct or indirect connection means. For example, when it is described in the sentence that the first device is connected (connected) to the second device, it may be interpreted that the first device is directly connected to the second device, or It may be construed that the first device is indirectly connected to the second device by another device or some kind of connecting means. In addition, in the drawings and embodiments where possible, elements/members/steps with the same reference numerals are used to indicate the same or similar parts. In different embodiments, reference may be made to related descriptions by using the same reference numerals or using the same terms for elements/members/steps.

4 is a circuit block schematic diagram of a sense amplifier device 400 according to an embodiment of the present invention. The sense amplifier device 400 may be a two-stage sense amplifier. In the embodiment of FIG. 4 , the sense amplifier device 400 includes sense amplifiers 410 to 430 . The input terminal of the sense amplifier 410 is connected to the bit line BLa. The input terminal of the sense amplifier 420 is connected to the bit line BLb. The bit line BLa and the bit line BLb can be inferred by referring to the related description of the bit line BL0 and the bit line BL1 shown in FIGS. 1 and 2 .

The bit line BLa is a plurality of memory cells in one sub-array of a memory cell array in a dynamic random access memory (DRAM), for example, a memory cell MC1. )), and the bit line BLb is connected to a plurality of memory cells (for example, memory cells MC2) among other sub-arrays of the memory cell array. The sub-array can be inferred with reference to the related description of the sub-arrays 110 to 140 shown in FIG. 1 , and the memory cell MC1 and the memory cell MC2 are the memory cells MC shown in FIG. 2 . ) can be inferred by referring to the related description, so the description is omitted here.

The sense amplifier 410 and the sense amplifier 420 may be a non-differential signal amplifier (single-ended signal amplifier) or any suitable type of amplifier. The sense amplifier 410 may sense and amplify the signal on the bit line BLa and output the amplified signal to the node SEN0 , and the sense amplifier 420 may detect the signal on the bit line BLb. and amplified, and the amplified signal can be output to the node (SEN1). When the sense amplifier 410 outputs the amplified signal corresponding to the signal on the bit line BLa to the node SEN0, the sense amplifier 420 sets the node SEN1 to the level of the reference voltage VSEN1 (eg For example, it can be set to 1.2 V). When the sense amplifier 420 outputs the amplified signal corresponding to the signal on the bit line BLb to the node SEN1 , the sense amplifier 410 sets the node SEN0 to the level of the reference voltage VSEN0 (eg, For example, it can be set to 1.2 V).

The sense amplifier 430 may be a differential signal amplifier. The sense amplifier 430 has a differential input pair and a differential output pair. A first input terminal of the differential input pair is connected to an output terminal of a sense amplifier 410 through a node SEN0, and a second input terminal of the differential input pair is connected to a sense amplifier 420 through a node SEN1. ) is connected to the output terminal of The differential output pair of the sense amplifier 430 provides the detection result for the bit line BLa and the bit line BLb to a next stage circuit (eg, an A/D converter). can A first output terminal of the differential output pair is connected to an input terminal of the sense amplifier 410 , and a second output terminal of the differential output pair is connected to an input terminal of the sense amplifier 420 . Accordingly, the sense amplifier 430 senses and amplifies the differential voltage between the node SEN0 and the node SEN1 , and outputs the amplified signal to the bit line BLa and the bit line BLb. can do.

In the above-described two-stage sense amplifier (sense amplifier device 400), a small signal on a bit line (bit line BLa or BLb) is amplified by a first stage sense amplifier (sense amplifier 410 or 420), The amplified signal is output to the second stage sense amplifier (sense amplifier 430). Accordingly, the intensity of the differential signal received by the sense amplifier 430 is greater than the intensity of the differential signal received by the sense amplifier (eg, the sense amplifier 150) shown in FIG. 1 . Thus, in spite of the reduction of the process, the embodiment shown in Fig. 4 can realize a sufficient sense signal margin. Accordingly, the sense amplifier device 400 has immunity to mismatch. Also, exact bit-line capacitance match is not required. Accordingly, in the edge sub-array (eg, the sub-array 110 or 140 shown in FIG. 1 ), the sense amplifier device 400 may be disposed on both sides, and the memory cells of the edge sub-array can be used

5 is a circuit schematic diagram of a sense amplifier 500 according to an embodiment of the present invention. The sense amplifier 500 is suitable for the sense amplifiers 410 and 420 of FIG. 4 . The reference voltage VSEN illustrated in FIG. 5 may be compared with the reference voltage VSEN0 or the reference voltage VSEN1 illustrated in FIG. 4 . The bit line BL shown in FIG. 5 can be compared with the bit line BLa and the bit line BLb shown in FIG. 4 . The node SEN shown in FIG. 5 may be compared with the node SEN0 or the node SEN1 shown in FIG. 4 . The reference voltage VSEN, the control signal SENC, and the control signal BLC shown in FIG. 5 can be provided by other devices (not shown, for example, a controller, a reference voltage generating circuit, etc.). have.

The sense amplifier 500 shown in FIG. 5 includes a transistor 510 and a transistor 520 . In the embodiment of FIG. 5 , transistor 510 includes a p-channel metal oxide semiconductor (PMOS) transistor or other transistor, and transistor 520 includes an n-channel metal oxide semiconductor (NMOS) transistor or other transistor. including transistors. A first terminal (eg, a source) of the transistor 510 is connected to the reference voltage VSEN. A second terminal (eg, drain) of the transistor 510 is connected to an output terminal of the sense amplifier 500 , and outputs an amplified signal (eg, a reference voltage VSEN) to the node SEN. do. The control terminal (eg, gate) of the transistor 510 is controlled by the control signal SENC. A first terminal (eg, a source) of the transistor 520 is connected to an input terminal of the sense amplifier 500 and receives a data signal of the bit line BL. A second terminal (eg, drain) of the transistor 520 is connected to a second terminal of the transistor 510 . A control terminal (eg, a gate) of the transistor 520 is controlled by a control signal BLC.

Fig. 6 is a sequence schematic diagram illustrating the signal shown in Fig. 5 according to one embodiment of the present invention. The horizontal axis in FIG. 6 represents time, and the vertical axis represents the signal level. 6 shows a control signal on the word line WL. A period in which the control signal on the word line WL is at a high logic level is referred to as a word line enable period WLE. When the control signal on the word line WL is at a high logic level, one corresponding memory cell of the plurality of memory cells connected to the bit line BL is selected, and the selected corresponding memory cell transfers data to the bit line output to (BL).

Please refer to FIGS. 5 and 6 . In the bit line pre-charge period PC, the control signal SENC turns on the transistor 510 and the control signal BLC drives the transistor 520 , so that the bit line ( BL) is pre-charged. The control signal BLC may drive the transistor 520 to set the level of the bit line BL to an appropriate precharge level (eg, 0.5 V).

Subsequently, before the initialization period 601 of the word line enable period WLE, the control signal SENC conducts the transistor 510 , and the control signal BLC cuts the transistor 520 . (turn off) The transistor 510 may set the level of the node SEN to the precharge level (the reference voltage VSEN) in the initialization period 601 . After the transistor 520 is cut off, in the initialization period 601 of the word line enable period WLE, since the word line WL turns on the memory cell to be read, the memory cell to be read is Data may be output on the precharged bit line BL. In the situation where the data is "1", the level of the bit line BL becomes higher than the pre-charge level. In the situation where the data is "0", the level of the bit line BL becomes lower than the pre-charge level.

When the initialization period 601 ends, the control signal SENC cuts off the transistor 510 . In the sensing period 602 of the word line enable period WLE after the initialization period 601 , the control signal SENC cuts off the transistor 510 , and the control signal BLC turns off the transistor 520 . ) to sense the bit line BL. In the sensing period 602, and also in a situation where the data of the bit line BL is in the first logic state (for example, "1"), since the transistor 520 is cut off, the node SEN is set to the precharge level ( For example, it can be stored at 1.2 V). In the sensing period 602 , and in a situation where the data of the bit line BL is in the second logic state (eg, “0”), the transistor 520 is turned on. Since the capacitance of the node SEN is smaller than the capacitance of the bit line BL, the node SEN is discharged until it approaches the level of the bit line BL.

7 is a circuit schematic diagram of a sense amplifier 700 according to another embodiment of the present invention. The sense amplifier 700 is suitable for the sense amplifiers 410 and 420 of FIG. 4 . The reference voltage VSEN illustrated in FIG. 7 may be compared with the reference voltage VSEN0 or the reference voltage VSEN1 illustrated in FIG. 4 . The bit line BL shown in FIG. 7 can be compared with the bit line BLa and the bit line BLb shown in FIG. 4 . The node SEN shown in FIG. 7 may be compared with the node SEN0 or the node SEN1 shown in FIG. 4 . The reference voltage VSEN, the control signal SENC, the control signal PBLCS, the reference voltage VREF_BLC, and the control signal NBLCS shown in FIG. 7 are other devices (not shown, for example, a controller). , a reference voltage generating circuit, etc.). The reference voltage VREF_BLC may be a fixed voltage according to design requirements.

The sense amplifier 700 shown in FIG. 7 includes a control circuit 710 , a transistor 720 , and a transistor 730 . The transistors 720 and 730 shown in FIG. 7 can be inferred with reference to the related descriptions of the transistors 510 and 520 shown in FIG. 5 , and thus descriptions thereof will be omitted. A first terminal (eg, a source) of the transistor 720 is connected to the reference voltage VSEN. A second terminal (eg, drain) of the transistor 720 is connected to an output terminal of the sense amplifier 700 , and outputs an amplified signal (eg, a reference voltage VSEN) to the node SEN do. A control terminal (eg, a gate) of the transistor 720 is controlled by the control signal SENC. A first terminal (eg, a source) of the transistor 730 is connected to an input terminal of the sense amplifier 700 and receives a data signal of the bit line BL. A second terminal (eg, drain) of the transistor 730 is connected to a second terminal of the transistor 720 . A control terminal (eg, a gate) of the transistor 730 is controlled by a control signal BLC.

The input terminal of the control circuit 710 is connected to the input terminal of the sense amplifier 700, and receives the data signal of the bit line BL. The control circuit 710 may generate a control signal BLC and supply it to the control terminal of the transistor 730 . The control circuit 710 can dynamically adjust the control signal BLC based on the level of the input terminal of the sense amplifier 700 (the level of the data signal of the bit line BL).

In the embodiment of FIG. 7 , the control circuit 710 includes a transistor 711 and a transistor 712 . In the embodiment of FIG. 7 , transistor 711 includes a PMOS transistor or other transistor, and transistor 712 includes an NMOS transistor or other transistor. A first terminal (eg, a source) of the transistor 711 receives the control signal PBLCS. A second terminal (eg, drain) of the transistor 711 is connected to the output terminal of the control circuit 710 , and generates a control signal BLC and supplies it to the control terminal of the transistor 730 . The control terminal (eg, gate) of the transistor 711 is controlled by the reference voltage VREF_BLC. A first terminal (eg, a source) of the transistor 712 receives the control signal NBLCS. A second terminal (eg, drain) of the transistor 712 is connected to a second terminal of the transistor 711 . A control terminal (eg, a gate) of the transistor 712 is connected to an input terminal of the control circuit 710 and receives a data signal of the bit line BL.

Fig. 8 is a sequence schematic diagram for explaining the signal shown in Fig. 7 according to one embodiment of the present invention. Please refer to FIGS. 7 and 8 . In the bit line precharge period PC, since the control signal PBLCS is pulled up, the transistor 711 is turned on to pull up the control signal BLC. In the bit line pre-charge period PC, the control signal SENC turns on the transistor 720 , and the control signal BLC drives the transistor 730 , thereby pre-charging the bit line BL. Carry out the charge. The transistor 730 may set the level of the bit line BL to an appropriate pre-charge level (eg, 0.5 V). Since this precharge level of the bit line BL is fed back to the control terminal of the transistor 712 , the transistor 712 dynamically adjusts the level of the control signal BLC based on the level of the bit line BL. can be adjusted with

When the bit line precharge period PC ends, the control signal PBLCS is pulled down, so the transistor 711 is cut off, and the control signal BLC is pulled down by the transistor 712 . Subsequently, in the initialization period 801 of the word line enable period WLE, the control signal SENC turns on the transistor 720 , and the control signal BLC turns off the transistor 730 . . The transistor 720 may set the level of the node SEN to the precharge level (the reference voltage VSEN) in the initialization period 801 . After the transistor 730 is cut off, the word line WL may turn on a memory cell to be read and output data on the precharged bit line BL.

When the initialization period 801 ends, the control signal SENC cuts off the transistor 720 . In the sensing period 802 of the word line enable period WLE, since the control signal PBLCS is pulled up again, the transistor 711 conducts and the control signal BLC is pulled up. In the sensing period 802 , the control signal SENC cuts the transistor 720 , and the control signal BLC drives the transistor 730 to sense the bit line BL. In the sensing period 802 , and also in a situation where the data of the bit line BL is in the first logic state (eg, “1”), since the transistor 730 is cut off, the node SEN is set to the precharge level ( For example, it can be stored at 1.2 V). In the sensing period 802 , and also in a situation where the data of the bit line BL is in the second logic state (eg, “0”), since the transistor 730 is turned on, the node SEN is connected to the bit line ( BL) is discharged until it approaches the level. Since the level of the bit line BL (the level of the data voltage) is fed back to the control terminal of the transistor 712 , the transistor 712 controls the level of the control signal BLC based on the level of the bit line BL. Levels can be adjusted dynamically.

In the bit line precharge period PC and the sensing period 802 , the control circuit 710 may dynamically control the control signal BLC based on the level of the bit line BL. Accordingly, the sense amplifier 700 can realize high-speed bit line pre-charging and sensing.

9 is a circuit schematic diagram of a voltage generator circuit according to still another embodiment of the present invention. The supply voltage VP, the bias voltage VBLP, and the reference voltage VSS shown in FIG. 9 may be provided by other devices (not shown, for example, a controller, a reference voltage generating circuit, etc.). have. The bias voltage VBLP may be a bit line precharge level target (eg, 0.5 V). The voltage generator circuit shown in Fig. 9 can supply a voltage to the control circuit 710, and all sense amplifiers share the voltage generator circuit. In the voltage generator shown in Fig. 9, the level of the supply voltage VP is equal to the high logic level of the control signal PBLCS, and the level of the output voltage VN is equal to the low logic level of the control signal NBLCS. The bias voltage VBLP can control the level of the reference voltage VREF_BLC and the level of the output voltage VN, and the bit line precharge level becomes equal to the level of the bias voltage VBLP.

A first terminal (eg, source) of the transistor 913 receives the supply voltage VP. A second terminal (eg, drain) of the transistor 913 is connected to a control terminal (eg, gate) of the transistor 913 and provides a reference voltage VREF_BLC. A first terminal (eg, drain) of the transistor 914 is connected to a second terminal of the transistor 913 . A second terminal (eg, source) of the transistor 914 is connected to a current source IBLC and provides an output voltage VN. A control terminal (eg, a gate) of the transistor 914 receives a bias voltage VBLP. The current source IBLC is further connected to the reference voltage VSS. The current source IBLC may control current consumption in the control circuit 710 of the sense amplifier.

Fig. 10 is a circuit schematic diagram for explaining the sense amplifiers 410 to 430 shown in Fig. 4 according to still another embodiment of the present invention. The sense amplifier 410 , the sense amplifier 420 , and the sense amplifier 430 shown in FIG. 4 can be inferred with reference to the related description of FIG. 10 . The reference voltages VSEN0 to VSEN1, the control signals SENC0 to SENC1, the control signals BLC0 to BLC1, the voltage PCS, the voltage NCS, and the control signal EQ shown in Fig. 10 are other devices. (not shown, for example, a controller, a reference voltage generating circuit, etc.) may provide.

The sense amplifier 410 shown in FIG. 10 includes transistors 411 to 412 . A first terminal (eg, a source) of the transistor 411 is connected to the reference voltage VSEN0. A second terminal (eg, drain) of the transistor 411 is connected to an output terminal of the sense amplifier 410 and outputs an amplified signal (eg, the reference voltage VSEN0) to the node SEN0 do. The control terminal (eg, gate) of the transistor 411 is controlled by the control signal SENC0. A first terminal (eg, a source) of the transistor 412 is connected to the input terminal of the sense amplifier 410 and receives the data signal of the bit line BLa. A second terminal (eg, drain) of the transistor 412 is connected to a second terminal of the transistor 411 . The control terminal (eg, gate) of the transistor 412 is controlled by the control signal BLC0. The sense amplifier 410 , the transistor 411 , and the transistor 412 shown in FIG. 10 refer to the related description of the sense amplifier 500 , the transistor 510 , and the transistor 520 shown in FIG. 5 . Since it can be inferred, the description is omitted here.

The sense amplifier 420 shown in FIG. 10 includes a transistor 421 and a transistor 422 . A first terminal (eg, a source) of the transistor 421 is connected to the reference voltage VSEN1 . The second terminal (eg, drain) of the transistor 421 is connected to the output terminal of the sense amplifier 420 , and outputs an amplified signal (eg, the reference voltage VSEN1 ) to the node SEN1 . do. The control terminal (eg, gate) of the transistor 421 is controlled by the control signal SENC1 . A first terminal (eg, a source) of the transistor 422 is connected to an input terminal of the sense amplifier 420 , and receives a data signal of the bit line BLb. A second terminal (eg, drain) of the transistor 422 is connected to a second terminal of the transistor 421 . The control terminal (eg, gate) of the transistor 422 is controlled by the control signal BLC1 . The sense amplifier 420 , the transistor 421 , and the transistor 422 shown in FIG. 10 refer to the related description of the sense amplifier 500 , the transistor 510 , and the transistor 520 shown in FIG. 5 . Since it can be inferred, the description is omitted here.

The sense amplifier 430 shown in FIG. 10 includes transistors 431 to 435. A first terminal and a second terminal (eg, a source and a drain) of the transistor 435 are connected to a bit line BLa and a bit line BLb, respectively. The control terminal (eg, gate) of the transistor 435 is controlled by the control signal EQ.

A first terminal (eg, source) of the transistor 431 and a first terminal (eg, source) of the transistor 432 are connected to the voltage PCS. The level of the voltage PCS can be determined based on design requirements. A second terminal (eg, a drain) of the transistor 431 and a control terminal (eg, a gate) of the transistor 432 are connected to a first output terminal of the sense amplifier 430 . The above-described first output terminal of the sense amplifier 430 may feed back the amplified signal to the input terminal of the sense amplifier 410 . A control terminal (eg, a gate) of the transistor 431 and a second terminal (eg, a drain) of the transistor 432 are connected to a second output terminal of the sense amplifier 430 . The above-described second output terminal of the sense amplifier 430 may feed back the amplified signal to the input terminal of the sense amplifier 420 .

A first terminal (eg, source) of the transistor 433 and a first terminal (eg, source) of the transistor 434 are connected to a voltage NCS. The level of the voltage NCS can be determined based on a design requirement. A second terminal (eg, drain) of the transistor 433 is connected to a first output terminal of the sense amplifier 430 . The above-described first output terminal of the sense amplifier 430 may feed back the amplified signal to the input terminal of the sense amplifier 410 . A control terminal (eg, gate) of the transistor 433 is connected to a second output terminal of the sense amplifier 430 , and receives an amplified signal (or reference voltage VSEN1 ) from the node SEN1 . A second terminal (eg, drain) of the transistor 434 is connected to a second output terminal of the sense amplifier 430 . The above-described second output terminal of the sense amplifier 430 may feed back the amplified signal to the input terminal of the sense amplifier 420 . A control terminal (eg, gate) of the transistor 434 is connected to a first input terminal of the sense amplifier 430 , and receives an amplified signal (or reference voltage VSEN0 ) from the node SEN0 .

Fig. 11 is a sequence schematic diagram for explaining the signal shown in Fig. 10 according to an embodiment of the present invention. In FIG. 11 , the dotted line waveform represents signals having a subscript '0' (eg, SENC0, VSEN0, BLC0, and SEN0). Waveforms of solid lines indicate signals having a subscript '1' (eg, SENC1, VSEN1, BLC1, and SEN1). Please refer to FIGS. 10 and 11 . In the bit line precharge period PC, the voltage PCS and the voltage NCS are pulled up (eg, pulled up from 0.3 V to 0.5 V), and the reference voltage VSEN0 is at a high level (eg, pulled up from 0.3 V to 0.5 V). For example, 1.3 V), the reference voltage VSEN1 becomes a low level (eg 0.5 V), and both the control signal SENC0 and the control signal SENC1 are at a low level (eg, 0.5 V). , 0 V), the control signal BLC0 becomes high level, and the control signal BLC1 becomes low level. Accordingly, in the bit line precharge period PC, the transistor 412 can precharge the bit line BL0 (for example, precharge from 0.3 V to 0.5 V), and the transistor 412 411 may set node SEN0 to the level of reference voltage VSEN0 (eg, 1.3 V), and transistor 421 may set node SEN1 to the level of reference voltage VSEN1 (eg, 1.3 V). For example, it can be set to 0.5 V).

When the bit line precharge period PC ends, the control signal BLC0 is pulled down, so that the transistor 412 is cut off. After the transistors 412 and 422 are cut off, the word line WL turns on the memory cell to be read, so that the memory cell to be read can output data on the precharged bit line BLa. . Subsequently, in the initialization period 1101 of the word line enable period WLE, the control signals SENC0 and SENC1 turn on the transistors 411 and 421, and the control signals BLC0 and BLC1 transmit the transistors 412 and 422 ) is cut. The transistors 411 and 421 may set the levels of the nodes SEN0 and SEN1 to the levels of the reference voltages VSEN0 and VSEN1 in the initialization period 1101 .

When the initialization period 1101 ends, the control signal BLC0 is pulled up (eg, pulled up from 0 V to 1.3 V), and the transistor 411 is cut off. In the sensing period 1102 of the word line enable period WLE, the control signal SENC0 goes to a high level (eg, 1.3 V), and the control signal SENC1 goes to a low level (eg, 0 V). ), when the sense amplifier 410 outputs the amplified signal corresponding to the signal on the bit line BLa to the node SEN0, the transistor 421 converts the node SEN1 to the reference voltage VSEN1. can be set to a level of (eg, 0.5 V). In the sensing period 1102, the control signal BLC0 is pulled up again, and since the control signal BLC1 maintains a low level, the transistor 422 is cut off and the transistor 412 connects the bit line BLa. can detect In a period in which the sense amplifier 410 senses the bit line BLa, the node SEN1 turns on the transistor 421 and the control signal BLC1 cuts the transistor 422 .

Fig. 12 is a circuit schematic diagram for explaining the sense amplifiers 410 to 430 shown in Fig. 4 according to still another embodiment of the present invention. The sense amplifier 430 and transistors 431 to 435 shown in FIG. 12 can be inferred with reference to the related description in FIG. 10, and thus descriptions are omitted here. The reference voltages VSEN0 to VSEN1, the control signals SENC0 to SENC1, the control signals PBLCS0 to PBLCS1, the reference voltage VREF_BLC, the control signals NBLCS0 to NBLCS1, the voltage PCS, and the voltage ( NCS) and the control signal EQ can be provided by other devices (not shown, for example, a controller, a reference voltage generating circuit, etc.).

The sense amplifier 410 shown in FIG. 12 includes transistors 411 to 414 . A first terminal (eg, a source) of the transistor 411 is connected to the reference voltage VSEN0. A second terminal (eg, drain) of the transistor 411 is connected to an output terminal of the sense amplifier 410 and outputs an amplified signal (eg, the reference voltage VSEN0) to the node SEN0 do. The control terminal (eg, gate) of the transistor 411 is controlled by the control signal SENC0. A first terminal (eg, a source) of the transistor 412 is connected to the input terminal of the sense amplifier 410 and receives the data signal of the bit line BLa. A second terminal (eg, drain) of the transistor 412 is connected to a second terminal of the transistor 411 . The control terminal (eg, gate) of the transistor 412 is controlled by the control signal BLC0. A first terminal (eg, a source) of the transistor 413 receives the control signal PBLCS0. A second terminal (eg, drain) of the transistor 413 is connected to a control terminal of the transistor 412 and provides a control signal BLC0 . The control terminal (eg, gate) of the transistor 413 is controlled by the reference voltage VREF_BLC. A first terminal (eg, source) of the transistor 414 receives the control signal NBLCS0. A second terminal (eg, drain) of the transistor 414 is connected to a second terminal of the transistor 413 . A control terminal (eg, a gate) of the transistor 414 is connected to the bit line BLa. The sense amplifier 410 and transistors 411 to 414 shown in FIG. 12 are the sense amplifier 700, transistor 720, transistor 730, transistor 711, and transistor 712 shown in FIG. Since it can be inferred by referring to the related description of , the description is omitted here.

The sense amplifier 420 shown in FIG. 12 includes transistors 421 to 424. A first terminal (eg, a source) of the transistor 421 is connected to the reference voltage VSEN1 . The second terminal (eg, drain) of the transistor 421 is connected to the output terminal of the sense amplifier 420 , and outputs an amplified signal (eg, the reference voltage VSEN1 ) to the node SEN1 . do. The control terminal (eg, gate) of the transistor 421 is controlled by the control signal SENC1 . A first terminal (eg, a source) of the transistor 422 is connected to an input terminal of the sense amplifier 420 , and receives a data signal of the bit line BLb. A second terminal (eg, drain) of the transistor 422 is connected to a second terminal of the transistor 421 . The control terminal (eg, gate) of the transistor 422 is controlled by the control signal BLC1 . A first terminal (eg, a source) of the transistor 423 receives the control signal PBLCS1 . A second terminal (eg, drain) of the transistor 423 is connected to a control terminal of the transistor 422 and provides a control signal BLC1 . The control terminal (eg, gate) of the transistor 423 is controlled by the reference voltage VREF_BLC. A first terminal (eg, source) of the transistor 424 receives the control signal NBLCS1 . A second terminal (eg, drain) of the transistor 424 is connected to a second terminal of the transistor 423 . A control terminal (eg, a gate) of the transistor 424 is connected to the bit line BLb. The sense amplifier 420 and transistors 421 to 424 shown in FIG. 12 are the sense amplifier 700, transistor 720, transistor 730, transistor 711, and transistor 712 shown in FIG. Since it can be inferred by referring to the related description of , the description is omitted here.

Fig. 13 is a sequence schematic diagram for explaining the signal shown in Fig. 12 according to an embodiment of the present invention. In FIG. 13 , the dotted line waveform represents signals having a subscript '0' (eg, SENC0, VSEN0, PBLCS0, BLC0, and SEN0). Waveforms of solid lines indicate signals having a subscript '1' (eg, SENC1, VSEN1, PBLCS1, BLC1, and SEN1). Please refer to FIGS. 12 and 13 . In the bit line precharge period PC, the voltage PCS and the voltage NCS are pulled up (for example, from 0.3 V to 0.5 V), and the reference voltage VSEN0 is at a high level (for example, 1.3 V), the reference voltage VSEN1 becomes a low level (eg, 0.5 V), and the control signal SENC0 and the control signal SENC1 both become a low level (eg, 0 V). , the control signal PBLCS0 goes to a high level (eg 1.3 V), the control signal PBLCS1 goes to a low level (eg 0 V), and the control signals NBLCS0 and NBLCS1 are both low level becomes this Therefore, in the bit line precharge period PC, since the control signal BLC0 is pulled up, the transistor 412 can precharge the bit line BL0 (for example, at 0.3 V). precharge to 0.5 V), the control signal BLC maintains a low level (eg, 0 V), so that the transistor 422 can be disconnected. In the bit line precharge period PC, the transistor 411 may set the node SEN0 to the level of the reference voltage VSEN0 (eg, 1.3 V), and the transistor 421 may ) may be set to the level of the reference voltage VSEN1 (eg, 0.5 V).

When the bit line precharge period PC ends, the control signal BLC0 is pulled down, so that the transistor 412 is cut off. After the transistors 412 and 422 are cut off, the word line WL turns on the memory cell to be read, so that the memory cell to be read can output data on the precharged bit line BLa. . Subsequently, in the initialization period 1301 of the word line enable period WLE, the control signals SENC0 and SENC1 turn on the transistors 411 and 421, and the control signals BLC0 and BLC1 turn on the transistors 412 and 422 ) is cut. The transistors 411 and 421 may set the levels of the nodes SEN0 and SEN1 to the levels of the reference voltages VSEN0 and VSEN1 in the initialization period 1301 .

When the initialization period 1301 ends, the control signal SENC0 is pulled up (eg, pulled up from 0 V to 1.3 V), and the transistor 411 is cut off. In the sensing period 1302 of the word line enable period WLE, the control signal SENC0 goes to a high level (eg, 1.3 V), and the control signal SENC1 goes to a low level (eg, 0 V). ), when the sense amplifier 410 outputs the amplified signal corresponding to the signal on the bit line BLa to the node SEN0, the transistor 421 converts the node SEN1 to the reference voltage VSEN1. can be set to a level of (eg, 0.5 V). In the sensing period 1302, since the control signal BLC0 is pulled up again and the control signal BLC1 remains at a low level, the transistor 422 is cut off and the transistor 412 senses the bit line BLa. can do. In a period in which the sense amplifier 410 senses the bit line BLa, the node SEN1 turns on the transistor 421 and the control signal BLC1 cuts the transistor 422 .

As described above, the above-described embodiment discloses a two-stage sense amplifier (sense amplifier device 400). In the sense amplifier device 400, after a small signal (data signal) of the bit line BLa or BLb is amplified by a first stage sense amplifier (sense amplifier 410 or 420), the amplified signal is converted into a second stage sense amplifier output to an amplifier (sense amplifier 430). The sense amplifier 430 receives the amplified differential signal (the amplified signal and the reference voltage provided by the sense amplifier 410 and the sense amplifier 420), and performs a second stage amplification operation on the amplified differential signal. can be carried out. Accordingly, the sense amplifier device 400 may sense (read) data of the bit line BLa and/or the bit line BLb. The intensity of the differential signal received by the sense amplifier 430 is greater than the intensity of the differential signal received by the sense amplifier (eg, the sense amplifier 150) shown in FIG. 1 . Although the manufacturing process is reduced, the sense amplifier device 400 can realize a sufficient sense signal margin. Accordingly, the sense amplifier device 400 does not require accurate bit-line capacitance match. In an edge sub-array (for example, the sub-array 110 or 140 shown in FIG. 1 ), the sense amplifier device 400 may be disposed on both sides, and memory cells of the edge sub-array may be used. can

As mentioned above, although this invention was disclosed by embodiment, of course, it is not for limiting this invention, In order that those skilled in the art may understand easily, within the scope of the technical idea of this invention, appropriate change and correction are naturally made. Therefore, the scope of patent protection should be determined based on the scope of the claims and their equivalents.

100: DRAM
110, 120, 130, 140: sub-array
150, 410, 420, 430, 500, 700: sense amplifier
400: sense amplifier unit
411, 412, 413, 414, 421, 422, 423, 424, 431, 432, 433, 434, 435, 510, 520, 711, 712, 720, 730, 913, 914: Transistors
601, 801, 1101, 1301: Initialization period
602, 802, 1102, 1302: detection period
710: control circuit
BL, BL0, BL1, BLa, BLb: bit line
BLC, BLC0, BLC1, CSP, CSN, EQ, NBLCS, NBLCS0, NBLCS1, PBLCS, PBLCS0, PBLCS1, SENC, SENC0, SENC1: control signal
C _BL : condenser
C _SN : memory element
IBLC: Current Source
MC, MC1, MC2: memory cells
NCS, PCS: Voltage
PC: bit line precharge period
SEN, SEN0, SEN1: node
SN: data
SW: switch
VBLP: bias voltage
VN: output voltage
VP: supply voltage
VREF_BLC, VSEN, VSEN0, VSEN1, VSS: reference voltage
WL: word line
WLE: Wordsun Enable Period

Claims (11)

a first sense amplifier having an input terminal connected to the first bit line;
a second sense amplifier having an input terminal connected to a second bit line;
It has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is connected to an output terminal of the first sense amplifier, and a second input terminal of the differential input pair includes a second input terminal of the second sense amplifier. connected to an output terminal, a first output terminal of the differential output pair connected to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair connected to the input terminal of the second sense amplifier 3rd sense amplifier connected to
A sense amplifier device comprising a. According to claim 1,
each of the first sense amplifier and the second sense amplifier is a non-differential signal amplifier;
wherein the third sense amplifier is a differential signal amplifier
Sense amp unit. According to claim 1,
The first sense amplifier,
a first transistor having a first terminal connected to a first reference voltage, a second terminal connected to the output terminal of the first sense amplifier, and a control terminal controlled by a first control signal;
a second transistor having a first terminal connected to the input terminal of the first sense amplifier, a second terminal connected to the second terminal of the first transistor, and a control terminal controlled by a second control signal
A sense amplifier device comprising a. 4. The method of claim 3,
The first transistor includes a PMOS transistor,
wherein the second transistor includes an NMOS transistor
Sense amp unit. 4. The method of claim 3,
In the bit line precharge period before the word line enable period, the first control signal turns on the first transistor, and the second control signal drives the second transistor, Precharge the bit line,
In an initialization period of the word line enable period, the first control signal turns on the first transistor, and the second control signal turns off the second transistor;
In a sensing period of the word line enable period after the initialization period, the first control signal cuts off the first transistor, the second control signal drives the second transistor, detecting the first bit line
Sense amp unit. 6. The method of claim 5,
In the sensing period, and in a situation where the data of the first bit line is in a first logic state, the second transistor is cut off;
In the sensing period, and in a situation where the data of the first bit line is in the second logic state, the second transistor is turned on
Sense amp unit. 4. The method of claim 3,
In a period in which the second sense amplifier senses the second bit line,
the first control signal turns on the first transistor, and the second control signal cuts off the second transistor
Sense amp unit. 4. The method of claim 3,
The first sense amplifier,
an input terminal connected to the input terminal of the first sense amplifier and used to generate and supply the second control signal to the control terminal of the second transistor, the input terminal of the first sense amplifier a control circuit that dynamically adjusts the second control signal based on a level
A sense amplifier device further comprising a. 9. The method of claim 8,
the control circuit,
a first terminal receives a third control signal, a second terminal is connected to an output terminal of the control circuit, generates and supplies the second control signal to the control terminal of the second transistor; a third transistor whose terminal is controlled at a second reference voltage;
a fourth transistor having a first terminal receiving a fourth control signal, a second terminal connected to the second terminal of the third transistor, and a control terminal connected to the input terminal of the control circuit
A sense amplifier device comprising a. 10. The method of claim 9,
The third transistor includes a PMOS transistor,
The fourth transistor is an NMOS transistor
A sense amplifier device comprising a. According to claim 1,
The third sense amplifier,
a first terminal connected to a first voltage, a second terminal connected to the first output terminal of the third sense amplifier, and a control terminal connected to the second output terminal of the third sense amplifier; a first transistor;
a first terminal connected to the first voltage, a second terminal connected to the second output terminal of the third sense amplifier, and a control terminal connected to the first output terminal of the third sense amplifier a second transistor,
a first terminal connected to a second voltage, a second terminal connected to the first output terminal of the third sense amplifier, and a control terminal connected to the second input terminal of the third sense amplifier; a third transistor;
a first terminal connected to the second voltage, a second terminal connected to the second output terminal of the third sense amplifier, and a control terminal connected to the first input terminal of the third sense amplifier 4th transistor
A sense amplifier device comprising a.

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