KR20210149364A - Vertical memory devices - Google Patents

Abstract

A vertical memory device includes a substrate including a cell region and a cell wiring region disposed in a first direction, and including first and second blocks disposed adjacent to each other in a second direction perpendicular to the first direction. A first stacked structure is provided on the substrate in the cell region and the cell wiring region within the first block, has a gate electrode and an insulating pattern alternately and repeatedly disposed thereon, and includes a pad portion having a step shape in the cell wiring region. A second stacked structure is provided on the substrate in the cell region and the cell wiring region within the second block, has a gate electrode and an insulating pattern alternately and repeatedly disposed thereon, and includes a dummy pad portion in the cell wiring region. A first interlayer insulating layer covering the first and second stacked structures is provided. Cell contact plugs passing through the first interlayer insulating layer and contacting the pad portion of the first stacked structure in the cell wiring region are provided. Dummy contact plugs passing through the first interlayer insulating layer and contacting the dummy pad portion of the second stacked structure in the cell wiring region are included. The cell contact plugs are arranged to have a first arrangement density in the pad portion, and the dummy contact plugs are arranged to have a second arrangement density lower than the first arrangement density in the dummy pad portion. According to the present invention, electrical failure is reduced.

Description

Vertical memory device {VERTICAL MEMORY DEVICES}

The present invention relates to a vertical memory device. More particularly, it relates to wiring of a vertical type memory device.

Recently, a vertical type memory device in which memory cells are vertically arranged has been developed. As the number of stacked memory cells in the vertical direction increases, the number of contact plugs connected to word lines of the memory cells and upper wirings formed on the contact plugs may be greatly increased. Accordingly, since the distance between the contact plugs is narrow, a defect in which the contact plug and the upper wirings adjacent thereto are bridged may occur.

An object of the present invention is to provide a vertical memory device in which electrical failure is reduced.

In order to achieve the object of the present invention, a vertical memory device according to embodiments of the present invention includes a cell region and a cell wiring region arranged in a first direction, and a second direction perpendicular to the first direction. A substrate including first and second blocks disposed adjacent to each other is provided. In the first block, a first stacked structure is provided on the substrate of the cell region and the cell wiring region, the gate electrode and the insulating pattern are alternately and repeatedly disposed, and the cell wiring region includes a pad portion having a step shape. provided In the second block, a second stacked structure is provided on the substrate of the cell region and the cell wiring region, and the gate electrode and the insulating pattern are alternately and repeatedly disposed, and the cell wiring region includes a dummy pad portion. A first interlayer insulating layer covering the first and second stacked structures is provided. Cell contact plugs passing through the first interlayer insulating layer and contacting a pad portion of the first stacked structure in the cell wiring region are provided. and dummy contact plugs passing through the first interlayer insulating layer and contacting a dummy pad portion of the second stacked structure in the cell wiring region. The cell contact plugs are arranged to have a first arrangement density in the pad area, and the dummy contact plugs are arranged to have a second arrangement density lower than the first arrangement density in the dummy pad area.

In the vertical memory device, since the dummy contact plugs have a second arrangement density lower than the first arrangement density of the cell contact plugs, a greater number of wirings may be easily disposed between the dummy contact plugs. have.

1 to 3 are plan views and cross-sectional views illustrating vertical memory devices according to example embodiments.
4 is a perspective view illustrating a wiring stack structure.
5 to 7 are plan views each illustrating vertical memory devices according to example embodiments.
8 to 20 are cross-sectional views and plan views illustrating a method of manufacturing a vertical memory device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, a direction substantially perpendicular to the upper surface of the substrate is defined as a vertical direction, and two directions perpendicular to each other among horizontal directions substantially parallel to the upper surface of the substrate are defined as first and second directions, respectively.

1 to 3 are plan views and cross-sectional views illustrating vertical memory devices according to example embodiments. 4 is a perspective view illustrating a wiring stack structure.

FIG. 2 is a cross-sectional view taken along line II' of FIG. 1 , and FIG. 3 is a cross-sectional view taken along line II-II' of FIG. 1 . That is, FIG. 2 is a cross-sectional view of a cell contact plug, and FIG. 3 is a cross-sectional view of a dummy contact plug. 4 illustrates a step shape of the wiring stack structure, and the stacked structure of the gate electrode and the insulating pattern included in the wiring stack structure is not shown in order to simplify the drawing.

1 to 4 , the vertical memory device includes stacked structures 144 , a channel structure 128 , a cell contact plug 148 , a dummy contact plug 150 formed on a substrate 100 , and A first connection line 162 may be included. In FIG. 1 , the first connection line 162 is simply illustrated as a single line. Also, in FIG. 1 , only a part of the first connection line is shown.

The substrate 100 may include a semiconductor material such as silicon, germanium, silicon-germanium, or a group III-V compound such as GaP, GaAs, and GaSb. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

In some exemplary embodiments, although not shown, the vertical memory device may have a COP structure in which memory cells are vertically disposed on a peripheral circuit. In this case, circuit patterns constituting a peripheral circuit for driving a memory cell, a lower interlayer insulating layer covering the circuit patterns, and a base semiconductor pattern may be further provided on the substrate 100 .

The substrate 100 may include a cell region A and a cell wiring region B, and the stacked structure 144 is disposed on the substrate 100 in the cell region A and the cell wiring region B. This may be provided. The cell region and the cell wiring region may be adjacent to each other in the first direction. The stacked structure 144 may have a shape extending in the first direction. In an exemplary embodiment, a plurality of stacked structures 144 may be disposed side by side in the second direction, and between the stacked structures 144 and in a portion within the stacked structures 144 in the vertical direction. An opening 130 extending to the surface of the substrate 100 and extending in the first direction may be disposed. The opening 130 may be a word line cutting area or a block cutting area. That is, the substrate may include each block, and a stacked structure may be provided on each of the blocks. Each of the blocks may be disposed while being spaced apart from each other in a second direction perpendicular to the first direction.

The stacked structure 144 may include a cell stacked structure 140 formed on the cell region A and a wiring stacked structure 142 formed on the cell interconnection B. The cell stacked structure 140 and the wire stacked structure 142 may be connected to each other to have one body. The wiring stack structure 142 may include pads for disposing wires respectively connected to the gate electrodes included in the cell stack structure 140 .

The cell stack structure 140 may include a plurality of gate electrodes 132 spaced apart in a vertical direction, and insulating patterns 102 formed between the gate electrodes 132 . That is, the gate electrode 132 and the insulating pattern 102 may be alternately and repeatedly disposed on the substrate 100 in the vertical direction. The gate electrodes 132 may extend in the first direction to serve as word lines of memory cells.

The gate electrode 132 may include a metal material. The gate electrode 132 may include a barrier pattern and a metal pattern.

A first interlayer insulating layer 112 covering the stacked structures 144 may be provided on the substrate 100 . An upper surface of the first interlayer insulating layer 112 may be substantially flat.

The cell stack structure 140 may include a channel structure 128 penetrating the gate electrodes 132 and the insulating pattern 102 . The channel structure 128 may include a charge storage structure 120 , a channel 122 , a buried insulating pattern 124 , and a capping pattern 126 . Although not shown, the charge storage structure 120 may include a first blocking pattern, a charge storage pattern, and a tunnel insulation pattern sequentially stacked.

In an exemplary embodiment, a semiconductor pattern 118 may be further provided between the bottom surface of the channel structure 128 and the top surface of the substrate 100 . The semiconductor pattern 118 may be electrically connected to the channel 122 .

The wiring stack structure 142 may have a structure in which the gate electrodes 132 and the insulating pattern 102 included in the cell stack structure 140 extend to the cell wiring region B.

The partial wiring stack structure 142 may be a first pad structure 142a including the gate electrode 132 included in the cell stack structure 140 and a pad for electrically connecting wires to each other. The first pad structure 142a may be formed in the pad area C. As shown in FIG. The partial wiring stack structure 142 may be a second pad structure 142b including a gate electrode 132 included in the cell stack structure 140 and a dummy pad not electrically connecting wires to each other. The second pad structure 142b may be formed in the pad region C. As shown in FIG.

In an exemplary embodiment, the first pad structure 142a including a pad may be provided in a first block of the substrate 100, and in a second block adjacent to the first block in the second direction, The second pad structure 142b including a dummy pad may be provided. For example, when the first to fourth blocks sequentially arranged in the second direction are disposed, a first pad structure 142a, a second pad structure 142b, a second pad structure 142b, and a first pad The structures 142a may be sequentially disposed. Accordingly, the pad structures may have a symmetrical shape with respect to the opening between the second and third blocks.

The stacked structure including the first pad structure 142a may be referred to as a first stacked structure, and the stacked structure including the second pad structure 142b may be referred to as a second stacked structure.

In the first pad structure 142a , upper surfaces of edge portions of the gate electrodes 132 included in the cell stack structure 140 in the first direction are located on different planes (ie, vertical levels). can Accordingly, an edge portion of the first pad structure 142a in the first direction may have a step shape. In an exemplary embodiment, the first pad structure 142a may include steps in the first direction and the second direction, respectively. For example, as shown in FIG. 4 , a staircase of the fourth floor may be formed in the second direction. An upper surface of each of the steps may be provided as a pad on which wirings are formed. In an exemplary embodiment, each of the pads may be regularly disposed so that the cell contact plugs 148 may be regularly disposed on the pads with uniform spacing.

The second pad structure 142b may serve as a dummy pad to which an electrical signal is not substantially applied. Accordingly, the shape of the edge of the second pad structure 142b in the first direction may not be limited. Therefore, as shown in FIG. 4 , it may not have the same shape as the first pad structure 142a. The second pad structure 142b may have a simpler step structure than the first pad structure 142a. In an exemplary embodiment, as shown in FIG. 4 , the second pad structure 142b may include steps in only the first direction.

In some example embodiments, although not illustrated, the second pad structure 142b may have the same step structure as the first pad structure 142a.

A second interlayer insulating layer 114 may be provided on the first interlayer insulating layer 112 . An upper surface of the first interlayer insulating layer 112 may be substantially flat.

Cell contact plugs ( 148) may be provided.

Dummy contact plugs ( 150) may be provided.

The cell contact plugs 148 may contact upper surfaces of the pads of the first pad structure 142a, respectively. The cell contact plugs 148 may be regularly disposed in the first and second directions. In an exemplary embodiment, when viewed from a plan view, the cell contact plugs 148 may be arranged in a line parallel to each other in the first direction and the second direction. For example, the cell contact plugs 148 may be disposed to be spaced apart from each other at a first interval in the first direction. The cell contact plugs 148 may be disposed to be spaced apart from each other at a second interval in the second direction. The second interval may be the same as the first interval or different from the first interval.

When viewed from a plan view, a first number of the cell contact plugs 148 may be disposed within a unit area of the pad portion C, such that the cell contact plugs 148 may have a first arrangement density.

The dummy contact plugs 150 may contact upper surfaces of edges of the second pad structure 142b in the first direction. The dummy contact plugs 150 may contact the upper surface of the step of the second pad structure 142b.

The dummy contact plugs 150 may have a different arrangement density than the cell contact plugs 148 . The dummy contact plugs 150 may have a second arrangement density lower than that of the cell contact plugs 148 . That is, in a plan view, a second number of the dummy contact plugs 150 smaller than the first number may be disposed within a unit area of the dummy pad portion D. As shown in FIG.

The arrangement of the dummy contact plugs 150 may vary according to the position of the step portion of the second pad structure 142b. At least some of the dummy contact plugs 150 may be disposed differently from the cell contact plugs 148 .

In an exemplary embodiment, a portion of the dummy contact plugs 150 is disposed to be the same as that of the cell contact plugs 148 , and a remaining portion of the dummy contact plugs 150 is the cell contact plugs. It may be arranged differently from the arrangement of (148).

In an exemplary embodiment, the dummy contact plugs 150 contacting the upper step of the second pad structure 142b and the dummy contact plugs 150 contacting the lower step of the second pad structure 142b include: They can have different layouts. The upper step of the second pad structure 142b may mean a staircase of at least two or more floors in the first direction from the uppermost step of the second pad structure 142b. Also, the lower step of the second pad structure 142b may refer to a step located below the upper step of the second pad structure 142b.

For example, as shown in FIGS. 1 and 3 , the dummy contact plugs 150 contacting the upper step of the second pad structure 142b may have the same arrangement as the cell contact plugs 148 . have. Accordingly, the dummy contact plugs 150 in contact with the upper step of the second pad structure 142b are spaced apart from each other by a first interval in the first direction, and are spaced apart from each other by a second interval in the second direction. can be

However, the dummy contact plugs 150 contacting the lower step of the second pad structure 142b may have a different arrangement from the cell contact plugs 148 . The dummy contact plugs 150 contacting the lower step of the second pad structure 142b are disposed in the same manner as when some dummy contact plugs are removed from the arrangement of the dummy contact plugs 150 contacting the upper step. can be

For example, the dummy contact plugs 150 in contact with the lower step of the second pad structure 142b may have a shape in which the dummy contact plugs 150 are not disposed in one or more rows in the first direction. As shown in FIG. 1 , the dummy contact plugs 150 may not be disposed in one or more rows of the portion adjacent to the opening 130 in the lower step of the second pad structure 142b.

As described above, as a portion of the dummy contact plugs 150 is disposed to be the same as that of the cell contact plugs 148 , a difference in arrangement density between the cell contact plug 148 and the dummy contact plugs 150 . Accordingly, defects in the cell contact plug 148 caused by etch loading generated when the cell contact plug is formed may be reduced. Also, since the remaining portions of the dummy contact plugs 150 are arranged differently from the arrangement of the cell contact plugs 148 and have a low arrangement density, the first connection lines 162 and the dummy contact plugs 150 are ) can be reduced in bridge failures that are connected to each other.

The first connection lines 162 connected to each of the cell contact plugs 148 may be provided on the second interlayer insulating layer 114 . One first connection line 162 extends while being connected to an upper surface of a target cell contact plug which is any one of the cell contact plugs 148 , and includes cell contact plugs 148 other than the target cell contact plug and It may not be connected to the dummy contact plugs 150 . Accordingly, the first connection lines 162 may extend on a portion between the cell contact plugs 148 and a portion between the dummy contact plugs 150 . At this time, if the first connection lines 162 are not disposed in normal positions, a defect in which the first connection line 162 and the dummy contact plugs 150 adjacent thereto are bridged may occur. have.

Since an electrical signal is not substantially applied to the dummy contact plug 150 , the first connection lines 162 may not contact the dummy contact plug 150 . That is, the dummy contact plug 150 may not be electrically connected to the first connection lines 162 .

In an exemplary embodiment, a portion of the first connection line 162 extends from the top surface of the target cell contact plug onto the dummy pad portion D and then in a first direction so as to be away from the cell area A It may have a shape extending to Accordingly, the first connection lines 162 may be intensively disposed on the dummy pad region D. As shown in FIG. In particular, more first connection lines 162 may be disposed on the lower step portion of the second pad structure 142b.

However, since the second arrangement density of the dummy contact plugs 150 is lower than the first arrangement density of the contact plugs 148 , the bridge between the first connection line 162 and the dummy contact plug 150 is defective. This can be reduced. 1, 3, and 4 , since some dummy contact plugs are removed from the lower step portion of the second pad structure 142b, the lower step of the second pad structure 142b A defect in which the first connection lines 162 disposed on the upper portion and the dummy contact plugs 150 are bridged with each other may be reduced.

Also, since the second arrangement density of the dummy contact plugs 150 is lower than the first arrangement density of the cell contact plugs 148 , the first connection line is disposed between the dummy contact plugs 150 . The number of the first connection lines 162 may be equal to or greater than the number of the first connection lines 162 disposed on the portion between the cell contact plugs 148 .

1, 3, and 4 , since some dummy contact plugs are removed from the lower step portion of the second pad structure 142b, the dummy contact plugs are disposed on the removed portion. The number of first connection lines 162 to be formed may be greater than the number of first connection lines 162 disposed on a portion between the cell contact plugs 148 . For example, two to three first connection lines 162 are disposed between the cell contact plugs 148 , and at least between the dummy contact plugs 150 than between the cell contact plugs 148 . One or more number of first connection lines 162 may be disposed.

A third interlayer insulating layer 160 may be provided on the second interlayer insulating layer 114 . The first connection lines 162 may be provided in the trench included in the third interlayer insulating layer 160 . Accordingly, the third interlayer insulating layer 160 may fill the space between the first connection lines 162 .

A fourth interlayer insulating layer 164 covering the first connection lines 162 may be provided on the third interlayer insulating layer 160 .

Contact plugs 166 may be provided through the fourth, third, and second interlayer insulating layers 164 , 160 , and 114 to respectively connect to the channel structure 128 of the cell region A . Also, although not shown, upper wirings may be further provided on the fourth interlayer insulating layer 164 . The upper wiring may include a wiring electrically connected to the contact plug 166 and a wiring connected to the first connection lines 162 .

Although an example of the arrangement of the dummy contact plugs has been described in this embodiment, the dummy contact plugs may be arranged in various ways to have a different arrangement density from the cell contact plugs. Hereinafter, embodiments of vertical memory devices according to the arrangement of the dummy contact plugs will be described. Each of the following embodiments is the same as described with reference to FIGS. 1 to 4 except for the arrangement of the dummy contact plugs.

5 is a plan view illustrating a vertical type memory device according to example embodiments.

5 to 7 below, in order to simplify the drawing, the first connection line is not shown.

Referring to FIG. 5 , some dummy contact plugs may be removed from the lower step portion of the second pad structure 142b.

The dummy contact plugs 150 contacting the lower step of the second pad structure 142b may have a shape in which the dummy contact plugs 150 are not arranged in one or more rows in the first direction. As illustrated, the dummy contact plugs 150 may be disposed in one or more columns of a portion adjacent to the opening 130 in the lower step of the second pad structure 142b. However, the dummy contact plugs 150 may have a shape in which the dummy contact plugs are not disposed in one or more rows in the first direction from the central portion of the second direction in the lower step of the second pad structure.

Although not shown, a first connection line extending while being connected to the upper surface of the target cell contact plug may be provided. In this case, the number of first connection lines 162 disposed on the portion where the dummy contact plugs are removed is the number of first connection lines 162 disposed on the portion between the cell contact plugs 148 . can be more than

6 is a plan view illustrating a vertical memory device according to example embodiments.

Referring to FIG. 6 , the dummy contact plugs 150 may be positioned only at an edge portion of the second pad structure 142b in the second direction.

That is, the dummy contact plugs 150 on the second pad structure 142b adjacent to the opening 130 may have the same arrangement as the cell contact plugs 148 . However, the dummy contact plugs 150 may not be disposed at a central portion of the second pad structure 142b in the second direction.

7 is a plan view illustrating a vertical memory device according to example embodiments.

Referring to FIG. 7 , the dummy contact plugs 150 may be positioned only at a central portion of the second pad structure 142b in the second direction.

That is, the dummy contact plug 150 disposed at the center portion of the second pad structure 142b in the second direction may have the same arrangement as the cell contact plugs 148 . However, the dummy contact plugs 150 may not be disposed at an edge portion of the second pad structure 142b in the second direction (ie, a portion adjacent to the opening).

8 to 20 are cross-sectional views and plan views for explaining a method of manufacturing a vertical memory device according to example embodiments.

8, 10, 12, 14, 15. 17, 18, 19 and 20 are cross-sectional views, and FIGS. 9, 11, 13, 8, 12, 16 and 14 are plan views. 14, 17, and 19 are cross-sectional views of a cell contact plug, and FIGS. 15, 18, and 20 are cross-sectional views of a dummy contact plug.

8 and 9 , a sacrificial layer and an insulating layer are alternately and repeatedly stacked on the substrate 100 . The insulating layer may include silicon oxide. The sacrificial layer may include a material having an etch selectivity with respect to the insulating layer, for example, a nitride such as silicon nitride.

By patterning the sacrificial layers and the insulating layers, the preliminary mold structure 110 is formed on the cell region A and the cell wiring region B of the substrate 100 . In the preliminary mold structure 110 , a sacrificial pattern 104 and an insulating pattern 102 may be repeatedly stacked alternately in a vertical direction.

An edge portion of the preliminary mold structure 110 on the cell wiring region B may have a step shape. In the cell wiring region B, the preliminary mold structure 110 on the pad region C and the dummy pad region D may have different step shapes. The preliminary mold structure 110 may have steps having substantially the same shape as that of the wiring stack structure 142 to be formed later.

10 and 11 , a first interlayer insulating layer 112 covering the preliminary mold structure 110 is formed on the substrate 100 . Thereafter, the upper surface of the first interlayer insulating layer 112 may be planarized through a planarization process. The first interlayer insulating layer 112 may include silicon oxide.

A channel hole is formed through the first interlayer insulating layer 112 and the preliminary mold structure 110 on the cell region A to expose the upper surface of the substrate 100, and the channel structure ( 128) is formed. In an exemplary embodiment, a semiconductor pattern 118 may be further formed on the upper surface of the substrate 100 exposed on the lower surface of the channel hole.

A portion of the preliminary mold structure 110 is etched to form openings 130 extending in the first direction. Accordingly, the preliminary mold structure may be converted into a plurality of mold structures 110a by the opening 130 . The opening 130 may be provided between the plurality of mold structures 110a in the second direction.

A top surface of the substrate 100 may be exposed on a bottom surface of the openings 130 . The opening 130 may serve as a word line cutting area or a block cutting area.

12 and 13 , each of the sacrificial patterns 104 included in the mold structures 110a is removed to form gaps between the insulating patterns 102 in a vertical direction, respectively.

In an exemplary embodiment, although not shown, in the process of removing a portion of the sacrificial patterns 104 , the sacrificial patterns 104 formed in a partial region of the cell wiring region B may remain without being removed. can

A conductive material is filled in the gaps to form the gate electrode 132 in the gaps. The conductive material may include a barrier pattern and a metal pattern. In an exemplary embodiment, the gate electrode 132 may include tungsten.

Through the above process, the mold structure 110a may be converted into a laminate structure 144 . The mold structure 110a on the cell area A may be converted into the cell stack structures 140 , and the mold structure 110a on the cell wiring area B may be converted into the wire stack structure 142 .

The wiring stack structure 142 includes first and second pad structures 142a and 142b. The first pad structure 142a is disposed in the pad area C in the cell wiring area B, and the second pad structure 142b is disposed in the dummy pad area D in the cell wiring area B. can be placed.

In addition, all conductive materials formed in the opening 130 are removed. Accordingly, the substrate 100 may be exposed on the bottom surface of the opening 130 .

14 , 15 and 16 , a second interlayer insulating layer 114 is formed on the first interlayer insulating layer 112 .

An etch mask is formed on the second interlayer insulating layer 114 . The second interlayer insulating layer 114 and the first interlayer insulating layer 112 on the cell interconnection region B are etched using the etch mask, thereby exposing a step upper surface of the interconnection stack structure 142 . The dummy contact holes 146a and dummy contact holes 146b are formed.

Specifically, the contact holes 146a are formed to expose the upper surface of the step of the first pad structure 142a, and the dummy contact holes 146b are formed of the step of the second pad structure 142b. It may be formed to expose the upper surface.

In an exemplary embodiment, the arrangement of the contact holes 146a may be the same as that of the cell contact plugs 148 described with reference to FIG. 1 . The arrangement of the dummy contact holes 146b may be the same as that of the dummy contact plugs 150 described with reference to FIG. 1 .

That is, when viewed from a plan view, the contact holes 146a may be regularly arranged with uniform spacing. Also, in a plan view, the contact holes 146a may have a first arrangement density.

15 and 16 , the dummy contact holes 146b may have a different arrangement density from the contact holes 146a. The dummy contact holes 146b may have a second arrangement density lower than the arrangement density of the contact holes 146a. In an exemplary embodiment, the arrangement of the dummy contact holes 146b may vary according to the position of the step portion of the second pad structure 142b.

In some example embodiments, the arrangement of the dummy contact holes 146b may be the same as any one of the arrangement of the dummy contact plugs described with reference to FIGS. 5 to 7 .

17 and 18 , a conductive layer is formed to fill the inside of the contact holes 146a and the dummy contact holes 146b. Thereafter, the conductive layer is planarized so that the conductive layer remains only inside the contact holes 146a and the dummy contact holes 146b. Accordingly, the cell contact plugs 148 contacting the step portion of the first pad structure 142a and the dummy contact plugs 150 contacting the step portion of the second pad structure 142b may be formed, respectively. In the planarization process, an upper surface of the second interlayer insulating layer 114 may be exposed.

19, 20 and 1 , a third interlayer insulating layer 160 is formed on the second interlayer insulating layer 114 . A portion of the third insulating interlayer 160 is etched to form a trench for forming the first connection lines 162 .

A conductive layer is formed in the trench. Thereafter, the conductive layer is planarized so that the conductive layer remains only inside the trench. Accordingly, first connection lines 162 connected to target cell contact plugs may be formed on the second interlayer insulating layer 114 .

One first connection line 162 may extend while contacting the upper surface of one target cell contact plug, and may not be connected to cell contact plugs 148 and dummy contact plugs other than the target cell contact plug 150 . have. Accordingly, the first connection lines 162 may extend on a portion between the cell contact plugs 148 and a portion between the dummy contact plugs 150 .

The dummy contact plugs 150 may have a second arrangement density lower than that of the cell contact plugs 148 . Accordingly, in a plan view, a greater number of first connection lines 162 may be disposed between the dummy contact plugs 150 having a low arrangement density. In an exemplary embodiment, the number of first connection lines 162 disposed between the dummy contact plugs 150 is the number of first connection lines 162 disposed between the cell contact plugs 148 . could be more than the number. For example, a greater number of the first connection lines 162 may be disposed in a portion having the same shape as that from which the dummy contact plug is removed, compared to other portions.

Again, referring to FIGS. 2 and 3 , a fourth interlayer insulating layer 164 is formed on the third interlayer insulating layer 160 . A contact plug 166 may be formed through the fourth, third, and second interlayer insulating layers 164 , 160 , and 114 to be respectively connected to the channel structure 128 of the cell region A . A vertical memory device may be manufactured through the above process.

Although described with reference to preferred embodiments of the present invention as described above, those of ordinary skill in the art can variously modify and modify the present invention within the scope without departing from the spirit and scope of the present invention as described in the claims. You will understand that it can be changed.

100: substrate 102: insulating pattern
104: sacrificial pattern 112: first interlayer insulating film
114: second interlayer insulating layer 128: channel structure
132: gate electrodes 140: cell stack structure
142: wiring stack structure 142a: first pad structure
142b: second pad structure 144: stacked structures
148: cell contact plug 150: dummy contact plug
160: third interlayer insulating film 162: first connection line
164: fourth interlayer insulating film

Claims (10)

A substrate comprising: a substrate including a cell region and a cell wiring region arranged in a first direction, and including first and second blocks adjacent to each other in a second direction perpendicular to the first direction;
a first laminate structure provided on the substrate of the cell region and the cell wiring region in the first block, the gate electrode and the insulating pattern being alternately and repeatedly disposed, and the cell wiring region including a pad portion having a step shape;
a second stacked structure provided on the substrate of the cell region and the cell wiring region in the second block, the gate electrode and the insulating pattern are alternately and repeatedly disposed, and the cell wiring region including a dummy pad portion;
a first interlayer insulating layer covering the first and second stacked structures;
cell contact plugs passing through the first interlayer insulating layer and contacting a pad portion of the first stacked structure in the cell wiring region; and
and dummy contact plugs passing through the first interlayer insulating layer and contacting a dummy pad portion of the second stacked structure in the cell wiring region;
The cell contact plugs are arranged to have a first arrangement density in the pad area, and the dummy contact plugs are arranged to have a second arrangement density lower than the first arrangement density in the dummy pad area. The vertical memory device of claim 1 , wherein a step shape of the first stacked structure and a step shape of the second stacked structure are different from each other. 3 . The method of claim 2 , wherein the steps of the first multilayer structure have a shape including steps in first and second directions parallel to and perpendicular to the upper surface of the substrate, respectively, and the steps of the second multilayer structure include the steps of the second multilayer structure. A vertical memory device having a shape including steps in one direction. According to claim 1, wherein the arrangement of the dummy contact plugs in contact with the upper stairway of two or more floors downward from the top of the second laminated structure is in contact with the lower stairway, which is a stair located below the upper stair of the second laminated structure. A vertical memory device different from the arrangement of the dummy contact plugs. 5 . The method of claim 4 , wherein the dummy contact plugs contacting the lower step of the second stacked structure are the same as some of the dummy contact plugs are removed from the arrangement of the dummy contact plugs contacting the upper step of the stacked structure on the dummy pad forming region. A vertical memory device arranged in a shape. The cell contact plug of claim 1 , wherein the cell contact plugs are regularly disposed in first and second directions parallel to and perpendicular to the upper surface of the substrate, and at least some of the dummy contact plugs are disposed differently from the cell contact plugs. vertical memory device. The vertical memory device of claim 1 , wherein connection lines do not contact the dummy contact plug, so that the dummy contact plug is not electrically connected to the connection line. The vertical memory device of claim 1 , further comprising a connection line in contact with one of the cell contact plugs and extending over a portion between the cell contact plugs and a portion between the dummy contact plugs. The vertical memory device of claim 8 , wherein the number of connection lines disposed on the portion between the dummy contact plugs is equal to or greater than the number of connection lines disposed on the portion between the cell contact plugs. The method of claim 8 , wherein the number of connection lines disposed on a portion between the dummy contact plugs in a portion different from that of the cell contact plugs is greater than the number of connection lines disposed on a portion between the cell contact plugs. Many vertical memory elements.

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