KR20210133512A - 2-terminal resistive random access memory by charge trap and preparation method thereof, and cross point array structure memory system comprising the same - Google Patents

Abstract

The present invention relates to a two-terminal resistive random access memory by a charge trap, a manufacturing method thereof, and a memory system of a cross point array structure including the same. The two-terminal resistive random access memory includes: a first metal layer; an insulator layer disposed on a base first metal layer, having a thickness of 1 to 15 nm, and including an insulating metal oxide; a semiconductor layer disposed on the insulator layer; and a second metal layer disposed on the semiconductor layer. An objective of the present invention is to provide the nonvolatile two-terminal resistive random access memory used at a low voltage by a charge trap and having a self-rectifying function, the manufacturing method thereof, and the memory system having a cross point array structure including the same.

Description

Two-terminal resistive random access memory by charge trap and preparation method thereof, and cross point array structure memory system comprising the same }

The present invention relates to a two-terminal resistance variable memory using a charge trap, a method for manufacturing the same, and a memory system having a cross-point array structure including the same.

The semiconductor industry is a highly technology-intensive industry based on cutting-edge technology and is the driving force behind the development of the information age. According to Moore's Law, which was proposed in 1965, it was predicted that the degree of integration of integrated circuits (ICs) would increase by doubling every year. due to innovation The basis for producing information and communication devices such as computers and smart phones that greatly affect our lives at present with high performance, low power, and reasonable price has also been achieved through miniaturization of semiconductor devices.

Memory that is currently widely used has a common denominator for storing information by storing electrons in a specific place based on the transistor structure. , since the size of the memory semiconductor is reduced, it has a higher capacity, so miniaturization plays a key role in improving the density. However, reducing the transistor device to 7 nm or less is recognized as a physical/technological limitation. In particular, in the case of memory semiconductors, since the number of stored electrons is also reduced, it is difficult to stably store information for 10 years, and the spacing between elements is also greatly affected by the operating characteristics of adjacent elements. It is necessary to develop a semiconductor memory using

In order to solve the problems of the existing three-terminal transistor structure and the method of storing information using electrons, research on a memory device using a two-terminal device structure and atomic/ion migration is being actively conducted.

The two-terminal device structure uses a simpler structure (metal/oxide/metal), and when an appropriate voltage/current condition is applied, the resistance is changed from a high resistance non-conducting state to a low resistance conducting state. These two resistance states are distinguished by a difference between '0' and '1', and refers to a memory device that recognizes them. Depending on the method in which the resistance is changed in the material, it is divided into PRAM (Phase Change Memory), which is the effect of phase change, MRAM (Magnetic RAM) due to the change of spin, and ReRAM (Resistive RAM) by the movement of ions in the material. names are distinguished. Among them, ReRAM is observed in various metal materials and oxide forms of oxygen presented on the periodic table of elements. is becoming In addition, the physical principle of changing resistance does not store electrons in a specific space, but uses the movement of atoms or ions in the material according to the external environment. Since a separate space for storing electrons is not required as in conventional memory devices, the possibility of miniaturization of the device is emerging as an advantage.

However, the conventional resistance change memory changes resistance by using a mechanism in which oxygen ions or oxygen vacancies directly move according to voltage application, and a large operating voltage is required to move oxygen ions, and oxygen ions or oxygen vacancies are There is a problem that stability is not guaranteed as time goes by depending on the diffusion effect of

Meanwhile, a three-dimensional stacked cross-point (X-point) structure memory system has recently been disclosed as a method of increasing memory capacity stagnated due to limitations in miniaturization. The crosspoint structure is a structure in which a plurality of lower electrodes (bit lines) and a plurality of upper electrodes (word lines) are formed to cross each other, and a memory node is formed at the intersection points of the memory elements. The dimensional stacked memory system has the advantage of realizing a higher capacity in the same chip area as memory devices composed of several atoms can be stacked layer by layer in a way that implements a skyscraper. In addition, since RRAM has a process advantage due to its simple structure, it is expected to exhibit improved performance compared to existing memory technologies by incorporating a structurally superior method of 3D.

However, in a memory system having such a crosspoint structure, a parasitic signal due to interference of unaddressed cells located on the same bit line or word line delays the execution of the crosspoint array. As the most serious problem affecting reliable operation, the "sneak current path" is known, and the "sneak current path" is the leakage current that occurs when addressing specific memory cells within a crosspoint array. means The sneak current path, for example, affects the read result of the cell state and causes the memory cell state to be read erroneously. The sneak path problem generally arises in passive arrays, particularly in situations that exhibit linear or near-linear current-voltage characteristics in the low-resistance state of memory cells. In the high-resistance state of a cell, it can be misread due to leakage current through adjacent cells in the low-resistance state.

Accordingly, in the conventional case, a method of reducing leakage current in a circuit by adding a transistor or a diode as a 'selector' has been disclosed. As a related art, in Republic of Korea No. 10-2013-0142761, a resistance variable nonvolatile memory device having a selector as a mechanical switch has been disclosed. However, the manufacturing process of adding a separate transistor or diode to the process of forming the crosspoint structure is difficult, and economical efficiency is low and durability is deteriorated.

Republic of Korea No. 10-2013-0142761

It is an object of the present invention to provide a nonvolatile two-terminal resistance variable memory having a self-rectifying function and used at a low voltage by a charge trap, a manufacturing method thereof, and a memory system having a cross-point array structure including the same.

In order to achieve the above object,

In one aspect of the present invention,

a first metal layer;

an insulator layer disposed on the first metal layer, having a thickness of 1 to 15 nm, and including an insulating metal oxide;

a semiconductor layer disposed on the insulator layer; and

A two-terminal resistance variable memory including a second metal layer disposed on the semiconductor layer is provided.

In addition, in another aspect of the present invention,

forming a semiconductor layer on the second metal layer;

forming an insulator layer having a thickness of 1 to 15 nm on the semiconductor layer; and

There is provided a method of manufacturing a two-terminal resistance variable memory including; forming a first metal layer on the insulator layer.

In addition, in another aspect of the present invention,

a plurality of first word lines spaced apart from each other in a first direction;

a plurality of bit lines disposed on the word line and spaced apart from each other in a second direction perpendicular to the first direction;

a plurality of first semiconductor layers disposed at each intersection of the first word line and the bit line, the first semiconductor layer stacked in the first word line direction from the bit line, and a first insulator layer having a thickness of 1 to 15 nm a first memory cell;

a plurality of second word lines disposed on the bit line and spaced apart from each other in a first direction; and

a plurality of second semiconductor layers disposed at intersections of the bit lines and second word lines, respectively, and stacked in a direction from the bit lines to the second word lines; and a second insulator layer having a thickness of 1 to 15 nm. a second memory cell;

The memory system of a crosspoint array structure is provided, wherein the first memory cell and the second memory cell perform a self-rectifying function.

The present invention is a two-terminal resistance variable memory including a junction structure of an insulator layer and a semiconductor layer, wherein the insulator layer is capable of electron tunneling and is capable of trapping charges. The presence or absence is determined, and accordingly, the thickness of the depletion layer formed on one surface of the semiconductor layer in contact with the insulator layer may be changed to change the electron tunneling resistance of the device.

The present invention can change the tunneling resistance by changing the thickness of the depletion layer of the semiconductor layer, so it consumes less power than the conventional resistance change memory that changes the resistance by directly moving oxygen ions or oxygen vacancies, and It has excellent stability characteristics.

In addition, the switching speed can be improved, and by including the insulator layer of 15 nm or less, directization can be improved, and the production cost can be lowered.

In addition, in the resistance variable memory of the present invention, a Schottky barrier exists at the interface between the semiconductor layer and the second metal layer, and a self-rectifying function can be performed by the Schottky barrier. Since an additional process for lamination is not required, it is easy to manufacture, and there are advantages of reducing the lamination thickness of the memory system and improving the directivity of the system.

1 and 2 are schematic diagrams showing an embodiment of a two-terminal resistance change memory provided in one aspect of the present invention,
3 is a schematic diagram showing the operating principle of a two-terminal resistance change memory provided in one aspect of the present invention;
4 is a schematic diagram showing a bandgap diagram of a two-terminal resistance change memory provided in one aspect of the present invention;
5 is a schematic diagram showing an embodiment of a memory system having a cross-point array structure provided in another aspect of the present invention;
6 is It is a schematic diagram showing a method of applying a voltage for measuring the electrical characteristics of the two-terminal resistance change memory provided in one aspect of the present invention,
7 is a graph measuring voltage-current characteristics of a two-terminal resistance change memory provided in one aspect of the present invention;
8 is a graph of measuring the voltage-current characteristics of the two-terminal resistance change memory provided in one aspect of the present invention for 10 times;
9 is a graph of measuring voltage-current characteristics according to the thickness of an insulator layer for a two-terminal resistance change memory provided in one aspect of the present invention;
10 is a graph comparing the rectification ratio according to the thickness of the insulator layer for the two-terminal resistance variable memory provided in one aspect of the present invention;
11 is a graph comparing the on-off current ratio according to the thickness of the insulator layer for the two-terminal resistance change memory provided in one aspect of the present invention;
12 is a graph comparing the thickness change of the depletion layer according to the thickness of the insulator layer for the two-terminal resistance change memory provided in one aspect of the present invention;
13 is a graph showing the result of analyzing the output current value over time for the two-terminal resistance change memory provided in one aspect of the present invention;
14 is a graph comparing voltage-current characteristics according to a second metal layer in a two-terminal resistance variable memory manufactured according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiment of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided in order to more completely explain the present invention to those of ordinary skill in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer description, and elements indicated by the same reference numerals in the drawings are the same elements. In addition, the same reference numerals are used throughout the drawings for parts having similar functions and functions. In addition, "including" a certain element throughout the specification means that other elements may be further included, rather than excluding other elements, unless otherwise stated.

In one aspect of the present invention

a first metal layer;

an insulator layer disposed on the first metal layer, having a thickness of 1 to 15 nm, and including an insulating metal oxide;

a semiconductor layer disposed on the insulator layer; and

A two-terminal resistance variable memory including a second metal layer disposed on the semiconductor layer is provided.

Hereinafter, a two-terminal resistance change memory provided in one aspect of the present invention will be described in detail with reference to the drawings.

1 is a diagram showing an embodiment of a two-terminal resistance variable memory provided in one aspect of the present invention, and FIG. 2 is a view showing another embodiment of a two-terminal resistance variable memory provided in an aspect of the present invention, 3 is a schematic diagram illustrating a bandgap diagram of a two-terminal resistance variable memory provided in one aspect of the present invention.

As shown in FIG. 1, the two-terminal resistance variable memory 100 provided in one aspect of the present invention includes an insulator layer 20 and an insulator layer 20 between two metal layers, that is, a first metal layer 10 and a second metal layer 40 As a resistance change memory having a structure in which a semiconductor layer 30 is disposed, an electron trap state of the insulator layer 10 by changing the direction of a voltage applied through the first metal layer 10 and the second metal layer 40 . may be a nonvolatile two-terminal resistance change memory capable of changing the electron tunneling resistance of the insulator layer 20 by changing the thickness of the depletion layer of the semiconductor layer 30 through this.

The two-terminal resistance variable memory 100 provided in one aspect of the present invention includes a first metal layer 10 .

The first metal layer 10 may serve as an electrode.

The first metal layer 10 includes platinum (Pt), tungsten (W), gold (Au), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), tantalum (Ta), and molyb. Denium (Mo), chromium (Cr), vanadium (V), titanium (Ti), aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), manganese (Mn), tin (Sn) and It may be an alloy thereof, and may be a nitride or an oxide containing the metal or alloy. In addition, it may be any one or more of graphite, carbon nanotubes, and fullerenes.

Also, the first metal layer 10 may have a multilayer structure. For example, the first metal layer 10 may include ruthenium (Ru) and a ruthenium oxide layer (RuO _x ), or an iridium (Ir) and an iridium oxide layer (IrO _x ), or tungsten (W), tungsten carbonitride or tungsten. It may include a platinum layer having a carbon capping layer, and may have a multilayer structure in which tantalum nitride, nickel, and tantalum nitride are stacked. The first metal layer 10 may be used to improve adhesion properties and performance of a memory device through a multilayer structure.

Also, the first metal layer 10 may have a thickness of 20 nm to 100 nm.

In addition, the two-terminal resistance variable memory 100 provided in one aspect of the present invention includes an insulator layer 20 disposed on the first metal layer, having a thickness of 1 to 15 nm, and including an insulating metal oxide. can do.

In this case, the insulator layer 20 may include an insulating metal oxide.

In order to have insulating properties, the insulating metal oxide may be preferably a metal oxide having a band gap of 5 eV or more, and more preferably a metal oxide having a band gap of 5 eV to 10 eV.

In addition, the metal oxide may have a dielectric constant of 5 to 12.

The insulating metal oxide may include at least one selected from _{Al 2} O ₃ , HfO ₂ , ZrO _{2 and MgO, preferably Al 2} O ₃ .

The insulator layer 20 may include a charge trap state, and the charge trap state may be a state including trapped electrons.

The insulator layer 20 may or may not contain trapped electrons, so that the internal electric field may be changed.

For example, when a positive voltage is applied to the first metal layer 10 , the insulator layer 20 may be switched to a state that does not include trapped electrons, and when a negative voltage is applied, this Conversely, it can be converted to a state containing trapped electrons.

In addition, the thickness of the insulator layer 20 may be 1 to 15 nm, preferably 1.3 to 10 nm, 1.5 to 10 nm, 2.5 to 10 nm, 2.7 to 10 nm, It may be 3 to 10 nm.

This is to enable electron tunneling through the insulator layer 20. If the thickness is less than 1 nm or exceeds 15 nm, the resistance change memory of the present invention does not exhibit electron tunneling, and thus the resistance change characteristic may not appear.

In addition, the insulator layer 20 may exhibit an excellent on-off current ratio by having a thickness of 1.5 nm or more, and may exhibit a high rectification ratio characteristic by having a thickness of 3 to 5 nm.

In addition, the two-terminal resistance variable memory 100 provided in one aspect of the present invention includes a semiconductor layer 30 disposed on the insulator layer 20 .

The semiconductor layer 30 is preferably an N-type semiconductor layer made of an N-type semiconductor in order to form a resistance change layer 31 showing an electron depletion state on one surface in contact with the insulator layer 20 . have.

The N-type semiconductor is ZnO, Al:ZnO, In ₂ O ₃ , SnO2, TiO ₂ , SnO ₂ , SrTiO _{3 , Ga 2} O ₃ and In—Ga—Zn oxide (IGZO), which may include at least one of, indium (In), gallium (Ga), tin (Sn) and zinc (Zn) as a metal oxide including at least one, preferably may be In-Ga-Zn oxide (IGZO) having higher electron mobility.

Preferably, the N-type semiconductor ^{may be a semiconductor doped with impurities in a ratio of 10 8} to 10 ¹⁶ compared to an intrinsic semiconductor, and a Fermi level of 0.5 to 1 compared to an intrinsic semiconductor eV can be high.

In addition, the semiconductor layer 30 may have a thickness of 50 to 250 nm.

In addition, the semiconductor layer 30 may include a resistance change layer disposed on one surface of the semiconductor layer 30 in contact with the insulator layer 20 .

The two-terminal resistance change memory 100 provided in one aspect of the present invention may change the resistance by changing the thickness of the resistance change layer 31 .

The resistance change layer 31 may be a depletion layer formed on one surface of the semiconductor layer 30 . That is, the resistance-variable layer 31 is a depletion layer whose thickness varies depending on the direction of applied voltage or whether or not the insulator layer 20 has charge trapping. can indicate

The thickness of the resistance change layer 31 or the depletion layer may be varied within a range of 2.5 to 5.5 nm. For example, the thickness of the resistance change layer 31 or the depletion layer may be 2.5 to 3.5 nm when the memory 10 is in a resistance state, and may be 4.5 to 5.5 nm when the memory 10 is in a high resistance state.

In the two-terminal resistance variable memory 100 provided in one aspect of the present invention, one surface of the semiconductor layer 30 in contact with the insulator layer as the internal electric field of the insulator changes according to the presence or absence of charge trapping of the insulator layer 20 . The thickness of the depletion layer formed in the ? In this case, it may be a layer in which a change in resistance occurs according to a change in the thickness of the depletion layer.

Accordingly, the electron state of the depletion layer may vary according to the direction of the applied voltage, and thus the thickness of the electron tunneling barrier may vary.

The two-terminal resistance variable memory provided in one aspect of the present invention may be a memory semiconductor that changes resistance through which electrons are tunneled by adjusting the thickness of the depletion layer.

That is, the thickness of the depletion layer may decrease or increase depending on the direction of the voltage applied to the first metal layer or the second metal layer, and accordingly, the resistance of the resistance variable memory 100 may decrease or increase, so that the device 100 . can be turned on or off.

Accordingly, since the two-terminal resistance change memory 100 provided in one aspect of the present invention does not directly move oxygen ions or oxygen vacancies for resistance change, the concentration of oxygen ions or oxygen vacancies in the resistance change layer 31 is It may be the same as the semiconductor layer 30 .

3 is a schematic diagram showing the operating principle of the two-terminal resistance variable memory 100 provided in one aspect of the present invention. The principle is explained as follows.

In the two-terminal resistance variable memory 100 provided in one aspect of the present invention, a voltage may be applied by the first electrode layer M1 and the second electrode layer M2, and at this time, the insulator is dependent on the direction of the applied voltage. It is possible to change the charge trap state of layer 20 .

For example, when a positive voltage is applied through the first electrode M1 , electrons trapped in the insulator layer 20 escape and the thickness of the depletion layer of the semiconductor layer 30 becomes small. , thus, the resistance variable memory 100 may exhibit a low resistive state (LRS) to form an on state.

On the contrary, when a negative voltage is applied through the first electrode M1 , electrons are trapped in the charge trap state of the insulator layer 20 , and the semiconductor layer is caused by the internal electric field of the insulator layer 20 . The thickness of the depletion layer in (30) is increased. Accordingly, the resistance variable memory 100 may exhibit a high resistive state (HRS) to form an off state.

As described above, in the two-terminal resistance variable memory 100 provided in one aspect of the present invention, the thickness of the depletion layer of the semiconductor layer 30 is changed according to the charge trap state of the insulator layer 20 to increase the resistance value of the device. By changing it, the memory element can be turned on/off. Accordingly, there is an advantage in use stability, that is, a lifespan characteristic, is superior to that of a conventional resistance-variable memory device in which oxygen ions or oxygen vacancies directly move to change resistance.

Meanwhile, the two-terminal resistance variable memory 100 provided in one aspect of the present invention includes a second metal layer 40 disposed on the semiconductor layer.

The second metal layer 40 includes platinum (Pt), tungsten (W), gold (Au), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), tantalum (Ta), and molyb. Denium (Mo), chromium (Cr), vanadium (V), aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), manganese (Mn), tin (Sn), and alloys thereof may be used. , It may be a nitride or oxide containing the metal or alloy. In addition, it may be any one or more of graphite, carbon nanotubes, and fullerenes.

Also, the second metal layer 40 may have a multilayer structure. For example, ruthenium (Ru) and ruthenium oxide layer (RuO _x ), or iridium (Ir) and iridium oxide layer (IrO _x ), or tungsten (W), tungsten carbonitride or tungsten carbon capping layer It may include a platinum layer having a multilayer structure in which tantalum nitride, nickel, and tantalum nitride are stacked. The second metal layer 40 may be used to improve adhesion properties and performance of the memory device through a multilayer structure.

In addition, the second metal layer 10 may have a thickness of 20 nm to 100 nm, preferably 30 to 70 nm.

In the two-terminal resistance variable memory 100 provided in one aspect of the present invention, a Schottky barrier is formed by the junction of the semiconductor layer 30 and the second metal layer 40, and through this, a self-rectifying function is achieved. Therefore, when applied to a semiconductor system having a cross-point structure, there is no need to provide a separate selector, and there is an advantage in that the semiconductor system can be formed with high integration density.

To this end, the first metal layer 10 may have the same or smaller work function as the second metal layer 40 , and the second metal layer 40 is preferably the same as the first metal layer 10 . Or it may have a larger work function.

For example, when the semiconductor layer 30 is made of In—Ga—Zn oxide (IGZO), the first metal layer 10 may be made of a metal having a work function of 4.5 eV or less, and more preferably 3.5 eV. It may be made of a metal having a work function of eV to 4.5 eV, and more preferably, a metal having a work function of 4.0 eV to 4.5 eV.

In addition, the second metal layer 40 may be made of a metal having a work function of 4.5 eV or more, and more preferably, a metal having a work function of 4.5 eV to 5 eV.

Accordingly, when the semiconductor layer 30 is made of In—Ga—Zn oxide (IGZO), the first metal layer 10 may be at least one of platinum (Pt), molybdenum (Mo), and titanium nitride (TiN). and the second metal layer 40 may include at least one of chromium (Cr), molybdenum (Mo), platinum (Pt), palladium (Pd), and gold (Au).

Through this, a self-rectifying function may be performed by forming a Schottky barrier at the interface between the semiconductor layer 30 and the second metal layer 40 .

In addition, as shown in FIG. 4 , when the semiconductor layer 30 is made of In—Ga—Zn oxide (IGZO), and the first metal layer M1 and the second metal layer M2 have the same work function, the same metal this can be used

In addition, the first metal layer 10 may have an electron affinity of 0.7 eV or more, and preferably, an electron affinity of 0.7 eV to 2.3 eV.

In addition, the second metal layer 10 may have an electron affinity of 0.7 eV or more, and preferably, an electron affinity of 0.7 eV to 2.1 eV.

On the other hand, in another aspect of the present invention

forming a semiconductor layer 30 on the second metal layer 40;

forming an insulator layer 20 having a thickness of 1 to 15 nm on the semiconductor layer 30; and

There is provided a method of manufacturing a two-terminal resistance variable memory including; forming a first metal layer (10) on the insulator layer (20).

Hereinafter, a method of manufacturing the two-terminal resistance variable memory 100 according to another aspect of the present invention will be described in detail for each step.

The method of manufacturing the two-terminal resistance variable memory 100 of the present invention includes forming a semiconductor layer 30 on the second metal layer 40 .

The semiconductor layer 30 may be an N-type semiconductor layer.

The N-type semiconductor may include at least one of ZnO, Al:ZnO, In ₂ O ₃ , SnO2, TiO ₂ , SnO ₂ , SrTiO _{3 , Ga 2} O ₃ and In-Ga-Zn oxide (IGZO). A metal oxide including at least one of indium (In), gallium (Ga), tin (Sn) and zinc (Zn), preferably In—Ga—Zn oxide having higher electron mobility (IGZO).

The semiconductor layer 30 may be deposited by chemical vapor deposition or physical vapor deposition, preferably sputtering, atomic layer deposition (ALD), and pulsed laser deposition (PLD). ) can be performed in any one of the methods.

The method of manufacturing the two-terminal resistance variable memory 100 of the present invention includes forming an insulator layer 20 having a thickness of 1 to 15 nm on the semiconductor layer 30 .

The insulating layer 20 includes an insulating metal oxide, and the insulating metal oxide may include at least one selected from _{Al 2} O ₃ , HfO ₂ , ZrO _{2 and MgO, preferably Al 2} O ₃ can be

The forming of the insulator layer 20 may be performed by depositing the insulating metal oxide by a chemical vapor deposition method or a physical vapor deposition method, preferably by sputtering or atomic layer deposition (ALD). ) and Pulsed Laser Deposition (PLD), which may be performed by any one method, and more preferably an atomic layer deposition (ALD) method, which is more advantageous for forming a thin film of a nanolayer of 15 nm or less. can be done by the method of

The insulator layer 20 may be formed to a thickness of 1 to 15 nm, preferably to a thickness of 1.3 to 10 nm, more preferably to a thickness of 1.5 to 10 nm, and may be formed to a thickness of 2.5 to 10 nm. It may be formed to a thickness of 10 nm, may be formed to a thickness of 2.7 to 10 nm, and may be formed to a thickness of 3 to 10 nm.

This is to enable electron tunneling through the insulator layer 20. If the thickness is less than 1 nm or exceeds 15 nm, the resistance change memory of the present invention does not exhibit electron tunneling, and thus the resistance change characteristic may not appear.

In addition, the insulator layer 20 may exhibit an excellent on-off current ratio by having a thickness of 1.5 nm or more, and may exhibit a high rectification ratio characteristic by having a thickness of 3 to 5 nm.

A method of manufacturing a two-terminal resistance variable memory according to the present invention includes forming a first metal layer (10) on the insulator layer (20).

The method of manufacturing a two-terminal resistive memory of the present invention is a resistive memory having a structure in which an insulator layer 20 and a semiconductor layer 30 are formed between two metal layers, and can rapidly switch on/off current, and has a self-rectifying function. can be performed.

To this end, the first metal layer 10 may have a work function equal to or smaller than that of the second metal layer 40 , and the second metal layer 20 preferably includes the first metal layer 10 and They may have the same or greater work function.

For example, when the semiconductor layer 30 is made of In—Ga—Zn oxide (IGZO), the first metal layer 10 may be made of a metal having a work function of 4.5 eV or less, and more preferably 3.5 eV. It may be made of a metal having a work function of eV to 4.5 eV, and the second metal layer 40 may be made of a metal having a work function of 4.5 eV or more, and more preferably, having a work function of 4.5 eV to 5 eV. It may be made of metal. For example, the first metal layer 10 may be at least one of platinum (Pt), molybdenum (Mo), and titanium nitride (TiN), and the second metal layer 40 is chromium (Cr), molybdenum (Mo). , platinum (Pt), palladium (Pd), and gold (Au).

Through this, a self-rectifying function may be performed by forming a Schottky barrier at the interface between the semiconductor layer 30 and the second metal layer 40 .

In the resistive memory manufactured by the method of manufacturing a two-terminal resistive memory of the present invention, as a voltage is applied to two metal layers, electron tunneling may occur in the insulator layer and a charge trap state may be changed. In addition, according to the change in the charge trap state of the insulator layer, the thickness of the resistance variable layer, that is, the depletion layer, may be changed on one surface of the semiconductor layer in contact with the insulator layer, and accordingly, the thickness of the barrier through which electrons are tunneled is changed to change the resistance. Changes may occur.

In addition, the resistance variable memory manufactured by the method of manufacturing the two-terminal resistance variable memory of the present invention can perform a self-rectifying function by forming a Schottky barrier at the interface between the semiconductor layer and the second metal layer.

In another aspect of the present invention

a plurality of first word lines spaced apart from each other in a first direction;

a plurality of bit lines disposed on the word line and spaced apart from each other in a second direction perpendicular to the first direction;

a plurality of first semiconductor layers disposed at each intersection of the first word line and the bit line, the first semiconductor layer stacked in the first word line direction from the bit line, and a first insulator layer having a thickness of 1 to 10 nm a first memory cell;

a plurality of second word lines disposed on the bit line and spaced apart from each other in a first direction; and

a second semiconductor layer disposed at each intersection of the bit line and the second word line, the second semiconductor layer being stacked in a direction from the bit line to the second word line; and a second insulator layer having a thickness of 1 to 10 nm. a second memory cell;

The memory system of a crosspoint array structure is provided, wherein the first memory cell and the second memory cell perform a self-rectifying function.

Hereinafter, the memory system of the crosspoint array structure of the present invention will be described in detail with reference to the drawings.

5 is a schematic diagram showing a memory system having a cross-point array structure according to the present invention.

The memory system 1 may include a plurality of first word lines 200 spaced apart from each other in a first direction and second word lines 300 arranged parallel to the first word line 200 . The first word line 200 and the second word line 300 are four first word lines 201 , 202 , 203 , 204 and a second word line 301 spaced apart and parallel to each other as shown in FIG. 5 . , 302 , 303 , and 304 , the number of the first word line 200 and the second word line 300 is not limited thereto, and may be larger or smaller.

In addition, the memory system 1 includes a plurality of bit lines disposed between the first word line 200 and the second line 300 and spaced apart from each other in a second direction perpendicular to the first direction. (400). The bit line 400 may include four bit lines 401, 402, 403, and 404 spaced apart and arranged in parallel as shown in FIG. 5, but the number of the bit lines 400 is not limited thereto. , may be more or less.

The first word line 200 , the second word line 300 , and the bit line 400 are platinum (Pt), tungsten (W), gold (Au), palladium (Pd), rhodium (Rh), iridium ( Ir), ruthenium (Ru), tantalum (Ta), molybdenum (Mo), chromium (Cr), vanadium (V), titanium (Ti), aluminum (Al), copper (Cu), silver (Ag), It may be nickel (Ni), manganese (Mn), tin (Sn), and alloys thereof, and may be a nitride or an oxide including the metal or alloy.

The first word line 200 and the second word line 300 may be made of the same metal, but are not limited thereto.

The bit line 400 may have a work function greater than that of the first word line 200 and the second word line 300 , and preferably have a work function of 4.5 eV or more, and more preferably 4.5 eV. It may have a work function of to 5 eV.

This is to form a Schottky barrier at the interface between the first semiconductor layer 502 and the bit line 400 and at the interface between the second semiconductor layer 602 and the bit line 400 . Through this, the memory system 1 of the present invention can perform a rectification function. Accordingly, the memory system 1 of the present invention may be a memory system having a self-rectifying function capable of performing a rectifying function without including a separate selector such as a diode.

The memory system 1 also includes a first memory cell 500 disposed at the intersection of the first word line and the bit line, and a second memory cell 600 disposed at the intersection of the second word line and the bit line. can do.

The first memory cell 500 includes a first semiconductor layer 502 stacked in a direction from the bit line 400 to the first word line 200 and a first insulator layer 501 having a thickness of 1 to 15 nm. ) may be included.

In addition, the second memory cell 600 includes a second semiconductor layer 602 stacked in a direction from the bit line 400 to the second word line 300 and a second insulator layer having a thickness of 1 to 10 nm. (601).

In addition, the first memory cell 500 includes a 1-1 metal layer stacked from the bit line to the first word line, a first insulator layer having a thickness of 1 to 15 nm, a first semiconductor layer, and a first -2 may include a metal layer.

In this case, the work function of the first and second metal layers may be equal to or greater than the work function of the first and second metal layers, whereby a Schottky barrier may be formed at the interface between the first semiconductor layer and the first and second metal layers. have.

In addition, the second memory cell includes a 2-1 metal layer, a second insulator layer having a thickness of 1 to 15 nm, a second semiconductor layer, and a 2-2 metal layer stacked from the bit line to the second word line direction. may include.

In this case, the work function of the 2-2 metal layer may be the same as or greater than the work function of the 2-1 metal layer, whereby a Schottky barrier may be formed at the interface between the second semiconductor layer and the 2-2 metal layer. have.

The memory system 1 includes an insulator layer and a semiconductor layer in the first memory cell 500 and the second memory cell 600, and a resistance change layer is formed on one surface of the semiconductor layer in contact with the insulator layer, The resistance through which electrons are tunneled may be changed by changing the thickness of the resistance variable layer according to the application of a voltage.

Hereinafter, the present invention will be described in detail through Examples and Experimental Examples.

However, the following examples and experimental examples are merely illustrative of the present invention, and the content of the present invention is not limited by the following examples.

<Example 1> Two-terminal resistance change memory of _{Pt/Al 2} O _{3 /IGZO/Au structure}

Step 1: Platinum (Pt) having a thickness of 50 nm and a thickness of 50 nm was formed on _{a SiO 2} /Si substrate using an e-beam evaporator to form a second metal layer.

Step 2: Using RF-sputtering (RF-sputtering) to form a 50 nm thick IGZO semiconductor layer on the second metal layer. At this time, as the deposition conditions, the oxygen partial pressure of 6%, the working pressure of 5 mtorr, and was carried out at room temperature.

Step 3: Using a thermal-atomic layer deposition (ALD), using TMA and H ₂ O source, and performing 10 cycles under the conditions performed at 200 ° C., 1 nm thick on the IGZO semiconductor layer An Al ₂ O ₃ insulator layer was formed.

Step 4: Using an electron beam evaporator (e-beam evaporator to form a first metal layer by forming 50 nm-thick Au on _{the Al 2} O _{3 insulator layer, a two-terminal resistance variable memory was manufactured.}

<Example 2>

In step 3 of Example 1, a two-terminal resistance change memory was manufactured in the same manner as in Example 1, except that the ALD was performed for 15 cycles and _{the thickness of the Al 2} O _{3 insulator layer was manufactured to 1.5 nm.} did.

<Example 3>

In step 3 of Example 1, a two-terminal resistance change memory was manufactured in the same manner as in Example 1, except that the ALD was performed for 20 cycles and _{the thickness of the Al 2} O _{3 insulator layer was manufactured to be 2 nm.} did.

<Example 4>

A two-terminal resistance change memory was manufactured in the same manner as in Example 1, except that in step 3 of Example 1, the ALD was performed for 25 cycles and _{the thickness of the Al 2} O _{3 insulator layer was manufactured to 2.5 nm.} did.

<Example 5>

A two-terminal resistance change memory was manufactured in the same manner as in Example 1, except that in step 3 of Example 1, the ALD was performed for 30 cycles and the Al ₂ O _{3 insulator layer was manufactured to have a thickness of 3 nm.} did.

<Example 6>

A two-terminal resistance variable memory was manufactured in the same manner as in Example 1, except that, in step 1 of Example 1, the second metal layer was formed of aluminum (Al).

<Experimental Example 1>

In order to analyze the electrical characteristics of the resistance change of the two-terminal resistance change memory manufactured according to the embodiment of the present invention, as shown in FIG. 6 , the second metal layer M2 is grounded, and the voltage applied to the first metal layer M1 is As a method of applying a voltage, voltage-current characteristics were measured, and the results are shown in FIG. 7 , and the results of repeated measurements 10 times are shown in FIG. 8 .

As shown in FIG. 7 , it can be seen that a set state is indicated in a positive voltage range and a reset state is indicated in a negative voltage range. It can be seen that it works stably.

<Experimental Example 2>

For the two-terminal resistance variable memory manufactured according to the embodiment of the present invention, in order to analyze the electrical characteristics according to the thickness of the insulator layer, for the resistance change memory manufactured according to Examples 1 to 5, the same as in Experimental Example 1 The voltage-current characteristics were measured by this method, and the results are shown in FIGS. 9 to 11 .

9 is a voltage-current curve for the resistance variable memory manufactured according to Examples 1 to 5, and FIG. 10 is a rectification ratio according to the thickness of the insulator layer under the condition of read Voltage = ±3V among the curves of FIG. ), and FIG. 11 is a graph showing the on/off current ratio according to the thickness of the insulator layer under the condition of read Voltage = -1V among the curves of FIG. 9 .

9 , it can be seen that the resistance variable memories manufactured according to Examples 1 to 5 exhibit a set state in a positive voltage range and a reset state in a negative voltage range.

In addition, it can be seen from FIG. 10 that the rectification characteristics are improved as the thickness of the insulator layer increases. In particular, the rectification characteristics are significantly better than when the thickness of the insulator layer has a thickness of 1.5 to 2.5 nm from 3 nm to 30K. can be seen to indicate

11, it can be seen that, when the thickness of the insulator layer is 1.5 nm, the on/off current ratio is remarkably high as 900, and at a thickness of 1.5 nm or more, it has a value of 600 or more.

Through this, it can be seen that when the thickness of the insulator layer is 1.5 nm or more, an excellent on/off current ratio can be obtained, and when the thickness of the insulator layer is 3 nm or more, better rectification characteristics can be obtained.

<Experimental Example 3> Change in thickness of depletion layer according to thickness of insulator layer

In order to analyze the characteristics of the depletion layer in the semiconductor layer according to the thickness of the insulator layer for the two-terminal resistance variable memory manufactured according to the embodiment of the present invention, the resistance change memory manufactured according to Examples 1 to 5, The thickness of the depletion layer was extracted by the following method, and the results are shown in FIG. 12 .

That is, after measuring the total capacitance of the device through capacitance-voltage measurement, the capacitance value measured in a single Al ₂ O ₃ was substituted to extract the depletion layer capacitance value, and the thickness of the depletion layer was calculated through the following equation.

C _d = capacitance of the depletion layer, ε _s = dielectric constant of the semiconductor layer W: thickness of the depletion layer

As shown in FIG. 12 , in the resistance variable memory manufactured according to Examples 1 to 5, it can be seen that the thickness of the depletion layer is 2.5 to 3.5 nm in the low resistance state and 4.5 to 5.5 nm in the high resistance state. . That is, in the two-terminal resistance variable memory manufactured according to the embodiment of the present invention, it can be seen that the thickness change of the depletion layer according to the change in the thickness of the insulator layer is insignificant.

<Experimental Example 4>

In order to confirm the durability of the two-terminal resistance change memory manufactured according to the embodiment of the present invention, that is, the stability over time, for the resistance change memory manufactured according to Example 4, the output current value according to time was analyzed. , the results are shown in FIG. 13 .

As shown in FIG. 13 , in the case of the two-terminal resistance variable memory manufactured according to the embodiment of the present invention, it can be seen that the current value is maintained very stably for a time of 1000 s, and through this, the stability over time is very excellent. it can be seen that

<Experimental Example 5> Evaluation of rectification characteristics according to the type of the second metal

In order to evaluate the rectification characteristics of the two-terminal resistive memory manufactured according to an embodiment of the present invention, the voltage-current characteristics of the two-terminal resistive memory manufactured in Examples 1 and 6 were measured, and the results are shown in FIG. 14 . It was.

As shown in FIG. 14 , it can be seen that Example 1 exhibits a rectification characteristic, whereas Example 6 has a lower rectification characteristic.

In Example 1, gold (Au) is used as the first metal and platinum (Pt) having a larger work function than gold (Au) is used as the second metal in contact with the semiconductor layer, between the IGZO semiconductor layer and the second metal layer. On the other hand, in Example 6, gold (Au) was used as the first metal and aluminum (Al) having a work function smaller than that of gold (Au) as the second metal in contact with the semiconductor layer. Because it used, it can be seen that it is because of the ohmic contact (omic contact) between the IGZO semiconductor layer and the aluminum (Al) Ti-Pt metal layer.

Through this, it can be seen that the work function of the second metal must be equal to or greater than that of the first metal in order to secure better self-rectification characteristics.

1: Cross-point array structure memory system
10: first metal layer
20: insulator layer
30: semiconductor layer
31: resistance change layer
40: second metal layer
100: 2-terminal resistance change memory
200, 201, 202, 203, 204: first word line
300, 301, 302, 303, 304: second word line
400, 401, 402, 403, 404: bit line
500: first memory cell
501: first insulator layer
502: first semiconductor layer
600: second memory cell
601: second insulator layer
602: second semiconductor layer

Claims (16)

a first metal layer;
an insulator layer disposed on the first metal layer, having a thickness of 1 to 15 nm, and including an insulating metal oxide;
a semiconductor layer disposed on the insulator layer; and
and a second metal layer disposed on the semiconductor layer.
The method of claim 1,
wherein the insulating metal oxide has a bandgap of 5eV to 10eV.
The method of claim 1,
The two-terminal resistance change memory, characterized in that the insulating metal oxide has a dielectric constant of 5 to 12.
The method of claim 1,
wherein the insulating metal oxide comprises at least one selected from _{Al 2} O ₃ , HfO ₂ , ZrO _{2 and MgO.}
The method of claim 1,
The semiconductor layer is a two-terminal resistance variable memory, characterized in that made of an N-type semiconductor.
The method of claim 1,
wherein the semiconductor layer includes a metal oxide including at least one of indium (In), gallium (Ga), tin (Sn), and zinc (Zn).
The method of claim 1,
wherein the semiconductor layer includes a resistance change layer disposed on one surface in contact with the insulator layer.
The method of claim 1,
wherein the two-terminal resistance change memory changes resistance by changing the thickness of the resistance change layer.
The method of claim 1,
The two-terminal resistance change memory is a two-terminal resistance change memory, characterized in that it has a self-rectifying function.
The method of claim 1,
wherein an interface between the semiconductor layer and the second metal layer has a Schottky barrier.
The method of claim 1,
The two-terminal resistance variable memory, characterized in that the work function of the first metal layer is equal to or smaller than the work function of the second metal layer.
The method of claim 1,
The first metal layer is made of a metal having a work function of 4.0 eV to 4.5 eV,
The insulator layer is made _{of Al 2} O _3,
The semiconductor layer is made of In-Ga-Zn oxide (IGZO),
wherein the second metal layer is made of a metal having a work function of 4.5 eV to 5 eV.
forming a semiconductor layer on the second metal layer;
forming an insulator layer having a thickness of 1 to 15 nm on the semiconductor layer; and
and forming a first metal layer on the insulator layer.
14. The method of claim 13,
The method of manufacturing the two-terminal resistive memory is characterized in that the two-terminal resistive memory having a self-rectifying function is manufactured.
a plurality of first word lines spaced apart from each other in a first direction;
a plurality of bit lines disposed on the word line and spaced apart from each other in a second direction perpendicular to the first direction;
a plurality of first semiconductor layers disposed at each intersection of the first word line and the bit line, the first semiconductor layer stacked in the first word line direction from the bit line, and a first insulator layer having a thickness of 1 to 15 nm a first memory cell;
a plurality of second word lines disposed on the bit line and spaced apart from each other in a first direction; and
a plurality of second semiconductor layers disposed at intersections of the bit lines and second word lines, respectively, and stacked in a direction from the bit lines to the second word lines; and a second insulator layer having a thickness of 1 to 15 nm. a second memory cell;
The memory system of a crosspoint array structure, wherein the first memory cell and the second memory cell perform a self-rectifying function.
16. The method of claim 15,
The first memory cell includes a 1-1 metal layer, a first insulator layer having a thickness of 1 to 15 nm, a first semiconductor layer, and a 1-2 metal layer stacked from the bit line to the first word line direction. do,
The second memory cell includes a 2-1 metal layer stacked in a direction from the bit line to the second word line, a second insulator layer having a thickness of 1 to 15 nm, a second semiconductor layer, and a 2-2 metal layer. Cross-point array structure memory system, characterized in that.

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