KR20210120630A - Embedded multi-die flip chip bonding packages - Google Patents

Abstract

Provided is a flip chip package having at least one die embedded therein. The flip chip package includes: a printed circuit board having a plurality of package bumps formed on one surface; a package pad formed of a plurality of layers to be mounted on an upper surface of the package bumps and providing an arbitrary position on the upper surface in which the plurality of layers are removed from an upper top side layer to an arbitrary intermediate layer; at least one buried die buried in a position from which the plurality of layers are removed from the package pad; and a plurality of micro bumps formed between the intermediate layer of the package pad and the buried die, and electrically connecting the buried die to the printed circuit board. As the signal transmission distance is dramatically reduced, delay, noise, and power consumption are reduced, so as to improve the electrical signal delay.

Description

Multi-die embedded flip chip bonding packages

The present invention relates to a multi die buried flip chip package.

A semiconductor wafer contains hundreds or thousands of semiconductor chips on which identical electrical circuits are printed. Since each semiconductor chip cannot communicate with the outside by itself, it is a semiconductor packaging process to connect electrical wires to each of the semiconductor chips so that they can communicate with the outside and then package the semiconductor chips.

And, with the development of the electronic industry, the demand for high-functionality, high-speed, and miniaturization of electronic components is increasing. In response to this trend, various mounting technologies are being studied. Among them, the flip chip bonding method is a method in which a chip and a substrate are in a state facing each other, and a connection from a pad of a chip to a substrate is connected using a solder bump or the like.

Compared to the wire bonding method, the flip chip bonding method can maintain a connection distance between the pads very short, thereby improving the signal transmission speed. Nevertheless, it is facing technical difficulties such as reducing the gap between devices, increasing the aspect ratio, and limiting the improvement of semiconductor performance and integration.

In addition, more than 50% of the total electrical signal delay of the actual high-speed electronic product is caused by the packaging delay occurring between the chip and the chip. Accordingly, semiconductor packaging technology is recognized as important, and in particular, the development of semiconductor packaging technology capable of improving electrical signal delay is required.

Accordingly, the present invention provides a multi-die buried flip chip package in which at least one die is embedded.

A die-embedded flip-chip package, which is one feature of the present invention for achieving the technical problem of the present invention, is

A printed circuit board having a plurality of package bumps formed on one surface, a plurality of layers is formed and mounted on the top surface of the package bumps, and a plurality of layers are removed from an upper top side layer to an arbitrary intermediate layer at an arbitrary position on the top surface. a package pad, at least one buried die buried in a position where the plurality of layers are removed from the package pad, and formed between an intermediate layer of the package pad and the buried die, wherein the buried die is printed and a plurality of micro bumps electrically connected to the circuit board.

A top surface of the at least one buried die may not protrude above the top surface of the package pad.

and a stacked die mounted on a portion of the top surface of one of said buried die.

and a plurality of first stacked die micro bumps formed between the stacking die and the buried die, and electrically connecting the stacked die to the printed circuit board through the embedding die.

A plurality of second stacked die micro bumps are formed between the stacked die and the package pad and electrically connect the stacked die to the printed circuit board.

A plurality of stacking dies may be mounted on a portion of an upper surface of the buried die.

A die may be vertically stacked on a portion of an upper surface of the plurality of stacked dies.

and a plurality of third micro bumps formed between the vertically stacked die and the stacked dies and electrically connecting the vertically stacked die to the printed circuit board through the stacked die and the buried die.

and a plurality of fourth micro bumps formed between the vertically stacked die and the buried die and electrically connecting the vertically stacked die to the printed circuit board, wherein the fourth micro bumps have a size of the third micro bumps. It may be larger than the size of the bumps.

According to the present invention, since dies communicating with each other are configured in one package, a signal transmission distance is remarkably reduced, delay, noise, and power consumption are reduced, thereby improving electrical signal delay.

In addition, since two or more chips are partially vertically stacked, high-speed signal transmission and reception between two dies is possible, and since there is no need for connection with a package ball to transmit high-speed signals for each chip in the stacked portion, the package pad Due to its small size, it can be competitively priced.

1 is an exemplary diagram of a typical flip chip package.
2 is an exemplary diagram of a die buried flip chip package according to a first embodiment of the present invention.
3 is another exemplary diagram of a die buried flip chip package according to the first embodiment of the present invention.
4 is an exemplary diagram of a multi-die buried flip chip package according to a second embodiment of the present invention.
5 to 10 are exemplary diagrams of a multi-die buried flip-chip package according to a third embodiment of the present invention.
11A to 11E are diagrams illustrating various types of flip chip packages according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

Throughout the specification, when a part "includes" a certain element, it means that other elements may be further included, rather than excluding other elements, unless otherwise stated.

Hereinafter, a multi-die buried flip chip package according to an embodiment of the present invention will be described with reference to the drawings. Prior to describing an embodiment of the present invention, a general one-die flip chip package will be described with reference to FIG. 1 .

1 is an exemplary diagram of a typical flip chip package.

FIG. 1A illustrates a case in which the package pad 40 has six layers as an example, and FIG. 1B illustrates a case in which the package pad 70 has four layers. In addition, (c) of FIG. 1 shows a path through which two pieces of package pads 70 are formed on one PCB 20, and signals are transmitted/received between the two chips.

As shown in (a) to (c) of FIG. 1 , the flip chip package 10 starts from the die 60 and passes through the micro bump 50 and the package pad 40 , the package bump ( 30) through the PCB 20, through which it is possible to communicate with the outside.

The flip chip package 10 has better electrical characteristics than the wire bonding method, and there is no height of the wire bonding loop, so that the chip mounting density can be increased in a small area. In addition, since the flip chip bonding method can use the entire surface of the die 60 as an electrical connection path, the number of input/output terminals can be increased.

As described above, although the general flip-chip package can keep the connection distance between the pads shorter than the wire bonding method, thereby improving the signal transmission speed, the chip and the PCB still composed of the micro bumps 50 and the die 60 The distance between (20) causes an electrical signal delay in phosphorus.

That is, it is assumed that a signal is transmitted/received between two chips as shown in FIG. 1(c). Then, the signal processed by the first die 61 is the first micro bump 51 - the first package pad 71 - the first package bump 31 - the PCB 20 - the second package bump 32 - The second package pad 72 - the second micro bump 52 - is transferred to the neighboring chip through the path of the second die 62 . Therefore, due to the distance between the chip and the PCB 20, a delay in the electrical signal is generated.

Accordingly, in the embodiment of the present invention, at least one die is embedded in the package pad to improve the delay of the electric signal and to generate one flip chip package including a plurality of dies. This will be described with reference to the drawings below.

2 is an exemplary diagram of a die buried flip chip package according to a first embodiment of the present invention.

As shown in FIG. 2 , in the embodiment of the present invention, a chip 110 including one die 111 and a plurality of micro bumps 112 may be packaged by seating at least one die 111 . Instead of being adhered to the pad (hereinafter, referred to as a 'package pad' for convenience of description) 120 , it is embedded in the package pad 120 .

In FIG. 2, an example of using a 6-layer printed circuit board (PCB) as a package pad will be described. However, since the printed circuit board of the four layers may be used as the package pad, and other boards performing the function of the printed circuit board may also be used as the package pad, the present invention is not limited thereto.

This is implemented by removing a portion of the first substrate 121 from the package pad 120 and inserting the chip 110 at the removed position.

Here, the first substrate 121 includes a first layer 121-1 serving as a top side layer, a substrate, and a second layer 121-2. In the embodiment of the present invention according to FIG. 2, since a 6-layer printed circuit board on which three substrates are overlapped is used, the first substrate, the second substrate, and the third substrate are referred to for convenience of description. At this time, the layers described in the description according to the embodiment of the present invention will be described using the copper wiring printed on the substrates 121 to 123 as an example, but any material that can transmit an electrical signal may be substituted. ,

The plurality of micro bumps 112 of the inserted chip 110 are connected to the third layer 122-1 of the second substrate 122 . At this time, the thickness of the die 111 is adjusted so that one surface of the die 111 of the chip 110 , that is, the surface to which the micro bumps 112 are not attached does not protrude out of the package pad 120 . In the embodiment of the present invention, the control of the thickness of the die 111 is described as an example, but by increasing the size of the micro bump 112 or adjusting the thickness of the substrates 121 and 122, one surface of the die 111 is It may be adjusted so as not to protrude out of the package pad 120 . However, in the embodiment of the present invention, it will be described that the thickness of the die 111 is adjusted for convenience of description.

Here, a method in which the signal processed by the die 111 moves to the PCB 140 through the micro bump 112 , the package pad 120 , and the package bump 130 is already known. A description is omitted. In addition, since the material and size of the micro bump 112 , the package pad 120 , and the package bump 130 may be implemented in various ways, the embodiment of the present invention is not limited to any one material and size.

As described above, by embedding the chip 110 in the package pad 120 and connecting the micro bumps 112 to the third layer 122-1, the gap between the micro bumps 112 and the package bumps 130 is reduced. It will be shorter than the conventional flip chip package. Accordingly, it is possible to reduce the delay of the electrical signal.

The flip chip package according to the first embodiment of the present invention may be implemented in another form as shown in FIG. 3 below.

3 is another exemplary diagram of a die buried flip chip package according to the first embodiment of the present invention.

FIG. 3A illustrates a package pad 120 including six metal layers, from the first layer 121-1 to the fourth layer 122-2, that is, the first substrate 121 and the second layer. It is an exemplary view implemented by removing a portion of the substrate 122 and embedding the chip 110 so that the micro bumps 112 are connected to the fifth layer 123 - 1 . And Fig. 3 (b) is an exemplary view when the package pad 120 is composed of a four-layer printed circuit board.

As shown in (a) of FIG. 3 , when the micro bumps 112 of the chip 110 are in contact with the fifth layer 123 - 1 , the thickness of the die 111 is determined by the die shown in FIG. 2 . It is implemented thicker than the thickness of (111). Even in this case, the thickness of the die 111 is adjusted so that one side of the die 111 on which the micro bumps 112 are not formed does not protrude out of the package pad 120 , or the first substrate 121 and the first substrate 121 are formed. 2 The thickness of the substrate 122 may be adjusted, or the size of the micro bumps 112 may be adjusted.

And, as shown in FIG. 3B , even if the package pad 150 is composed of four layers, a part of the first substrate 151 is removed and the chip 110 is inserted into the removed position. can be implemented Even when implemented as shown in FIG. 3B , the thickness of the die 111 may be adjusted so that the chip 110 does not protrude out of the package pad 120 , or the thickness of the removed substrate 151 may be adjusted. .

In the first embodiment of FIGS. 2 and 3, one chip is embedded in a flip chip package as an example. However, in order to increase the processing speed of different dies, one chip is embedded and a portion of the embedded chip Other chips may be stacked, ie mounted, perpendicular to the . This will be described with reference to FIG. 4 .

The package pad of the flip chip package according to various embodiments to be described later is described as using a 6-layer printed circuit board for convenience of explanation, but as shown in FIG. 3(b), a 4-layer printed circuit board can also be used. Also, for convenience of description, the micro-bump is illustrated as being connected to the third layer, but it may be implemented by modifying it to be connected to the fifth layer as shown in FIG. 2A .

4 is an exemplary diagram of a multi-die buried flip chip package according to a second embodiment of the present invention.

When a plurality of chips are vertically stacked at the same location, various factors such as bonding alignment, wafer warpage, wafer warpage, bonding reliability, and inspection must be considered. Accordingly, in the embodiment of the present invention, chips are vertically stacked in a staggered structure so that a part of another chip overlaps a part of the chip inserted into the package pad.

In this case, for convenience of description, a chip embedded in the package pad is referred to as a 'buried chip', and a chip stacked vertically on a portion of the embedded chip is referred to as a 'stacked chip', but the present invention is not limited thereto.

That is, as shown in FIG. 4 , the buried chip 160 is embedded in the package pad 120 , and a part of the stacked chip 170 is vertically stacked so as to overlap a part of the buried chip 160 . In the embodiment of the present invention, it is described as an example that the three micro bumps among the micro bumps of the stacked chip 170 and the three micro bumps of the buried chip 160 are connected to each other as an example, but the present invention is not limited thereto. .

At this time, the first part (①) of the stacked chip 170 is used to transmit a high-speed signal through which close mutual communication with the embedded chip 160 is made. And since the micro bumps configured in the second part (②) are connected to the PCB 140 like micro bumps of a general flip chip, the micro bumps in the first part (①) transmit signals at a general speed due to a relatively delay than the micro bumps of the first part (①). It is transferred to the PCB (140). Accordingly, different signal transmission rates can be implemented even with a single chip.

Next, various examples of forming a flip chip package with three or more dies will be described with reference to FIGS. 5 to 10 .

5 to 10 are exemplary diagrams of a multi-die buried flip-chip package according to a third embodiment of the present invention.

As shown in FIG. 5 , two stacked chips 171 and 172 may be stacked as both first and second parts of the buried chip 160 .

Alternatively, as shown in FIG. 6 , the stacked chip 173 may be stacked not only on the first and second portions on both sides of the buried chip 160 , but also on the third portion at the center of the buried chip 160 . .

In addition, as shown in FIG. 7 , the first stacked chip 171 and the second stacked chip 172 are stacked on the first part and the second part corresponding to a part of the buried chip 160 , respectively, and the stacked chips are stacked. Another third stacked chip 174 may be stacked vertically over the first stacked chip 171 and the second stacked chip 172 . At this time, the first part (③), which is a part of another stacked chip 174, is connected to the buried chip 160 through the second stacked chip 172, and the second part (④), which is another part, is connected to the first It is connected to the buried chip 160 through the stacked chip 171 .

In FIG. 7 , micro bumps 112 are not formed in a portion where the third stacked chip 174 is not connected to the first stacked chip 172 and the second stacked chip 172 , so that it is not connected to the buried chip 160 . It is shown as an example.

However, as shown in FIG. 8 , the sizes of the micro bumps 114 in the portions ⑤ in which the micro bumps are not formed among the third stacked chips 174 , the first stacked chip 171 and the second stacked chip 172 , are determined as shown in FIG. 8 . It may be set to be different from the size of the micro bumps 112 connected to the , so as to be connected to the die 111 of the embedded chip 160 .

In addition, although one chip is embedded in the package pad 120 in FIGS. 2 to 7 , a plurality of chips are embedded in the package pad 120 and stacked vertically on a portion of the embedded embedded chip. may be laminated. That is, as shown in FIG. 9 , two buried chips 181 and 182 are buried in the package pad 120 with a predetermined interval therebetween, and work is performed in the first buried chip 181 and the second buried chip 182 . The stacked chips 170 may be stacked so that portions overlap each other.

Also, as shown in FIG. 10 , a third stacked chip 183 may be additionally stacked on an upper portion of the two stacked chips 181 and 182 . In addition, the third stacked chip 173 may be connected to the package pad 120 .

Next, an example in which a plurality of flip chips are connected to the die of the buried chip 160 in the above-described various types of flip chip packages will be described with reference to FIG. 11 .

11A to 11E are diagrams illustrating various types of flip chip packages according to an embodiment of the present invention.

One stacked chip 170 is mounted on one buried chip 110 as shown in FIG. 11A , or a plurality of stacked chips 170 are mounted on one buried chip 110 as shown in FIG. 11B . can be Also, a plurality of stacked chips 170 may be mounted on the plurality of buried chips 110 in FIGS. 11C to 11E .

Also, as shown in FIG. 11D , the micro bumps of the plurality of buried chips 110 may be connected to different layers. That is, the micro bumps of one buried chip may be connected to the third layer 122-1, and the micro bumps of another buried chip may be connected to the fifth layer 123-1.

As described above, the processing speed may be improved by reducing noise and power consumption or vertically stacking dies having different processing speeds through one or more die buried flip chip packages implemented in various forms.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improved forms of the present invention are also provided by those skilled in the art using the basic concept of the present invention as defined in the following claims. is within the scope of the right.

Claims (9)

A printed circuit board having a plurality of package bumps formed on one surface,
A package pad formed of a plurality of layers and mounted on the top surface of the package bumps, from which a plurality of layers are removed from an upper top side layer to an arbitrary intermediate layer at an arbitrary position on the top surface;
at least one buried die buried in a position in which the plurality of layers are removed from the package pad; and
a plurality of micro bumps formed between the intermediate layer of the package pad and the buried die and electrically connecting the buried die to the printed circuit board
A die embedded flip chip package comprising: According to claim 1,
and a top surface of the at least one buried die does not protrude above a top surface of the package pad. According to claim 1,
A stacked die mounted on a portion of the top surface of one of the buried die
A die embedded flip chip package comprising: 4. The method of claim 3,
A plurality of first stacked die micro bumps are formed between the stacked die and the buried die and electrically connect the stacked die to the printed circuit board through the buried die.
A die embedded flip chip package comprising: 5. The method of claim 4,
a plurality of second stacked die micro bumps formed between the stacked die and the package pad and electrically connect the stacked die to the printed circuit board
A die embedded flip chip package comprising: 4. The method of claim 3,
wherein a plurality of the stacked dies are mounted on a portion of an upper surface of the buried die. 7. The method of claim 6,
A die buried flip chip package, wherein a die is vertically stacked on a portion of an upper surface of the plurality of stacked dies. 8. The method of claim 7,
a plurality of third micro bumps formed between the vertically stacked die and the stacked dies and electrically connecting the vertically stacked die to the printed circuit board through the stacked die and the buried die;
Further comprising a die embedded flip chip package. 9. The method of claim 8,
a plurality of fourth micro bumps formed between the vertically stacked die and the buried die and electrically connecting the vertically stacked die to the printed circuit board;
and a size of the fourth micro bumps is larger than a size of the third micro bumps.

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