KR20210119591A - Low-power selector with graphene edge - Google Patents

Abstract

A resistive memory having a low power selector in accordance with the present invention is provided. The resistive memory includes: an upper electrode; a graphene layer disposed under the upper electrode and having a graphene electrode formed in an edge region; and a selector layer including a selector formed between the upper electrode and the graphene electrode.

Description

Low-power selector with graphene edge

FIELD OF THE INVENTION The present invention relates to a low power selector in a resistive memory. More specifically, it relates to a low-power selector using the edge of graphene.

Resistive memory is considered as a key hardware element in the implementation of complex neuromorphic networks due to its simple structure and small size, which are easy to manufacture. However, an increase in leakage current and unstable operation occur due to the sneak path phenomenon, which is a disadvantage when integrating a resistive memory. To compensate for this, a selector material is applied to the resistive memory.

Although the integration and miniaturization of the existing resistive memory devices have progressed a lot, the possibility of integration and miniaturization of the selector material is uncertain. This is because the effect of electric fields on this is difficult to understand because most selector materials are unlikely to form conductive filaments.

Accordingly, an object of the present invention is to provide a low-power selector using an edge of graphene in order to solve the above-described problem.

In addition, an object of the present invention is to reduce the leakage current of a resistive RAM (RRAM) and stably drive it by applying a CuGeS chalcogen material to the graphene edge.

A resistive memory having a low power selector according to the present invention for solving the above problems is provided. The resistive memory includes an upper electrode; a graphene layer disposed under the upper electrode and having a graphene electrode formed in an edge region; and a selector layer including a selector formed between the upper electrode and the graphene electrode.

According to an embodiment, the upper electrode may be configured as a TiN electrode, and an edge region of the graphene layer may be configured as a graphene edge electrode.

According to an embodiment, the selector may be formed of a chalcogenide selector made of a chalcogenide material.

According to an embodiment, the selector may be a CuGeS selector made of a CuGeS chalcogenide material.

According to an embodiment, the graphene layer may be composed of a graphene layer of 0.3 nm or less, and an edge region of the graphene layer may be formed as an electrode of the resistive memory.

According to an embodiment, a Pt electrode configured to be bonded to the graphene layer may be further included, and the Pt electrode may be formed to be thicker than a thickness of the graphene layer.

According to an embodiment, the TiN electrode may include a first electrode region and a second electrode region formed below the first electrode region by a predetermined height.

According to an embodiment, the TiN electrode may further include a vertical connection part vertically connecting the first electrode region and the second electrode region.

According to an embodiment, the selector includes a first region and a second region formed below the first region by a predetermined height, and the first region and the second region of the selector are the TiN electrode. It may be configured to be bonded to the first electrode region and the second electrode region.

According to an embodiment, the selector may further include a vertical connection part vertically connecting the first area and the second area.

According to an embodiment, the graphene layer includes a first graphene layer and a second graphene layer disposed under the first graphene layer, and a memory is disposed between the upper electrode and the first graphene layer. It may include a vertically structured memory cell formed of a material.

According to an embodiment, the vertical structure memory cell may be configured to be bonded to the first graphene layer and the second graphene layer.

According to an embodiment, the graphene layer further includes a third graphene layer disposed under the second graphene layer, and the vertical structure memory cell includes the first graphene layer to the third graphene layer. It may be configured to bond with the layer.

A non-volatile memory is provided according to another aspect of the present invention. The inactive memory may include an upper electrode; a graphene layer disposed under the upper electrode and having a graphene electrode formed in an edge region; a selector layer including a selector formed between the upper electrode and the graphene electrode; and a vertical structure memory cell formed of a memory material between the upper electrode and the graphene layer.

According to an embodiment, the vertical memory cell is a vertical memory cell disposed in a plurality of columns and rows between the upper electrode and the graphene layer.

According to an embodiment, the upper electrode may be configured as a TiN electrode, and an edge region of the graphene layer may be configured as a graphene edge electrode.

According to an embodiment, the selector is a CuGeS selector made of a CuGeS chalcogenide material.

According to an embodiment, the graphene layer may be composed of a graphene layer of 0.3 nm or less, and an edge region of the graphene layer may be formed as an electrode of the vertical structure resistance memory.

According to an embodiment, the inactive memory may be configured as a resistive random access memory (RRAM), and a resistance strength may be changed according to past information of a previously flowing current.

According to an embodiment, the RRAM is operatively coupled to a neuromorphic processor, and when a voltage greater than or equal to a threshold is applied from the neuromorphic processor, the device resistance of the vertical structure resistance memory is applied with a voltage equal to or less than the threshold. When the resistance value is changed to a lower resistance value than that in the case where a voltage lower than the threshold value is applied, the device resistance may be changed back to the previous resistance value.

According to the present invention, a CuGeS chalcogenide material using an atomically thin (0.3 nm) edge of graphene as an electrode can be applied as a selector to overcome the above-mentioned problems.

In addition, according to the present invention, the graphene edge electrode increases the resistance of the electrode-selector interface compared to the thick metal-based electrode, resulting in a decrease in OFF-state leakage current. When the CuGeS selector is embedded in the vertical structure, the thin graphene edge electrode and the wide TiN filler electrode show I-V characteristics with large asymmetric current distribution. This phenomenon is due to the ion congestion effect, which is strongly dependent on the voltage polarity and Cu ion transport direction.

In addition, according to the present invention, when the selector to which the graphene edge is applied and the RRAM are combined, the leakage current is ^{reduced up to 10 3} times and the memory window is increased.

In addition, according to the present invention, the degree of integration is increased by using thin graphene, and the advantage of a small leakage current can be derived by using a selector, so that it can be applied to the field of electronics and electricity. In particular, when applied to a resistive memory, it can solve the sneak path problem, so it can be applied to the memory semiconductor field.

In addition, according to the present invention, as a result, the low-power selector using the graphene edge can not only increase the degree of integration by using a thin two-dimensional material, but also significantly reduce the leakage current because the interface resistance between the electrode and the selector increases. . In addition, when applied to resistive memory, it has the advantage of supplementing the sneak path problem.

Currently, the digital and analog industries are based on silicon bulk semiconductors, but as the degree of integration of semiconductor circuits becomes more and more important, the application of thin two-dimensional materials and reduction of leakage current are important. Considering this, a low-power selector using graphene edges can be an important basis for ultra-high-density 3D memory.

The features and effects of the present invention described above will become more apparent through the following detailed description in relation to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention. will be able

1 shows a structure and component mapping relationship for a graphene edge electrode and a Cu-based chalcogenide selector according to the present invention.
Fig. 2 shows the mechanism of operation of the selector field according to the present invention;
Figure 3 shows the IV characteristics of the graphene chalcogenide selector showing the opposite polarity according to the present invention.
4 shows IV characteristics of graphene edge RRAM according to various examples according to the present invention.
5 shows IV characteristics and resistance characteristics of a 1S-1R graphene edge device according to the present invention.
6 shows the overall structure of a low-power selector using a graphene edge, and images of transmission electron microscopy and energy dispersive spectroscopy.

The features and effects of the present invention described above will become more apparent through the following detailed description in relation to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention. will be able

Since the present invention can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to a specific embodiment, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

In describing each figure, like reference numerals are used for like elements.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. and/or includes a combination of a plurality of related listed items or any of a plurality of related listed items.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present application. shouldn't

The suffix module, block, and part for the components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have distinct meanings or roles by themselves.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings so that a person skilled in the art can easily implement it. In the following description of embodiments of the present invention, if it is determined that a detailed description of a related known function or a known configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Cu-based chalcogenides are solid electrolytes with large amounts of Cu + ions that facilitate the flow of current under certain conditions. These materials can be easily deposited as thin fillers to form selector devices embedded in the memory layer. can These thin-film-based selectors are particularly suitable for the case of 3D vertical architectures, as these pillars do not require large selector devices (eg vertical transistors) and large ON/OFF ratios can be achieved with RRAM. Point architectures are preferable compared to simple planar junction architectures because there are fewer critical lithography steps for each layer and lower integration costs.

The 3D vertical architecture density is directly affected by the thickness of the planar electrode of each memory stack. In this regard, metal-oxide RRAMs can be scaled vertically to the atomic limit using graphene-edge electrodes. However, integrating a thin selector into a high-density 3D vertical architecture requires consideration of the memory and expandability of the selector. In this regard, there is no consideration for the scaling property of the selector other than the study on the scaling of the RRAM. In this specification, we intend to explain the ultimate scalability of CuGeS using an atomically thin single-layer graphene edge electrode with a 3D vertical structure. Together with the selector device, these vertical scale electrodes reduce leakage current and improve the selectivity of the memory window and memory layer.

In this regard, Figure 1 shows the structure and component mapping relationship for the graphene edge electrode and Cu-based chalcogenide selector according to the present invention. Specifically, Fig. 1 (a) is a schematic diagram of a Cu-based chalcogenide selector with a graphene edge electrode of a 3D vertical structure. 1B is an istropic view of a selector with a graphene edge electrode. Figure 1 (c) is an SEM image of the device. In this regard, scale bar: 200 nm, inset: high-resolution TEM image; Scale bar: 50 nm. Fig. 1(d) relates to element mapping of the device cross-section. In this regard, Cu, blue; Ge, red; S, emerald; Ti, green; Si, orange; O, marked in pink. On the other hand, the Cu distribution is represented by two bands due to the Cu grid at the top.

1A and B show schematics of a front view and an isometric view of a Cu-based chalcogenide selector with graphene edge electrodes. TiN and graphene edge electrodes act as top and bottom electrodes, respectively, with a CuGeS chalcogenide selector layer interposed therebetween.

1C shows a scanning electron microscope (SEM) image of the device with a transmission electron microscope (TEM) image in an inset. A memory cell with only one single layer may be considered herein to simplify analysis. It can be observed that the optimal thickness of the CuGeS layer for operation with the RRAM cell is 20 nm. Thicker layers resulted in higher threshold voltage requirements, which were not ideal for device performance. On the other hand, a thinner layer can increase the ohmic conduction with more tunneling current. Distributed mobile ions and other elements were observed by energy dispersive spectroscopy (EDS), which can be represented as a color-coded map in FIG. 1d .

The stoichiometry of the chalcogenide layer in the present invention can be considered particularly important in 3D vertical memory architectures. Unlike the simple junction structure, a significant difference can be observed between the regions of the columnar electrode (TiN) and the planar electrode (graphene) in the 3D vertical structure. Therefore, a high concentration of Cu+ ions accumulate near the graphene edge compared to thick Pt when a negative bias is applied due to the higher electric field concentration near the sharp edge of the graphene.

On the other hand, Figure 2 shows the operation mechanism of the selector field according to the present invention. Specifically, Fig. 2(a) shows an operation mechanism of the selector device at a lower bias and Fig. 2(b) at a higher bias. Fig. 2 (c) shows the potential distribution of the selector device at a lower bias and (d) a higher bias. 2(e) and (f) show the mechanism of action of Pt and Gr chalcogenide selectors. Figure 2 (g) shows the I-V characteristics of the Pt and graphene-based selector device.

In Fig. 2(a), Cu + ions migrate towards the cathode when a bias is applied across the electrode until a balance between the force of the electric field and the concentration gradient is reached. The potential difference from the transferred charge causes polarization at the electrode boundary, resulting in a double layer. The portion with the high concentration gradient of ions is referred to as the dispersion layer (Figs. 2(a), (c)). For the reduction-oxidation process to occur in the double layer, the applied potential must overcome the potential associated with the double layer, also referred to as overpotential. Below the threshold voltage, a small current is observed due to electron tunneling through the double layer. Above the threshold, Cu + ions decrease near the electrode, resulting in a large ion current flow (Fig. 2(b), (d)). Once a Cu layer is formed on the cathode, this layer acts like a new cathode, and the overpotential for further reduction of Cu is reduced. This action allows an additional ionic current to flow through the junction.

In this specification, we compared the properties of planar electrodes with two different thicknesses using an atomically thin graphene-edge electrode and a thick metal (Pt) electrode. In a previous report, the edge of a single graphene layer (0.3 nm thick) was used as one electrode in a metal-oxide RRAM. These thin electrodes form a significantly thin active memory layer in the 3D vertical structure, increasing the number of stacks and the density of chips. The electrodes were observed to exhibit low power consumption and programming voltage/current. It should be noted that thin metal #lm below 5 nm deposited by conventional e-beam evaporation tends to form discontinuous islands, and a sharp non-linear increase in sheet resistance can be observed as the thickness decreases. Therefore, a much thicker electrode is required if a metal such as Pt is used instead of graphene.

In this regard, as the electrode thickness increases, the interfacial resistance between the metal and the chalcogenide compound selector decreases, resulting in a large leakage current in the OFF state. For atomically thin graphene edge electrodes, the interface resistance increases, which naturally reduces leakage current. Figures 2(e) and (f) show two different operating mechanisms for selectors while using metal (Pt selector) or graphene (Gr selector) as electrodes. As shown in Fig. 2e, since the junction area between Cu chalcogenide and Pt is large, the interfacial resistance of the Pt selector is lower than that of the Gr selector. Therefore, the Pt selector has high conductivity at low voltage bias. In contrast, as shown in Fig. 2f, the interfacial resistance of the Gr selector is higher than that of the Pt selector due to the graphene thickness. Figure 2g shows two I-V characteristics.

In this regard, the electrode scaling effect on the chalcogenide selector can be applied to both sides of the Gr selector structure. Asymmetric I-V characteristics of the Gr selector are observed depending on the polarity of the applied voltage.

On the other hand, Figure 3 shows the I-V characteristics of the graphene chalcogenide selector showing the opposite polarity according to the present invention. Figure 3 (a) is graphene and Figure 3 (b) shows a schematic diagram of the device for ion migration with a positive bias applied to the TiN electrode, respectively. Figure 3 (c) shows the I-V characteristics of the ion movement in which a positive bias is applied to the graphene and (d) TiN electrodes, respectively.

Figures 3(a) and (b) show the operating mechanism of the Gr selector in the case of opposite voltage polarity. As shown in Fig. 3(a), when a positive voltage is applied to the graphene electrode, the electric field is concentrated near the edge of the graphene due to its distribution characteristics. Therefore, Cu + ions can be easily transferred to the wide TiN electrode, causing a large current. In contrast, when a positive voltage is applied to the TiN electrode (Fig. 3(b)), a high concentration of Cu + ions can be observed near the graphene edge, causing a current concentration effect. Therefore, when a positive voltage is applied to the TiN electrode, the threshold voltage is large and the leakage current is small. A direct result of this physical phenomenon can be confirmed in the I-V characteristics of FIGS. 3(c) and (d). The Pt selector may be a near-zero bias selector with greater leakage current than the Gr selector. The elemental composition ratio was the same in both samples. As shown in Fig. 2(g), the Pt selector exhibits an ohmic characteristic and the current to the Gr selector increases exponentially.

4 shows IV characteristics of graphene edge RRAM according to various examples according to the present invention. Specifically, (a) and (b) of FIG. 4 are IV characteristics of a graphene edge RRAM without a selector layer, and the TiN layer is an anode in both cases. Fig. 4(c) compares the IV curves of the 1S1R structure and various edge electrode materials (graphene and Pt). Figure 4(d) shows the SET and RESET voltage distributions of the graphene RRAM according to the presence or absence of the selector layer. 4(e) shows the resistance distribution of graphene according to the presence or absence of a selector layer. The memory window of the 1S1R structure is larger than that of graphene RRAM without a selector. _{Figure 4 (f) shows the 1/3 V read} current distribution of graphene according to the presence or absence of a selector layer.

IV characteristics of the graphene edge RRAM according to the presence or absence of the graphene electrode can be experimentally obtained (Figs. 4(a) and (b), respectively). As shown in Fig. 4(a), the nonlinearity coefficients of the RRAM according to the presence or absence of the selector layer are 1.9 × 10 ³ and 5.41, respectively. A comparison of the 1S1R structure with two different edge electrode materials (graphene and Pt) is shown in Fig. 4(c). Pt devices exhibit much higher current levels than expected. The reason for this difference is the difference in the thickness of the electrodes. According to Ohm's law, it is known that the resistance of HRS increases as the reciprocal of the cell area increases. Since Pt is much thicker than graphene, the cross-section of the Pt electrode is also much larger, resulting in a smaller HRS value and a smaller memory window. Due to the large difference in resistance level, the selector material may exhibit stronger nonlinearity with respect to the graphene electrode.

Fig. 4(d) shows the SET/RESET voltage distribution for the standalone RRAM 1R and 1S1R structures. The 1S1R structure requires a larger SET voltage for operation compared to that required in the 1R structure due to the voltage drop across the selector layer. As shown in Fig. 4(e), the memory window of 1S1R is larger than that of graphene RRAM due to the higher HRS resistance. The overall HRS current distribution of the 1S1R structure is more than two times lower than that of the 1R structure, as shown in Fig. 4f. The reduced off-state current and increased memory window are a direct result of the built-in selector hierarchy.

On the other hand, Figure 5 shows the I-V characteristics and resistance characteristics of the 1S-1R graphene edge device according to the present invention. Specifically, Fig. 5(a) shows repeated DC I-V curves (50 cycles) of a representative 1S-1R graphene edge device. In this regard, the worst case is indicated by the red line. Figure 5(b) shows repeated pulse measurements of a representative 1S-1R graphene edge device. The pulse widths and amplitudes of SET and RESET are 200 ms, 100 ms, and 3.5V and -4V, respectively. The read voltage was 1.8V.

The repeated DC and pulse measurement results of a representative 1S-1R gray pained edge device are shown in FIG. 5 . Due to the presence of the selector, the device exhibits a low current until the selector is turned on (Fig. 5(a)). The supply voltage was between 0.5-1.2V and the worst case is indicated by the red curve. A pulse measurement method may be used to investigate the repeatability of the 1S-1R structure in FIG. 5(b). Although the LRS and HRS values have fluctuated, they can still maintain a reasonable memory window for more than 800 cycles.

In relation to the above-described resistive memory according to the present invention, a memory having a low-power selector will be described as follows. In this regard, FIG. 6 shows the overall structure of a low-power selector using graphene edges, and images of transmission electron microscopy and energy dispersive spectroscopy. In the case of using TiN as the upper electrode, the structure has a CuGeS selector between the graphene edge electrode and the upper electrode. A passivation layer is formed using SiO2. Pt is bonded to graphene as a pad for easy measurement.

Referring to FIG. 6 , a resistive memory having a low-power selector may include a selector layer including an upper electrode 100 , a graphene layer 200 , and a selector 250 . In this regard, the upper electrode 100 may be configured as a TiN electrode, and the edge region of the graphene layer 200 may be configured as a graphene edge electrode.

The graphene layer 200 may be disposed under the upper electrode 100 , and a graphene electrode may be formed in an edge region. Meanwhile, the selector layer may include the selector 250 formed between the upper electrode 100 and the graphene electrode.

According to an embodiment, the selector 250 may be formed of a chalcogenide selector made of a chalcogenide material.

According to an embodiment, the selector 250 may be formed of a CuGeS selector made of a CuGeS chalcogenide material.

According to an embodiment, the graphene layer 200 may be formed of a graphene layer of 0.3 nm or less, and an edge region of the upper graphene layer 200 may be formed as an electrode of a resistive memory.

Referring to FIG. 6 , the resistive memory may further include a Pt electrode 400 configured to be bonded to the graphene layer 200 . The Pt electrode 400 may be formed to be thicker than the thickness of the graphene layer 200 .

The upper electrode 100 and the selector 250 according to an embodiment may be formed of a plurality of regions having a layered structure. In this regard, the TiN electrode corresponding to the upper electrode 100 includes a first electrode region ER1 and a second electrode region ER2 formed below the first electrode region ER1 by a predetermined height. can do. In addition, the TiN electrode corresponding to the upper electrode 100 may further include a vertical connection part VC that vertically connects the first electrode region ER1 and the second electrode region ER2 .

The selector 250 may include a first region R1 and a second region R2 formed below the first region R1 by a predetermined height. In this regard, the first region R1 and the second region R2 of the selector 250 include the first electrode region ER1 and the second electrode region ER2 of the TiN electrode corresponding to the upper electrode 100 , and It may be configured to be bonded. Meanwhile, the selector 250 may further include a vertical connection part VC that vertically connects the first region R1 and the upper second region R2.

The resistive memory with a low power selector described herein may be configured as a 3D vertical structure memory.

Referring to FIG. 6 , the graphene layer 200 may include a first graphene layer 210 and a second graphene layer 220 disposed below the first graphene layer 210 . In this regard, the resistive memory may further include a vertical structure memory cell 300 formed of a memory material between the upper electrode 100 and the first graphene layer 210 .

According to an embodiment, the vertical structure memory cell 300 may be configured to be bonded to the first graphene layer 210 and the second graphene layer 220 .

According to an embodiment, the graphene layer 200 may further include a third graphene layer disposed under the second graphene layer 220 . The vertical structure memory cell 300 may be configured to be bonded to the first graphene layer 210 to the third graphene layer 230 .

A non-volatile memory having a low power selector according to another aspect of the present invention is provided. The non-volatile memory may be configured to include an upper electrode 100 , a graphene layer 200 , a selector 250 , and a vertical memory cell 300 . The graphene layer 200 may be disposed under the upper electrode 100 , and a graphene electrode may be formed in an edge region. The selector layer may include a selector formed between the upper electrode 100 and the graphene electrode.

The vertical structure memory cell 300 may be formed of a memory material between the upper electrode 100 and the graphene layer 200 . The vertical structure memory cell 300 may be characterized as a vertical structure memory cell disposed in a plurality of columns and rows between the upper electrode 100 and the graphene layer 200 .

According to an embodiment, the upper electrode 100 may be configured as a TiN electrode, and an edge region of the graphene layer may be configured as a graphene edge electrode.

According to an embodiment, the selector 250 may be a CuGeS selector made of a CuGeS chalcogenide material.

According to an embodiment, the graphene layer 200 may be formed of a graphene layer of 0.3 nm or less, and an edge region of the graphene layer 200 may be formed as an electrode of a vertical structure resistance memory.

According to an embodiment, the non-volatile memory may be configured as a resistive random access memory (RRAM). In this regard, the inactive memory formed of the RRAM may be characterized in that the strength of the resistance changes according to past information of the current that has flowed in the past.

According to an embodiment, the RRAM is operatively coupled to the neuromorphic processor, and when a voltage greater than or equal to a threshold value is applied from the neuromorphic processor, the device resistance of the vertical structure resistance memory is lower than the threshold when a voltage is applied. It can be configured to change to a lower resistance value. Also, in the RRAM, when a voltage less than a threshold value is applied from the neuromorphic processor, the device resistance may be changed back to the previous resistance value.

In the above, a memory having a low-power selector according to the present specification has been described. In this regard, the scaling characteristics of CuGeS chalcogenide selectors in 3D vertical RRAM structures using atomically thin graphene edge electrodes are described herein. The graphene-edge electrode exhibited increased resistance across the electrode-selector interface when compared to that exhibited by the thicker metal-based electrode, resulting in a decrease in the off-state leakage current. When the selector is embedded in the 3D vertical structure, the thin graphene edge and the wide TiN filler electrode show a sharp difference in I-V characteristics with a highly asymmetric current distribution. This phenomenon is a direct result of ion polarity, which is highly dependent on voltage polarity and Cu ion transport direction. By combining the selector with the metal-oxide RRAM, it can be observed that the leakage current is greatly reduced. In addition, strong non-linearities may be introduced to increase the memory window. Recent developments in terms of various 3D architectures for scaled resistive memory may provide a path for high-density RRAM storage. In addition, the development of an embedded selector that can accommodate this RRAM scaling trend will be an important step to achieve ultra-high-density 3D memory technology.

In this regard, resistive memory is regarded as a key component in the hardware implementation of complex neural formation networks due to its simplicity, compactness and manageable power dissipation. However, breakthroughs in selector material technology and bit cost-effective three-dimensional (3D) device architectures are needed to provide sufficient device density while maintaining the advantages of two-terminal devices. In the scaling progress of the memristor device, the scalability of the selector material remains uncertain. Herein, atomically thin graphene edges in 3D vertical memory structures are used to study the effect of highly concentrated electric fields in CuGeS chalcogenide selector layers. This specification presents important steps in understanding the properties of mobile ions in solid chalcogenide electrolytes and the potential of microselector devices.

According to the present invention, a CuGeS chalcogenide material using an atomically thin (0.3 nm) edge of graphene as an electrode can be applied as a selector to overcome the above-mentioned problems.

In addition, according to the present invention, the graphene edge electrode increases the resistance of the electrode-selector interface compared to the thick metal-based electrode, resulting in a decrease in OFF-state leakage current. When the CuGeS selector is embedded in the vertical structure, the thin graphene edge electrode and the wide TiN filler electrode show I-V characteristics with large asymmetric current distribution. This phenomenon is due to the ion congestion effect, which is strongly dependent on the voltage polarity and Cu ion transport direction.

In addition, according to the present invention, when the selector to which the graphene edge is applied and the RRAM are combined, the leakage current is ^{reduced up to 10 3} times and the memory window is increased.

In addition, according to the present invention, the degree of integration is increased by using thin graphene, and the advantage of a small leakage current can be derived by using a selector, so that it can be applied to the field of electronics and electricity. In particular, when applied to a resistive memory, it can solve the sneak path problem, so it can be applied to the memory semiconductor field.

In addition, according to the present invention, as a result, the low-power selector using the graphene edge can not only increase the degree of integration by using a thin two-dimensional material, but also significantly reduce the leakage current because the interface resistance between the electrode and the selector increases. . In addition, when applied to resistive memory, it has the advantage of supplementing the sneak path problem.

Currently, the digital and analog industries are based on silicon bulk semiconductors, but as the degree of integration of semiconductor circuits becomes more and more important, the application of thin two-dimensional materials and reduction of leakage current are important. Considering this, a low-power selector using graphene edges can be an important basis for ultra-high-density 3D memory.

The features and effects of the present invention described above will become more apparent through the following detailed description in relation to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention. will be able

Since the present invention can have various changes and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to a specific embodiment, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

According to the software implementation, not only the procedures and functions described in this specification but also the design and parameter optimization for each component may be implemented as a separate software module. The software code may be implemented as a software application written in a suitable programming language. The software code may be stored in a memory and executed by a controller or a processor.

Claims (20)

A resistive memory having a low power selector, comprising:
upper electrode;
a graphene layer disposed under the upper electrode and having a graphene electrode formed in an edge region;
and a selector layer comprising a selector formed between the upper electrode and the graphene electrode. According to claim 1,
wherein the upper electrode is configured as a TiN electrode, and an edge region of the graphene layer is configured as a graphene edge electrode. According to claim 1,
wherein the selector is formed of a chalcogenide selector made of a chalcogenide material. 4. The method of claim 3,
The resistive memory, characterized in that the selector is a CuGeS selector made of a CuGeS chalcogenide material. According to claim 1,
The resistive memory, wherein the graphene layer is composed of a graphene layer of 0.3 nm or less, and an edge region of the graphene layer is formed as an electrode of the resistive memory. 6. The method of claim 5,
and a Pt electrode configured to bond with the graphene layer, wherein the Pt electrode is formed to be thicker than a thickness of the graphene layer. 3. The method of claim 2,
wherein the TiN electrode includes a first electrode region and a second electrode region formed below the first electrode region by a predetermined height. 8. The method of claim 7,
The TiN electrode further includes a vertical connection portion vertically connecting the first electrode region and the second electrode region. 8. The method of claim 7,
The selector includes a first area and a second area formed below the first area by a predetermined height,
and the first region and the second region of the selector are configured to bond with the first electrode region and the second electrode region of the TiN electrode. 10. The method of claim 9,
and the selector further includes a vertical connection part vertically connecting the first region and the second region. According to claim 1,
The graphene layer includes a first graphene layer and a second graphene layer disposed under the first graphene layer,
and a vertically structured memory cell formed of a memory material between the upper electrode and the first graphene layer. 12. The method of claim 11,
wherein the vertically structured memory cell is configured to bond with the first graphene layer and the second graphene layer. 12. The method of claim 11,
The graphene layer further comprises a third graphene layer disposed under the second graphene layer,
wherein the vertical structure memory cell is configured to bond with the first graphene layer through the third graphene layer. In non-volatile memory,
upper electrode;
a graphene layer disposed under the upper electrode and having a graphene electrode formed in an edge region;
a selector layer including a selector formed between the upper electrode and the graphene electrode; and
and a vertically structured memory cell formed of a memory material between the upper electrode and the graphene layer. 15. The method of claim 14,
wherein the vertical memory cell is a vertical memory cell disposed in a plurality of columns and rows between the upper electrode and the graphene layer. 15. The method of claim 14,
wherein the upper electrode is configured as a TiN electrode, and an edge region of the graphene layer is configured as a graphene edge electrode. 15. The method of claim 14,
The resistive memory, characterized in that the selector is a CuGeS selector made of a CuGeS chalcogenide material. 15. The method of claim 14,
The graphene layer is composed of a graphene layer of 0.3 nm or less, and an edge region of the graphene layer is formed as an electrode of the vertical structure resistive memory. 15. The method of claim 14,
The inactive memory is composed of a resistive random access memory (RRAM), characterized in that the resistance is changed according to the past information of the current flowing in the past, the inactive memory. 15. The method of claim 14,
The RRAM is operatively coupled to the neuromorphic processor, and when a voltage greater than or equal to a threshold value is applied from the neuromorphic processor, the device resistance of the vertical structure resistive memory has a lower resistance value than when a voltage less than or equal to the threshold is applied. , and when a voltage equal to or less than the threshold value is applied, the device resistance is changed back to the previous resistance value.

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