KR20210102711A - Drain-extended FinFET with a High-k Dielectric Field Plate and Method of fabricating the same - Google Patents

Abstract

The present invention provides a drain extension type finFET having a high dielectric constant field plate capable of improving breakdown voltage and driving resistance characteristics, and a manufacturing method thereof. According to the present invention, by forming a high dielectric constant field plate on a drain extension region and a channel, the electric field peak formed between the channel and the drain region can be effectively dispersed. Accordingly, a high breakdown voltage can be secured, and the driving resistance can be reduced by forming an electron accumulation layer in the drain extension region.

Description

Drain-extended FinFET with a High-k Dielectric Field Plate and Method of fabricating the same

The present invention relates to an extended drain finFET and a manufacturing method thereof, and more particularly, to an extended drain finFET having a high dielectric constant field plate capable of improving breakdown voltage and driving resistance characteristics, and a manufacturing method thereof.

High voltage transistors are an essential component of system-on-chip (SoC) technology for a variety of applications such as input/output interface circuits, power management circuits, memory and driver circuits for RF amplifiers.

Recently, in order to stably avoid breakdown and electrostatic discharge (ESD), research and development on high voltage transistors that can operate stably at an excellent operating voltage and have excellent transistor performance and low on resistance characteristics this is being requested In addition, Fin Field-Effect Transistor (FinFET) has superior gate control compared to planar transistors, excellent resistance to short channel effects (SCE), and high compatibility with existing planar transistors and technologies. It is widely used in technology.

However, the conventional finFET has many limitations in securing a sufficient breakdown voltage due to a narrow fin structure and a high electric field peak generated from a high doping concentration difference between the channel and the drain.

In addition, LDMOS (Laterally Double diffused Metal Oxide Semiconductor), DeMOS (Drain extended Metal Oxide semiconductor), and RESURF (Reduced Surface Field) technology used in the field plate configuration have excellent electrical performance and high compatibility with existing CMOS processes. It is being utilized by efficiently integrating low-voltage and high-voltage transistors into a single-chip system. This RESURF technique is very effective in alleviating the electric field peak between the channel and the drain, but since the driving resistance is high due to the drain extension region with a low doping concentration, for the realization of a high voltage transistor, the breakdown voltage-drive resistance tradeoff has to be solved. pointed out as a problem.

1 is a diagram illustrating an example of a drain extended FinFET (DeFinFET) to which a conventional RESURF technology is applied.

Referring to FIG. 1 , in the conventional extended drain finFET to which RESURF technology is applied, a source 11, a channel 12, a drain extended region 13, and a drain 14 are sequentially formed in a fin body 10, and the channel It has a structure in which a gate insulating film 15 and a gate 16 are formed on (12). That is, the drain extension region 13 is formed between the source 11 and the drain 14 to be adjacent to the channel 12 , which is somewhat effective in alleviating the high electric field peak formed between the channel 12 and the drain 14 . . However, there is a problem in that the driving resistance is fatally increased due to the low doping concentration and the drain extension region 13 having a narrow fin line width.

Korean Patent Laid-Open 10-2012-0091993

The problem to be solved by the present invention is to reduce the high electric field peak formed between the channel and the drain in order to secure a trade-off between the breakdown voltage and the driving resistance, and a drain extension type having a high dielectric constant field plate capable of securing a low driving resistance To provide a FinFET and a method for manufacturing the same.

In order to solve the above problems, the drain extended type finFET having a high dielectric constant field plate of the present invention includes a substrate, a fin body protruding onto the substrate, a source formed on one side of the fin body, a drain formed on the other side of the fin body, and a channel formed between the source and the drain, a drain extension region formed between the drain and the channel, a gate insulating film formed on the channel and the drain extension region, and a high dielectric constant field plate formed on the gate insulating film.

The high dielectric constant field plate may be formed to surround both the upper surface and the side surface of the gate insulating layer.

The high dielectric constant field plate is silicon dioxide (SiO ₂ ), hafnium oxide (HfO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), titanium dioxide (TiO ₂ ), zirconium oxide (ZrO _{2 )} ), tantalum oxide (Ta ₂ O ₅ ), and lanthanum oxide (La ₂ O ₃ ) may include at least one.

The high dielectric constant field plate may have a high dielectric constant of 3.9 or more.

The gate insulating layer may be formed to cover both upper surfaces and side surfaces of the channel and the drain extension region.

It may further include a gate formed on the high dielectric constant field plate.

The gate may be formed to surround an upper surface and a side surface of the high dielectric constant field plate, and may be formed to be disposed on the channel.

The gate may be formed to surround an upper surface and a side surface of the high dielectric constant field plate, and may include a portion of the channel and the drain extension region.

The gate may include polysilicon (Poly Si), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN). ), molybdenum nitride (MoN), copper (Cu), gold (Au), and cobalt (Co) may be included.

It may further include a lower insulating layer covering the lower side of the fin body.

It may further include a contact formed on the source and the drain.

In order to solve the above problems, the method for manufacturing an extended drain type finFET having a high dielectric constant field plate according to the present invention includes forming a fin body on a substrate, and forming a lower insulating layer on the substrate to expose the fin body. forming a channel and drain extension region in the fin body, forming a gate insulating film to surround the fin body, forming a high dielectric constant field plate to surround the gate insulating film, a source and a source in the fin body forming a drain and forming a gate on the high dielectric constant field plate.

The method may further include forming a first dummy gate on the fin body before forming the drain extension region.

The first dummy gate may be formed on an upper surface of the fin body where the channel is formed.

The forming of the drain extension region may include implanting an n-type or p-type dopant into the fin body using the first dummy gate.

Before forming the source and drain, forming a second dummy gate on the high dielectric constant field plate and using the second dummy gate, the upper surface of the fin body where the source and the drain are formed is exposed The method may further include etching the gate insulating layer and the high dielectric constant field plate.

The forming of the source and drain may include implanting an n-type or p-type dopant having a higher concentration than a dopant implanted into the drain extension region into the exposed fin body.

After forming the gate, the method may further include forming a contact on the source and the drain, respectively.

According to the present invention, the electric field peak formed between the channel and the drain region can be effectively dispersed by forming the high dielectric constant field plate on the drain extension region and the channel. Accordingly, a high breakdown voltage can be secured, and the driving resistance can be reduced by forming the electron accumulation layer in the drain extension region.

In addition, since the high dielectric constant field plate can improve gate control in the channel and drain extension regions due to its high dielectric constant, the transistor's sub-threshold swing (SS) and current flashing ratio (I _ON /I _OFF ), etc. Electrical properties can be improved.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a diagram illustrating an example of a drain extended FinFET (DeFinFET) to which a conventional RESURF technology is applied.
2 is a view showing an extended drain type FinFET having a high dielectric constant field plate of the present invention.
3 is a graph showing the electric field distribution in the FinFET according to the dielectric material of the high dielectric constant field plate in the extended-drain FinFET according to the present invention.
4 is a graph showing the electron concentration distribution in the FinFET according to the dielectric material of the high permittivity field plate in the extended-drain FinFET according to the present invention.
5 is a graph showing breakdown voltage, driving resistance, and figure of merit according to dielectric materials of a high dielectric constant field plate in the extended-drain finFET of the present invention.
6 to 14 are views illustrating a method of manufacturing an extended drain type FinFET having a high dielectric constant field plate according to the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

While the present invention is susceptible to various modifications and variations, specific embodiments thereof are illustrated and shown in the drawings and will be described in detail hereinafter. However, it is not intended to limit the invention to the particular form disclosed, but rather the invention includes all modifications, equivalents and substitutions consistent with the spirit of the invention as defined by the claims.

It will be understood that when an element, such as a layer, region, or substrate, is referred to as being “on” another component, it may be directly on the other element or intervening elements in between. .

Although the terms first, second, etc. may be used to describe various elements, components, regions, layers and/or regions, such elements, components, regions, layers and/or regions are not It will be understood that they should not be limited by these terms.

2 is a view showing an extended drain type FinFET having a high dielectric constant field plate of the present invention.

Referring to FIG. 2 , the drain extended finFET having a high dielectric constant field plate according to the present invention includes a substrate 110 , a fin body 120 , a lower insulating layer 130 , and a source 121 formed in the fin body 120 . ), a drain 122 , a channel 123 , a drain extension region 124 , a gate insulating layer 140 , a high dielectric constant field plate 150 , and a gate 160 .

The fin body 120 may be formed on the substrate 110 . Here, the substrate 110 may be made of any one of a semiconductor, polymer, or insulator substrate such as silicon (Si) and silicon on insulator (SOI).

The fin body 120 may be formed to protrude in a first direction D1 on the substrate 110 and may be formed to extend in a second direction D2 perpendicular to the first direction. Here, the width of the fin body 120 may have a width in the range of 3 nm to 1 μm, and the length of the fin body 120 may have a length in the range of 30 nm to 1 μm. Also, the height of the fin body 120 may be formed within a range of 10 nm to 200 nm.

The fin body 120 may be formed by patterning and etching the substrate 110 using a photolithography process. Accordingly, the fin body 120 may have the same semiconductor material and lattice size as the substrate 110 . For example, a photoresist material layer is deposited on the substrate 110 , and the photoresist material layer is exposed and developed according to the fin body 120 pattern, so that a portion of the photoresist material is removed. The remaining photoresist material protects the underlying material from subsequent processing steps such as etching. Other masks may be used in the etch process, such as oxide or silicon nitride masks.

The lower insulating layer 130 may be formed on both sides of the fin body 120 to prevent the fin body 120 and other elements from being electrically connected to each other. That is, the lower insulating layer 130 may be formed on both sides of the substrate 110 of the fin body 120 , and the upper surface of the fin body 120 may be formed to have a higher upper surface than the upper surface of the lower insulating layer 130 . have. Accordingly, the fin body 120 may have a shape protruding from the lower insulating layer 130 . The material of the lower insulating layer 130 _{may be formed of any one of silicon oxide (SiO 2} ), silicon nitride (Si ₃ N ₄ ), and TEOS, and the fin body 120 using CMP and etching processes. can be exposed.

A source 121 , a drain 122 , a channel 123 , and a drain extension region 124 may be formed in the fin body 120 .

The source 121 and the drain 122 may be respectively formed on one side or the other side of the fin body 120 . For example, the source 121 and the drain 122 form a mask on the fin body 120 , and a high concentration of the source 121 and the drain 122 is formed in the fin body 120 using the formed mask. It can be formed by implanting an n-type or p-type dopant, respectively. As another embodiment, after etching the region where the source 121 and the drain 122 of the fin body 120 are formed using the mask, a selective epitaxial growth method is utilized to perform the n-type or p-type process. The source 121 and drain 122 regions including the type dopant may be formed.

The channel 123 and the drain extension region 124 may be formed in a region between the source 121 and the drain 122 in the fin body 120 . Preferably, the channel 123 may be formed adjacent to the source 121 , and the drain extension region 124 may be formed between the channel 123 and the drain 122 . Here, the channel 123 and the drain extension region 124 are formed between the source 121 and the drain 122 , and may be formed by separating the channel 123 and the drain extension region 124 using a mask. . For example, by using a mask to implant an n-type or p-type dopant having a lower impurity concentration than that of the source 121 and drain 122 into the drain extension region 124, the channel 123 and the drain extension region 124 are implanted. These can be formed separately. The length of the drain extension region 124 preferably ranges from 3 nm to 1 μm.

The gate insulating layer 140 may be formed on the channel 123 and the drain extension region 124 . In more detail, the gate insulating layer 140 may be formed to cover both the upper surface and the side surface of the channel 123 and the drain extension region 124 . Materials of the gate insulating layer 140 include silicon dioxide (SiO ₂ ), hafnium oxide (HfO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), titanium dioxide (TiO ₂ ), zirconium oxide. (ZrO ₂ ), tantalum oxide (Ta ₂ O ₅ ), and lanthanum oxide (La ₂ O ₃ ) It may be formed to include at least one.

A high dielectric constant field plate 150 may be formed on the gate insulating layer 140 . In more detail, the high dielectric constant field plate 150 may be formed to cover both the upper and side surfaces of the gate insulating layer 140 surrounding the channel 123 and the drain extension region 124 . Accordingly, the high dielectric constant plate may have a shape surrounding the channel 123 and the drain extension region 124 .

Materials of the high dielectric constant field plate 150 include silicon dioxide (SiO ₂ ), hafnium oxide (HfO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), titanium dioxide (TiO ₂ ), At least one of zirconium oxide (ZrO ₂ ), tantalum oxide (Ta ₂ O ₅ ), and lanthanum oxide (La ₂ O ₃ ) may be formed.

That is, the drain extended finFET to which the conventional RESURF technology is applied has a drain extended region formed between the source and the drain adjacent to the channel, and is somewhat effective in alleviating the high electric field peak formed between the channel and the drain. However, there is a disadvantage in that the driving resistance is fatally increased due to the low doping concentration and the drain extension region having a narrow fin line width. Accordingly, there is a problem in that the trade-off between the breakdown voltage and the driving resistor has to be solved in order to implement a high voltage transistor.

However, in the extended drain finFET according to the present invention, the electric field peak formed between the channel 123 and the drain 122 region is effectively reduced by forming the high dielectric constant field plate 150 on the drain extended region 124 and the channel 123 . can be dispersed.

3 is a graph showing the electric field distribution in the FinFET according to the dielectric material of the high dielectric constant field plate 150 in the extended-drain FinFET according to the present invention.

Referring to FIG. 3 , when the permittivity of air is 1, the permittivity of the high permittivity field plate 150 formed on the channel 123 and the drain 122 _{is changed from air to hafnium oxide (HfO 2} , permittivity: 25). As it increases, it can be seen that the electric field peak formed between the channel 123 and the drain 122 is effectively dispersed.

4 is a graph showing the electron concentration distribution in the FinFET according to the dielectric material of the high dielectric constant field plate 150 in the extended-drain FinFET according to the present invention.

Referring to FIG. 4A , as the dielectric constant of the high dielectric constant field plate 150 _{increases from air to hafnium oxide (HfO 2} ), the electron density concentrated between the channel 123 and the drain 122 is dispersed. it can be confirmed that In addition, referring to FIG. 4B , as the dielectric constant of the high dielectric constant field plate 150 _{increases from air to hafnium oxide (HfO 2} ), it can be seen that the electron accumulation layer formed in the drain extension region 124 expands. have.

5 is a graph showing the breakdown voltage, driving resistance, and figure of merit according to the dielectric material of the high dielectric constant field plate 150 in the extended-drain finFET of the present invention.

Referring to FIG. 5( a ), as the dielectric constant of the high dielectric constant field plate 150 _{increases from air to hafnium oxide (HfO 2} ), it can be seen that the driving resistance decreases and the breakdown voltage is improved, as shown in FIG. 5( b ) ), it can be seen that the higher the dielectric constant, the better the figure of merit.

That is, the dispersion effect of the electric field peak of the high dielectric constant field plate 150 reduces impact ionization in the semiconductor material constituting the fin body 120 , thereby improving the breakdown voltage of the extended drain type finFET. In addition, the electron accumulation layer formed in the drain extension region 124 by the high dielectric constant field plate 150 has an effect of reducing the driving resistance. Therefore, in the extended drain finFET according to the present invention, the breakdown voltage of the extended drain finFET can be improved by forming the high dielectric constant field plate 150 having a high dielectric constant formed in the channel 123 and the drain extended region 124 , and driving By reducing the resistance, it has the effect of effectively improving the figure of merit.

In addition, since the high dielectric constant field plate 150 can improve control of the gate 160 in the channel 123 and the drain extension region 124 due to its high dielectric constant, the sub-threshold swing (SS) and Electrical characteristics such as the current flashing ratio (I _ON /I _{OFF ) can be improved.}

Therefore, the high dielectric constant field plate 150 is preferably formed of a material having a high dielectric constant of 3.9 or more. More specifically, it is preferable to form a material having a high dielectric constant in the range of 3.9 to 1600. For example, referring to FIGS. 3 to 5 , when the high dielectric constant field plate 150 is _{made of a material having a dielectric constant smaller than SiO 2} (dielectric constant 3.9), the electric field peak between the channel 123 and the drain 122 is Since it increases and the driving resistance decreases, it is difficult to secure a trade-off between the breakdown voltage and the driving resistance, and there are disadvantages in that the figure of merit is lowered.

Continuing to refer to FIG. 2 , a gate 160 may be formed on the high dielectric constant field plate 150 . That is, the gate 160 is formed on the high dielectric constant field plate 150 , and may be formed to surround the upper surface and the side surface of the high dielectric constant field plate 150 corresponding to the position corresponding to the channel 123 . In this case, the gate 160 may be manufactured to partially extend into the drain extension region 124 adjacent to the channel 123 .

The gate 160 may include a material suitable for the gate 160 of an n-type transistor or a p-type transistor. For example, the gate 160 may include a conductive material having a work function controlled by a doping impurity. Alternatively, the gate 160 may include a conductive material having a mid-gap work function of a middle value of the work functions of the gate 160 of the n-type transistor and the p-type transistor.

For example, the material of the gate 160 is polysilicon (Poly Si), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M), titanium nitride (TiN), tantalum nitride ( TaN), tungsten nitride (WN), molybdenum nitride (MoN), copper (Cu), gold (Au), and cobalt (Co) may be formed of any one material.

The contact may be formed on the source 121 and the drain 122, respectively, and may be formed of a material having conductivity.

6 to 14 are views illustrating a method of manufacturing an extended drain type FinFET having a high dielectric constant field plate according to the present invention.

6 and 14 , the method of manufacturing the extended drain type FinFET having the high dielectric constant field plate 150 according to the present invention includes the steps of forming the fin body 120 on the substrate 110 , the fin body 120 . ) to be exposed, forming the lower insulating layer 130 on the substrate 110 , forming the drain extension region 124 in the fin body 120 , and the gate insulating layer 140 surrounding the fin body 120 . ), forming the high dielectric constant field plate 150 to surround the gate insulating layer 140 , forming the source 121 and the drain 122 in the fin body 120 , and the high dielectric constant field plate and forming a gate (160) on (150).

Referring to FIG. 6 , FIG. 6(a) is a plan view viewed from the top of the FinFET, FIG. 6(b) is a cross-sectional view when the plane AA' is cut in FIG. 6(a), and FIG. 6(c) is FIG. It is a cross-sectional view when the BB' plane is cut in 6(a). Referring to FIGS. 6A , 6B and 6C , first, a fin body 120 may be formed on the substrate 110 . Here, the substrate 110 may be made of any one of a semiconductor, polymer, or insulator substrate such as silicon (Si) and silicon on insulator (SOI). Also, the fin body 120 may be formed by patterning and etching the substrate 110 using a photolithography process to protrude upwardly of the substrate 110 .

Referring to FIG. 7 , lower insulating layers 130 may be formed on both sides of the fin body 120 . That is, the lower insulating layer 130 may be formed on both sides of the substrate 110 of the fin body 120 , and the upper surface of the fin body 120 may be formed to have a higher upper surface than the upper surface of the lower insulating layer 130 . have. Accordingly, the fin body 120 may have a shape protruding from the lower insulating layer 130 . The material of the lower insulating layer 130 _{may be formed of any one of silicon oxide (SiO 2} ), silicon nitride (Si ₃ N ₄ ), and TEOS, and the fin body 120 using CMP and etching processes. may be formed to be exposed.

Referring to FIG. 8 , a first dummy gate 101 may be formed on the fin body 120 and the lower insulating layer 130 . The first dummy gate 101 may be formed using a patterning process using a lithography process and an etching process. Here, the first dummy gate 101 may include poly-Si or a photoresist.

Referring to FIG. 9 , a channel 123 and a drain extension region 124 may be formed in the fin body 120 . For example, an n-type or p-type dopant 103 may be implanted into the fin body 120 using the first dummy gate 101 as a mask. Accordingly, the fin body 120 corresponding to the lower portion of the first dummy gate 101 to which the dopant 103 is not implanted may function as the channel 123 , and the drain extension region 124 may be formed except for the channel 123 . It may be formed by implanting a dopant 103 into the region. In more detail, in the fin body 120 , the remaining region excluding the region where the source 121 and the drain 122 to be described later are formed may function as the drain extension region 124 .

Referring to FIG. 10 , after the first dummy gate 101 is removed, the gate insulating layer 140 and the high dielectric constant field plate 150 may be formed on the fin body 120 . That is, the gate insulating layer 140 is formed to cover both the upper surface and the side surface of the fin body 120 , and the high dielectric constant field plate 150 is formed to surround all of the gate insulating layer 140 surrounding the fin body 120 . can be In this case, the gate insulating layer 140 and the high dielectric constant field plate 150 are formed of silicon dioxide (SiO ₂ ), hafnium oxide (HfO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), and titanium dioxide. (TiO ₂ ), zirconium oxide (ZrO ₂ ), tantalum oxide (Ta ₂ O ₅ ), and lanthanum oxide (La ₂ O ₃ ) may be formed of at least one material. Here, the high dielectric constant field plate 150 is preferably formed of a material having a high dielectric constant, such as _{hafnium oxide (HfO 2 ).}

Referring to FIG. 11 , the second dummy gate 102 may be formed on the high dielectric constant field plate 150 . The second dummy gate 102 may be formed using a patterning process using a lithography process and an etching process. At this time, using the second dummy gate 102 as a mask, the gate insulating layer 140 and the high dielectric constant field plate 150 are exposed so that the upper portion of the fin body 120 at the position where the source 121 and the drain 122 are formed is exposed. ) may be formed to be etched.

Referring to FIG. 12 , a source 121 and a drain 122 are formed in the fin body 120 . The source 121 and the drain 122 may be formed by implanting a high concentration of n-type or p-type dopant into the fin body 120 exposed through the second dummy gate 102 . That is, the source 121 and the drain 122 may be implanted with a dopant having a higher concentration than that of the dopant implanted into the drain extension region 124 . Accordingly, a region in the fin body 120 excluding the region in which the source 121 and the drain 122 are formed is defined as the drain extension region 124 . As another embodiment, after etching a region where the source 121 and the drain 122 of the fin body 120 are formed using the second dummy gate 102 , a selective epitaxial growth method is utilized. Accordingly, the source 121 and drain 122 regions including the n-type or p-type dopant may be formed. Accordingly, the fin body 120 may have a structure in which a source 121 , a channel 123 , a drain extension region 124 , and a drain 122 are sequentially formed as shown in FIG. 12 .

Referring to FIG. 13 , after the second dummy gate 102 is removed, a gate 160 may be formed on the high dielectric constant field plate 150 . The gate 160 may be formed to surround the upper surface and the side surface of the high dielectric constant field plate 150 corresponding to a position corresponding to the channel 123 or a region including a part of the channel 123 and the drain extension region 124 . can

Materials of the gate 160 include polysilicon (Poly Si), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M), titanium nitride (TiN), tantalum nitride (TaN), It may be formed of any one of tungsten nitride (WN), molybdenum nitride (MoN), copper (Cu), gold (Au), and cobalt (Co).

Referring to FIG. 14 , a contact 170 may be formed on the source 121 and the drain 122 , respectively. That is, the contact 170 may be formed on the fin body 120 corresponding to the source 121 and the drain 122 . As another embodiment, the contact 170 forms a separate insulating layer on the outside of the extended drain type FinFET, forms a via hole in the insulating layer, and then forms the contact 170 with the source 121 and the drain 122 through the via hole. It may be formed so as to be in contact.

As described above, in the extended drain type FinFET having the high dielectric constant field plate 150 according to the present invention, the high dielectric constant field plate 150 is formed on the drain extended region 124 and the channel 123 to form the channel 123 . An electric field peak formed between the region and the drain 122 may be effectively dispersed. Accordingly, a high breakdown voltage can be secured, and the driving resistance can be reduced by forming the electron accumulation layer in the drain extension region 124 . In addition, since the high dielectric constant field plate 150 can improve control of the gate 160 in the channel 123 and the drain extension region 124 due to its high dielectric constant, the sub-threshold swing (SS) and Electrical characteristics such as the current flashing ratio (I _ON /I _{OFF ) can be improved.}

On the other hand, the embodiments of the present invention disclosed in the present specification and drawings are merely presented as specific examples to aid understanding, and are not intended to limit the scope of the present invention. It will be apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

101: first dummy gate 102: second dummy gate
110: substrate 120: pin body
121: source 122: drain
123: channel 124: drain extension region
130: lower insulating layer 140: gate insulating film
150: high dielectric constant field plate 160: gate
170: contact

Claims (18)

Board;
a pin body protruding onto the substrate;
a source formed on one side of the fin body;
a drain formed on the other side of the fin body;
a channel formed between the source and the drain;
a drain extension region formed between the drain and the channel;
a gate insulating layer formed on the channel and the drain extension region; and
and a high dielectric constant field plate formed on the gate insulating layer. According to claim 1,
and the high dielectric constant field plate is formed to surround both the upper and side surfaces of the gate insulating layer. According to claim 1,
The high dielectric constant field plate is silicon dioxide (SiO ₂ ), hafnium oxide (HfO ₂ ), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), titanium dioxide (TiO ₂ ), zirconium oxide (ZrO _{2 )} ), tantalum oxide (Ta ₂ O ₅ ), and lanthanum oxide (La ₂ O ₃ ) Extended drain FinFET comprising at least one. According to claim 1,
The high dielectric constant field plate has a high dielectric constant of 3.9 or higher drain extended type FinFET. According to claim 1,
and the gate insulating layer is formed to cover both upper and side surfaces of the channel and the drain extension region. According to claim 1,
The extended drain type FinFET further comprising a gate formed on the high dielectric constant field plate. The method of claim 6, wherein the gate,
The extended drain type FinFET is formed to surround the upper surface and the side surface of the high dielectric constant field plate, and is formed to be disposed on the channel. The method of claim 6, wherein the gate,
The extended drain type finFET is formed to surround the upper surface and the side surface of the high dielectric constant field plate, and is formed to include the channel and a part of the drain extension area. 7. The method of claim 6,
The gate includes polysilicon (Poly Si), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN). ), molybdenum nitride (MoN), copper (Cu), gold (Au) and cobalt (Co) containing any one of the extended drain type FinFET. According to claim 1,
The extended drain type FinFET further comprising a lower insulating layer covering the lower side of the fin body. According to claim 1,
The extended-drain FinFET further comprising a contact formed on the source and the drain. forming a fin body on a substrate;
forming a lower insulating layer on the substrate to expose the fin body;
forming a channel and drain extension region in the fin body;
forming a gate insulating layer to surround the fin body;
forming a high dielectric constant field plate to surround the gate insulating layer;
forming a source and a drain in the fin body; and
and forming a gate on the high dielectric constant field plate. 13. The method of claim 12, wherein before forming the drain extension,
and forming a first dummy gate on the fin body. 14. The method of claim 13,
and the first dummy gate is formed on an upper surface of the fin body where the channel is formed. 14. The method of claim 13, wherein the forming of the drain extension region comprises:
and implanting an n-type or p-type dopant into the fin body by using the first dummy gate. 13. The method of claim 12, wherein before forming the source and drain,
forming a second dummy gate on the high dielectric constant field plate; and
and etching the gate insulating layer and the high dielectric constant field plate using the second dummy gate to expose upper surfaces of the fin body where the source and the drain are formed. 16. The method of claim 15, wherein forming the source and drain comprises:
and implanting an n-type or p-type dopant having a higher concentration than the dopant implanted into the drain extension region into the exposed fin body. 13. The method of claim 12, wherein after forming the gate,
The method of manufacturing an extended drain type FinFET further comprising forming a contact on the source and the drain, respectively.

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