KR20210096185A - High Aspect Ratio Electroplating Structure and Anisotropic Electroplating Process - Google Patents

Abstract

The device includes a dielectric layer having a first surface and a second surface. The device also includes a first set of high aspect ratio electroplated structures disposed on a first surface of the dielectric layer and a second set of high aspect ratio electroplated structures disposed on a second surface of the dielectric layer opposite the first set of high aspect ratio electroplated structures. Includes a high aspect ratio electroplated structure.

Description

High Aspect Ratio Electroplating Structure and Anisotropic Electroplating Process

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from U.S. Patent Application No. 16/693,169, filed on November 22, 2019, and also claims the benefit of, U.S. Provisional Application No. 62/771,442, filed November 26, 2018, each of which is incorporated herein by reference in its entirety.

technical field

FIELD OF THE INVENTION The present invention relates generally to electroplating structures and electroplating processes.

Electroplating processes for fabricating structures such as copper or copper alloy circuit structures such as leads, traces and via interconnects are generally known and include, for example, the fabrication of fine line circuits by Castellani et al. and application of photoresist therefor. No. 4,315,985 entitled U.S. Patent No. 4,315,985. A process of this type is used, for example, in connection with the manufacture of a disk drive head suspension as disclosed in the following patent: Bennin et al., US patent entitled Low Resistance Earth Ground Joint for Dual Stage Actuating Disk Drive Suspension 8,885,299; US Pat. No. 8,169,746 entitled Integrated Reed Suspension with Multiple Trace Configuration to Rice et al.; U.S. Patent No. 8,144,430 entitled Multilayer Ground Planar Structure for Integrated Reed Suspension to Hentges et al.; US Pat. No. 7,929,252, titled Multilayer Ground Planar Structures for Integrated Reed Suspensions to Hentges et al.; No. 7,388,733 to Swanson et al., entitled Method of Making Precious Metal Conductive Leads for Suspension Assemblies; and US Pat. No. 7,384,531 entitled Plated Ground Feature for Integrated Reed Suspension to Peltoma et al. Processes of this type are also used in connection with the manufacture of camera lens suspensions as disclosed, for example, in US Pat. No. 9,366,879, entitled Camera Lens Suspension with Polymer Bearings to Miller.

Superfilling and super conformal plating processes and compositions are also known and disclosed, for example, in Vereecken et al., "Chemistry of Additives in Damascene Copper Plating" (IBM J. of Res. & Dev). ., vol. 49, no. 1, January 2005); Andricacos et al. "Damascene Copper Electroplating for Chip Interconnection" (IBM J. of Res. & Dev., vol. 42, no. 5, September 1998); and Moffat et al. “Curvature-improving sorbent coverage mechanism for bottom-up superfilling and bump control in damascene treatment” (Electrochimica Acta 53, pp. 145-154, 2007). By this process, electroplating inside the trench (eg, a photoresist mask trench defining space for the structure to be electroplated) occurs preferentially at the bottom. Thereby, voids in the deposited structure can be avoided. All previously identified patents and documents are hereby incorporated by reference in their entirety for all purposes.

There remains a continuing need for improved circuit structures. In addition, there is a continuing need for efficient and effective processes, including electroplating processes for manufacturing circuits and other structures.

A device comprising a high-aspect ratio electroplated structure and a method of forming a high-aspect ratio electroplated structure are described. A method of making a metal structure comprises providing a substrate having a metal base characterized by a height to width aspect ratio and electroplating a metal crown on the base to form a metal structure having a height to width aspect ratio greater than the aspect ratio of the base. includes steps.

Other features and advantages of embodiments of the present invention will become apparent from the accompanying drawings and the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention are illustrated by way of example and not limitation in the drawings in the accompanying drawings in which like reference numbers indicate like elements.
1 shows a coil fabricated using current printed circuit technology.
2 illustrates a high-density precision coil including a high-aspect-ratio electroplated structure according to an embodiment.
3 depicts a diagram used to represent electromagnetic forces generated by a high-density precision coil comprising a high-aspect-ratio electroplated structure in accordance with an embodiment.
4 depicts a device comprising multiple layers of a high aspect ratio electroplated structure in accordance with an embodiment configured for a linear motor type application.
5 illustrates a high aspect ratio electroplating structure in accordance with some embodiments.
6 illustrates a high aspect ratio electroplating structure in accordance with some embodiments.
7 illustrates a high aspect ratio electroplating structure in accordance with some embodiments.
8 depicts a device having multiple layers of a high aspect ratio electroplating structure in accordance with some embodiments having a high density of cross-sectional area.
9 shows a graph illustrating SPS coverage during a high current density plating technique and a low current density plating technique according to an embodiment.
10A-10F illustrate a process for forming a high aspect ratio electroplating structure in accordance with an embodiment.
11 illustrates a high aspect ratio electroplating structure in accordance with some embodiments.
12 illustrates a perspective view of a high aspect ratio electroplating structure in accordance with some embodiments.
13A and 13B illustrate high-density precision coils formed using a high-aspect-ratio electroplating structure in accordance with an embodiment.
14 illustrates a high aspect ratio electroplating structure including a high resolution laminated conductor layer according to an embodiment.
15 illustrates a high-density precision coil including a high-aspect-ratio electroplated structure according to an embodiment.
16A-16C illustrate a process for forming a high aspect ratio electroplating structure in accordance with another embodiment.
17 illustrates the selective formation of a high aspect ratio electroplating structure in accordance with an embodiment.
18 illustrates a perspective view of a high aspect ratio electroplating structure in accordance with an embodiment formed with metal crown portions formed selectively on traces.
19 illustrates a hard drive disk suspension flexure including a high aspect ratio electroplated structure in accordance with an embodiment.
FIG. 20 shows a cross-sectional view of the hard disk drive suspension flexure shown in FIG. 19 ;
21A and 21B illustrate a process for forming a high aspect ratio electroplating structure in accordance with an embodiment using photoresist during a conformal plating process.
22 depicts exemplary chemistries used in a process for forming an initial metal layer, a standard/conformal plating process, and a crown plating process in accordance with various embodiments.
23 shows a perspective view of a top surface of an inductively coupled coil formed with a high aspect ratio electroplating structure according to an embodiment.
FIG. 24 shows a perspective view of the rear surface of the embodiment of the inductive coupling coil shown in FIG. 21;
25 shows a perspective view of the top surface of an inductive coupling coil 2502 in accordance with an embodiment coupled with a radio frequency identification chip.
26A-26J illustrate a method of forming an inductively coupled coil formed of a high aspect ratio electroplating structure according to an embodiment.
27 shows a plan view of a flexure for a suspension for a hard disk drive including a high aspect ratio electroplated structure according to an embodiment.
FIG. 28 shows a cross-section of the gap portion of the flexure at the gap portion taken along line A shown in FIG. 27 .
29 shows a gimbal part having a mass structure according to an embodiment.
30 shows a cross-section of a proximal portion of a flexure comprising a high aspect ratio electroplated structure according to an embodiment taken along line B as shown in FIG. 27 .
31 shows a cross-section of a proximal portion of a flexure comprising a high aspect ratio structure according to an embodiment taken along line C as shown in FIG. 27 .
32 illustrates a top view of a proximal portion of a flexure comprising a high aspect ratio structure in accordance with an embodiment.
33 illustrates a process for forming a high aspect ratio electroplating structure in accordance with an embodiment.
Fig. 34 shows a more detailed process similar to the type described with reference to Fig. 33;
35 illustrates a coil according to one embodiment made using the process described herein.

A high aspect ratio electroplating structure and manufacturing method according to an embodiment of the present invention will be described. High aspect ratio electroplating structures provide more dense conductor pitch than current technology. For example, a high aspect ratio electroplating structure in accordance with various embodiments includes a conductor stack having a cross-sectional area of the conductor stack greater than 50%. In addition, high aspect ratio electroplating structures enable multiple conductor layers in accordance with embodiments. In addition, the high aspect ratio electroplating structure according to various embodiments enables precise interlayer alignment. For example, a high aspect ratio electroplated structure may have an interlayer alignment of less than 0.030 mm. High aspect ratio electroplating structures in accordance with various embodiments allow for reduced overall stack height.

High aspect ratio electroplating structures in accordance with various embodiments enable thin dielectric material between coils and magnets formed using high aspect ratio electroplating structures. This allows the coil to generate stronger electromagnetic fields than current printed circuit coils as shown in FIG. 1 . Thus, high aspect ratio electroplating structures are more cost effective, produce higher performance devices, and reduce the required footprint of the devices over current technology.

2 illustrates a high-density precision coil including a high-aspect-ratio electroplated structure according to an embodiment. High aspect ratio electroplated structures 202 are formed in-line with dielectric material between each row and each high aspect ratio electroplated structure 204 . High-density precision coils can be formed into helical coils or other coil types.

.

의 크기의 강도는 코일과 자석 사이의 거리에 따라 감소하므로

는 구리를 통해 유동하는 전류이다. 전도체가 아닌 단면(302)의 임의의 영역은 힘(

)에 기여하지 않는다.3 shows a diagram used to represent electromagnetic forces generated by a high-density precision coil comprising a high-aspect-ratio electroplated structure in accordance with an embodiment. This figure includes a coil section 302 proximate to a magnet 304 . The highest electromagnetic force 306 is in the coil layer 308 closer to the magnet 304 . The coil layer 310 further away from the magnet 304 applies less force. The main factors influencing force come from the Lorenz equation:

.

The magnitude of the strength decreases with the distance between the coil and the magnet, so

is the current flowing through the copper. Any region of cross-section 302 that is not a conductor is

) does not contribute to

The main factors affecting the force performance of a coil are the number of turns in the magnetic field (the winding closest to the magnet's poles will provide the greatest force), and the distance of the coil from the magnet (the layer closest to the magnet will apply more force). ), and the total percentage of copper cross-sectional area in the magnetic field. The use of high aspect ratio electroplating structures in accordance with various embodiments improves on this aspect compared to coils using current coil technology.

For example, a two-layer coil using current technology would have an overall thickness of about 210 micrometers, a conductor pitch of 38 micrometers, a cross-section percentage of about 20% copper, an estimated resistance of 3.1 ohms, an estimated The force ratio is 1.0 (estimated B ratio of 1.0 and estimated J ratio of 1.0) and the estimated power ratio is 1.0. In comparison, a high-density precision coil including a high-aspect-ratio electroplated structure according to various embodiments has an overall thickness of about 116 micrometers, a conductor pitch of 40 micrometers, a cross-sectional percentage of about 60% copper, and an estimated resistance of 5.5 ohms. , with an estimated force ratio of 1.2 (an estimated B ratio of 1.5 and an estimated J ratio of 0.8) and an estimated power ratio of 0.71. Accordingly, the high-density precision coil including the high-aspect-ratio electroplating structure according to various embodiments is a higher performance device. Thus, in accordance with some embodiments, these high-density precision coils provide 20% more power with 30% less power in a half-thick coil using current state-of-the-art technology.

필드(자속 밀도)의 장점을 취해 선형 모터의 힘 성능을 개선시킨다. 따라서, 선형 모터에 대한 다층 고종횡비 전기도금 구조의 사용은 현재의 기술을 사용하는 것보다 적은 층을 필요로 할 것이다. 또한, 이러한 구조는 낮은 저항과 같은 전기적 특성을 얻는데 더 큰 융통성을 제공한다.4 depicts a device comprising multiple layers of a high aspect ratio electroplated structure in accordance with an embodiment configured for a linear motor type application. Because of dimensional advantages over current technology, each layer 402a - d of the high aspect ratio electroplating structure more closely approximates the magnet 404 than is possible with current technology as shown in FIG. 1 . Also, the closer proximity of each layer 402a-d to the magnet 404 is

It takes advantage of the field (magnetic flux density) to improve the force performance of linear motors. Thus, the use of multilayer high aspect ratio electroplating structures for linear motors will require fewer layers than using current technology. In addition, this structure provides greater flexibility in obtaining electrical properties such as low resistance.

5 depicts a high aspect ratio electroplating structure in accordance with some embodiments at a stage during the manufacturing process. At this stage of the manufacturing process, a layer of high aspect ratio electroplated structure 602 is formed using semi-additive technology, having an initial height to width aspect ratio (A/B) of about 1:1. Create fine pitch, resist confinement, and conductors. For example, a high aspect ratio electroplated structure may have a height of 20 micrometers and a width of 20 micrometers. In accordance with some embodiments, the plating process is stopped at this point to remove confinement such as a seed layer and photoresist mask using techniques including those known in the art.

6 illustrates a high aspect ratio electroplating structure in accordance with some embodiments at another stage in the manufacturing process. At this stage in the manufacturing process, a layer of high aspect ratio electroplated structure 702 is formed using a crown plating technique to convert the semi-stacked conductor into a high aspect ratio, high percentage metal conductor circuit. For example, high aspect ratio electroplated structures have a final height to width ratio (A/S) greater than one to one. The final height to width ratio may range from 1.2 to 3.0 inclusive, according to various embodiments. Other embodiments include a final height-to-width ratio greater than 3.0. However, those skilled in the art will appreciate that any final height to width ratio can be obtained using the techniques described herein to meet design and performance criteria. In the forming step as shown in FIG. 6 formed from the previous step as shown in FIG. 5, there is no particular limitation on the final height of the high aspect ratio electroplating structure as disclosed in the various embodiments.

7 depicts a high aspect ratio electroplating structure at another stage during the manufacturing process, in accordance with some embodiments. At this stage of the manufacturing process, layers of high aspect ratio electroplated structures 802a,b are formed using planarization techniques for conversion, whereby multiple layers of high aspect ratio electroplated structures are laminated using semi-stacking techniques to form subsequent layers. make it possible to form 8 illustrates a device having multiple layers of a high aspect ratio electroplated structure in accordance with some embodiments having a high fraction of conductor cross-sectional area 901 .

Methods used to form high aspect ratio electroplating structures from structures such as those shown in FIG. 5 include using low current density plating techniques. This plating technique coats the sidewalls until the desired space is obtained between the high aspect ratio electroplating structures. In various embodiments, if the spacing between the high aspect ratio electroplating structures is not narrowed sufficiently, unwanted pinching at the top may occur. Pinching occurs where the top edges of adjacent structures grow together and close the gap, resulting in a short circuit. In various embodiments, the low current density plating process is improved by sufficient fluid exchange to ensure that a fresh plating bath is continuously available to the surface where copper plating is occurring. Methods used to form high aspect ratio electroplating structures also include the use of high current density plating techniques. This high current density plating technique operates at high percentage mass transfer limits. It plates primarily or only the top of the conductive material forming the high aspect ratio electroplating structure. Precise current density control improves the high current density plating process. 9 shows an upper line 1002 showing high SPS coverage during a high current density plating technique according to an embodiment and a bottom line 1004 showing a low, very uniform accelerator coverage during a low current density plating technique according to an embodiment. shows a graph with

10A-10F illustrate a process for forming a high aspect ratio electroplating structure in accordance with an embodiment. 10A shows a trace 1102 formed at the thick limit of resist performance at time T1 of the process. In some embodiments, pre-plated traditional traces are formed from copper using a process such as a damascene process or formed using etching and deposition techniques including those known in the art. 10B shows the formation of a high aspect ratio electroplating structure at time T2 during a low current density or conformal plating process. A conformal plating process according to an embodiment grows all surfaces of the trace at approximately the same rate. Additionally, conformal plating processes suppress plating kinetics (low accelerator coverage). The conformal plating process provides a very uniform metal concentration, which has high and uniform inhibitor coverage for compensation. This suppressed plating kinetics effect can be improved by including a leveler in the plating bath. Lower current densities are required to achieve uniform metal concentrations and high and uniform inhibitor coverage. According to some embodiments, a conformal plating process using 2 A/dm2 (amperes/square decimeter) is used, for example, for plating of copper, brightener additives, temperature and fluid dynamics of the plater. One example of such a conformal plating process includes, but is not limited to, a low current density plating process. At low current densities, the plating bath remains uniformly restrained to provide conformal plating. In another embodiment, the addition of a leveler may be used in the plating bath to provide higher current density and faster plating. In another embodiment, increasing the copper content closer to the solubility limit of copper sulfate in the plating bath may be used to further increase the current density. This provides the ability to double or even larger the current density to achieve the same conformal plating quality. For example, the copper content can be as high as 40 g/l at reduced acid content to prevent common ion effects.

In some embodiments, the low current density plating process deposits a conductive material, such as copper, on the top and sidewalls of the trace 1102 , for example, T2 is approximately 5 minutes after the onset of the process during the low current density plating process ( T1+5 min). 10C illustrates the formation of a high aspect ratio electroplating structure at time T3 after process initiation during a low current density plating process. In an embodiment, the low current density plating process deposits a conductive material, such as copper, on the top and sidewalls of the trace 1102 , for example, T3 is approximately 5 minutes after the onset of the process during the low current density plating process (T1 ). +15 min).

10D illustrates the formation of a high aspect ratio electroplating structure at time to process T4 during a crown plating process, such as a high current anisotropic super-plating process. For example, T4 is about 15 minutes and 10 seconds after the start of the process (T1 + 15 minutes and 10 seconds). In some embodiments, the high current anisotropic superplating process is crown plating. Crown plating is based on balancing the interaction between the following factors: metal concentration in solution; brightener additives; inhibitor additives; mass transfer - rate of fluid exchange with respect to a surface; leveler; and current density in the substrate. The metal concentration in the solution may include, but is not limited to, copper. Brightener additives may include SPS (bis(3-sulfopropyl)-disulfide), DPS (3-N,N-dimethylaminodithiocarbamoyl-1-propanesulfonic acid) and MPS (mercaptopropylsulfonic acid). can, but is not limited thereto. Inhibitor additives include co-block polymers of straight chain PEG, poloxamine, polyethylene and polypropylene glycol of various molecular weights, including those known to those skilled in the art, such as water-soluble poloxamers known under various trade names such as BASF Pluronic f127 and random copolymers such as high performance fluids of the DOW® UCON series of varying molecular weights and also varying proportions of monomers and polyvinylpyrrolidone of varying molecular weights.

A high current anisotropic superplating process in accordance with some embodiments includes a suppressed exchange current that is 1% of an accelerating current. In addition, the sidewalls of the high aspect ratio electroplated structures that are formed have near zero accelerator coverage. Near-zero accelerator coverage is achieved by shifting the Nernst potential for copper deposition to match the inhibitor coverage. In addition, high excess potential and copper solubility (transport phenomenon) result in high accelerator coverage at the top of the structure being formed. The copper bulk concentrate can also be tuned to support near-zero accelerator coverage during the process. For example, copper bulk concentrate for high current anisotropic superplating processes is 14 g/l or less. In some embodiments, the copper bulk concentrate is dependent on specific hydrodynamics. Because various embodiments of the process are run at a high fraction of the mass transfer limit, small differences in fluid velocity across the article to be plated will affect what the mass transfer limit is, so It is difficult to achieve sufficient control of the gap between the plated lines without a high degree of control. A high current anisotropic superplating process in accordance with some embodiments includes a leveler additive to eliminate accelerator coverage to minimize or eliminate plating on the sidewalls of the structure being formed. In another embodiment, a plating bath is used without leveler additives.

At elevated current densities, such as those used during high current anisotropic superplating processes, a triple feedback mechanism operates in accordance with some embodiments. The mass transfer effect depletes the copper in the space between the traces. Moreover, the high current density supports an accelerator (eg, SPS) dominant surface. Mass transfer is orchestrated to lower the Nernst potential through the copper mass transfer effect to keep the sidewalls in an inhibited state. For example, the fluid boundary layer thickness and the spacing between each trace are designed to lower the Nernst potential.

In addition, the high current anisotropic superplating process in accordance with some embodiments includes operating at copper concentrations where these differences can create greater than four-fold concentration differences. Under these conditions, the low copper concentration and the Nernst dislocation contribute to the reduction of the plating rate. For example, when the Nernst potential shifts in the range of approximately 50 millivolts (“mV”) to 60 mV, it can contribute to a 20-fold reduction in plating rate. This condition induces Tafel dynamics in which the current changes tenfold for every 120 mV change in the applied voltage rather than the rectifier voltage in the case of copper plating. The low sidewall current is fed back to the top surface of the structure being formed with a short diffusion length, promoting faster metal transfer from the plating bath (solution) to the surface and instead of suppression, higher accelerator coverage and higher Nernst potential. In some embodiments, two additive systems (eg, brighteners and inhibitors) are used. The leveler blocks the SPS action of the top side of the plated features, reducing the feedback mechanism.

As the spacing between metal conductors or traces continues to shrink, the height-to-width aspect ratio of the space between the metal conductors substantially increases. In accordance with some embodiments, the methods of the electroplating process provided herein achieve plating at a spacing between metal conductors with an aspect ratio of at least 7:1.

A method of forming a high aspect ratio electroplating structure in accordance with some embodiments provides for the selective formation of metal crown plating at selective locations or regions. In one exemplary embodiment, the selective formation of the metal crown is achieved by performing an electroplating process according to the following relationship:

는 물질 전달 한계의 67 퍼센트(%) 이상이다. 다른 실시예에 따르면, 금속 크라운의 선택적 형성은 다음 관계에 따라 전기도금 프로세스를 수행함으로써 달성된다:where C is the concentration of the metal to be plated (copper in this case), and C infinity is the bulk concentration of the plating bath. This relationship can also be expressed as performing a phosphorus electroplating process, where

is greater than or equal to 67 percent (%) of the mass transfer limit. According to another embodiment, the selective formation of the metal crown is achieved by performing an electroplating process according to the following relationship:

는 물질 전달 한계의 80% 이상이다. 다른 양태에서, 금속 크라운의 선택적 형성은 다음 관계에 따라 전기도금 프로세스를 수행함으로써 달성된다:or here

is greater than 80% of the mass transfer limit. In another aspect, selective formation of the metal crown is accomplished by performing an electroplating process according to the following relationship:

where i is the current density and i _limit is the current density limit.

10E shows the formation of a high aspect ratio electroplating structure at time T5 during a high current anisotropic superplating process. For example, T5 is about 15 minutes and 30 seconds after the start of the process (T1 + 15 minutes and 30 seconds). In another embodiment, the formation of a high aspect ratio electroplated structure as shown in FIG. 10E occurs at time T5=T1+5 minutes. 10F shows the formation of a high aspect ratio electroplating structure at time T6 during a high current anisotropic superplating process. This describes the end of the crown plating process that completes the formation of the high aspect ratio electroplating structure in accordance with some embodiments. For example, T6 is about 20 minutes (T1+20 minutes) after the start of the process. In another embodiment, the formation of a high aspect ratio electroplated structure as shown in FIG. 10F occurs at time T6=T1+10 minutes.

In some embodiments, a method of forming a high aspect ratio electroplating structure uses a process including conformal plating and anisotropic plating as described herein. The conformal plating process uses 2/3 of the total plating time in accordance with some embodiments. In another embodiment, the conformal plating process uses 1/3 of the total plating time. Also, the conformal plating process starts at 2 A/dm 2 (“ASD”) for a low metal plating bath or 4 ASD for a high metal plating bath. For example, the plating bath contains 12 g/l copper and 1.85 moles (mol/l) sulfuric acid. Alternatively, the conformal plating process is a process of plating at a rate of 0.4 to 1.2 μm/min. The conformal plating process according to an embodiment continues until the spacing between the traces reaches a range comprising 6-8 micrometers. The current density will slowly decrease as the surface area of the structure being formed increases. However, this process will achieve a uniform current density and growth rate of all surfaces being formed. In some embodiments, the current may be increased to maintain the current density as the surface area of the high aspect ratio structure being formed increases.

According to some embodiments, the anisotropic plating process uses 1/3 of the total plating time to form a high aspect ratio electroplating structure. The anisotropic plating process increases the ASD to 7 ASD (3.5 times the current of the conformal plating process), but on average doubles that at the top of the metal structure being formed. The same fluid flow used in the conformal plating process can be maintained. For example, the plating rate is 3 μm/min, and the top of the structure is formed on the sidewalls of the structure at near zero plating rate. As the structure grows, the average current decreases by half, but the peak current density remains at about 14 ASD at the top of the structure according to an embodiment. For example, the peak current density slightly exceeds the 50% mass transfer limit of the top surface, and the sidewalls are plated at less than 10% mass transfer limit or a 5:1 plating rate even though the sidewalls are exposed to about 3 g/l of copper. do. At higher fractions of the mass transfer limit, higher plating rate ratios can be achieved.

Embodiments of a method of forming a high aspect ratio electroplating structure include variations on those previously described to form a high aspect ratio electroplating structure including different properties. For example, the copper content of a plating bath composed of an anisotropic bath may differ from 13.5 g/l as described above. Varying the copper content of the flat trace bath while using the same current density can be used to control the spacing between high aspect ratio electroplating structures. Another embodiment of the method described herein includes using a flat trace bath having a flat trace bath having a copper content of 12 g/l to form a high aspect ratio electroplating structure spaced 8 microns apart. Another embodiment of the method described herein includes using a flat trace bath having a flat trace bath of 15 g/l to form a high aspect ratio electroplating structure spaced 4 microns apart. Accordingly, it will be understood by those skilled in the art that adjusting other parameters of the methods described herein can be used to alter the properties of high aspect ratio electroplating structures. Some embodiments of the methods described herein include adjusting the current density to suit current plater conditions, such as mass transfer rates, metals contained in the plating bath, fluid rates, copper concentrations, additives used, and temperature. .

Methods of forming high aspect ratio electroplating structures also include using thin dielectric processes. In accordance with some embodiments, a photosensitive polyimide is used as the dielectric between each high aspect ratio electroplating structure. Liquid photosensitive polyimide enables small via capability, good coverage between high aspect ratio conductors, good registration/margin capability, is a high reliability material, and has a coefficient of thermal expansion that closely matches that of copper (" CTE"). Liquid photosensitive polyimides can easily fill the gaps between high aspect ratio electroplated structures. According to some embodiments, the use of liquid photosensitive polyimide is used to create via access up to 0.030 millimeters. Other dielectrics that may be used include, but are not limited to, KMPR and SU-8.

11 illustrates a high aspect ratio electroplating structure in accordance with some embodiments formed using the methods described herein. Each high aspect ratio electroplating structure 1202 includes a number of grain lines 1204 indicating how the electroplating process proceeds to form the structure. A thin dielectric 1206 is formed between the high aspect ratio electroplated structures 1202 and disposed over the high aspect ratio electroplated structures 1202 . 12 shows a perspective view of a high aspect ratio electroplating structure 1302 in accordance with some embodiments formed using the methods described herein.

The methods described herein can be used to form high aspect ratio electroplated structures that form high density precision coils. 13A illustrates a high-density precision coil formed using a high-aspect-ratio electroplating structure in accordance with an embodiment. Coil 1402 is formed of a high aspect ratio electroplated structure as described herein. The high-density precision coil also includes a central coil via 1404 . The central coil via 1404 reduces the voltage drop across the coil during the fabrication steps described herein. The central coil via 1404 also enables the ability to better control the variability of pitch within the coil through better control of voltage drop and current during the anisotropic plating process described herein. The central coil via 1404 also allows better control of the voltage drop of the formed high-density precision coil. 13B shows a cross-section of a central coil via 1404 as part of a high-density precision coil described herein.

14 illustrates a high aspect ratio electroplating structure including a high resolution laminated conductor layer according to an embodiment. The first conductor layer 1502a includes a high aspect ratio electroplated structure 1504 formed using techniques including those described herein. The first dielectric layer 1508 is formed using a thin dielectric process using techniques including those described herein. The first dielectric layer 1508 fills all the spaces between the high aspect ratio electroplated structures of the first conductor layer 1502a and forms a coating over the high aspect ratio electroplated structures 1504 . The first dielectric layer 1508 is planarized using techniques known in the art. The second conductor layer 1502b includes a high aspect ratio electroplated structure 1506 formed on the planarized surface of the first dielectric layer 1508 . The second dielectric layer 1510 includes those described herein to fill all spaces between the high aspect ratio electroplated structures 1506 of the second conductor layer 1502b and to form a coating over the high aspect ratio electroplated structures 1506 . It is formed using a thin dielectric process using The second dielectric layer 1510 may also be planarized. Additional layers comprising high aspect ratio electroplating structures may be formed using the techniques described herein.

15 illustrates a high-density precision coil comprising a high-aspect ratio electroplated structure in accordance with an embodiment that includes a high-resolution laminated conductor layer. The first conductor layer 1602a includes a high aspect ratio electroplated structure formed using techniques including those described herein. The first dielectric layer 1608 is formed using a thin dielectric process using techniques including those described herein. The first dielectric layer 1608 fills all the spaces between the high aspect ratio electroplated structures of the first conductor layer 1602a and forms a coating over the high aspect ratio electroplated structures. The first dielectric layer 1608 is planarized using techniques known in the art. The second conductor layer 1602b includes a high aspect ratio electroplated structure formed on the planarized surface of the first dielectric layer 1608 . The second dielectric layer 1610 fills all the spaces between the high aspect ratio electroplated structures of the second conductor layer 1602b and forms a coating over the high aspect ratio electroplated structures using techniques including those described herein. formed using the process. The second dielectric layer 1610 may also be planarized. Additional layers comprising high aspect ratio electroplating structures may be formed using the techniques described herein.

The high-density precision coil is formed with a first distance 1614 between the high aspect ratio electroplated structure of the first conductor layer 1602a and the high aspect ratio electroplated structure of the second conductor layer 1602b. In various embodiments, the first distance 1614 is less than 0.020 millimeters. In another embodiment, the first distance 1614 is 0.010 millimeters. The high-density precision coil is formed with a second distance 1616 between the surface 1618 of the second dielectric layer 1610 and the high aspect ratio electroplated structure of the first conductor layer 1602a. In various embodiments, the second distance 1616 is less than 0.010 millimeters. In some embodiments, the second distance 1616 is 0.005 millimeters. In some embodiments, the second distance 1616 may be the starting gap minus the final desired gap divided by two. The high-density precision coil is formed to have a third distance 1620 between the high aspect ratio electroplated structure of the first conductor layer 1602a and the surface of the first dielectric layer 1622 . In various embodiments, the third distance 1620 is less than 0.020 millimeters. In some embodiments, the third distance 1620 is less than 0.015 millimeters. In another embodiment, the third distance 1620 is 0.010 millimeters. In various embodiments, a first dielectric layer is formed on the substrate 1624 using techniques including those described herein. In some embodiments, the substrate 1624 is a layer of stainless steel. Those skilled in the art will be able to fabricate the substrate 1624 from other materials including, but not limited to, steel alloys, copper alloys such as bronze, pure copper, nickel alloys, beryllium copper alloys, and other metals including those known in the art. It will be understood that it is possible to form

Other advantages of forming devices using high aspect ratio electroplating structures as described herein include devices having high structural strength, high reliability, and high heat dissipation capacity. High structural strength is provided through the ability to form very dense metal high aspect ratio electroplating structures in all layers of the device. In addition, the process of forming the metal high aspect ratio electroplating structures described herein provides cross-directional alignment of the interlayer structures that add high structural strength. The high structural strength of devices formed using the process for forming metal high aspect ratio electroplating structures described herein is also a result of good adhesion to structures of dielectric layer materials, such as photosensitive polyimide layers. In some embodiments, high aspect ratio electroplating structures formed using the techniques described herein are coated with a layer of nonmagnetic nickel to increase adhesion of the dielectric layer. This will further increase the high structural strength of final devices formed using the high aspect ratio electroplating structures described herein.

Additionally, the reliability of devices formed using the high aspect ratio electroplating structures described herein is high due to the use of high reliability materials such as photosensitive polyimide for the dielectric layer that provides robust electrical performance. Use of the techniques described herein provides the ability to form devices with less dielectric material and reduce the overall thickness of the formed devices. Thus, heat dissipation increases due to increased thermal conductivity compared to devices using current process technology.

16A-16C illustrate a process for forming a high aspect ratio electroplating structure in accordance with another embodiment. 16A shows a trace 1802 formed on a substrate 1804 using a scribe etch. A metal layer is formed over the substrate 1804 , in accordance with some embodiments. A photoresist layer is formed over the metal layer using techniques, including techniques known in the art. In some embodiments, the photoresist layer is a photosensitive polyimide deposited over the metal layer in liquid form. The photoresist is patterned and developed using techniques including techniques known in the art. The metal layer is then etched using techniques including techniques known in the art. After the etching process, traces 1802 are formed.

16B illustrates the formation of a high aspect ratio electroplating structure using a conformal plating process as described herein. 16C illustrates the formation of a high aspect ratio electroplating structure using a crown plating process as described herein. In various embodiments, the high aspect ratio electroplating structure is formed without using a conformal plating process such as that described with reference to FIG. 16B . Instead, a crown plating process as described with reference to FIG. 16C is used after formation of the trace 1802 as shown in FIG. 16A .

17 illustrates the selective formation of a high aspect ratio electroplating structure in accordance with an embodiment. Once the traces 1902 are formed using techniques including the techniques described herein, a photoresist layer 1904 is formed over the one or more sections of the formed traces 1902 . The photoresist layer 1904 may be a photosensitive polyimide and is deposited and formed using techniques including those described herein. A metal crown 1906 is formed on the trace 1902 using one or both of a conformal plating process and a crown plating process as described herein. 18 illustrates a perspective view of a high aspect ratio electroplating structure in accordance with an embodiment formed to have a metal crown portion selectively formed on the trace. According to some embodiments, the selective formation of metal crown portions on the traces improves structural properties of the high aspect ratio electroplating structure, improves the electrical performance of the high aspect ratio electroplated structure, improves heat transfer properties, and improves the high aspect ratio electroplating structure, in accordance with some embodiments. Used to meet custom dimensional requirements for devices formed using the structure. Examples of electrical performance improvements include, but are not limited to, capacitance, inductance, and resistance characteristics of high aspect ratio electroplated structures. Additionally, the selective formation of metal crown portions on the traces can be used to tune the mechanical or electrical properties of circuits formed using high aspect ratio electroplating structures.

19 illustrates a hard drive disk suspension flexure 2102 comprising a high aspect ratio electroplated structure in accordance with an embodiment formed using selective forming as described herein. 20 shows a cross-sectional view of the hard disk drive suspension flexure shown in FIG. 19 taken along line A-A. A cross-section of flexure 2102 includes high aspect ratio electroplated structures 2104 and traces 2106 . The high aspect ratio electroplated structure 2104 is formed using selective forming techniques as described herein. Forming a high aspect ratio electroplated structure 2104 for use as a conductor in a predetermined region of the flexure may achieve a reduction in DC resistance. This makes it possible to form fine lines and spaces at required positions on the flexure, while at the same time meeting the design requirements for DC resistance and improving the electrical performance of the flexure.

21A and 21B illustrate a process for forming a high aspect ratio electroplating structure according to an embodiment using photoresist during a conformal plating process. 21A shows a trace 2302 formed on a substrate 2304 using techniques including those described herein. 21B illustrates forming a high aspect ratio electroplating structure using a plating process as described herein. A photoresist portion 2306 is formed over the substrate 2304 using deposition and patterning techniques, including those described herein. Once the photoresist portion 2306 is formed, one or both of a conformal plating process and a crown plating process are performed to form the metal portion 2308 on the trace 2302 . The photoresist portion 2306 may be used to better define the spacing between the high aspect ratio electroplating structures.

22 depicts exemplary chemistries used in a process for forming an initial metal layer, a standard/conformal plating process, and a crown plating process in accordance with various embodiments.

23 shows a perspective view of a top surface 2501 of an inductively coupled coil 2502 formed from a high aspect ratio electroplated structure 2504 in accordance with an embodiment having an integrated tuning capacitor. The use of high aspect ratio electroplated structures to form the inductively coupled coil reduces the footprint of the inductively coupled coil compared to inductively coupled coils that use current technology to form the coil. This allows the inductively coupled coil 2502 to be used in applications where space is limited. In addition, the use of integrated capacitors in the inductively-coupling coil further reduces the footprint of the inductively-coupled coil as no additional space requirements are required to accommodate discrete capacitors such as surface mount technology (“SMT”) capacitors.

FIG. 24 shows a perspective view of the back surface 2604 of the embodiment of the inductive coupling coil 2502 shown in FIG. 23 . 25 shows a perspective view of the top surface of an inductive coupling coil 2502 in accordance with an embodiment coupled with a radio frequency identification (“RFID”) chip 2704 .

26A-26J illustrate a method of forming an inductively coupled coil 2502 formed from a high aspect ratio electroplated structure 2504 in accordance with an embodiment. According to various embodiments, the inductively coupled coil includes an integrated tuning capacitor. 26A shows a substrate 2802 formed using techniques, including techniques known in the art. In some embodiments, substrate 2802 is formed of stainless steel. Other materials that may be used for the substrate include, but are not limited to, steel alloys, copper, copper alloys, aluminum and non-conductive materials that may be metallized using techniques including plasma vapor deposition, chemical vapor deposition, and electroless chemical deposition. it doesn't happen A shadow mask 2804 is formed over the substrate 2802 . Shadow mask 2804 in accordance with some embodiments is a high-K dielectric. Examples of high-K dielectrics that may be used include titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, SU-8, KMPR and others. High permittivity dielectric materials include, but are not limited to. According to some embodiments, the shadow mask 2804 is formed using a sputter process using techniques including techniques known in the art. In some embodiments, shadow mask 2804 is formed to have a thickness in a range including 500 to 1000 angstroms. In another embodiment, the shadow mask 2804 is formed using screen printing of a high-k ink. Examples of high-k inks are from one or more of titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, and other high-k dielectric materials. It includes an ink containing epoxy loaded with particles made of. In another embodiment, the shadow mask 2804 is formed using a slot die application of a photo-imageable dielectric doped with a high-K filler. Examples of high-K fillers include zirconium dioxide (ZrO2).

26B shows a metallic capacitor plate 2806 formed over shadow mask 2804. Metallic capacitor plate 2806 and substrate 2802 form the two capacitor plates of the integrated capacitor. The thickness of the shadow mask 2804 may be used to set the effective capacitance of the integrated capacitor. Also, the purity of the high-K dielectric used to form the shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. The surface area of the metallic capacitor plate 2806 may also be used to set the effective capacitance of the integrated capacitor.

26C shows a shadow mask 2804 , a metallic capacitor plate 2806 , and a base dielectric layer 2808 formed over at least a portion of the substrate 2802 . According to some embodiments, the base dielectric layer 2808 is formed by depositing a dielectric material, patterning the dielectric material, and curing the dielectric material using techniques including techniques known in the art. Examples of dielectric materials that may be used include, but are not limited to, polyimide, SU-8, KMPR and hard baked photoresists such as those sold by IBM®. Base dielectric layer 2808 may be patterned or etched to form vias. For example, jumper vias 2812 and shunt capacitor vias 2810 are formed in base dielectric layer 2808 . A shunt capacitor via 2810 is formed to interconnect the integrated capacitor to the remainder of the circuit to be formed. Similarly, jumper vias 2812 are used to interconnect circuit elements to be formed on substrate 2802 .

26D shows a coil 2814 formed over a base dielectric layer 2808 using a high aspect ratio electroplating structure to form the coil using techniques including techniques described herein. In some embodiments, coil 2814 is a single layer coil. The coil 2814 includes a central connection 2816 that connects to one of the shunt capacitor vias 2810 and one of the jumper vias 2812 in electrical contact with the metallic capacitor plate 2806 of the integrated capacitor. Coil 2814 also includes a capacitor connection 2818 for connecting coil 2814 to the other of shunt capacitor vias 2810 in electrical contact with a substrate 2802 configured as a bottom plate of an integrated capacitor. According to various embodiments, the terminal pad 2820 is formed of a high aspect ratio electroplating structure using techniques, including techniques described herein. Terminal pads 2820 may be formed during the same process of forming coil 2814 .

26E shows a covercoat 2822 formed over the coil 2814 , the terminal pad 2820 , and the base dielectric layer 2808 to surround the coil side of the inductively coupled coil. The covercoat 2822 is formed using deposition, etching, and patterning steps, including those known in the art. Covercoat 2822 may be formed of, for example, polyimide solder mask, SU-8, KMPR, or epoxy.

26F shows the rear side of an inductively coupled coil formed in accordance with an embodiment. At least a first solder pad 2824 and a second solder pad 2826 are formed on opposite sides of the substrate 2802 from the coil 2814 . According to some embodiments, first solder pad 2824 and second solder pad 2826 are formed of gold using deposition and patterning techniques, including those known in the art. A first solder pad 2824 and a second solder pad 2826 are formed to provide electrical contacts for attaching an integrated circuit chip, such as an RFID chip, to the substrate 2802 .

26G shows a backside dielectric layer 2828 formed on the backside of an inductively coupled coil formed in accordance with an embodiment. A method of forming an inductively coupled coil may optionally include forming a backside dielectric layer 2828 on a substrate 2802 . Backside dielectric layer 2828 is formed using techniques similar to those for forming base dielectric layer 2808 . In accordance with some embodiments, the backside dielectric layer 2828 is patterned to prevent shorting between the substrate 2802 and the attached integrated circuit chip. The backside dielectric layer 2828 according to various embodiments is patterned to provide a jumper pattern 2830 for the substrate 2802 to be etched to form jumper paths in a subsequent step. Other patterns of the backside dielectric may also be formed to etch other portions of the substrate 2802 .

26H shows an inductively coupled coil 2834 according to an embodiment formed into its final shape. The portion of the substrate 2802 not covered by the backside dielectric layer 2828 is etched. This etched portion includes a jumper pattern 2830 to form a jumper path 2832 . Etching is performed using techniques, including techniques known in the art. Those skilled in the art will appreciate that other portions of substrate 2802 may be etched to form other conductive paths similar to jumper paths 2832 . 26I shows the coil side of an inductively coupled coil 2834 according to an embodiment that includes a jumper path 2832 .

26J shows the coil side of an inductive coupling coil 2834 according to an embodiment, which includes an integrated chip 2836 attached to the back side of the induction coil. The method of forming the inductively coupled coil 2834 may optionally include attaching an integrated chip 2836, such as an RFID chip, to the inductively coupled coil 2834 using techniques including techniques known in the art. can These integrated chips 2836 are attached using adhesives including, but not limited to, conductive epoxies, solders, and other materials used to connect electrical connections.

Integrating capacitors into devices including high aspect ratio electroplating structures provides the ability to take advantage of the small footprint requirements enabled by high aspect ratio electroplating structures. Another embodiment of an inductively coupled coil includes an inductively coupled coil having a plurality of integrated capacitors. Integrated capacitors may be connected in parallel or series as is known in the art. Other devices incorporating high aspect ratio electroplating structures that may include integrated capacitors include, but are not limited to, buck converters, signal conditioning devices, tuning devices, and other devices including one or more inductors and one or more capacitors.

High aspect ratio electroplating structures according to embodiments described herein may be used to form devices or form part of devices to optimize performance and achieve small footprints. These devices include power converters (e.g. buck transformers, voltage dividers, AC transformers), actuators (e.g. linear, VCM), antennas (e.g. RFID, wireless power delivery and security chips for battery charging) , wireless passive coils, rechargeable cell phone and medical device batteries, proximity sensors, pressure sensors, contactless connectors, micromotors, microfluidic devices, cooling/heat sinks on package, long and narrow flexible circuits with air core capacitance and inductance ( Magnetic resonance imaging for e.g. catheters), interdigit acoustic wave transducers, haptic vibrators, implants (e.g. pacemakers, stimulators, bone growth devices), procedures (e.g., esophagus, colonoscopy) (“MRI”) devices, beyond haptic (eg, clothing, gloves), coated surfaces for detection/unfiltering, security systems, high energy density batteries, induction heating devices (for small local areas) , magnetic fields for fluid/drug dispersion and dose delivery via channel pulses, tracking and information devices (e.g. agriculture, food, valuables), credit card security, acoustic systems (e.g. speaker coils, recharging of headphones) mechanisms, earphones), heat transfer, mechanical-heat conduction seals, energy harvesters, and interlocking features (similar to hook and loop fasteners). In addition, high aspect ratio electroplating structures as described herein can be used to form high bandwidth, low impedance interconnects. The use of high aspect ratio electroplated structures in interconnects can be used to improve electrical properties (e.g., resistance, inductance, capacitance), improve heat transfer properties, and customize dimensional requirements (thickness control). Interconnects comprising high aspect ratio electroplating structures as described herein may be used to tune the bandwidth of one or more circuits for a given frequency range. Other interconnect applications involving high aspect ratio electroplating structures may integrate one or more circuits of varying currents (eg, signals and power). The use of high aspect ratio electroplating structures enables circuits with different cross-sections, some of which can be fabricated together in close proximity to maintain a condensed overall package size with more current carrying capacity. High aspect ratio electroplated structures may also be used in interconnects for mechanical purposes. For example, it may be desirable to project some areas of a circuit over others to function as mechanical stops, bearings, electrical contact areas, or to provide added stiffness.

27 shows a plan view of a flexure for a suspension for a hard disk drive including a high aspect ratio electroplated structure according to an embodiment. The flexure 2900 includes a distal portion 2901 , a gimbal portion 2902 , a middle portion 2904 , a gap portion 2906 , and a proximal portion 2908 . The proximal portion 2908 is configured to attach to the baseplate such that the distal portion 2901 extends over the rotating disk medium. Gimbal portion 2902 in accordance with some embodiments includes one or more motors, such as a piezoelectric motor, and one or more electrical components, such as a head slider and heat-assisted magnetic writing (“HAMR”)/ and components for thermally-assisted magnetic recording (“TAMR”) or microwave assisted magnetic recording (“MAMR”). The one or more motors and one or more electrical components extend from the distal portion 2901 of the flexure 2900 through the intermediate portion 2904 over the gap portion 2906 and beyond the proximal portion 2908 . electrically connected to other circuits through one or more traces formed on the conductor layer of Gap 2906 is a portion of the flexure from which a substrate layer, such as a stainless steel layer, has been partially and completely removed. Accordingly, one or more traces in the conductor layer of the flexure extend over the gap portion 2906 without any support. Those skilled in the art will appreciate that the flexure may have one or more gaps 2906 at any location along the flexure.

FIG. 28 shows a cross section of the gap portion of the flexure at the gap portion taken along line A as shown in FIG. 27 . Interstitial portions 2906 include traces 3002 disposed over dielectric layer 3004 . A dielectric layer, such as a polyimide layer, is disposed over the substrate 3006, such as a stainless steel layer. Substrate 3006 and dielectric layer 3004 form voids 3008 such that traces 3002 extend over voids 3008 . Trace 3002 includes a metal crown portion for forming a high aspect ratio structure. Metal crown portions are selectively formed on trace 3002 using techniques described herein. A metal crown portion is formed on the trace 3002 to provide additional strength to span the void 3008 and, in use, electrically engage the interconnects in the region of the void 3008 .

29 shows a gimbal portion 2902 having a mass structure 3102 according to an embodiment. Mass structure 3102 is formed using a high aspect ratio electroplating structure using the techniques described herein. In some embodiments, the mass structure 3102 is used as a weight to tune the resonance of the gimbal portion 2902 . Accordingly, the shape, size, and location of the mass structure 3102 may be determined to tune the resonance of the gimbal portion 2902 to improve the performance of the hard drive suspension. The processes described herein used to form high aspect ratio structures can be used to maintain the size of high aspect ratio structures so that resonances can be finely tuned. Moreover, this process can form high aspect ratio structures at dimensions beyond the capabilities of current lithographic processes, allowing better control over the final structures formed.

Mass structure 3102 may also be configured for use as a mechanical stop. For example, one or more mechanical stops may be formed into any shape that acts as a backstop and/or may be used to align the mounting of components on gimbal portion 2902 or other portions of the flexure. can

30 illustrates a cross-section of a proximal portion of a flexure comprising a high aspect ratio electroplated structure according to an embodiment taken along line B as shown in FIG. 27 . Proximal portion 2904 includes a conductor layer comprising traces 3002a,b,c,d disposed over dielectric layer 3004 . A dielectric layer 3004 is disposed over the substrate 3006 . A cover layer 3001 is disposed over the conductor layer and the dielectric layer. The conductor layer includes conventional traces 3002a,b and 3002c,d, wherein at least a portion of the traces are formed by a metal crown portion 3202a, to form a high aspect ratio electroplated structure using the techniques described herein. b) is formed to include. One or more portions of traces 3002a,b,c,d may be formed to include metal crown portions 3202a,b to tune the impedance of each trace. For example, the resistance of the trace may be tuned as needed to meet desired performance characteristics. Another example includes using a metal crown portion to tune the impedance by closing the distance between adjacent traces 3002a,b,c,d.

31 illustrates a cross-section of a proximal portion of a flexure comprising a high aspect ratio structure according to an embodiment taken along line C as shown in FIG. 27 . The proximal portion of the flexure includes a conductor layer including at least one trace 3002 disposed over the dielectric layer 3004 . A dielectric layer 3004 is disposed on the substrate 3008 . In addition, a cover layer 3001 is disposed over what is formed to include a metal crown portion to form a high aspect ratio electroplating structure using the techniques described herein. Trace 3002 is constructed in a high aspect ratio structure to match the impedance of the trace with the terminating connector and to provide strength to the joint that electrically couples trace 3002 with the connector. 32 shows a top view of a proximal portion 2908 of a flexure comprising a high aspect ratio structure in accordance with an embodiment. The use of high aspect ratio structures as described for use with flexures is also applicable to other circuit board technologies, such as, for example, use in microcircuits and radio frequency (“RF”) circuits.

33 illustrates a process for forming a high aspect ratio electroplating structure in accordance with an embodiment. As shown, a copper layer 3318 is used as the substrate. However, other conductive materials may be used as the substrate. At 3301 , a dielectric layer 3320 as described herein is disposed over the copper layer 3318 , marked and punched. Dielectric layer 3320 may be formed using materials including, but not limited to, optically imageable or non-optically imageable materials, polymers, ceramics, and other insulating materials. Copper layer 3318 is, in some embodiments, a copper alloy layer as described herein. In some embodiments, one or more through holes or vias 3322 are marked and punched in the dielectric layer to expose the copper layer 3318 . According to some embodiments, dielectric layer 3320 is an optically imageable dielectric material and one or more through holes or vias 3322 are created using patterning and developing techniques including those described herein. Other embodiments include using laser drilling or laser etching in dielectric layer 3320 to create one or more through holes or vias 3322 . In some embodiments, the copper alloy layer has a thickness in a range comprising from 15 microns to 40 microns. At 3302 , traces 3324 or other conductive features are disposed on the dielectric layer 3320 on the side of the dielectric layer opposite the copper layer 3318 . In some embodiments, the seed layer is sputtered to form a pattern on the dielectric layer 3320 using techniques including those described herein. Another embodiment includes using electroless plating to form the seed layer. A plating process such as that described herein is used to form one or more traces 3324 and conductive features to a desired thickness using techniques including those described herein.

At 3304 , a conformal plating process such as that described herein is applied to the conductive features and one or more traces on the side of the dielectric layer 3320 opposite the copper layer 3318 using techniques including those described herein. Used to build one or more traces and conductive features to further enhance shape or increase thickness. In some embodiments, at 3304 , a crown plating process as described herein is used in addition to a conformal plating process on the side of dielectric layer 3320 opposite to copper layer 3318 . In some embodiments, a crown plating process is used instead of a conformal plating process.

At 3306 , a dielectric layer 3326 , such as a covercoat, is placed on the conductive features and one or more traces 3324 on the side of the dielectric layer opposite the copper layer 3318 using techniques including those described herein. is placed on In some embodiments, no covercoat is included. For example, the one or more traces 3324 and conductive features formed may be plated with a layer of gold. At 3308 , the copper layer 3318 is etched to form a pattern using techniques including techniques described herein. In some embodiments, the copper layer 3318 is etched to form one or more traces 3328 and/or one or more conductive features.

At 3310 , a conformal plating process as described herein further enhances the shape of one or more traces 3328 and conductive features formed in copper layer 3318 using techniques including those described herein, or used to build one or more traces 3328 and conductive features to increase the thickness. In some embodiments, at 3310 , a crown plating process as described herein is used in addition to the conformal plating process on the copper layer 3318 . In some embodiments, a crown plating process is used instead of a conformal plating process.

At 3312 , a dielectric layer 3330 , such as a covercoat, is disposed over the conductive features and one or more traces 3328 formed from the copper layer 3318 using techniques including those described herein. In some embodiments, no covercoat is included. For example, the formed one or more traces 3328 and conductive features may be plated with a layer of gold. In some embodiments, the process is used to fabricate multiple circuits or devices on a single substrate. In such an embodiment, at 3316 the circuit or device may be singulated and optionally packaged using techniques including those known in the art. In some embodiments, circuits and/or devices are singulated using techniques including, but not limited to, laser ablation, fracturing, cutting, etching, and the like. In some embodiments, the covercoats described herein may be patterned using the patterning techniques described herein. For example, a covercoat is applied to the blanket layer. According to some embodiments, the covercoat is applied using a slot die coat to apply the optically imageable dielectric material. Other techniques may be used, such as roller coating, spray coating, dry film lamination or other known methods for applying light imageable or non-light imageable materials. If the material is non-optically imageable, other methods may be used to pattern the material (eg, laser or etching). In some embodiments, one or both of the dielectric layers/covercoats may be formed to have a surface finish, for example to aid adhesion to other structures or substrates. In some embodiments, the surface finish is formed on the dielectric layer/covercoat by texturing or patterning the dielectric layer/covercoat.

In some embodiments, at 3314 , terminal pads 3332 , such as nickel terminals plated with a gold layer, may be formed on the substrate 3318 using electroless plating and solder may be provided. According to some embodiments, the surface finish formed on the exposed copper layer disposed on the top and/or bottom side is plated using electroless or electrolytic plating of nickel, gold, or other industry standard surface finish. Also, solder may be applied to these areas.

34 shows a more detailed process similar to the type described with reference to FIG. 33 used to form a high aspect ratio electroplating structure in accordance with some embodiments.

35 shows a coil made using the process described herein. Coil 3501 includes multiple, eg, three or more, coil sections that are electrically coupled to form coil 3501 . In some embodiments, such as shown in FIG. 35 , the number of turns in the outer coil section 3504 is equal to the inner coil section 3502 between the two outer coil sections 3504 . In some embodiments, inner coil section 3402 includes more windings than outer coil section 3504 . Another embodiment includes, for example, with reference to FIG. 35 , a plurality of coil sections having a subset of the plurality of coil sections electrically coupled, two of the plurality of coil sections being electrically coupled and the remaining coil sections being electrically coupled. is not electrically coupled to the other two coil sections. Accordingly, any combination of any number of coil sections may be included in any number of coil sections electrically coupled to any other coil section.

A plurality of layers including any one or more of the traces and conductive features made using the techniques described herein may be formed by laminating each layer, wherein the connections between each layer are formed using a conductive adhesive, such as a conductive adhesive. It may consist of a via through a layer filled with a conductive material.

According to some embodiments, the processes described herein are used to form coils integrated with other circuit components, such as resistance temperature detectors (RTDs), strain gauges, and other sensors.

According to some embodiments, the processes described herein are used to form any one or more of a mechanical structure and an electromechanical structure.

Although described in connection with these embodiments, those skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

Claims (20)

is a device,
a dielectric layer having a first surface and a second surface;
a first set of high aspect ratio electroplating structures disposed on a first surface of the dielectric layer;
An apparatus comprising a second set of high aspect ratio electroplated structures disposed on a second surface of the dielectric layer opposite the first set of high aspect ratio electroplated structures. The apparatus of claim 1 including a second dielectric layer disposed over the first set of high aspect ratio electroplated structures. The apparatus of claim 1 including a third dielectric layer disposed over the second set of high aspect ratio electroplated structures. The dielectric layer of claim 1 , wherein the dielectric layer electrically couples at least one high aspect ratio electroplated structure of the first set of high aspect ratio electroplated structures with at least one high aspect ratio electroplated structure of the second set of high aspect ratio electroplated structures. A device comprising vias for facilitating The apparatus of claim 1 , wherein the first set of high aspect ratio electroplated structures and the second set of high aspect ratio electroplated structures are configured to form a coil. The apparatus of claim 1 , configured to form a coil having two outer coil sections and an inner coil section between the two outer coils. The apparatus of claim 1 including a first terminal pad coupled with at least one high aspect ratio electroplating structure of the first set of high aspect ratio electroplating structures. 8. The device of claim 7, wherein the first terminal pad is a nickel terminal plated with a layer of gold. The apparatus of claim 1 , wherein at least a portion of the first set of high aspect ratio electroplating structures is formed using a crown plating process. The apparatus of claim 1 , wherein the second set of high aspect ratio electroplated structures is formed by etching a substrate. 12. The apparatus of claim 11, wherein at least a portion of the second set of high aspect ratio electroplating structures is formed using a crown plating process. is a coil,
a dielectric layer having a first surface and a second surface;
a first set of high aspect ratio electroplating structures disposed on a first surface of the dielectric layer;
A coil comprising a second set of high aspect ratio electroplated structures disposed on a second surface of the dielectric layer opposite the first set of high aspect ratio electroplated structures. The dielectric layer of claim 12 , wherein the dielectric layer electrically couples at least one high aspect ratio electroplated structure of the first set of high aspect ratio electroplated structures with at least one high aspect ratio electroplated structure of the second set of high aspect ratio electroplated structures. Coils containing vias for interfacing. 13. The coil of claim 12, wherein the first set of high aspect ratio electroplated structures and the second set of high aspect ratio electroplated structures are for a first coil section of the coil. 15. The coil of claim 14, comprising a third set of high aspect ratio electroplated structures and a fourth set of high aspect ratio electroplated structures for the second coil section of the coil. 16. The coil of claim 15, comprising a fifth set of high aspect ratio electroplated structures and a sixth set of high aspect ratio electroplated structures for a third coil section of the coil. 17. The coil of claim 16, wherein the first coil section is electrically coupled to the second coil section and the third coil section. 17. The coil of claim 16, wherein the second coil section is electrically coupled to the third coil section. 13. The coil of claim 12, wherein the second set of high aspect ratio electroplated structures is formed by etching a substrate. 20. The coil of claim 19, wherein at least a portion of the second set of high aspect ratio electroplating structures is formed using a crown plating process.

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