KR20210092861A - Display apparatus - Google Patents

Abstract

The present invention provides a display device which mitigates the color separation by reflected light. The display apparatus comprises: a first thin film transistor and a second thin film transistor disposed on a substrate and including a first electrode layer and a second electrode layer, respectively; an insulating layer having a first contact hole and a second contact hole exposing portions of the first electrode layer and the second electrode layer, respectively; a first pixel electrode disposed on the insulating layer and connected to the first thin film transistor through the first contact hole; and a second pixel electrode disposed on the same layer as the first pixel electrode and connected to the second thin film transistor through the second contact hole, wherein: an upper surface of the first pixel electrode in contact with the first electrode layer in the first contact hole has a first step lowered in a first direction; and an upper surface of the second pixel electrode in contact with the second electrode layer in the second contact hole has a second step lowered in a second direction opposite to the first direction.

Description

Display apparatus

The present invention relates to a display device, and more particularly, to a display device for improving color separation by reflected light.

A display device is a device that visually displays data. The display device is sometimes used as a display unit of a small product such as a mobile phone, or is used as a display unit of a large product such as a television.

The display device includes a plurality of pixels that receive an electrical signal and emit light in order to display an image to the outside. Each pixel includes a light emitting device, for example, an organic light emitting diode (OLED) as a light emitting device in the case of an organic light emitting display device. In general, an organic light emitting display device operates by forming a thin film transistor and an organic light emitting diode on a substrate, and the organic light emitting diode emits light by itself.

Recently, as the use of the display device is diversified, various designs for improving the quality of the display device are being attempted.

Embodiments of the present invention may selectively dispose a step difference correction layer on a substrate among a plurality of pixels. Through this, the step direction of the pixel electrodes respectively disposed in the contact holes formed in the planarization layer of the plurality of pixels is uniformly formed so that the direction of the step is toward or away from the emission region, and the direction of light reflected by the pixel electrodes is An object of the present invention is to provide a display device that improves color separation by being the same.

However, these problems are exemplary, and the scope of the present invention is not limited thereto.

An embodiment of the present invention, each disposed on a substrate, a first thin film transistor including a first electrode layer and a second thin film transistor including a second electrode layer; an insulating layer having a first contact hole and a second contact hole exposing portions of the first electrode layer and the second electrode layer, respectively; a first pixel electrode disposed on the insulating layer and connected to the first thin film transistor through the first contact hole; and a second pixel electrode disposed on the same layer as the first pixel electrode and connected to the second thin film transistor through the second contact hole, wherein the first electrode layer and the first electrode layer in the first contact hole An upper surface of the contacting first pixel electrode has a first step lowering in a first direction, and an upper surface of the second pixel electrode in contact with the second electrode layer in the second contact hole is opposite to the first direction. Disclosed is a display device having a second step that is lowered in a second direction.

In one embodiment, the substrate may further include a step difference correction layer disposed between the substrate and the insulating layer and partially overlapping the first contact hole.

In an embodiment, the display device further includes a conductive line disposed between the substrate and the step difference correction layer to extend in a third direction intersecting the first direction and the second direction, wherein the conductive line is the first contact A portion of the hole and a portion of the second contact hole may overlap.

In an embodiment, a top surface of the first pixel electrode overlapping the conductive line may be lower than a top surface of the first pixel electrode overlapping the step difference correction layer.

In an embodiment, the conductive line may partially overlap the step difference correction layer.

In one embodiment, the conductive line may be a light emission control line.

In an embodiment, the conductive line may be cut off at a portion overlapping the first contact hole.

In an embodiment, the method further includes a gate insulating layer disposed between the step difference correction layer and the conductive line, the gate insulating layer having a third contact hole and a fourth contact hole partially exposing the conductive line, and the step difference correction layer may be connected to the conductive line through the third contact hole and the fourth contact hole.

In an embodiment, the first pixel electrode may extend in the first direction, and the second pixel electrode may extend in the second direction.

In an embodiment, the display device further comprises: a pixel defining layer having a first opening defining a first emission region of the first pixel electrode and a second opening defining a second emission region of the second pixel electrode; The first opening may be positioned in the first direction with respect to the first contact hole, and the second opening may be positioned in the second direction with respect to the second contact hole.

In an embodiment, the first step may have a first inclined surface inclined toward the first light emitting area, and the second step may have a second inclined surface inclined toward the second light emitting area.

In an embodiment, a first intermediate layer and a second intermediate layer disposed on the first pixel electrode and the second pixel electrode, respectively; and a counter electrode covering the first intermediate layer and the second intermediate layer, wherein when the first intermediate layer emits light of a green wavelength, the second intermediate layer emits light of a red or blue wavelength, When the first intermediate layer emits light of a red or blue wavelength, the second intermediate layer may emit light of a green wavelength.

In an embodiment, the first thin film transistor includes a semiconductor layer and a gate electrode partially overlapping the semiconductor layer, disposed on the gate electrode, and partially overlapping the gate electrode, comprising an upper electrode of the storage capacitor. Further, the step difference correction layer may be disposed on the same layer as the upper electrode.

In an embodiment, the first thin film transistor may overlap the storage capacitor, and the gate electrode may correspond to a lower electrode of the storage capacitor.

In an embodiment, the first thin film transistor may further include a third electrode layer disposed between the substrate and the first electrode layer, and the step difference correction layer may be disposed on the same layer as the third electrode layer.

In an embodiment, the first thin film transistor may include a semiconductor layer and a gate electrode partially overlapping the semiconductor layer, and the third electrode layer may connect the semiconductor layer and the first electrode layer.

In an embodiment, the step correction layer may have an island shape.

In an embodiment, the first pixel electrode may extend in the second direction, and the second pixel electrode may extend in the first direction.

In an embodiment, the display device further comprises: a pixel defining layer having a first opening defining a first emission region of the first pixel electrode and a second opening defining a second emission region of the second pixel electrode; The first opening is located on the side in the second direction with respect to the first contact hole, the second opening is located on the side in the first direction with respect to the second contact hole, and the first step is in the first direction. It may have a first inclined surface inclined toward the direction, and the second step may have a second inclined surface inclined toward the second direction.

In an embodiment, a first intermediate layer and a second intermediate layer disposed on the first pixel electrode and the second pixel electrode, respectively; and a counter electrode covering the first intermediate layer and the second intermediate layer, wherein when the first intermediate layer emits light of a red or blue wavelength, the second intermediate layer emits light of a green wavelength; When the first intermediate layer emits light of a green wavelength, the second intermediate layer may emit light of a red or blue wavelength.

Other aspects, features and advantages other than those described above will become apparent from the following detailed description, claims and drawings for carrying out the invention.

According to an embodiment of the present invention made as described above, it is possible to implement a display device in which a phenomenon in which colors are separated by reflected light is improved. Of course, the scope of the present invention is not limited by these effects.

1 is a plan view schematically illustrating a display device according to an embodiment of the present invention.
2 is a plan view schematically illustrating a display panel according to an embodiment of the present invention.
3 is an equivalent circuit diagram of any one pixel of a display device according to an embodiment of the present invention.
4 is an equivalent circuit diagram of any one pixel of a display device according to an embodiment of the present invention.
5 is a plan view illustrating one pixel circuit of a display device according to an embodiment of the present invention.
6A to 6C are cross-sectional views schematically illustrating a cross-section taken along line II-II' of FIG. 5 .
7A is a plan view schematically illustrating a part of a display device according to an embodiment of the present invention.
7B is a cross-sectional view schematically illustrating a cross-section taken along line III-III' of FIG. 7A.
8A is a plan view schematically illustrating a part of a display device according to an embodiment of the present invention.
8B is a cross-sectional view schematically illustrating a cross-section taken along line IV-IV' of FIG. 8A.
9 is a plan view illustrating one pixel circuit of a display device according to an embodiment of the present invention.
10A is a cross-sectional view schematically illustrating a cross-section taken along the line V-V' of FIG. 9 .
FIG. 10B is a cross-sectional view schematically illustrating a cross-section taken along line VI-VI' of FIG. 9 .
FIG. 10C is a cross-sectional view schematically illustrating a cross-section taken along the line V-V' of FIG. 9 .
11A is a cross-sectional view schematically illustrating a cross-section taken along line III-III' of FIG. 7A.
11B is a cross-sectional view schematically illustrating a cross-section taken along line IV-IV' of FIG. 8A.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and a method of achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. .

In the following embodiments, terms such as first, second, etc. are used for the purpose of distinguishing one component from another, not in a limiting sense.

In the following examples, the singular expression includes the plural expression unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have means that the features or components described in the specification are present, and the possibility of adding one or more other features or components is not excluded in advance.

In the drawings, the size of the components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

Where certain embodiments are otherwise feasible, a specific process sequence may be performed different from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the order described.

As used herein, "A and/or B" refers to A, B, or A and B. And, "at least one of A and B" represents the case of A, B, or A and B.

In the following embodiments, when a film, region, or component is connected, when the film, region, or component is directly connected, or/and in the middle of another film, region, or component Including cases where they are interposed and indirectly connected. For example, in the present specification, when it is said that a film, region, component, etc. are electrically connected, when the film, region, component, etc. are directly electrically connected, and/or another film, region, component, etc. is interposed therebetween. to indicate an indirect electrical connection.

The x-axis, y-axis, and z-axis are not limited to three axes on a Cartesian coordinate system, and may be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a plan view schematically illustrating a display device according to an embodiment of the present invention.

Referring to FIG. 1 , the display device 1 includes a display area DA that implements an image and a peripheral area PA disposed around the display area DA. The display device 1 may provide an image to the outside by using light emitted from the display area DA.

The substrate 100 may be made of various materials such as glass, metal, or plastic. According to an embodiment, the substrate 100 may include a flexible material. Here, the flexible material refers to a substrate that can be bent, bent, and folded or rolled. The substrate 100 made of such a flexible material may be made of ultra-thin glass, metal, or plastic.

In the display area DA of the substrate 100 , pixels PX having various display elements such as organic light-emitting diodes (OLEDs) may be disposed. The pixels PX are configured in plurality, and the plurality of pixels PX may be arranged in various forms such as a stripe arrangement, a pentile arrangement, and a mosaic arrangement to implement an image.

When the display area DA is viewed in a planar shape, the display area DA may have a rectangular shape as shown in FIG. 1 . As another embodiment, the display area DA may be provided in a polygonal shape such as a triangle, a pentagon, or a hexagon, or a circular shape, an oval shape, or an irregular shape.

The peripheral area PA of the substrate 100 is an area disposed around the display area DA, and may be an area in which no image is displayed. In the peripheral area PA, various wirings that transmit electrical signals to be applied to the display area DA, and pads to which a printed circuit board or a driver IC chip is attached may be located.

2 is a plan view schematically illustrating a display panel according to an embodiment of the present invention.

Referring to FIG. 2 , the display panel 10 includes a display area DA and a peripheral area PA, and includes a plurality of pixels PXs disposed in the display area DA. Each of the plurality of pixels PX may include a display element such as an organic light emitting diode (OLED). Each pixel PX may emit, for example, red, green, blue, or white light through the organic light emitting diode OLED. Hereinafter, in the present specification, each pixel PX means a sub-pixel emitting light of a different color, and each pixel PX is, for example, a red (R) sub-pixel, a green (G) sub-pixel and It may be one of the blue (B) sub-pixels. The display area DA may be covered with an encapsulation member (not shown) to be protected from external air or moisture.

Each pixel PX may be electrically connected to external circuits disposed in the peripheral area PA. In the peripheral area PA, the first scan driving circuit 130, the second scan driving circuit 131, the light emission control driving circuit 133, the terminal 140, the data driving circuit 150, the first power supply wiring ( 160) and the second power supply wiring 170 may be disposed.

The first scan driving circuit 130 and the second scan driving circuit 131 may provide a scan signal to each pixel PX through the scan line SL. The second scan driving circuit 131 may be disposed in parallel with the first scan driving circuit 130 with the display area DA interposed therebetween. Some of the pixels PXs disposed in the display area DA may be electrically connected to the first scan driving circuit 130 , and others may be connected to the second scan driving circuit 131 . In another embodiment, the second scan driving circuit 131 may be omitted.

The emission control driving circuit 133 may provide an emission control signal to each pixel PX through the emission control line EL.

The terminal 140 may be disposed on one side of the substrate 100 . The terminal 140 may be exposed without being covered by the insulating layer to be electrically connected to the printed circuit board (PCB). The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10 . The printed circuit board (PCB) transmits a signal or power from a control unit (not shown) to the display panel 10 .

The control signal generated by the controller may be transmitted to the first and second scan driving circuits 130 and 131 through the printed circuit board (PCB), respectively. The controller applies first and second power voltages ELVDD and ELVSS to the first and second power supply lines 160 and 170, respectively, through the first and second connection lines 161 and 171, respectively, refer to FIG. 3 to be described later). can provide The first power voltage ELVDD is provided to each pixel PX through the driving voltage line PL connected to the first power supply line 160 , and the second power voltage ELVSS is the second power supply line 170 . It may be provided on the opposite electrode 230 (refer to FIG. 6A to be described later) of each pixel PX connected to the .

The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each pixel PX through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151 . 2 illustrates that the data driving circuit 150 is disposed on the printed circuit board (PCB), in another embodiment, the data driving circuit 150 may be disposed on the substrate 100 . For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power supply line 160 .

The first power supply wiring 160 may include a first sub wiring 162 and a second sub wiring 163 extending in parallel along the x-direction with the display area DA interposed therebetween. The second power supply wiring 170 may partially surround the display area DA in a loop shape with one side open.

3 is an equivalent circuit diagram of any one pixel of a display device according to an embodiment of the present invention.

Referring to FIG. 3 , each pixel PX includes a pixel circuit PC connected to a scan line SL and a data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

The pixel circuit PC includes a driving TFT (T1), a switching TFT (T2), and a storage capacitor (Cst). The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and the data signal ( Dm) to the driving thin film transistor T1.

The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and corresponds to the difference between the voltage received from the switching thin film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL. store the voltage

The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. can control The organic light emitting diode (OLED) may emit light having a predetermined luminance by a driving current.

In FIG. 3 , a case in which the pixel circuit PC includes two thin film transistors and one storage capacitor has been described, but the present invention is not limited thereto. For example, the pixel circuit PC may include three or more thin film transistors and/or two or more storage capacitors. In an embodiment, the pixel circuit PC may include seven thin film transistors and one storage capacitor. This will be explained in FIG. 4 .

4 is an equivalent circuit diagram of any one pixel of a display device according to an embodiment of the present invention, and FIG. 5 is a plan view illustrating any one pixel circuit of the display device according to an embodiment of the present invention. Also, FIGS. 6A to 6C are cross-sectional views schematically illustrating a cross-section taken along line II-II′ of FIG. 5 .

4 and 5 , one pixel PX may include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC.

For example, as shown in FIG. 4 , the pixel circuit PC may include a plurality of thin film transistors T1 to T7 and a storage capacitor Cst. The thin film transistors T1 to T7 and the storage capacitor Cst are connected to the signal lines SL, SL-1, SL+1, EL, DL, the first initialization voltage line VL1, the second initialization voltage line VL2, and the driving device. It may be connected to the voltage line PL.

The signal lines SL, SL-1, SL+1, EL, DL apply the previous scan signal Sn-1 to the scan line SL transmitting the scan signal Sn and the first initialization thin film transistor T4. The previous scan line SL-1 to transmit, the scan line SL+1 after transferring the scan signal Sn to the second initialization thin film transistor T7, the operation control thin film transistor T5 and the light emission control thin film transistor ( T6) may include an emission control line EL transmitting the emission control signal En, and a data line DL crossing the scan line SL and transmitting the data signal Dm. The driving voltage line PL transfers the driving voltage ELVDD to the driving thin film transistor T1 , the first initialization voltage line VL1 transfers the initialization voltage Vint to the first initialization thin film transistor T4 , and the second The initialization voltage line VL2 may transfer the initialization voltage Vint to the second initialization thin film transistor T7 .

The driving gate electrode G1 of the driving thin film transistor T1 is connected to the lower electrode CE1 of the storage capacitor Cst, and the driving source electrode S1 of the driving thin film transistor T1 is the operation control thin film transistor T5. ) is connected to the lower driving voltage line PL, and the driving drain electrode D1 of the driving thin film transistor T1 is connected to the pixel electrode ( 210 (refer to FIG. 6a) and is electrically connected. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and supplies the _{driving current I OLED to the organic light emitting diode OLED.}

The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL, and the switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and the switching thin film transistor T2 is connected to the data line DL. The switching drain electrode D2 of the transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and connected to the lower driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on according to the scan signal Sn received through the scan line SL and drives the data signal Dm transferred to the data line DL as a driving source of the thin film transistor T1 A switching operation of transferring to the electrode S1 is performed.

The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL, and the compensation source electrode S3 of the compensation thin film transistor T3 is the driving drain electrode D1 of the driving TFT T1. ) and connected to the pixel electrode 210 of the organic light emitting diode (OLED) via the emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the storage capacitor Cst ) is connected to the lower electrode CE1 , the first initialization drain electrode D4 of the first initialization thin film transistor T4 , and the driving gate electrode G1 of the driving thin film transistor T1 . The compensation thin film transistor T3 is turned on according to the scan signal Sn received through the scan line SL to electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1. By connecting the driving thin film transistor (T1) is diode-connected.

The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1, and the first initialization source electrode S4 of the first initialization thin film transistor T4 is It is connected to the first initialization voltage line VL1, and the first initialization drain electrode D4 of the first initialization thin film transistor T4 has the lower electrode CE1 of the storage capacitor Cst and the compensation drain of the compensation thin film transistor T3. It is connected to the electrode D3 and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1 to drive the initialization voltage Vint. The driving gate of the thin film transistor T1 An initialization operation for initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transferring it to the electrode G1 is performed.

The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, and the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the lower driving voltage line PL and connected, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2. there is.

The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, and the emission control source electrode S6 of the emission control thin film transistor T6 is the driving thin film transistor T1. It is connected to the driving drain electrode D1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is the second initialization thin film transistor T7. It is electrically connected to the second initialization source electrode S7 and the pixel electrode 210 of the organic light emitting diode OLED.

The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on according to the emission control signal En received through the emission control line EL, and the driving voltage ELVDD is applied to the main organic light emitting diode. It is transmitted to the OLED so that the driving current I _OLED flows through the organic light emitting diode (OLED).

The second initialization gate electrode G7 of the second initialization thin film transistor T7 is then connected to the scan line SL+1, and the second initialization source electrode S7 of the second initialization thin film transistor T7 emits light. It is connected to the emission control drain electrode D6 of the control thin film transistor T6 and the pixel electrode 210 of the main organic light emitting device OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7. is connected to the second initialization voltage line VL2.

Meanwhile, since the scan line SL and the subsequent scan line SL+1 are electrically connected to each other, the same scan signal Sn may be applied to the scan line SL and the subsequent scan line SL+1. Accordingly, the second initialization thin film transistor T7 is then turned on according to the scan signal Sn transmitted through the scan line SL+1 to initialize the pixel electrode 210 of the organic light emitting diode (OLED). can be performed.

The upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the common electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Accordingly, the organic light emitting diode OLED receives the driving current I _OLED from the driving thin film transistor T1 and emits light to display an image.

In FIG. 4 , the compensation thin film transistor T3 and the first initialization thin film transistor T4 are shown as having a dual gate electrode, but the compensation thin film transistor T3 and the first initialization thin film transistor T4 have one gate electrode. can have

Hereinafter, the structure of one pixel PX will be described in more detail with reference to FIGS. 5, 6A, 6B, and 6C. 6B and 6C correspond to some modified embodiments of FIG. 6A, and will be described with reference to FIG. 6A, and differences from FIG. 6A will be mainly described with respect to FIGS. 6B and 6C.

Driving thin film transistor (T1), switching thin film transistor (T2), compensation thin film transistor (T3), first initialization thin film transistor (T4), operation control thin film transistor (T5), light emission control thin film transistor (T6) and second initialization thin film The transistor T7 is disposed along the semiconductor layer 1130 , and some regions of the semiconductor layer 1130 include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , and a first initialization thin film. The semiconductor layers of the transistor T4 , the operation control thin film transistor T5 , the emission control thin film transistor T6 , and the second initialization thin film transistor T7 may be formed.

The semiconductor layer 1130 may be formed on the substrate 100 , the buffer layer 110 is formed on the substrate 100 as shown in FIG. 6A , and the semiconductor layer 1130 is formed on the buffer layer 110 . can be formed.

The substrate 100 may include glass or a polymer resin. Polymer resins include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethyeleneterepthalate, polyphenylene sulfide, polya It may include polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 including the polymer resin may have flexible, rollable, or bendable properties. The substrate 100 may have a multilayer structure including a layer including the above-described polymer resin and an inorganic layer (not shown).

The buffer layer 110 may reduce or block penetration of foreign matter, moisture, or external air from the lower portion of the substrate 100 , and may provide a flat surface on the substrate 100 . The buffer layer 110 may include an inorganic material such as an oxide or nitride, an organic material, or an organic/inorganic composite, and may have a single-layer or multi-layer structure of an inorganic material and an organic material.

The semiconductor layer 1130 may include low temperature poly-silicon (LTPS). Polysilicon materials have high electron mobility (100 cm ² /Vs or more), low energy consumption, and excellent reliability. As another example, the semiconductor layer 1130 may be formed of amorphous silicon (a-Si) and/or an oxide semiconductor, some semiconductor layers among the plurality of thin film transistors are formed of low-temperature polysilicon (LTPS), and others The semiconductor layer may be formed of amorphous silicon (a-Si) and/or an oxide semiconductor.

A first gate insulating layer 111 is disposed on the semiconductor layer 1130 , and a scan line SL, a previous scan line SL-1, and a subsequent scan line SL+1 are disposed on the first gate insulating layer 111 . and a light emission control line EL.

The first gate insulating layer 111 is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta) ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like.

Meanwhile, a region of the scan line SL that overlaps with the channel regions of the switching and compensation thin film transistors T2 and T3 becomes the switching and compensation gate electrodes G2 and G3, respectively, and among the previous scan lines SL-1, A region overlapping the channel region of the first initialization thin film transistor T4 becomes the first initialization gate electrode G4, and then overlaps with the channel region of the second initialization thin film transistor T7 among the scan lines SL+1. The region becomes the second initialization gate electrode G7, and the region overlapping the channel regions of the operation control and emission control thin film transistors T5 and T6 among the emission control line EL is the operation control and emission control gate electrode ( G5, G6).

The second gate insulating layer 113 may be provided on the scan line SL, the previous scan line SL-1, the subsequent scan line SL+1, and the emission control line EL. The second gate insulating layer 113 is a silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta) ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like.

An electrode voltage line HL, a first initialization voltage line VL1 and a second initialization voltage line VL2 may be disposed on the second gate insulating layer 113 . The electrode voltage line HL covers at least a portion of the driving gate electrode G1 , and may form a storage capacitor Cst together with the driving gate electrode G1 .

The lower electrode CE1 of the storage capacitor Cst may be integrally formed with the gate electrode G1 of the driving thin film transistor T1. For example, the gate electrode G1 of the driving thin film transistor T1 may function as the lower electrode CE1 of the storage capacitor Cst. A region of the electrode voltage line HL that overlaps the driving gate electrode G1 may be the upper electrode CE2 of the storage capacitor Cst. Accordingly, the second gate insulating layer 113 may function as a dielectric layer of the storage capacitor Cst.

In an embodiment of the present invention, a step difference correction layer DG may be disposed on the second gate insulating layer 113 . The step correction layer DG may have an island shape and may be formed of the same material as the upper electrode CE2 of the storage capacitor Cst. For example, the upper electrode CE2 and the step difference correction layer DG of the storage capacitor Cst may be formed of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), or gold (Au). , nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu) One or more metals selected from among may be formed in a single layer or in multiple layers.

An interlayer insulating layer 115 is positioned on the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2. The interlayer insulating layer 115 is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O) ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ), and the like.

A data line DL, a driving voltage line PL, first and second initialization connection lines 1173a and 1173b, a node connection line 1174 and an electrode layer 1175 may be disposed on the interlayer insulating layer 115 . The data line DL, the driving voltage line PL, the node connection line 1174, and the electrode layer 1175 include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like. and may be formed as a multi-layer or a single layer including the above materials. For example, the data line DL, the driving voltage line PL, the node connection line 1174, and the electrode layer 1175 may have a multilayer structure of Ti/Al/Ti.

The data line DL may be connected to the switching source region S2 of the switching thin film transistor T2 through the contact hole 1154 . A part of the data line DL may be understood as a switching source electrode.

The driving voltage line PL may be connected to the upper electrode CE2 of the capacitor Cst through a contact hole 1158 formed in the interlayer insulating layer 115 . Accordingly, the electrode voltage line HL may have the same voltage level (constant voltage) as the driving voltage line PL. Also, the driving voltage line PL may be connected to the operation control source region S5 through the contact hole 1155 .

The first initialization voltage line VL1 is connected to the first initialization thin film transistor T4 through the first initialization connection line 1173a, and the second initialization voltage line VL2 is connected to the second initialization thin film through the second initialization connection line 1173b. It may be connected to the transistor T7. Meanwhile, the first initialization voltage line VL1 and the second initialization voltage line VL2 may have the same constant voltage (eg, -2V, etc.).

One end of the node connection line 1174 may be connected to the compensation drain region D3 through the contact hole 1156 , and the other end may be connected to the driving gate electrode G1 through the contact hole 1157 .

The electrode layer 1175 includes the semiconductor layer of the light emission control thin film transistor T6 through the contact hole 1153 penetrating the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 111. connected The light emission control thin film transistor T6 may be electrically connected to the pixel electrode 210 of the organic light emitting diode (OLED) through the electrode layer 1175 .

A planarization layer 117 is positioned on the data line DL, the driving voltage line PL, the first and second initialization connection lines 1173a 1173b, the node connection line 1174, and the electrode layer 1175, and the planarization layer 117 is formed. An organic light emitting diode (OLED) may be positioned thereon.

Meanwhile, although the structure of one pixel circuit PC is described in FIGS. 4 and 5 , a plurality of pixels PX having the same pixel circuit PC are arranged along the x-direction and the y-direction. The first initialization voltage line VL1 , the previous scan line SL-1 , the second initialization voltage line VL2 , and the subsequent scan line SL+1 are connected to each other in the two pixel circuits PC disposed adjacently along the y-direction. can be shared

That is, the first initialization voltage line VL1 and the previous scan line SL-1 are connected to another pixel circuit PC disposed on the pixel circuit PC shown in FIG. 5 along the y-direction with respect to the drawing. It may be electrically connected to the second initialization thin film transistor. Accordingly, the previous scan signal applied to the previous scan line SL-1 may be transmitted as a subsequent scan signal to the second initialization thin film transistor of the other pixel circuit PC. Similarly, the second initialization voltage line VL2 and the subsequent scan line SL+1 are another pixel circuit disposed adjacent to the lower portion of the pixel circuit PC shown in FIG. 5 along the y-direction with respect to the drawing. It may be electrically connected to the first initialization thin film transistor of the PC to transmit the previous scan signal and the initialization voltage.

Referring back to FIG. 6A , the planarization layer 117 may have a flat top surface so that the pixel electrode 210 can be formed flat. The planarization layer 117 may be formed as a single layer or a multilayer film made of an organic material. The planarization layer 117 is a general general-purpose polymer such as Benzocyclobutene (BCB), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PXMMA), or Polystylene (PS), a polymer derivative having a phenolic group, an acrylic polymer , imide-based polymers, arylether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof. The planarization layer 117 may include an inorganic material. The planarization layer 117 is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta _{2 )} O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like. When the planarization layer 117 is made of an inorganic material, chemical planarization polishing may be performed in some cases. Meanwhile, the planarization layer 117 may include both an organic material and an inorganic material.

The organic light emitting diode OLED may include a pixel electrode 210 , a counter electrode 230 , and an intermediate layer 220 disposed therebetween and including an emission layer.

The pixel electrode 210 may be connected to the electrode layer 1175 through the contact hole 1163 , and the electrode layer 1175 may be connected to the emission control drain region through the contact hole 1153 .

The pixel electrode 210 may be a (semi)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 includes a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a compound thereof, and a transparent or translucent electrode layer formed on the reflective film. can do. The transparent or translucent electrode layer includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ; indium oxide), and indium gallium. At least one selected from the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO) may be included. In some embodiments, the pixel electrode 210 may be provided in a stacked structure of ITO/Ag/ITO.

A pixel defining layer 119 may be disposed on the planarization layer 117 , and the pixel defining layer 119 has an opening OP through which a central portion of the pixel electrode 210 is exposed, thereby forming the emission area EA of the pixel. can play a role in defining In addition, the pixel defining layer 119 prevents arcs from occurring at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210 . may play a role in preventing The pixel defining layer 119 is made of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenol resin, and may be formed by spin coating or the like.

The intermediate layer 220 may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent or phosphorescent material emitting red, green, blue, or white light. The organic light emitting layer may be a low molecular weight organic material or a high molecular weight organic material, and below and above the organic light emitting layer, a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL; electron transport layer) and A functional layer such as an electron injection layer (EIL) may be optionally further disposed. The intermediate layer 220 may be disposed to correspond to each of the plurality of pixel electrodes 210 . However, the present invention is not limited thereto, and at least some of the layers included in the intermediate layer 220 may be integrally formed over the plurality of pixel electrodes 210 .

The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or translucent electrode, and is formed of a metal thin film having a small work function including Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and compounds thereof. can be formed. In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In ₂ O _{3 may be further disposed on the metal thin film.} Meanwhile, the counter electrode 230 may be integrally formed to correspond to the plurality of pixel electrodes 210 .

The display device 1 (refer to FIG. 1 ) according to an embodiment of the present invention is disposed between the substrate 100 and the interlayer insulating layer 115 and partially overlaps the contact hole 1163 exposing a portion of the electrode layer 1175 . and a step difference correction layer (DG).

Referring to FIG. 5 , in one embodiment, the conductive line ML is disposed between the substrate 100 and the step difference correction layer DG to extend in the x-direction, and may further include a conductive line ML partially overlapping the contact hole 1163 . can For example, the conductive line ML may be the above-described light emission control line EL.

As shown in FIG. 6A , the conductive line ML may partially overlap the step difference correction layer DG. As another example, the conductive line ML and the step difference correcting layer DG may not overlap each other, and the end of the conductive line ML and the end of the step difference correcting layer DG may coincide.

When the step difference correcting layer DG partially overlaps the contact hole 1163 is included, the interlayer insulating layer 115 disposed on the step difference correcting layer DG may be formed along the shape of the step difference correcting layer DG. , an electrode layer 1175 disposed on the interlayer insulating layer 115 and connected to the emission control drain region D6 of the emission control thin film transistor T6 may also be formed along the shape of the step difference correction layer DG.

The pixel electrode 210 contacts the electrode layer 1175 through the contact hole 1163 , and a portion in contact with the electrode layer 1175 may be formed along the shape of the step difference correction layer DG. That is, the upper surface of the pixel electrode 210 overlapping the conductive line ML may be lower than the upper surface of the pixel electrode 210 overlapping the step difference correction layer DG.

The pixel electrode 210 is extended in the +y direction so that the opening OP of the pixel defining layer 119 may be located on the +y direction side with respect to the contact hole 1163 . Referring to the enlarged view of FIG. 6A , The pixel electrode 210 may have a step h that is lowered in the +y direction by the step difference correction layer DG.

That is, the lower surface of the upper surface of the pixel electrode 210 in contact with the electrode layer 1175 exposed by the contact hole 1163 may be adjacent to the emission area EA, and the step h of the pixel electrode 210 may be ) may have an inclined surface N inclined toward the emission area EA.

External light entering the inner surface of the substrate 100 is reflected back to the outside through the pixel electrode 210, which is a reflective electrode, and proceeds. The pixel electrode 210 is lowered in the +y direction by the step difference correction layer DG. When the rising step h is included, external light may be reflected in the direction (refer to the arrow of FIG. 6A ) toward the light emitting area EA by the step h of the pixel electrode 210 and travel.

6A shows that the pixel electrode 210 extends in the +y direction, but as shown in FIG. 6C , the pixel electrode 210 may extend in the -y direction. When a portion of the pixel electrode 210 in contact with the electrode layer 1175 has a step h that is still lowered in the +y direction by the step difference correction layer DG, the inner surface of the substrate 100 is reversed in FIG. 6A . External light, etc. entering toward the pixel electrode 210 may be reflected by the step h of the pixel electrode 210 in a direction (refer to the arrow of FIG. 6C ) toward the area in which the light emitting area EA does not exist.

Although the +y direction and the -y direction are used in FIGS. 6A and 6C , these are for convenience of description and may be symmetrically arranged left and right differently from the illustration. That is, according to an embodiment of the present invention, as shown in FIG. 6A , the lower surface of the upper surface of the pixel electrode 210 in contact with the electrode layer 1175 exposed by the contact hole 1163 is closer to the emission area EA than the higher surface. Alternatively, as shown in FIG. 6C , a higher surface of the upper surface of the pixel electrode 210 may be closer to the emission area EA than a lower surface.

As in an embodiment of the present invention, when a step correction layer DG disposed between the substrate 100 and the interlayer insulating layer 115 and partially overlapping with the contact hole 1163 is included, the step difference correction layer DG is formed. The step (h) direction of the pixel electrode 210 in the contact hole 1163 can be adjusted through this, and the direction in which external light is reflected by the pixel electrode 210 in the contact hole 1163 and travels can be adjusted.

6A shows that the interlayer insulating layer 115 is disposed between the electrode layer 1175 and the step difference correcting layer DG, but as shown in FIG. 6B , the interlayer insulating layer 115 is formed between the first interlayer insulating layer 115a and the second interlayer. The insulating layer 115b may be included, and the step difference correction layer DG may be disposed on the first interlayer insulating layer 115a.

The pixel electrode 210 is in contact with the second electrode layer 1175b through the contact hole 1163 , and the second electrode layer 1175b is the first electrode layer through the contact hole 1153 formed in the second interlayer insulating layer 115b. (1175a) may be connected. Also, the first electrode layer 1175a may be connected to the emission control thin film transistor T6 through the contact hole 1143 . The step difference correcting layer DG may be disposed on the same layer as the first electrode layer 1175a, and the step difference correcting layer DG may be made of the same material as the first electrode layer 1175a.

7A is a plan view schematically illustrating a part of a display device according to an embodiment of the present invention, and FIG. 7B is a cross-sectional view schematically illustrating a cross-section taken along line III-III' of FIG. 7A. In FIG. 7B , the same reference numerals as those of FIG. 6A refer to the same members, and thus redundant descriptions thereof will be omitted.

In FIG. 7A , a plurality of pixels PX may be disposed on the display area DA (refer to FIG. 1 ) of the display device 1 (refer to FIG. 1 ), for example, a first pixel PX1 and a second pixel PX2 . and a third pixel PX3. Although the drawing shows an example in which the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 are arranged in a pentile type, the number and arrangement of the pixels PX may vary. there is.

In an exemplary embodiment, the first pixel electrode 210R of the first pixel PX1 and the third pixel electrode 210B of the third pixel PX3 may extend in the first direction. For example, as shown in the drawings, the first direction may be a -y direction, and the first pixel electrode 210R and the third pixel electrode 210B may extend in the -y direction.

That is, the first opening OP1 and the third opening OP3 defining the first emission area EA1 of the first pixel electrode 210R and the third emission area EA3 of the third pixel electrode 210B, respectively. may be located on the -y-direction side with respect to the first contact hole 1163R and the third contact hole 1163B, respectively.

Also, the second pixel electrode 210G of the second pixel PX2 may extend in a second direction opposite to the first direction. For example, as shown in the drawings, the second direction may be the +y direction, and the second pixel electrode 210G may extend in the +y direction.

That is, the second opening OP2 defining the second emission area EA2 of the second pixel electrode 210G may be located on the +y-direction side with respect to the second contact hole 1163G.

The first pixel electrode 210R, the second pixel electrode 210G, and the third pixel electrode 210B extend in the first direction and the third direction intersecting the extending direction, respectively, and the first contact hole 1163R ), the conductive line ML may pass to overlap a portion of the second contact hole 1163G and a portion of the third contact hole 1163B. For example, the conductive line ML may correspond to the above-described light emission control line EL. Here, the third direction may be the x direction.

In the drawing, the conductive line ML partially overlaps the upper portion of the regions of the first to third contact holes 1163R, 1163G, and 1163B with respect to the center of the drawing, but may pass while partially overlapping the lower portion. That is, the conductive line ML shown in the drawing may move in parallel in the -y direction to overlap some regions of the first to third contact holes 1163R, 1163G, and 1163B.

In one embodiment, the direction in which the pixel electrodes 210R, 210G, and 210B extend among the first pixel PX1, the second pixel PX2, and the third pixel PX3 is different from that of the second pixel PX2. A step difference correction layer DG may be disposed to partially overlap the second contact hole 1163G. In this case, the step difference correction layer DG may partially overlap the conductive line ML. As another example, the step difference correcting layer DG may not overlap the conductive line ML, and an end of the conductive line ML may coincide with an end of the step difference correcting layer DG.

Referring to FIG. 7B , the first thin film transistor TFT1 includes a first electrode layer 1175R, the second thin film transistor TFT2 includes a second electrode layer 1175G, and the third thin film transistor TFT3 includes A third electrode layer 1175B may be included. For example, the first to third thin film transistors TFT1 , TFT2 , and TFT3 may correspond to the emission control thin film transistor T6 in each pixel circuit PC.

Referring to the enlarged view of FIG. 7B , the top surface of the first pixel electrode 210R in contact with the first electrode layer 1175R exposed by the first contact hole 1163R is in a first direction (eg, -y direction). ), the upper surface of the second pixel electrode 210G having a first step h1 that is lowered to ) and in contact with the second electrode layer 1175G exposed by the second contact hole 1163G has a first direction opposite to the first direction. The second step h2 may be lowered in two directions (eg, the +y direction). Also, the upper surface of the third pixel electrode 210B in contact with the third electrode layer 1175B exposed by the third contact hole 1163B has a third step that is lowered in the first direction (eg, the -y direction). (h3) can have.

That is, the first to third pixel electrodes 210R, 210G, and 210B contacting the first to third electrode layers 1175R, 1175G, and 1175B exposed by the first to third contact holes 1163R, 1163G, and 1163B, respectively. ) may be adjacent to the first to third light emitting areas EA1 , EA2 , and EA3 .

In an exemplary embodiment, the first to third steps h1, h2, and h3 of the first to third pixel electrodes 210R, 210G, and 210B may correspond to the first to third light emitting regions EA1, EA2, and EA3, respectively. It may have first to third inclined surfaces N1 , N2 , and N3 inclined toward the .

In one embodiment, the first pixel PX1 and the third pixel PX3 have upper surfaces of the first pixel electrode 210R and the third pixel electrode 210B overlapping the conductive line ML to be high; In the second pixel PX2 , a top surface of the second pixel electrode 210G overlapping the step difference correction layer DG may be formed to be high.

According to an embodiment of the present invention, first to third pixels in contact with the first to third electrode layers 1175R, 1175G, and 1175B exposed by the first to third contact holes 1163R, 1163G, and 1163B, respectively A lower surface of the upper surfaces of the electrodes 210R, 210G, and 210B may be unified to be adjacent to the first to third light emitting areas EA1 , EA2 , and EA3 , respectively, than a higher surface.

In an embodiment, the first to third intermediate layers 220R, 220G, and 220B are respectively disposed on the first to third pixel electrodes 210R, 210G, and 210B, and the first to third intermediate layers 220R, 220G , 220B, the counter electrode 230 may be disposed. In this case, the first intermediate layer 220R may emit light of a red wavelength, the second intermediate layer 220G may emit light of a green wavelength, and the third intermediate layer 220B may emit light of a blue wavelength.

As another example, the first and third intermediate layers 220R and 220B may emit light of a green wavelength, and the second intermediate layer 220G may emit light of a red or blue wavelength.

As a comparative example, the step difference correction layer may not exist. When the pixels are arranged in a pentile shape, directions in which the pixel electrodes extend are shifted from each other. Typically, a pixel electrode of a pixel emitting light of a red or blue wavelength and a pixel electrode of a pixel emitting light of a green wavelength are opposite to each other. In this case, if the step correction layer is not present, in the case of a pixel emitting light of a green wavelength, a surface having a high upper surface of the pixel electrode in contact with the electrode layer exposed by the contact hole is adjacent to the emission region. That is, a step direction of a pixel electrode of a pixel emitting light of a green wavelength is formed opposite to a direction of a step difference of a pixel electrode of a pixel emitting light of a red or blue wavelength based on each light emitting region.

External light that enters the inner surface of the substrate is reflected back to the outside by the pixel electrode, the pixel emitting light of red or blue wavelength reflects external light toward the emission region, and the pixel emitting light of green wavelength is External light and the like are reflected so as to move away from the light emitting area. In this case, since there is no unity in the direction in which external light is reflected, a phenomenon in which colors are separated into magenta and green in which red and blue are mixed occurs.

In one embodiment of the present invention, the step difference correction layer DG may be disposed in the second pixel PX2 in which the pixel electrode 210 extends oppositely among the first to third pixels PX1 , PX2 , and PX3 . . In this case, the first and third pixel electrodes 210R and 210B have first and third steps h1 and h3 that decrease in the -y direction, respectively, and the second pixel electrode 210G has a step difference correction layer DG. ) may have a second step h2 that is lowered in the +y direction.

That is, the lowering direction of the first to third steps h1, h2, and h3 of the first to third pixel electrodes 210R, 210G, and 210B forms the first to third light emitting regions EA1, EA2, and EA3. can be unified towards In this case, the first to third steps h1 , h2 , and h3 of the first to third pixel electrodes 210R, 210G, and 210B cause the first to third steps of the external light coming toward the inner surface of the substrate 100 , respectively. 3 The light emitting areas EA1, EA2, and EA3 may be reflected in a direction (refer to the arrow of FIG. 7B ) and travel. Through this, there is unity in the direction in which external light is reflected, and the phenomenon of color separation into magenta and green, which is a mixture of red and blue, can be improved.

8A is a plan view schematically illustrating a part of a display device according to an embodiment of the present invention, and FIG. 8B is a cross-sectional view schematically illustrating a cross-section taken along line IV-IV' of FIG. 8A. In FIGS. 8A and 8B , the same reference numerals as those of FIGS. 7A and 7B refer to the same members, and thus a redundant description thereof will be omitted.

In an exemplary embodiment, the first pixel electrode 210R of the first pixel PX1 and the third pixel electrode 210B of the third pixel PX3 may extend in the first direction. For example, as shown in the drawings, the first direction may be a -y direction, and the first pixel electrode 210R and the third pixel electrode 210B may extend in the -y direction.

That is, the first opening OP1 and the third opening OP3 defining the first emission area EA1 of the first pixel electrode 210R and the third emission area EA3 of the third pixel electrode 210B, respectively. may be located on the -y-direction side with respect to the first contact hole 1163R and the third contact hole 1163B, respectively.

Also, the second pixel electrode 210G of the second pixel PX2 may extend in a second direction opposite to the first direction. For example, as shown in the drawings, the second direction may be the +y direction, and the second pixel electrode 210G may extend in the +y direction.

That is, the second opening OP2 defining the second emission area EA2 of the second pixel electrode 210G may be located on the +y-direction side with respect to the second contact hole 1163G.

The first pixel electrode 210R, the second pixel electrode 210G, and the third pixel electrode 210B extend in the first direction and the third direction intersecting the extending direction, respectively, and the first contact hole 1163R ), the conductive line ML may pass to overlap a portion of the second contact hole 1163G and a portion of the third contact hole 1163B. For example, the conductive line ML may correspond to the above-described light emission control line EL. Here, the third direction may be the x direction.

In the drawing, the conductive line ML partially overlaps the upper portion of the regions of the first to third contact holes 1163R, 1163G, and 1163B based on the drawing, but may pass while partially overlapping the lower portion. That is, the conductive lines ML shown in the drawing may be arranged to move in parallel in the -y direction.

In one embodiment, among the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 , the first and third pixels 210R, 210G, and 210B in which the pixel electrodes 210R, 210G, and 210B extend in different directions. Step difference correction layers DG and DG' may be disposed to partially overlap the first and third contact holes 1163R and 1163B of PX1 and PX3, respectively. In this case, the step difference correction layers DG and DG' may partially overlap the conductive line ML. As another example, the step difference correction layers DG and DG' may not overlap the conductive line ML, and the ends of the step difference correction layers DG and DG' may coincide with the ends of the conductive line ML.

Referring to the enlarged view of FIG. 8B , the top surface of the first pixel electrode 210R in contact with the first electrode layer 1175R exposed by the first contact hole 1163R is in the first direction (eg, the +y direction). ), the upper surface of the second pixel electrode 210G having a first step h1 that is lowered to ) and in contact with the second electrode layer 1175G exposed by the second contact hole 1163G has a first direction opposite to the first direction. It may have a second step h2 that is lowered in two directions (eg, -y direction). In addition, the upper surface of the third pixel electrode 210B in contact with the third electrode layer 1175B exposed by the third contact hole 1163B has a third step that is lowered in the first direction (eg, the +y direction). (h3) can have.

That is, the first to third pixel electrodes 210R, 210G, and 210B contacting the first to third electrode layers 1175R, 1175G, and 1175B exposed by the first to third contact holes 1163R, 1163G, and 1163B, respectively. ), a higher surface of the upper surface may be adjacent to the first to third light emitting areas EA1 , EA2 , and EA3 .

In an embodiment, the first and third steps h1 and h3 of the first and third pixel electrodes 210R and 210B form the first and third inclined surfaces N1 and N3 inclined in the +y direction. The second step h2 of the second pixel electrode 210G may have a second inclined surface N2 inclined in the -y direction.

In one embodiment, the first pixel PX1 and the third pixel PX3 have upper surfaces of the first pixel electrode 210R and the third pixel electrode 210B overlapping the step difference correction layer DG to be high. , the second pixel PX2 may have a high top surface of the second pixel electrode 210G overlapping the conductive line ML.

According to an embodiment of the present invention, first to third pixels in contact with the first to third electrode layers 1175R, 1175G, and 1175B exposed by the first to third contact holes 1163R, 1163G, and 1163B, respectively A lower surface of the upper surfaces of the electrodes 210R, 210G, and 210B may be unified to be farther from the first to third light emitting regions EA1 , EA2 , and EA3 than a higher surface.

In an embodiment, the first intermediate layer 220R may emit light of a red wavelength, the second intermediate layer 220G may emit light of a green wavelength, and the third intermediate layer 220B may emit light of a blue wavelength. there is. As another example, the first and third intermediate layers 220R and 220B may emit light of a green wavelength, and the second intermediate layer 220G may emit light of a red or blue wavelength.

In one embodiment of the present invention, step difference correction layers DG are provided in the first and third pixels PX1 and PX3 in which the pixel electrode 210 is oppositely extended among the first to third pixels PX1, PX2, and PX3. , DG') can be placed. In this case, the direction in which the first to third steps h1 , h2 , and h3 of the first to third pixel electrodes 210R, 210G, and 210B decreases is in the first to third light emitting regions EA1 , EA2 , and EA3 . can be unified so as to move away from

That is, the external light entering toward the inner surface of the substrate 100 is transmitted through the first to third steps due to the first to third steps h1, h2, and h3 of the first to third pixel electrodes 210R, 210G, and 210B, respectively. The organic light emitting diode (OLED1, OLED2, OLED3) may be reflected in a direction away from (refer to the arrow of FIG. 8B) and proceed. Through this, there is unity in the direction in which external light is reflected, and the phenomenon of color separation into magenta and green, which is a mixture of red and blue, can be improved.

9 is a plan view showing one pixel circuit of a display device according to an embodiment of the present invention, and FIGS. 10A and 10C are cross-sectional views schematically illustrating a cross-section taken along the line V-V' of FIG. 10b is a cross-sectional view schematically illustrating a cross-section taken along line VI-VI' of FIG. 9 . 9, 10A, 10B, and 10C, the same reference numerals as in FIGS. 5, 6A, and 6B refer to the same members, and thus redundant descriptions thereof will be omitted.

In one embodiment of the present invention, the conductive line ML disposed between the substrate 100 and the step difference correction layer DG to extend in the third direction (eg, the x-direction) is connected to the contact hole 1163 and the contact hole 1163 . It can be cut off at the overlapping part.

Referring to FIGS. 9, 10A, and 10B , the conductive line ML does not exist under the contact hole 1163 formed in the planarization layer 117 partially exposing the electrode layer 1175 because it does not overlap, and the step difference is corrected. Only the layer DG may be disposed to partially overlap.

The conductive line ML cut off at a portion overlapping the contact hole 1163 may be connected to the step difference correction layer DG by the contact holes 1140a and 1140b formed in the second gate insulating layer 113 . That is, the step difference correction layer DG may serve as a bridge connecting the disconnected conductive lines ML. For example, the conductive line ML may be a light emission control line EL that transmits a light emission control signal En (refer to FIG. 4 ). The light emission control signal En travels along the disconnected conductive line ML and passes through a contact hole. It may be transmitted to the light emission control thin film transistor T6 through the fields 1140a and 1140b and the step difference correction layer DG.

As described above in FIG. 6A , when the step difference correction layer DG partially overlaps with the contact hole 1163 is included, the interlayer insulating layer 115 disposed on the step difference correction layer DG is formed of the step difference correction layer DG. It may be formed according to the shape, and the electrode layer 1175 disposed on the interlayer insulating layer 115 and connected to the emission control drain region D6 of the emission control thin film transistor T6 also conforms to the shape of the step difference correction layer DG. can be formed according to

The pixel electrode 210 contacts the electrode layer 1175 through the contact hole 1163 , and a portion in contact with the electrode layer 1175 may be formed along the shape of the step difference correction layer DG. That is, the upper surface of the pixel electrode 210 overlapping the conductive line ML may be lower than the upper surface of the pixel electrode 210 overlapping the step difference correction layer DG.

The pixel electrode 210 may extend in the +y direction so that the opening OP of the pixel defining layer 119 may be located on the +y direction side with respect to the contact hole 1163 , and the pixel electrode 210 may compensate for the step difference. It may have a step h that is lowered in the +y direction by the layer DG.

That is, the lower surface of the upper surface of the pixel electrode 210 in contact with the electrode layer 1175 exposed by the contact hole 1163 may be adjacent to the emission area EA, and the step h of the pixel electrode 210 may be ) may have an inclined surface N inclined toward the emission area EA.

As in an embodiment of the present invention, when a step correction layer DG disposed between the substrate 100 and the interlayer insulating layer 115 and partially overlapping with the contact hole 1163 is included, the step difference correction layer DG is formed. The step (h) direction of the pixel electrode 210 in the contact hole 1163 can be adjusted, and the direction in which external light is reflected by the pixel electrode 210 and travels can be adjusted.

In FIG. 10A , the interlayer insulating layer 115 is disposed between the electrode layer 1175 and the step difference correction layer DG, but as shown in FIG. 10C , the interlayer insulating layer 115 is formed between the first interlayer insulating layer 115a and the second interlayer. The insulating layer 115b may be included, and the step difference correction layer DG may be disposed on the first interlayer insulating layer 115a. The pixel electrode 210 is in contact with the second electrode layer 1175b through the contact hole 1163 , and the second electrode layer 1175b is the first electrode layer through the contact hole 1153 formed in the second interlayer insulating layer 115b. (1175a) may be connected. The step difference correcting layer DG may be disposed on the same layer as the first electrode layer 1175a, and the step difference correcting layer DG may be made of the same material as the first electrode layer 1175a.

Although FIG. 10C shows that the conductive line ML is disposed under the contact hole 1163, this is only to show that the step difference correction layer DG and the contact hole 1140a are connected through the contact hole 1140a. The conductive line ML overlapping the contact hole 1163 is not disposed, and as shown in FIGS. 9 and 10B , the disconnected conductive line ML passes through the contact holes 1140a and 1140b to the step difference correction layer DG. ) is associated with

11A is a cross-sectional view schematically illustrating a cross-section taken along line III-III' of FIG. 7A, and FIG. 11B is a cross-sectional view schematically illustrating a cross-section taken along line IV-IV' of FIG. 8A. In FIGS. 11A and 11B , the same reference numerals as those of FIGS. 7B and 8B refer to the same members, and thus a redundant description thereof will be omitted.

11A and 11B correspond to some modified embodiments of FIGS. 7B and 8B, respectively, and the differences will be mainly described.

Referring to FIG. 11A , in an exemplary embodiment, a second direction in which the pixel electrodes 210R, 210G, and 210B extend among the first pixel PX1, the second pixel PX2, and the third pixel PX3 is different. The step difference correction layer DG may be disposed to partially overlap the second contact hole 1163G of the pixel PX2 . At this time, the conductive line ML disposed between the substrate 100 and the step difference correction layer DG so as to extend in the third direction (eg, the x-direction) is formed at a portion overlapping the second contact hole 1163G. can be cut off

The conductive line ML cut off as described above in FIGS. 9 and 10A may be connected to the step difference correction layer DG by the contact holes 1140a and 1140b, and transmits the emission control signal En to the emission control thin film transistor ( T6).

Referring to FIG. 11B , in an embodiment, the first pixel electrodes 210R, 210G, and 210B have different extending directions among the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 . And step difference correction layers DG and DG' may be disposed to partially overlap the first and third contact holes 1163R and 1163B of the third pixels PX1 and PX3. At this time, the conductive line ML disposed between the substrate 100 and the step difference correction layers DG and DG' so as to extend in the third direction (eg, the x direction) is formed through the first and third contact holes ( 1163R, 1163B) may be cut off at the overlapping portion, respectively.

In this case, the disconnected conductive line ML is connected to the first step difference correction layer DG by contact holes 1140a and 1140b in the case of the first pixel PX1, and the contact hole in the case of the third pixel PX3. It may be connected to the second step difference correcting layer DG' by means of fields 1140a' (some not shown). Through this, the light emission control signal En can be transmitted to the light emission control thin film transistor T6 without interruption.

11A and 11B show the conductive lines ML disposed under the first to third contact holes 1163R, 1163G, and 1163B, but this is the step correction layers DG and DG' and the contact holes 1140a. , 1140a ′), the conductive line ML overlapping the contact hole 1163 is not disposed as shown in FIG. 10A .

The display device 1 according to an embodiment of the present invention may include a step difference correction layer DG disposed between the substrate 100 and the planarization layer 117 as an insulating layer and partially overlapping the contact hole 1163 . In this way, since the direction of the step h of the pixel electrode 210 positioned in the contact hole 1163 of the one pixel PX can be formed to be uniform, the phenomenon of color separation can be improved.

So far, only the display device has been mainly described, but the present invention is not limited thereto. For example, it will be said that a display device manufacturing method for manufacturing such a display device also falls within the scope of the present invention.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

1: display device
10: display panel
100: substrate
210: pixel electrode
220: middle layer
230: counter electrode
1175: electrode layer
1153, 1163: contact hole
ML: Challenge Line
DG: step correction layer
h: step

Claims (20)

a second thin film transistor each disposed on the substrate and including a first thin film transistor including a first electrode layer and a second electrode layer;
an insulating layer having a first contact hole and a second contact hole exposing portions of the first electrode layer and the second electrode layer, respectively;
a first pixel electrode disposed on the insulating layer and connected to the first thin film transistor through the first contact hole; and
a second pixel electrode disposed on the same layer as the first pixel electrode and connected to the second thin film transistor through the second contact hole;
an upper surface of the first pixel electrode in contact with the first electrode layer in the first contact hole has a first step lowered in a first direction;
A top surface of the second pixel electrode in contact with the second electrode layer in the second contact hole has a second step that is lowered in a second direction opposite to the first direction. According to claim 1,
and a step difference correction layer disposed between the substrate and the insulating layer and partially overlapping the first contact hole. 3. The method of claim 2,
and a conductive line disposed between the substrate and the step difference correction layer to extend in a third direction intersecting the first direction and the second direction,
and the conductive line overlaps a portion of the first contact hole and a portion of the second contact hole. 4. The method of claim 3,
and a top surface of the first pixel electrode overlapping the conductive line is lower than a top surface of the first pixel electrode overlapping the step difference correction layer. 4. The method of claim 3,
The conductive line partially overlaps the step difference correction layer. 4. The method of claim 3,
The conductive line is a light emission control line. 4. The method of claim 3,
The conductive line is cut off at a portion overlapping the first contact hole. 8. The method of claim 7,
a gate insulating layer disposed between the step difference correction layer and the conductive line and having a third contact hole and a fourth contact hole partially exposing the conductive line;
The step difference correction layer is connected to the conductive line through the third contact hole and the fourth contact hole. 3. The method of claim 2,
the first pixel electrode extends in the first direction;
and the second pixel electrode extends in the second direction. 10. The method of claim 9,
and a pixel defining layer having a first opening defining a first emission region of the first pixel electrode and a second opening defining a second emission region of the second pixel electrode;
The first opening is positioned in the first direction with respect to the first contact hole, and the second opening is positioned in the second direction with respect to the second contact hole. 11. The method of claim 10,
The first step has a first inclined surface inclined toward the first light emitting area, and the second step has a second inclined surface inclined toward the second light emitting area. 10. The method of claim 9,
a first intermediate layer and a second intermediate layer respectively disposed on the first pixel electrode and the second pixel electrode; and
A counter electrode covering the first intermediate layer and the second intermediate layer, further comprising;
When the first intermediate layer emits light of a green wavelength, the second intermediate layer emits light of a red or blue wavelength,
When the first intermediate layer emits light of a red or blue wavelength, the second intermediate layer emits light of a green wavelength. 3. The method of claim 2,
The first thin film transistor includes a semiconductor layer and a gate electrode partially overlapping the semiconductor layer,
an upper electrode of the storage capacitor disposed on the gate electrode and partially overlapping the gate electrode;
The step difference correction layer is disposed on the same layer as the upper electrode, the display device. 14. The method of claim 13,
The first thin film transistor overlaps the storage capacitor,
and the gate electrode corresponds to a lower electrode of the storage capacitor. 3. The method of claim 2,
The first thin film transistor further includes a third electrode layer disposed between the substrate and the first electrode layer,
The step difference correction layer is disposed on the same layer as the third electrode layer, the display device. 16. The method of claim 15,
The first thin film transistor includes a semiconductor layer and a gate electrode partially overlapped with the semiconductor layer,
The third electrode layer connects the semiconductor layer and the first electrode layer. 3. The method of claim 2,
The step difference correction layer is an island shape, the display device. 3. The method of claim 2,
the first pixel electrode extends in the second direction;
and the second pixel electrode extends in the first direction. 19. The method of claim 18,
and a pixel defining layer having a first opening defining a first emission region of the first pixel electrode and a second opening defining a second emission region of the second pixel electrode;
The first opening is located on a side in the second direction with respect to the first contact hole, and the second opening is located on a side in the first direction with respect to the second contact hole,
The first step has a first inclined surface inclined in the first direction, and the second step has a second inclined surface inclined toward the second direction. 19. The method of claim 18,
a first intermediate layer and a second intermediate layer respectively disposed on the first pixel electrode and the second pixel electrode; and
A counter electrode covering the first intermediate layer and the second intermediate layer, further comprising;
When the first intermediate layer emits light of a red or blue wavelength, the second intermediate layer emits light of a green wavelength,
When the first intermediate layer emits light of a green wavelength, the second intermediate layer emits light of a red or blue wavelength.

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