KR20210085643A - Thin film transistors and display apparatus comprising thin film transistor - Google Patents

Abstract

One embodiment of the present invention provides a thin film transistor in which an active layer is protected by an optical filter layer, a display device including the thin film transistor, and a manufacturing method for the thin film transistor. Therefore, the thin film transistor can selectively block light incident onto an oxide semiconductor layer without increasing a size of a gate electrode.

Description

A thin film transistor and a display device including a thin film transistor {THIN FILM TRANSISTORS AND DISPLAY APPARATUS COMPRISING THIN FILM TRANSISTOR}

The present invention relates to a thin film transistor and a display device including the thin film transistor. More specifically, the present invention relates to a thin film transistor including an optical filter layer and a display device including the thin film transistor.

Since the thin film transistor may be manufactured on a glass substrate or a plastic substrate, a switching element or driving element of a display device such as a liquid crystal display device or an organic light emitting device. is widely used as

The thin film transistor, based on the material constituting the active layer, is an amorphous silicon thin film transistor in which amorphous silicon is used as an active layer, a polysilicon thin film transistor in which polycrystalline silicon is used as an active layer, and an oxide semiconductor as an active layer. It may be classified as an oxide semiconductor thin film transistor.

An oxide semiconductor TFT having high mobility and a large resistance change according to oxygen content has an advantage in that desired physical properties can be easily obtained. In addition, since the oxide constituting the active layer can be formed at a relatively low temperature during the manufacturing process of the oxide semiconductor thin film transistor, the manufacturing cost is low. Since the oxide semiconductor is transparent due to the nature of the oxide, it is also advantageous for realizing a transparent display.

However, when light is irradiated to the oxide semiconductor layer, the driving of the oxide semiconductor thin film transistor may become unstable, such as a change in threshold voltage. Accordingly, it is necessary to block light incident to the oxide semiconductor layer in order to improve driving stability and reliability of the oxide semiconductor thin film transistor.

An embodiment of the present invention is to provide a thin film transistor including an optical filter layer capable of selectively blocking light incident to an oxide semiconductor layer without reducing an aperture ratio.

An embodiment of the present invention is to provide a thin film transistor capable of selectively blocking light incident to an oxide semiconductor layer without increasing the size of the gate electrode.

Another embodiment of the present invention is to provide a thin film transistor capable of selectively blocking light incident to an oxide semiconductor layer without increasing a parasitic cap between a source/drain electrode and a gate electrode.

An embodiment of the present invention is to provide a display device including the thin film transistor as described above and a method of manufacturing the thin film transistor as described above.

An embodiment of the present invention for achieving the above-described technical problem includes an optical filter layer on a substrate, a light blocking layer on the substrate overlapping the optical filter layer, and an active layer spaced apart from the light blocking layer and overlapping at least in part with the light blocking layer and wherein the light blocking layer is disposed between the substrate and the active layer, the optical filter layer has a larger area than the light blocking layer, and is disposed between the substrate and the light blocking layer.

The light filter layer may include an oxide semiconductor material.

The optical filter layer is IGZO (InGaZnO) based, IGZTO (InGaZnSnO) based, IZO (InZnO) based, IGO (InGaO) based, ITO (InSnO) based, GZTO (GaZnSnO) based, GZO (GaZnO) based, ITZO (InSnZnO) based At least one of an IGTO (InGaSnO)-based, GZTO (GaZnSnO)-based, and GO (GaO)-based oxide semiconductor material may be included.

The light filter layer may have a protrusion protruding from the light blocking layer in a plan view.

The light filter layer may block light having a wavelength of 500 nm or less.

The optical filter layer may have an energy bandgap of 3.1 eV or less.

The optical filter layer may have a thickness of 30 nm or more.

The optical filter layer may have a thickness of 30 nm to 150 nm.

The optical filter layer may have a carrier density ^{of 1×10 18} pieces/cm ^{3 or less.}

The active layer includes an oxide semiconductor material.

The active layer may include a first oxide semiconductor layer on the light blocking layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

The light blocking layer may be in contact with the light filter layer.

The light blocking layer may be disposed to be spaced apart from the light filter layer.

The light blocking layer may be disposed on one surface of the substrate, and the light filter layer may be disposed on the other surface of the substrate.

The light blocking layer may be a gate electrode.

The thin film transistor may include a gate electrode overlapping the active layer, and the active layer may be disposed between the gate electrode and the light blocking layer.

Another embodiment of the present invention provides a display device including the thin film transistor.

Another embodiment of the present invention includes the steps of sequentially forming an oxide layer and a metal layer for forming an optical filter layer on a substrate, forming an optical filter layer and a light blocking layer by patterning using a halftone mask, and the light blocking layer and and forming an active layer spaced apart and overlapping the light blocking layer, wherein the optical filter layer has a larger area than the light blocking layer.

The optical filter layer is IGZO (InGaZnO) based, IGZTO (InGaZnSnO) based, IZO (InZnO) based, IGO (InGaO) based, ITO (InSnO) based, GZTO (GaZnSnO) based, GZO (GaZnO) based, ITZO (InSnZnO) based At least one of an IGTO (InGaSnO)-based, GZTO (GaZnSnO)-based, and GO (GaO)-based oxide semiconductor material may be included.

The optical filter layer may have an energy bandgap of 3.1 eV or less.

The optical filter layer may have a thickness of 30 nm or more.

Since the thin film transistor according to an embodiment of the present invention includes an optical filter layer having light transmittance, it is possible to selectively block light incident to the oxide semiconductor layer without lowering the aperture ratio. As a result, the threshold voltage change of the thin film transistor is suppressed, and the thin film transistor can have excellent reliability.

In addition, according to an embodiment of the present invention, since the light filter layer disposed in contact with the gate electrode blocks light of a low wavelength band, it is possible to selectively block light incident to the oxide semiconductor layer without increasing the size of the gate electrode. have. As a result, since the size of the thin film transistor does not substantially increase, it is easy to secure an aperture ratio of a display device using the thin film transistor.

According to an embodiment of the present invention, since light incident to the oxide semiconductor layer can be selectively blocked without increasing the area of the gate electrode, an increase in parasitic cap between the source/drain electrode and the gate electrode is prevented. can be As a result, unnecessary power consumption by the parasitic cap can be prevented.

In addition to the above-mentioned effects, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

1 is a plan view of a thin film transistor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line I-I' of FIG. 1 .
3 is a schematic diagram of a path of light incident to a thin film transistor.
4 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
5 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
6 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
7 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
8 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
9 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
10A, 10B, and 10C are energy band diagrams illustrating the NBTIS degradation mechanism of a thin film transistor.
11A and 11B are graphs of a threshold voltage change of a thin film transistor by light irradiation.
12A and 12B are, respectively, a light transmittance graph and a light absorption rate graph of glass, IGZO (InGaZnO), IGZTO (InGaZnSnO), and IZO (InZnO) according to wavelength.
13A and 13B are a light transmittance graph and a light absorption rate graph of IZO (InZnO) for each thickness, respectively.
14A, 14B, and 14C are graphs of a threshold voltage change of an oxide thin film transistor having an active layer made of IZO (InZnO), respectively.
15 is a schematic diagram of a display device according to another embodiment of the present invention.
16 is a schematic diagram of a shift resist.
17 is a circuit diagram of a stage provided in the shift resist of FIG. 16 .
18 is a circuit diagram of one pixel of FIG. 15 .
19 is a plan view of the pixel of FIG. 18 .
20 is a cross-sectional view taken along II-II' of FIG. 19 .
21 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention.
22 is a circuit diagram of one pixel of a display device according to still another exemplary embodiment of the present invention.
23 is a circuit diagram of one pixel of a display device according to another exemplary embodiment of the present invention.
24 is a plan view of the pixel of FIG. 23 .
FIG. 25 is a cross-sectional view taken along line III-III' of FIG. 24 .
26A to 26H are cross-sectional views illustrating a manufacturing process of a display device according to an exemplary embodiment.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to inform those who have the scope of the invention. The invention is only defined by the scope of the claims.

Since the shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to the matters shown in the drawings. Like elements may be referred to by the same reference numerals throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless the expression 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

For example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., the expression 'directly' or 'directly' is used. One or more other parts may be positioned between the two parts unless otherwise specified.

Spatially relative terms "below, beneath", "lower", "above", "upper", etc. are one element or component as shown in the drawings. and can be used to easily describe the correlation with other devices or components. The spatially relative terms should be understood as terms including different orientations of the device during use or operation in addition to the orientation shown in the drawings. For example, if an element shown in the figures is turned over, an element described as "beneath" or "beneath" another element may be placed "above" the other element. Accordingly, the exemplary term “below” may include both directions below and above. Likewise, the exemplary terms “above” or “on” may include both directions above and below.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless the expression "

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

In adding reference numerals to components of each drawing describing embodiments of the present invention, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings.

In embodiments of the present invention, the source electrode and the drain electrode are only distinguished for convenience of description, and the source electrode and the drain electrode may be interchanged. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. Also, the source electrode of one embodiment may be a drain electrode in another embodiment, and the drain electrode of one embodiment may be a source electrode in another embodiment.

In some embodiments of the present invention, for convenience of description, a source region and a source electrode are distinguished and a drain region and a drain electrode are distinguished, but embodiments of the present invention are not limited thereto. The source region may be a source electrode, and the drain region may be a drain electrode. Also, the source region may be the drain electrode, and the drain region may be the source electrode.

1 is a plan view of a thin film transistor 100 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II′ of FIG. 1 .

1 and 2 , the thin film transistor 100 according to an embodiment of the present invention includes an optical filter layer 120 on a substrate 110 , a gate electrode 130 on the optical filter layer 120 , and a gate electrode 130 . ) on the active layer 150 . In the thin film transistor 100 according to an embodiment of the present invention, the gate electrode 130 serves as a light blocking layer. Accordingly, in the embodiment according to FIGS. 1 and 2 , the light blocking layer is the gate electrode 130 . As such, in the embodiment of FIGS. 1 and 2 , the gate electrode 130 is the same as the light blocking layer, so for convenience of explanation, the expression “gate electrode 130” is used instead of the expression “light blocking layer”. The structure of the transistor 100 will be described.

Glass or plastic may be used as the substrate 110 . As the plastic, a transparent plastic having flexible properties, for example, polyimide may be used.

The optical filter layer 120 is disposed on the substrate 110 .

According to an embodiment of the present invention, the optical filter layer 120 may be made of an oxide semiconductor material. For example, IGZO (InGaZnO), IGZTO (InGaZnSnO), IZO (InZnO), IGO (InGaO), ITO (InSnO), GZTO (GaZnSnO), GZO (GaZnO), ITZO (InSnZnO) The optical filter layer 120 may be made of at least one of an IGTO (InGaSnO)-based, GZTO (GaZnSnO)-based, and GO (GaO)-based oxide semiconductor material.

1 and 2 , the optical filter layer 120 has a larger area than the gate electrode 130 , which is a light blocking layer, and is disposed between the substrate 110 and the gate electrode 130 .

The gate electrode 130 is disposed on the optical filter layer 120 to overlap the optical filter layer 120 . The gate electrode 130 blocks light incident from the substrate 110 to protect the active layer 130 . The gate electrode 130 serves as a light blocking layer. According to an embodiment of the present invention, the gate electrode 130 contacts the optical filter layer 120 and is disposed between the substrate 110 and the active layer 150 . However, the exemplary embodiment of the present invention is not limited thereto, and the gate electrode 130 may be disposed to be spaced apart from the optical filter layer 120 .

The gate electrode 130 is an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, molybdenum ( Mo) or a molybdenum-based metal such as a molybdenum alloy, may include at least one of chromium (Cr), tantalum (Ta), neodium (Nd), and titanium (Ti). The gate electrode 130 may have a multilayer structure including at least two conductive layers having different physical properties.

A gate insulating layer 140 is disposed on the gate electrode 130 . The gate insulating layer 140 may include at least one of silicon oxide and silicon nitride, and may include molar metal oxide or metal nitride. The gate insulating layer 140 may have a single layer structure or a multilayer structure.

An active layer 150 is disposed on the gate insulating layer 140 . The active layer 150 is spaced apart from the gate electrode 130 and at least partially overlaps the gate electrode 130 .

According to an embodiment of the present invention, the active layer 150 includes an oxide semiconductor material. The active layer 150 according to an embodiment of the present invention is an oxide semiconductor layer.

Active layer 150, for example, IZO (InZnO) based, IGO (InGaO) based, ITO (InSnO) based, IGZO (InGaZnO) based, IGZTO (InGaZnSnO) based, GZTO (GaZnSnO) based, GZO (GaZnO) based It may include at least one of a GO (GaO)-based, and ITZO (InSnZnO)-based oxide semiconductor material. However, the exemplary embodiment of the present invention is not limited thereto, and the active layer 150 may be made of other oxide semiconductor materials known in the art.

A source electrode 161 and a drain electrode 162 are disposed on the active layer 150 . The source electrode 161 and the drain electrode 162 are spaced apart from each other and are respectively connected to the active layer 150 . The source electrode 161 and the drain electrode 162 may directly contact the active layer 150 , respectively.

The source electrode 161 and the drain electrode 162 are molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodium (Nd), and copper, respectively. (Cu), and at least one of alloys thereof. Each of the source electrode 161 and the drain electrode 162 may be formed of a single layer made of a metal or a metal alloy, or may be formed of a multilayer of two or more layers.

According to an embodiment of the present invention, the gate electrode 130 is disposed under the active layer 150 to protect the active layer 150 from light incident from the substrate 110 side.

However, even when the entire active layer 150 overlaps the gate electrode 130 , the light reflected from the source electrode 161 and the drain electrode 162 and the light reflected back from the gate electrode 130 are reflected in the active layer. (150) can be reached.

FIG. 3 is a schematic diagram of paths of light L1 , L2 , and L3 incident to the thin film transistor 100 .

Referring to FIG. 3 , even if the light blocking layer, the gate electrode 130 , is disposed to overlap the active layer 150 with respect to the incident direction of the light L1 , L2 , and L3 , the light incident on the side of the gate electrode 130 . Lights L1 and L3 may be reflected from the source electrode 161 and the drain electrode 162 and then re-reflected from the gate electrode 130 to reach the active layer 150 .

Lights L1 and L3 that are incident on the side surface of the gate electrode 130 , are reflected from the source electrode 161 and the drain electrode 162 , are reflected back from the gate electrode 130 , and are incident on the active layer 150 . When the gate electrode 130 is made large in order to block , a parasitic capacitance between the source electrode 161 and the gate electrode 130 and between the drain electrode and the gate electrode 130 may be increased. If the parasitic cap is increased, unnecessary power consumption may be generated for driving the thin film transistor 100 .

In addition, when the gate electrode 130 increases, the area of the thin film transistor 100 increases, which is disadvantageous to the integration of the thin film transistor 100 , and there is a limitation in manufacturing a high-resolution display device. In addition, when the gate electrode 130 increases, the aperture ratio of the display device may decrease.

Therefore, there is a limit in increasing the size of the gate electrode 130 .

According to an embodiment of the present invention, instead of increasing the size of the gate electrode 130 , the optical filter layer 120 is disposed under the gate electrode 130 , and the active layer ( 150) and filters the incident light.

According to an embodiment of the present invention, since the optical filter layer 120 has a larger area than the gate electrode 130 , a part of the optical filter layer 120 protrudes from the gate electrode 130 in a plan view to form the protrusion 121 . do.

1 and 2 , the optical filter layer 120 has a protrusion 121 protruding from the gate electrode 130, which is a light blocking layer, in plan view.

According to an embodiment of the present invention, the light filter layer 120 selectively blocks light. Accordingly, the energy of the light L1 and L3 passing through the protrusion 121 is reduced. Accordingly, the energy of the light incident to the active layer 150 through the side surface of the gate electrode 130 is lowered, so that the electrical stress on the active layer 150 can be reduced, and the electrical characteristics due to the light irradiation and the resulting heat are reduced. Deterioration can be prevented.

The size of the protrusion 121 that filters light incident to the active layer 150 through the side surface of the gate electrode 130 is not particularly limited.

The protrusion 121 may have widths w1 and w2 exceeding 0 μm, and in some cases may have widths w1 and w2 corresponding to the pixel size. The protrusion 121 may have a width of 1 μm or more, or a width of 5 μm or more. Also, the protrusion 121 may have a width of 10 μm or less or a width of 5 μm or less. The width of the protrusion 121 may be appropriately designed according to the structure of the pixel and the size of the pixel.

According to an embodiment of the present invention, the light filter layer 120 blocks blue-based light. More specifically, according to an embodiment of the present invention, the optical filter layer 120 may block light having a wavelength of 500 nm or less. Since the optical filter layer 120 blocks relatively high energy visible light having a wavelength of 500 nm or less, damage to the active layer 150 can be prevented, and a threshold voltage change of the thin film transistor 100 due to light irradiation is prevented. can be

For example, the optical filter layer 120 according to an embodiment of the present invention may block light having a wavelength of 200 to 500 nm, and more specifically, may block light having a wavelength of 300 to 500 nm. As a result, the blue-based light is blocked, so that the active layer 150 of the thin film transistor 100 can be effectively protected.

The optical filter layer 120 according to an embodiment of the present invention may block light having a wavelength of 450 nm or less, and may block light having a wavelength of 350 to 450 nm.

According to an embodiment of the present invention, the optical filter layer 120 does not block light of all wavelengths, but blocks light of a lower frequency band among visible ray regions. Accordingly, light damaging the active layer 150 may be selectively blocked.

Since the light filter layer 120 according to an embodiment of the present invention can pass light other than a blue series, light transmittance of a display device using the thin film transistor 100 is not significantly reduced. In particular, when the thin film transistor 100 according to an embodiment of the present invention is used in a liquid crystal display, the light incident from the backlight is not blocked more than necessary, so that the display performance of the liquid crystal display is not deteriorated.

For selective light blocking, the light filter layer 120 according to an embodiment of the present invention may have an energy bandgap of 3.1 eV or less. According to an embodiment of the present invention, the energy bandgap refers to an energy difference between a conduction band (CB) and a valence band (VB).

According to an embodiment of the present invention, when light is incident on the optical filter layer 120 , electrons in the valence band VB absorb light energy and are excited into the conduction band CB, and at this time, light absorption is performed. The light energy absorbed by the light filter layer 120 may be emitted as, for example, thermal energy.

According to an embodiment of the present invention, the optical filter layer 120 has an energy bandgap in the range of 2.5 to 3.1 eV, and can absorb blue-based light.

According to an embodiment of the present invention, the optical filter layer 120 may include an oxide semiconductor material.

In general, the energy bandgap of the oxide semiconductor material may vary depending on the composition and may also vary depending on the manufacturing method. According to an embodiment of the present invention, in order for the oxide semiconductor material constituting the optical filter layer 120 to have an energy bandgap in the range of 2.5 to 3.1 eV, deposition conditions, heat treatment conditions, or crystallization conditions for the optical filter layer 120 . can be controlled.

According to an embodiment of the present invention, the optical filter layer 120 is, for example, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, and at least one of a GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, IGTO (InGaSnO)-based, GZTO (GaZnSnO)-based, and GO (GaO)-based oxide semiconductor material.

IGZO (InGaZnO), IGZTO (InGaZnSnO), IZO (InZnO), IGO (InGaO), ITO (InSnO), GZTO (GaZnSnO), GZO (GaZnO), ITZO (InSnZnO), IGTO ( The optical filter layer 120 having an energy bandgap in the range of 2.5 to 3.1 eV may be manufactured using InGaSnO)-based, GZTO (GaZnSnO)-based, and GO (GaO)-based oxide semiconductor materials. For example, when using IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based and IZO (InZnO)-based oxide semiconductor materials, the optical filter layer 120 having an energy bandgap in the range of 2.5 to 3.1 eV can be easily manufactured. have.

When the thickness of the optical filter layer 120 is too thin, the light blocking effect by the optical filter layer 120 hardly occurs. Accordingly, according to an embodiment of the present invention, the optical filter layer 120 may have a thickness of 30 nm or more. When the thickness of the light filter layer 120 is less than 30 nm, the light blocking effect is insignificant.

As the light filter layer 120 is thicker, the light blocking effect is generally increased. However, when the thickness is greater than a certain thickness, the light blocking effect by the light filter layer 120 does not increase any more even if the thickness of the light filter layer 120 increases. In consideration of this phenomenon, the optical filter layer 120 may have a thickness of 150 nm or less. According to an embodiment of the present invention, even if the thickness of the optical filter layer 120 exceeds 150 nm, the increase in the light blocking effect is insignificant compared to the case where the thickness of the optical filter layer 120 is 150 nm.

According to one embodiment of the present invention, the optical filter layer 120 may have conductivity. When the optical filter layer 120 has conductivity, a parasitic cap may be generated between the source electrode 161 and the optical filter layer 120 and between the drain electrode and the optical filter layer 120 . In order to prevent or minimize the occurrence of such a parasitic cap, the light filter layer 120 having low electrical conductivity may be used.

According to an embodiment of the present invention, in order to minimize a parasitic cap that may be generated between the source electrode 161 and the optical filter layer 120 and between the drain electrode and the optical filter layer 120 , the optical filter layer 120 . ) may have a carrier density of 1 x 10 ¹⁸ pieces/cm ^{3 or less.} When the carrier density of the optical filter layer 120 is 1 x 10 ¹⁸ pieces/cm ³ or less, there is very little equatorial parasitic cap between the source electrode 161 and the optical filter layer 120 and between the drain electrode and the optical filter layer 120 ( capacitance) may occur, or parasitic caps may be ignored.

According to an embodiment of the present invention, in order to prevent a parasitic cap from being generated between the source electrode 161 and the optical filter layer 120 and between the drain electrode and the optical filter layer 120, the optical filter layer 120 may have a carrier density of 1 x 10 ¹⁷ pieces/cm ^{3 or less.}

4 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention. In the thin film transistor 200 of FIG. 4 , the gate electrode 130 serves as a light blocking layer. Accordingly, in the embodiment according to FIG. 4 , the light blocking layer is the gate electrode 130 .

According to another embodiment of the present invention, the active layer 150 may have a multilayer structure. For example, the active layer 150 may include a first oxide semiconductor layer 151 on the gate electrode 130 and a second oxide semiconductor layer 152 on the first oxide semiconductor layer 151 .

According to another embodiment of the present invention, the first oxide semiconductor layer 151 serves as the main channel layer, and the second oxide semiconductor layer 152 protects the first oxide semiconductor layer 151 in addition to the role of the channel layer. It can act as a protective barrier.

The first oxide semiconductor layer 151 is, for example, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, It may include at least one of a GZO (GaZnO)-based and ITZO (InSnZnO)-based oxide semiconductor material. However, the embodiment of the present invention is not limited thereto, and the first oxide semiconductor layer 151 may be made of other oxide semiconductor materials known in the art.

The second oxide semiconductor layer 152 may have excellent film stability. According to an embodiment of the present invention, the second oxide semiconductor layer 152 is IGZO (InGaZnO)-based, IGO (InGaO)-based, IGTO (InGaSnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GO ( It may include at least one of a GaO)-based and a GZO (GaZnO)-based oxide semiconductor material. However, the exemplary embodiment of the present invention is not limited thereto, and the second oxide semiconductor layer 152 may be made of other oxide semiconductor materials known in the art.

By adjusting the etch rates of the first oxide semiconductor layer 151 and the second oxide semiconductor layer 152 , the active layer 150 may have a stable positive taper shape, respectively.

5 is a cross-sectional view of a thin film transistor 300 according to another embodiment of the present invention. In the thin film transistor 300 of FIG. 5 , the gate electrode 130 serves as a light blocking layer. Accordingly, in the embodiment according to FIG. 5 , the light blocking layer is the gate electrode 130 .

Referring to FIG. 5 , a buffer layer 181 is disposed on the optical filter layer 120 , and a gate electrode 130 serving as a light blocking layer is disposed on the buffer layer 181 . As such, the light filter layer 120 and the light blocking layer may be disposed to be spaced apart from each other.

6 is a cross-sectional view of a thin film transistor 400 according to another embodiment of the present invention. In the thin film transistor 400 of FIG. 6 , the gate electrode 130 serves as a light blocking layer. Accordingly, in the embodiment according to FIG. 6 , the light blocking layer is the gate electrode 130 .

Referring to FIG. 6 , the light blocking layer, the gate electrode 130 , may be disposed on one surface of the substrate 110 , and the light filter layer 120 may be disposed on the other surface of the substrate 110 .

7 is a cross-sectional view of a thin film transistor 500 according to another embodiment of the present invention. The thin film transistor 500 of FIG. 7 has a separate light blocking layer 180 different from the gate electrode 130 .

Referring to FIG. 7 , the optical filter layer 120 is disposed on the substrate 110 , and the light blocking layer 180 is disposed on the optical filter layer 120 . The light blocking layer 180 blocks light incident from the substrate 110 to protect the active layer 130 .

A passivation layer 182 is disposed on the light blocking layer 180 . The passivation layer 182 insulates the light blocking layer 180 from the active layer 150 and protects the active layer 150 .

The active layer 150 is disposed on the passivation layer 182 . The active layer 150 may be formed of an oxide semiconductor material. The active layer 150 may have a single-layer structure or a multi-layered structure in which a plurality of oxide semiconductor layers are stacked.

The gate insulating layer 140 is disposed on the active layer 150 , and the gate electrode 130 is disposed on the gate insulating layer 140 . According to another embodiment of the present invention, the gate electrode 130 is distinguished from the light blocking layer 180 .

A region of the active layer 130 that overlaps with the gate electrode 160 becomes the channel portion 131 , and a region of the active layer 130 that does not overlap with the gate electrode 160 becomes conductive and the conductive portions 132 and 133 of the active layer 130 . ) becomes Conductive portions 132 and 133 are formed on both sides of the channel portion 131 . One of the conductive portions 132 and 133 becomes the source region 132 and the other becomes the drain region 133 .

An interlayer insulating layer 170 is disposed on the gate electrode 130 , and a source electrode 161 and a drain electrode 162 are disposed on the interlayer insulating layer 170 .

The interlayer insulating layer 170 is an insulating layer made of an insulating material. The source electrode 161 and the drain electrode 162 are spaced apart from each other and respectively connected to the active layer 130 . The source electrode 161 and the drain electrode 162 are respectively connected to the active layer 130 through a contact hole formed in the interlayer insulating layer 170 .

As shown in FIG. 7 , a structure in which the gate electrode 130 is disposed on the active layer 150 is also referred to as a top gate structure. The optical filter layer 120 may also be applied to the thin film transistor 500 having a top gate structure.

8 is a cross-sectional view of a thin film transistor 600 according to another embodiment of the present invention. The thin film transistor 600 of FIG. 8 has a separate light blocking layer 180 different from the gate electrode 130 .

Referring to FIG. 8 , the buffer layer 181 is disposed on the light filter layer 120 , and the light blocking layer 180 is disposed on the buffer layer 181 . As such, the light filter layer 120 and the light blocking layer 180 may be disposed to be spaced apart from each other.

9 is a cross-sectional view 700 of a thin film transistor according to another embodiment of the present invention. The thin film transistor 700 of FIG. 9 has a separate light blocking layer 180 different from the gate electrode 130 .

Referring to FIG. 9 , the light blocking layer 180 may be disposed on one surface of the substrate 110 , and the light filter layer 120 may be disposed on the other surface of the substrate 110 .

10A, 10B, and 10C are energy band diagrams illustrating the NBTIS degradation mechanism of a thin film transistor.

NBTIS (Negative Bias Temperature Illuminance Stress) is a phenomenon in which a threshold voltage moves in a negative (-) direction under a stress condition in which a thin film transistor is irradiated with light at a constant temperature and a constant illuminance. Referring to FIG. 10A , electrons in the valence band VB absorb light energy by light irradiated to the active layer 150 and are excited to the conduction band CB, thereby contributing to the flow of current, thereby generating NBTIS.

Referring to FIG. 10B , oxygen vacancies (Vo) of the active layer 150 are changed by the light irradiated to the active layer 150 , and NBTIS may occur.

Referring to FIG. 10C , light is irradiated to excess oxygen included in the active layer 150 , and electrons are emitted from the excess oxygen, thereby generating NBTIS.

When NBTIS degradation occurs in the thin film transistor, the threshold voltage of the thin film transistor is changed, and the reliability of the thin film transistor is deteriorated.

11A and 11B are graphs of a threshold voltage change of a thin film transistor by light irradiation.

11a is a thin film transistor having the same structure as in FIG. 1 and having an active layer 150 made of an IGO (InGaO) (In:Ga = 9:1) oxide semiconductor material, at a temperature of 60° C., 4500 nits of visible light ( It is the result of measuring the threshold voltage of the thin film transistor before (before) and after (after) irradiation with white light.

11b is a thin film transistor having an active layer 150 made of an ITZO (InSnZnO) (In:Sn:Zn = 2.6:1:3) oxide semiconductor material, at a temperature of 60 ° C. Below are the results of measuring the threshold voltage of the thin film transistor before and after.

To measure the threshold voltage (Vth), when the gate voltage (Vgs) was applied in the range of -20V to +20V, the drain-source current (Ids) was measured. 11A and 11B , “before stress” is a graph of gate voltage before temperature and light are applied, and “after stress” is a graph of gate voltage after application of temperature and light.

Referring to FIG. 11A , after the thin film transistor was irradiated with visible light (white light) of 4500 nits at a temperature of 60° C., the threshold voltage shifted about 12V in the negative (-) direction. In the case of Figure 11a, NBTIS can be said to be -12V.

Referring to FIG. 11B , after the thin film transistor was irradiated with visible light (white light) of 4500 nits at a temperature of 60° C., the threshold voltage shifted about 9V in the negative (-) direction. In the case of Figure 11b, NBTIS can be said to be -9V.

According to an embodiment of the present invention, light incident to the active layer 150 of the thin film transistor 100 may be effectively blocked by the optical filter layer 120 . As a result, a threshold voltage change caused by light irradiation is reduced, and NTBIS is reduced in the thin film transistor 100 , so that the thin film transistor can stably maintain switching characteristics. Accordingly, the thin film transistor according to an embodiment of the present invention may have excellent reliability.

12A and 12B are, respectively, a light transmittance graph and a light absorption rate graph of glass, IGZO (InGaZnO), IGZTO (InGaZnSnO), and IZO (InZnO) according to a wavelength. 12A and 12B, the thickness of IGZO (InGaZnO), IGZTO (InGaZnSnO), and IZO (InZnO) is 100 nm, respectively. 12A and 12B, "GLS" indicates the light transmittance and light absorption rate of the glass.

12A and 12B, at a wavelength of 50 nm or less, it can be seen that the light transmittance of IGZO (InGaZnO), IGZTO (InGaZnSnO), and IZO (InZnO) is decreased and the light absorption is increased. Therefore, it can be confirmed that IGZO (InGaZnO), IGZTO (InGaZnSnO), and IZO (InZnO) selectively absorb light having a wavelength of 500 nm or less.

More specifically, IGZO, IGZTO and IZO may block light having a wavelength of 200 to 500 nm, and in particular, may effectively block light having a wavelength of 300 to 500 nm. IGZO, IGZTO and IZO can block blue-based light.

12A and 12B, IGZO, IGZTO and IZO can easily block light having a wavelength of 450 nm or less, in particular, it can be confirmed that it is useful for blocking light having a wavelength of 350 to 450 nm.

13A and 13B are a light transmittance graph and a light absorbance graph for each thickness of IZO (InZnO) according to a wavelength, respectively. 13A and 13B, "GLS" indicates the light transmittance and light absorption rate of the glass.

Referring to FIGS. 13A and 13B , it can be seen that the light transmittance of IZO (InZnO) decreases and the light absorption rate increases as the thickness increases.

Specifically, when the thickness of IZO (InZnO) is as thin as 10 nm, the light blocking effect by the optical filter layer 120 is not large, and when the thickness is 30 nm or more, it can be confirmed that a relatively large light blocking effect occurs.

As the thickness of IZO (InZnO) increases, the light blocking effect increases, but even if the thickness exceeds 150 nm, it can be confirmed that the light blocking effect does not significantly increase compared to the case where the thickness of IZO (InZnO) is 150 nm.

14A, 14B, and 14C are graphs of a threshold voltage change of an oxide thin film transistor having an active layer made of IZO (InZnO), respectively.

Specifically, FIG. 14a shows a thin film transistor having the same structure as in FIG. 1 having an active layer 150 made of an IZO (InZnO) (In:Zn = 1:1) oxide semiconductor material, 4500 nits at a temperature of 60° C. It is the result of measuring the threshold voltage of the thin film transistor before and after irradiating visible light (white light). The optical filter layer 120 is not disposed in the thin film transistor of FIG. 14A .

To measure the threshold voltage (Vth), when the gate voltage (Vgs) was applied in the range of -20V to +20V, the drain-source current (Ids) was measured. In FIG. 14A , “before” is a graph of gate voltage before temperature and light are applied, and “after” is a graph of gate voltage after temperature and light are applied.

Referring to FIG. 14A , after the thin film transistor was irradiated with visible light (white light) of 4500 nits at a temperature of 60° C., the threshold voltage shifted about 3.5V in the negative (-) direction. In the case of Figure 14a, NBTIS can be said to be -3.5V.

14B is a graph showing a change in threshold voltage when an InGaZnSnO (IGZTO) layer with a thickness of 100 nm is disposed under the gate electrode 130 as the optical filter layer 120 .

Referring to FIG. 14B , after the thin film transistor was irradiated with visible light (white light) of 4500 nits at a temperature of 60° C., the threshold voltage shifted about 2.8V in the negative (-) direction. In the case of FIG. 14B , it can be said that NBTIS is -2.8V.

14C is a graph showing a change in threshold voltage when an IZO (InZnO) layer having a thickness of 100 nm is disposed under the gate electrode 130 as the optical filter layer 120 .

Referring to FIG. 14C , after the thin film transistor was irradiated with visible light (white light) of 4500 nits at a temperature of 60° C., the threshold voltage shifted about 2.4V in the negative (-) direction. In the case of Figure 14c, NBTIS can be said to be -2.8V.

Comparing FIGS. 14A, 14B, and 14C, when the optical filter layer 120 is disposed under the gate electrode 130, it can be seen that the magnitude of the threshold voltage change is reduced and the magnitude of the NBTIS is reduced.

15 is a schematic diagram of a display device 800 according to another embodiment of the present invention.

As shown in FIG. 15 , the display device 800 according to an exemplary embodiment includes a display panel 210 , a gate driver 220 , a data driver 230 , and a controller 240 .

The display panel 210 includes gate lines GL, data lines DL, and a pixel P disposed at intersections of gate lines GL and data lines DL. An image is displayed on the display panel 210 by driving the pixel P.

The controller 240 controls the gate driver 220 and the data driver 230 .

The controller 240 controls the gate control signal GCS and the data driver 230 for controlling the gate driver 220 using a vertical/horizontal synchronization signal and a clock signal supplied from an external system (not shown). Outputs a data control signal DCS for In addition, the controller 240 samples the input image data input from the external system, rearranges it, and supplies the image data RGB to the data driver 230 .

The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. Also, the gate control signal GCS may include control signals for controlling the shift register.

The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

The data driver 230 supplies a data voltage to the data lines DL of the display panel 210 . Specifically, the data driver 230 converts the image data RGB input from the controller 240 into a data voltage and supplies the data voltage to the data lines DL.

The gate driver 220 sequentially supplies the gate pulses GP to the gate lines GL for one frame. Here, one frame refers to a period in which one image is output through the display panel 210 . Also, the gate driver 220 supplies a gate-off signal Goff capable of turning off the switching device to the gate line GL during the remaining period in which the gate pulse GP is not supplied during one frame.

According to an embodiment of the present invention, the gate driver 220 is mounted on the display panel 210 . As such, a structure in which the gate driver 220 is directly mounted on the display panel 210 is referred to as a gate in panel (GIP) structure.

Referring to FIG. 15 , the gate driver 220 mounted on the display panel 210 includes a shift register 250 . The shift register 250 generates and supplies the gate pulse GP.

The shift register 250 sequentially supplies the gate pulse GP to the gate lines GL for one frame using the start signal Vst and the gate clock CLK signal transmitted from the controller 240 . do. The gate pulse GP has a turn-on voltage capable of turning on the switching element (thin film transistor) formed in the pixel P.

The shift register 250 supplies a gate-off signal Goff capable of turning off the switching element to the gate line GL during the remaining period in which the gate pulse GP is not supplied during one frame. Hereinafter, the gate pulse GP and the gate-off signal Goff are collectively referred to as a scan signal SS.

FIG. 16 is a schematic diagram of the shift register 250 , and FIG. 17 is a circuit diagram of the stage 251 provided in the shift register 250 of FIG. 16 .

As shown in FIG. 16 , the shift register 250 according to an embodiment of the present invention may include g stages 251 ( ST1 to STg ).

The shift register 250 transmits one scan signal SS to the pixels P connected to one gate line GL through one gate line GL. Each of the stages 251 may be connected to one gate line GL. When g gate lines GL are formed in the display panel 210 , the shift register 250 includes g stages 251 , ST1 to STg, and g scan signals SS1 to SSg. ) is created.

In general, each stage 251 outputs the gate pulse GP once in one frame, and the gate pulse GP is sequentially output in each stage 251 .

Each of the stages 251 sequentially outputting the gate pulse GP is, as shown in FIG. 17 , a pull-up transistor Pu, a pull-down transistor Pd, a start transistor Tst, a reset transistor Trs, and It includes an inverter (I).

The pull-up transistor Pu is turned on or off according to the logic state of the Q node, and when turned on, receives the clock signal CLK and outputs the gate pulse GP [Vout(SS)].

The pull-down transistor Pd is connected between the pull-up transistor Pu and the turn-off voltage VSS1, is turned off when the pull-up transistor Pu is turned on, and is turned on and gated when the pull-up transistor Pu is turned off An off signal Goff is output.

As such, the output Vout of the stage 251 includes the gate pulse GP and the gate-off signal Goff. The gate pulse GP has a high level voltage, and the gate-off signal Goff has a low level voltage.

The start transistor Tst charges the Q node with the high level voltage VD in response to the previous stage output PRE from the previous stage. When the corresponding stage 251 is the first stage ST1, the start pulse Vst is supplied instead of the previous output PRE.

The reset transistor Trs discharges the Q node to the low potential voltage VSS, which is the reset voltage, in response to the output NXT from the next stage. When the corresponding stage 251 is the last stage STg, the reset pulse Rest is supplied instead of the downstream output NXT.

The control signal input to the gate terminal of the reset transistor Trs generally maintains a low state when the Q node is high.

When a high level signal is input to the Q node, the pull-up transistor Pu is turned on, and a gate pulse GP is output. At this time, when the reset transistor Trs is turned off, the low potential voltage VSS is not supplied to the reset transistor Trs.

When the gate pulse GP is output, a high-level control signal is input to the gate terminal of the reset transistor Trs, the reset transistor Trs is turned on, and the pull-up transistor Pu is turned off. As a result, the gate pulse GP is not output through the pull-up transistor Pu.

The inverter I performs a function of transmitting a Qb node control signal for generating the gate-off signal Goff to the pull-down transistor Pd through the Qb node when the gate pulse GP is not generated.

The data voltage is output to the data lines DL every one horizontal period by a turn-on voltage capable of turning on the switching element of each pixel P connected to the gate line GL, and one horizontal period in one frame. During the remaining period except for , the gate-off signal Goff for maintaining the switching device in the turned-off state should be output to the gate line GL.

To this end, the inverter I transmits the Qb node control signal to the pull-down transistor Pd through the Qb node during the remaining period except for one horizontal period of one frame.

The pull-down transistor Pd is turned on by the Qb node control signal supplied from the inverter I, and the gate-off signal Goff is output to the gate line GL.

According to another embodiment of the present invention, the thin film transistors disposed in the gate driver 220 and the data driver 230 are shown in FIGS. 2, 4, 5, 6, 7, 8 and 9. It may have the same structure as any one of the thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , and 700 .

According to another embodiment of the present invention, the thin film transistors disposed in the shift resistor 250 are the thin film transistors 100 shown in FIGS. 2, 4, 5, 6, 7, 8 and 9. 200, 300, 400, 500, 600, and 700) may have the same structure as any one of the above structures.

According to another embodiment of the present invention, the thin film transistors disposed on the stage 251 are the thin film transistors 100 and 200 shown in FIGS. 2, 4, 5, 6, 7, 8 and 9 . , 300, 400, 500, 600, 700) may have the same structure as any one of.

18 is a circuit diagram of one pixel P of FIG. 15 , FIG. 19 is a plan view of the pixel P of FIG. 18 , and FIG. 20 is a cross-sectional view taken along II-II′ of FIG. 19 .

18, 19 and 20 , the pixel P of the display device 800 according to an embodiment of the present invention includes a pixel driver PDC and a display device 710 connected to the pixel driver PDC. include

The circuit diagram of FIG. 18 is an equivalent circuit diagram of one pixel P of the display device 800 including an organic light emitting diode (OLED) as the display element 710 . Accordingly, the display device 800 according to an embodiment of the present invention is an organic light emitting display device.

The pixel driver PDC of FIG. 18 includes a first thin film transistor TR1 serving as a switching transistor and a second thin film transistor TR2 serving as a driving transistor.

The first thin film transistor TR1 and the second thin film transistor TR2 of FIGS. 18, 19 and 20 have a bottom gate structure.

According to another embodiment of the present invention, at least one of the first thin film transistor TR1 and the second thin film transistor TR2 is shown in FIGS. 2 , 4 , 5 , 6 , 7 , 8 and 9 . It may have the same structure as any one of the thin film transistors 100, 200, 300, 400, 500, 600, and 700 illustrated in FIG.

Referring to FIG. 18 , the first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL. do.

The data line DL provides the data voltage Vdata to the pixel driver PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

The driving power line PL provides the driving voltage Vdd to the display device 710 , and the second thin film transistor TR2 controls the driving voltage Vdd. Here, the driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode OLED as the display device 710 .

When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode G2 of the second thin film transistor TR2 connected to the display device 710 . do. The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode G2 and the source electrode S2 of the second thin film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

The amount of current supplied to the organic light emitting diode OLED as the display device 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, and accordingly, the amount of light output from the display device 710 is controlled. The gradation can be controlled.

19 and 20 , the first thin film transistor TR1 includes an optical filter layer 120 on a substrate 110 , a first gate electrode G1 , and a first active layer A1 .

The second thin film transistor TR2 includes an optical filter layer 120 on the substrate 110 , a second gate electrode G2 , and a second active layer A2 .

The substrate 110 may be made of glass or plastic. As the substrate 110 , a plastic having a flexible property, for example, polyimide (PI) may be used.

19 and 20 , the optical filter layer 120 is disposed on the substrate 110 . The light filter layer 120 selectively blocks light. Since the optical filter layer 120 has already been described, a detailed description of the optical filter layer 120 will be omitted below in order to avoid duplication.

A first gate electrode G1 , a second gate electrode G2 , and a first capacitor electrode C11 of the first capacitor C1 are disposed on the optical filter layer 120 to overlap the optical filter layer 120 . The optical filter layer 120 under the first gate electrode G1 and the optical filter layer 120 under the second gate electrode G2 are spaced apart from each other.

The optical filter layer 120 under the first gate electrode G1 has a larger area than the first gate electrode G1, and the optical filter layer 120 under the second gate electrode G2 has a second gate electrode G2. have a larger area.

19 and 20 , the first gate electrode G1 is integrally formed with the gate line GL and extends from the gate line GL. The light filter layer 120 is also disposed under the gate line GL.

According to another embodiment of the present invention, the second gate electrode G2 is connected to the first capacitor electrode C11 of the first capacitor C1. The second gate electrode G2 may be integrally formed with the first capacitor electrode C11 of the first capacitor C1 .

A gate insulating layer 140 is disposed on the gate line GL, the first gate electrode G1 , the second gate electrode G2 , and the first capacitor electrode C11 . The gate insulating layer 140 is made of an insulating material. The gate insulating layer 140 may be formed of, for example, an insulating material such as silicon oxide or silicon nitride.

A first active layer A1 and a second active layer A2 are disposed on the gate insulating layer 140 .

Referring to FIG. 20 , the first active layer A1 and the second active layer A2 may be disposed on the same layer. In this case, the first active layer A1 and the second active layer A2 may be patterned together by the same process using the same material. However, the exemplary embodiment is not limited thereto, and the first active layer A1 and the second active layer A2 may be disposed on different layers or may be made of different materials.

According to an embodiment of the present invention, the first active layer A1 and the second active layer A2 include an oxide semiconductor material.

The first active layer A1 may have a multilayer structure. Referring to FIG. 4 , the first active layer A1 may include a first oxide semiconductor layer 151 and a second oxide semiconductor layer 152 on the first oxide semiconductor layer 151 .

The second active layer A2 may also have a multilayer structure. Referring to FIG. 4 , the second active layer A2 may include a first oxide semiconductor layer 151 and a second oxide semiconductor layer 152 on the first oxide semiconductor layer 151 .

A first source electrode S1 and a first drain electrode D1 are disposed on at least a portion of the first active layer A1 . The first source electrode S1 and the first drain electrode D1 are spaced apart from each other and connected to the first active layer A1, respectively.

At least one of the first source electrode S1 and the first drain electrode D1 may be connected to the data line DL. Referring to FIG. 19 , the first source electrode S1 extends from the data line DL and is integrally formed with the data line DL.

A second source electrode S2 and a second drain electrode D2 are disposed on at least a portion of the second active layer A2 . The second source electrode S2 and the second drain electrode D2 are spaced apart from each other and connected to the second active layer A2, respectively.

19 and 20 , the first drain electrode D1 is connected to the first capacitor electrode C11. Specifically, the first drain electrode D1 contacts the first capacitor electrode C11 through the first contact hole H1 formed in the gate insulating layer 140 .

According to another embodiment of the present invention, the second drain electrode D2 is integrally formed with the driving power line PL. The second drain electrode D2 may extend from the driving power line PL.

19 and 20 , the second source electrode S2 may extend on the gate insulating layer 140 to become the second capacitor electrode C12 . A portion of the second source electrode S2 may be the second capacitor electrode C12 . The first capacitor electrode C11 and the second capacitor electrode C12 overlap each other and constitute the first capacitor C1 .

According to an embodiment of the present invention, the first source electrode S1 , the first drain electrode D1 , the second source electrode S2 , the second drain electrode D2 , the data line DL, and the driving power line (PL) and the second capacitor electrode C12 may be made together by the same process using the same material.

With this configuration, the first thin film transistor TR1 and the second thin film transistor TR2 are formed.

A passivation layer 170 is disposed on the first thin film transistor TR1 and the second thin film transistor TR2 . The passivation layer 170 planarizes upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the pixel driver PDC. The protective layer 170 is also referred to as a planarization layer.

A display device 710 is disposed on the protective layer 170 . Specifically, the first electrode 711 , the emission layer 712 , and the second electrode 713 are sequentially disposed on the protective layer 170 to form the display device 710 . The display device 710 is connected to the pixel driver PDC.

The first electrode 711 of the display device 710 is disposed on the protective layer 170 . The first electrode 711 may be connected to the second thin film transistor TR2 through the second contact hole H2 . The second contact hole H2 may be formed in the protective layer 170 .

Referring to FIG. 20 , the first electrode 711 is connected to the second source electrode S2 of the second thin film transistor TR2 through the second contact hole H2, and as a result, the first electrode 711 may also be electrically connected to the second capacitor electrode C12.

A bank layer 750 is disposed on an edge of the first electrode 711 . The bank layer 750 defines a light emitting area of the display device 710 .

A light emitting layer 712 is disposed on the first electrode 711 . Here, the emission layer 712 is an organic emission layer including an organic material. A second electrode 713 is disposed on the emission layer 712 . Accordingly, the display device 710 is completed.

The display device 710 illustrated in FIG. 20 is an organic light emitting diode (OLED). Accordingly, the display device 800 according to an embodiment of the present invention is an organic light emitting display device.

According to an embodiment of the present invention, the first thin film transistor TR1 and the second thin film transistor TR2 have a bottom gate structure. Since the thin film transistor having the bottom gate structure has a relatively small area compared to the thin film transistor having the top gate structure, the first thin film transistor TR1 and the second thin film transistor TR2 may be integrated in the display device with high density. As a result, the high-resolution display device 800 can be manufactured.

21 is a circuit diagram of any one pixel P of the display device 900 according to another embodiment of the present invention. 21 is an equivalent circuit diagram of a pixel P of an organic light emitting diode display.

The pixel P of the display device 900 illustrated in FIG. 21 includes an organic light emitting diode (OLED) serving as a display device 710 and a pixel driver PDC driving the display device 710 . The display device 710 is connected to the pixel driver PDC.

Signal lines DL, GL, PL, RL, and SCL for supplying signals to the pixel driver PDC are disposed in the pixel P.

The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, and the driving voltage Vdd for driving the pixel is supplied to the driving power line PL. The reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL.

Referring to FIG. 21 , when the gate line of the n-th pixel P is referred to _{as “GL n ”, the gate line of the neighboring n-th pixel P is “GL n-1} ”, and the n-th pixel P is “GL n-1 ”. The gate line “GL _n-1 ” of the pixel P serves as the sensing control line SCL of the n-th pixel P.

The pixel driver PDC includes, for example, a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, and a first thin film transistor TR1 as shown in FIG. 21 . ) to detect the characteristics of the second thin film transistor TR2 (driving transistor) and the second thin film transistor TR2 that control the magnitude of the current output to the display device 710 according to the data voltage Vdata transmitted through and a third thin film transistor TR3 (reference transistor) for At least one of the first thin film transistor TR1 , the second thin film transistor TR2 , and the third thin film transistor TR3 is shown in FIGS. 2 and 4 , 5 , 6 , 7 , 8 and 9 . It may have the same structure as any one of the thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , and 700 .

A first capacitor C1 is positioned between the gate electrode G2 of the second thin film transistor TR2 and the display device 710 . The first capacitor C1 is also referred to as a storage capacitor Cst.

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and the data voltage Vdata supplied to the data line DL is applied to the gate electrode of the second thin film transistor TR2. (G2).

The third thin film transistor TR3 is connected to the first node n1 between the second thin film transistor TR2 and the display device 710 and the reference line RL, and is turned on or turned on by the sensing control signal SCS. It is turned off, and the characteristic of the second thin film transistor TR2 serving as the driving transistor is sensed during the sensing period.

The second node n2 connected to the gate electrode G2 of the second thin film transistor TR2 is connected to the first thin film transistor TR1 . A first capacitor C1 is formed between the second node n2 and the first node n1 .

When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode G2 of the second thin film transistor TR2 . The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode G2 and the source electrode S2 of the second thin film transistor TR2.

When the second thin film transistor TR2 is turned on, a current is supplied to the display device 710 through the second thin film transistor TR2 by the driving voltage Vdd for driving the pixel, and the display device 710 emits light. This is output.

22 is a circuit diagram of one pixel P of the display device 1000 according to another exemplary embodiment of the present invention.

The pixel P of the display device 1000 shown in FIG. 22 includes an organic light emitting diode (OLED) serving as a display device 710 and a pixel driver PDC driving the display device 710 . The display device 710 is connected to the pixel driver PDC.

The pixel driver PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 . At least one of the first thin film transistor TR1 , the second thin film transistor TR2 , the third thin film transistor TR3 , and the fourth thin film transistor TR4 is shown in FIGS. 2 and 4 , 5 , 6 and 7 . , may have the same structure as any one of the thin film transistors 100, 200, 300, 400, 500, 600, and 700 illustrated in FIGS. 8 and 9 .

Signal lines DL, EL, GL, PL, SCL, and RL for supplying driving signals to the pixel driver PDC are disposed in the pixel P.

Compared to the pixel P of FIG. 21 , the pixel P of FIG. 22 further includes a light emission control line EL. The light emission control signal EM is supplied to the light emission control line EL.

In addition, compared to the pixel driver PDC of FIG. 21 , the pixel driver PDC of FIG. 22 further includes a fourth thin film transistor TR4 which is an emission control transistor for controlling the emission timing of the second thin film transistor TR2 . include

Referring to Figure 22, the gate lines of the n-th pixel (P) to as a gate line "GL _n", adjacent n-1-th pixel (P) of the are "GL _n-1", n-1 th The gate line “GL _n-1 ” of the pixel P serves as the sensing control line SCL of the n-th pixel P.

A first capacitor C1 is positioned between the gate electrode G2 of the second thin film transistor TR2 and the display device 710 . Also, a second capacitor C2 is positioned between a terminal to which the driving voltage Vdd is supplied among the terminals of the fourth thin film transistor TR4 and one electrode of the display device 710 .

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and the data voltage Vdata supplied to the data line DL is applied to the gate electrode of the second thin film transistor TR2. (G2).

The third thin film transistor TR3 is connected to the reference line RL, is turned on or turned off by the sensing control signal SCS, and senses characteristics of the second thin film transistor TR2 serving as the driving transistor during the sensing period.

The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the emission control signal EM. When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2 , and light is output from the display device 710 .

The pixel driver PDC according to another embodiment of the present invention may be formed in various structures other than those described above. The pixel driver PDC may include, for example, five or more thin film transistors.

23 is a circuit diagram of one pixel P of a display device 1100 according to another embodiment of the present invention, FIG. 24 is a plan view of the pixel P of FIG. 23 , and FIG. 25 is FIG. 24 It is a cross-sectional view taken along III-III' of

The circuit diagram of FIG. 23 is an equivalent circuit diagram of one pixel P of a liquid crystal display including a liquid crystal LC as a display element. The pixel P is disposed on the display unit DA.

23 , 24 and 25 , a display device 1100 according to another exemplary embodiment includes a substrate 310 , a pixel driver PDC and a pixel driver PDC disposed on the substrate 310 , and a connected liquid crystal capacitor Clc. The liquid crystal capacitor Clc corresponds to a display device.

The pixel driver PDC includes a thin film transistor TR connected to the gate line GL and the data line DL, and a storage capacitor Cst connected between the thin film transistor TR and the second electrode 372 of the display device. includes The liquid crystal capacitor Clc is connected in parallel with the storage capacitor Cst between the thin film transistor TR and the second electrode 372 .

The liquid crystal capacitor Clc is a voltage difference between the data signal supplied to the first electrode 371 serving as the pixel electrode through the thin film transistor TR and the common voltage Vcom supplied to the second electrode 372 serving as the common electrode. is charged, and the liquid crystal is driven according to the charged voltage to control the amount of light transmission. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

According to another embodiment of the present invention, the thin film transistor TR is the thin film transistor 100, 200, 300, 400 shown in FIGS. 2, 4, 5, 6, 7, 8 and 9. , 500, 600, 700) may have the same structure as any one of.

Referring to FIG. 25 , a display device 1100 according to another embodiment of the present invention includes a substrate 310 , an optical filter layer 120 on the substrate 310 , and a gate electrode G on the optical filter layer 120 . , an active layer (A) on the gate electrode (G), a source electrode (S) connected to the active layer (A), a drain electrode (D), and a first electrode (371) connected to the drain electrode (D).

The substrate 310 may be made of glass or plastic. As the substrate 310, a plastic having a flexible property, for example, polyimide (PI) may be used.

A light filter layer 120 is disposed on the substrate 310 ;

A gate line GL and a gate electrode G are disposed on the light filter layer 120 . The light filter layer 120 has a larger area than the gate electrode G.

Referring to FIG. 24 , the gate electrode G extends from the gate line GL and is integrally formed with the gate line GL. The gate electrode G and the light filter layer 120 block external light incident to the active layer A.

A gate insulating layer 320 is disposed on the gate electrode G1 . The gate insulating layer 320 is made of an insulating material, and insulates the gate electrode G1 from the active layer A.

An active layer A is disposed on the gate insulating layer 320 . The active layer A1 at least partially overlaps the gate electrode G.

According to an embodiment of the present invention, the active layer A1 includes an oxide semiconductor material. The active layer (A) may have a multilayer structure. The active layer A1 may include a first oxide semiconductor layer 151 on the gate insulating layer 320 and a second oxide semiconductor layer 152 on the first oxide semiconductor layer 151 .

A source electrode (S) and a drain electrode (D) are disposed on the active layer (A). The source electrode S and the drain electrode D are spaced apart from each other and connected to the active layer A, respectively.

At least one of the source electrode S and the drain electrode D may be connected to the data line DL. At least one of the source electrode S and the drain electrode D may extend from the data line DL. Referring to FIG. 24 , the data line DL is integrally formed with the source electrode S.

The thin film transistor TR is constituted by the gate electrode G, the active layer A, the source electrode S, and the drain electrode D.

Referring to FIG. 25 , a passivation layer 340 is disposed on the source electrode S and the drain electrode D. Referring to FIG. The passivation layer 340 protects the thin film transistor TR.

A passivation layer 350 is disposed on the passivation layer 240 . The passivation layer 350 planarizes an upper portion of the thin film transistor TR1 and protects the pixel driver PDC. The protective layer 350 is also referred to as a planarization layer.

Referring to FIG. 25 , a second electrode 372 is disposed on the protective layer 350 . A common voltage is applied to the second electrode 372 . Accordingly, the second electrode 372 is also referred to as a common electrode.

The interlayer insulating layer 360 is disposed on the second electrode 372 , and the first electrode 371 is disposed on the interlayer insulating layer 360 . The first electrode 371 is connected to the thin film transistor TR through the contact hole CH1 . Specifically, the first electrode 371 is connected to the drain electrode D1 of the thin film transistor TR through the contact hole CH1 formed in the interlayer insulating layer 360 , the protective layer 350 , and the passivation layer 340 . contact

24 and 25 , the first electrode 371 has a line electrode shape and the second electrode 372 has a surface electrode shape, but the embodiment of the present invention is not limited thereto. . The first electrode 371 may have a surface electrode shape, the second electrode 372 may have a line electrode shape, and both the first electrode 371 and the second electrode 372 may have a line electrode shape. , both the first electrode 371 and the second electrode 372 may have a planar electrode shape.

A liquid crystal layer 450 is disposed on the first electrode 371 . Specifically, the liquid crystal layer 450 is disposed between the substrate 310 and the opposite substrate 410 .

Referring to FIG. 25 , a color filter 420 is disposed on the opposite substrate 410 , and a black matrix 430 is disposed between the color filters. The black matrix 430 allows pixel areas to be distinguished from each other.

Although an embodiment in which the color filter 420 is disposed on the opposite substrate 410 is disclosed in FIG. 25 , another embodiment of the present invention is not limited thereto. The color filter 420 may be disposed on the substrate 310 .

According to another embodiment of the present invention, since the thin film transistor TR having a bottom gate structure has a small area, it is advantageous for high integration of the thin film transistor. Accordingly, according to an exemplary embodiment of the present invention, a high-resolution display device 1100 may be manufactured.

Hereinafter, a method of manufacturing the display device 800 according to an exemplary embodiment will be described with reference to FIGS. 26A to 26H .

26A to 26H are cross-sectional views illustrating a manufacturing process of the thin film transistor 100 according to an embodiment of the present invention.

Referring to FIG. 26A , an oxide layer OXL and a metal layer ML for forming an optical filter layer are sequentially formed on a substrate 110 . The metal layer ML is used to form the light blocking layer. When the gate electrode 130 is a light blocking layer, the metal layer ML may be used to form the gate electrode.

According to an embodiment of the present invention, the gate electrode 130 may serve as a light blocking layer, and the gate electrode 130 may serve as a light blocking layer. As described above, according to an embodiment of the present invention, since the gate electrode 130 is the same as the light blocking layer, for convenience of description, the expression “gate electrode 130” is used instead of the expression “light blocking layer”. A method of manufacturing the transistor 100 will be described.

The oxide layer OXL for forming the optical filter layer may have an energy bandgap of 3.1 eV or less. The oxide layer OXL for forming the optical filter layer may be formed of an oxide semiconductor material. For example, IGZO (InGaZnO), IGZTO (InGaZnSnO), IZO (InZnO), IGO (InGaO), ITO (InSnO), GZTO (GaZnSnO), GZO (GaZnO), ITZO (InSnZnO) The oxide layer OXL for forming the optical filter layer may be made of at least one of an IGTO (InGaSnO)-based, GZTO (GaZnSnO)-based, and GO (GaO)-based oxide semiconductor material.

The metal layer ML is formed on the oxide layer OXL for forming the optical filter layer. The metal layer ML may include a metal. The metal layer ML is, for example, an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, or a copper-based metal such as copper (Cu) or a copper alloy. It may include at least one of a metal, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodium (Nd), and titanium (Ti). The metal layer ML may have a multilayer structure including at least two conductive layers having different physical properties.

Referring to an embodiment of the present invention, the light filter layer 120 and the gate electrode 130 serving as the light blocking layer are formed by patterning using the halftone mask 610 .

A patterning process using the halftone mask 610 is shown step by step in FIGS. 26A to 26F .

Referring to FIG. 26A , a photoresist layer 510 is disposed on the metal layer ML, and a halftone mask 610 is disposed on the photoresist layer 510 .

The halftone mask 610 is disposed to be spaced apart from the photoresist layer 510 , and light L is irradiated through the halftone mask 610 to selectively expose the photoresist layer 510 .

Referring to FIG. 26A , the halftone mask 610 includes a light blocking part 611 , a light transmitting part 612 , and a semi-transmissive part 613 .

The photoresist layer 510 is selectively exposed by exposure using the halftone mask 610 .

Referring to FIG. 26B , the selectively exposed photoresist layer 510 is developed to form a photoresist pattern 511 .

Referring to FIG. 26C , the oxide layer OXL and the metal layer ML for forming the optical filter layer are patterned by etching using the photoresist pattern 511 as a mask to form the optical filter layer 120 and the gate electrode 130, respectively. is formed

Referring to FIG. 26D , the photoresist pattern 511 is further ashed to form a new photoresist pattern 512 . As a result, a portion of the gate electrode 130 is exposed from the photoresist pattern 512 .

Referring to FIG. 26E , an edge portion of the gate electrode 130 is removed by etching using the photoresist pattern 512 as a mask. Accordingly, a portion of the light filter layer 120 is exposed from the gate electrode 130 . A portion of the light filter layer 120 exposed from the gate electrode 130 becomes the protrusion 121 .

Referring to FIG. 26F , the remaining photoresist pattern 512 is removed to complete the data line DL, the light filter layer 120 , and the gate electrode 130 .

Referring to FIG. 26G , the gate insulating layer 140 is formed on the optical filter layer 120 and the gate electrode 130 , and the active layer 150 is formed on the gate insulating layer 140 . The active layer 150 at least partially overlaps the gate electrode 130 .

Referring to FIG. 26H , a source electrode 161 and a drain electrode 162 are formed on at least a portion of the active layer 150 . As a result, a thin film transistor is made.

The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and it is in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical matters of the present invention. It will be clear to those of ordinary skill in the art. Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning, scope, and equivalent concept of the claims should be construed as being included in the scope of the present invention.

110: substrate 120: light filter layer
130: gate electrode 140: gate insulating film
150: active layer 161: source electrode
162: drain electrode 180: light blocking layer
710: display element 711: first electrode
712: light emitting layer 713: second electrode
DL: data line
PL: drive power line
A1, A2: active layer
G1, G2: gate electrode
S1, S2: source electrode
D1, D2: drain electrode

Claims (21)

an optical filter layer on the substrate;
a light blocking layer on the substrate overlapping the light filter layer; and
and an active layer spaced apart from the light blocking layer and overlapping the light blocking layer;
The light blocking layer is disposed between the substrate and the active layer,
The light filter layer has a larger area than the light blocking layer, and is disposed between the substrate and the light blocking layer. According to claim 1,
wherein the optical filter layer comprises an oxide semiconductor material. According to claim 1,
The optical filter layer is IGZO (InGaZnO) based, IGZTO (InGaZnSnO) based, IZO (InZnO) based, IGO (InGaO) based, ITO (InSnO) based, GZTO (GaZnSnO) based, GZO (GaZnO) based, ITZO (InSnZnO) based A thin film transistor comprising at least one of an oxide semiconductor material based on, IGTO (InGaSnO) based, GZTO (GaZnSnO) based and GO (GaO) based oxide semiconductor material. According to claim 1,
wherein the light filter layer has a protrusion protruding from the light blocking layer in a planar view. According to claim 1,
The light filter layer blocks light having a wavelength of 500 nm or less, a thin film transistor. According to claim 1,
The light filter layer has an energy bandgap of 3.1 eV or less, a thin film transistor. According to claim 1,
The light filter layer has a thickness of 30 nm or more, a thin film transistor. According to claim 1,
The light filter layer has a thickness of 30 nm to 150 nm, a thin film transistor. According to claim 1,
The light filter layer has ^{a carrier density of 1 x 10 18} pieces/cm ³ or less, a thin film transistor. According to claim 1,
wherein the active layer comprises an oxide semiconductor material. According to claim 1, wherein the active layer,
a first oxide semiconductor layer on the light blocking layer; and
A thin film transistor comprising a; a second oxide semiconductor layer on the first oxide semiconductor layer. According to claim 1,
The light blocking layer is in contact with the light filter layer, thin film transistor. According to claim 1,
The light blocking layer is spaced apart from the light filter layer, the thin film transistor. According to claim 1,
The light blocking layer is disposed on one surface of the substrate,
and the optical filter layer is disposed on the other surface of the substrate. According to claim 1,
The light blocking layer is a gate electrode, a thin film transistor. According to claim 1,
a gate electrode overlapping the active layer;
wherein the active layer is disposed between the gate electrode and the light blocking layer. A display device comprising the thin film transistor of any one of claims 1 to 16. sequentially forming an oxide layer and a metal layer for forming an optical filter layer on a substrate;
forming a light filter layer and a light blocking layer by patterning using a halftone mask; and
and forming an active layer spaced apart from the light blocking layer and overlapping the light blocking layer;
The method of claim 1, wherein the light filter layer has a larger area than the light blocking layer. 19. The method of claim 18,
The optical filter layer is IGZO (InGaZnO) based, IGZTO (InGaZnSnO) based, IZO (InZnO) based, IGO (InGaO) based, ITO (InSnO) based, GZTO (GaZnSnO) based, GZO (GaZnO) based, ITZO (InSnZnO) based A method of manufacturing a thin film transistor, comprising at least one of an IGTO (InGaSnO)-based, GZTO (GaZnSnO)-based, and GO (GaO)-based oxide semiconductor material. 19. The method of claim 18,
The optical filter layer has an energy bandgap of 3.1 eV or less, a method of manufacturing a thin film transistor. 19. The method of claim 18,
The optical filter layer has a thickness of 30 nm or more, a method of manufacturing a thin film transistor.

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