KR20210083728A - Display device and method of driving thereof - Google Patents

Abstract

A display device and a driving method thereof are provided. The display device comprises: a display panel provided with a display area in which a plurality of sub-pixels are arranged along columns and rows; a plurality of data lines arranged one-by-one for each column of a pair of sub-pixels arranged in the display area and supplying a data voltage to sub-pixels arranged in both sub-pixel columns, respectively; a plurality of gate lines arranged one-by-one for each row of sub-pixels arranged in the display area and supplying a scan signal to sub-pixels arranged in rows of each sub-pixel; a plurality of gate driving units arranged one-by-one for each gate line disposed in the display area and generating a scan signal which is to be supplied by each gate line to the sub-pixels; and a plurality of signal lines arranged in each sub-pixel column unit alternately with the plurality of data lines and supplying signals for operation of the gate driving units, wherein the gate driving unit includes a plurality of gate drivers, and each gate driver is arranged in the display area in correspondence to the constant number of consecutive sub-pixel columns to supply the scan signal to a corresponding gate line. The present invention can maximally secure the display area for displaying an image.

Description

Display device and its driving method {DISPLAY DEVICE AND METHOD OF DRIVING THEREOF}

The present invention relates to a display device, and more particularly, to a display device capable of realizing a narrow bezel while reducing a non-display area of a display panel, and a driving method thereof.

As the information society develops, the demand for display devices having various forms and functions for visually displaying electrical information signals is increasing. In response to these demands, a display device such as a Liquid Crystal Display Device (LCD) or an Organic Light Emitting Diode Display (hereinafter referred to as an “OLED display device”) is used as a display device.

In addition, in order to improve the performance of the display device, various studies on enlargement, thickness reduction, weight reduction, high resolution, and low power consumption are continuously being conducted.

In particular, in the display panel constituting the display device, a display region in which sub-pixels defined by a plurality of gate lines and data lines are arranged in a matrix structure, and signal lines for supplying signals to gate lines and data lines of the display region are arranged. It consists of a non-display area.

Recently, in order to reduce manufacturing cost and simplify a process, a GIP (Gant On Panel) structure display device in which a gate driving circuit for supplying a scan signal (gate signal) is directly mounted on a display panel has been developed.

However, the GIP structure display device has a problem in that it is difficult to implement a narrow bezel in the display device because the non-display area of the display panel increases.

Therefore, it is required to develop a narrow bezel display device that meets the needs of consumers while having the advantages of the conventional GIP structure display device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of maximally securing a display area for displaying an image by arranging a driving circuit of a display panel in a display area, and a method of driving the same.

Another object of the present invention is to provide a display device capable of realizing a narrow bezel by minimizing a non-display area of a display panel and a driving method thereof.

Another object to be solved by the present invention is to provide a display device and a driving method thereof in which the output reliability of the scan signal is improved by preventing the Q node of the gate driving unit from floating in the entire section where the scan signal is output.

Another object of the present invention is to provide a display device capable of displaying an image and touch driving by preventing the Q node of a gate driver from being in a floating state, and a driving method thereof.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an embodiment of the present invention includes: a display panel including a display area in which a plurality of sub-pixels are disposed along rows and columns; a plurality of data lines arranged one for each column of a pair of sub-pixels arranged in the display area and supplying data voltages to sub-pixels arranged in both sub-pixel columns, respectively; a plurality of gate lines arranged one for each row of sub-pixels arranged in the display area and supplying scan signals to sub-pixels arranged in rows of each sub-pixel; a plurality of gate drivers disposed one for each gate line disposed in the display area and configured to generate a scan signal supplied by each gate line to sub-pixels; and a plurality of signal lines alternately arranged in units of each sub-pixel column with the plurality of data lines and supplying signals for an operation of the gate driver, wherein the gate driver includes a plurality of gate drivers, and each gate driver is disposed in the display area so as to correspond to a constant number of consecutive sub-pixel columns and supplies a scan signal to the corresponding gate line.

A method of driving a display device according to another embodiment of the present invention is a display device including a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels are disposed along rows and columns, wherein the plurality of gates supplying a scan signal to a gate driver disposed in a display area of the display panel from a previous (n-1 th) gate line among the lines; increasing the voltage level of the Q node of the gate driver by the supplied scan signal; outputting a first clock signal as a scan signal to a current (n-th) gate line in response to the increased Q node voltage; dropping the Q node of the gate driver to a gate low voltage in response to a second clock signal; and supplying and maintaining a gate-low voltage to a current (n-th) gate line in response to the Q-node voltage whose voltage level is lowered.

The details of other embodiments are included in the detailed description and drawings.

According to the present invention, the display area for displaying an image can be secured as much as possible by disposing the driving circuit of the display panel in the display area.

The present invention has the effect of realizing a narrow bezel by minimizing the non-display area of the display panel.

The present invention has the effect of improving the output reliability of the scan signal by preventing the Q node of the gate driver from floating in the entire section in which the scan signal is output.

The present invention has the effect of enabling image display and touch driving by preventing the Q node of the gate driver from being in a floating state.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram illustrating a display device according to embodiments of the present invention.
2 and 3 are diagrams illustrating a structure of a sub-pixel of a display panel according to embodiments of the present invention.
4 is a block diagram illustrating a schematic configuration of a display panel according to embodiments of the present invention.
5 is a diagram illustrating a structure in which a gate driver is disposed in a display area of a display panel according to the first embodiment of the present invention.
6 is a waveform diagram illustrating a process in which a scan signal is generated from a gate driver according to the embodiment of FIG. 5 .
7 is a block diagram illustrating a schematic configuration of a display panel according to another exemplary embodiment of the present invention.
8 is a diagram illustrating a structure in which a gate driver is disposed in a display area of a display panel according to a second exemplary embodiment of the present invention.
9 is a waveform diagram illustrating a process in which a scan signal is generated from a gate driver according to the embodiment of FIG. 8 .
10 is a diagram illustrating a structure in which a gate driver is disposed in a display area of a display panel according to a third exemplary embodiment of the present invention.
11 is a waveform diagram for explaining a process of generating a scan signal from a gate driver according to the embodiment of FIG. 10 .
12A to 15B are diagrams for explaining a process in which a scan signal is generated by the gate driver and then supplied to the gate line according to the third embodiment of the present invention.
16 is a flowchart illustrating a method of driving a display device according to embodiments of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in a singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of two parts is described as 'on', 'on', 'on', 'on the side', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used. Also, for example, when the positional relationship of the two parts is described as 'on', it may be described with positions such as 'on the top', 'on the bottom', and 'on the side'.

When an element or layer is referred to as "on" another element or layer, it includes all cases with another layer or other element interposed therebetween or directly on the other element.

Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, the present invention will be described with reference to the drawings.

1 is a block diagram illustrating a display device according to embodiments of the present invention. 2 and 3 are diagrams illustrating a structure of a sub-pixel of a display panel according to embodiments of the present invention.

1 to 3 , the display device 100 of the present invention includes a display panel 110 having a pixel array formed thereon, and a display panel driving circuit for writing input image data to the display panel 110 . do. The display panel driving circuit writes input image data into pixels composed of sub-pixels. The display panel driving circuit includes a data driving circuit 120 , a gate driving circuit 130 , and a controller 150 .

Here, the data driving circuit 120 is also called a data driver or a source driver, and the gate driving circuit 130 is also called a gate driver or a scan driver. Also, the controller 150 may be a timing controller used in a conventional display technology or a control device that further performs other control functions including a timing controller.

The display panel 110 may be a liquid crystal display panel including an upper substrate and a lower substrate facing each other with a liquid crystal layer interposed therebetween. Also, it may be an organic light emitting display panel in which an organic light emitting diode (OLED) is disposed in each sub-pixel.

A pixel array on which an input image is displayed is formed in the active area of the display panel 110 . The pixel array includes sub-pixels arranged in a matrix form by a cross structure of a plurality of data lines DL and a plurality of gate lines GL.

Here, a direction parallel to the gate line GL of the display panel 110 is defined as an X direction (or a first direction) and a direction parallel to the data line DL is defined as a Y direction (or a second direction). Accordingly, the X direction may be referred to as a horizontal direction and the Y direction may be referred to as a vertical direction.

When the display panel is a display panel used in a liquid crystal display, each of the pixels is sub-pixels or red (R) in which red (R), green (G), and blue (B) color filter layers are disposed to realize color. , green (G), blue (B), and white (W) color filter layers may be disposed in sub-pixels. Here, the white (W) color filter layer may be a layer implemented only with a transparent insulating layer without forming a separate color filter layer.

Referring to FIG. 2 , on the lower substrate of the display panel 110 , a plurality of data lines DL, a plurality of gate lines GL, and thin film transistors (TRs) disposed in regions corresponding to each sub-pixel are provided. , a pixel electrode connected to the thin film transistor (TR), a storage capacitor (Cst) connected to the pixel electrode, and a common electrode (Vcom) that forms an electric field to control the transmittance of the liquid crystal together with the pixel electrode. have.

When the display panel 110 is a liquid crystal display device, the thin film transistor TR is turned on in response to a scan signal (gate signal) to supply the data voltage supplied from the data line DL to the pixel electrode. The pixel electrode generates an electric field between the common electrode Vcom and rotates liquid crystal molecules of the liquid crystal layer to adjust transmittance of a light source (a light source of a backlight unit, not shown) supplied from the outside of the display panel 110 .

In addition, when the display panel is a display panel used in an organic light emitting display device, red (R), green (G), and blue (B) organic light emitting diodes (OLEDs) are disposed in each sub-pixel or in each sub-pixel. A blue (B) or white (W) organic light emitting layer may be disposed, and red (R), green (G), and blue (B) color filter layers may be disposed in corresponding regions.

Referring to FIG. 3 , each sub-pixel SP of the organic light emitting diode display is connected to the organic light emitting diode OLED, the data line DL, and the gate line GL to control the organic light emitting diode OLED. and a pixel circuit unit. The pixel circuit unit may include a switching transistor TR1 , a driving transistor TR2 , and a storage capacitor Cst.

An anode electrode of the organic light emitting diode OLED is connected to the driving transistor TR2 , and a cathode electrode of the organic light emitting diode OLED is connected to the second power source ELVSS. Here, the second power supply ELVSS may be a low voltage power supply. The switching transistor TR1 is turned on when the scan signal is supplied through the gate line GL and transfers the data signal supplied from the data line DL to the storage capacitor Cst.

One terminal of the storage capacitor Cst is connected to the gate electrode of the driving transistor TR2 and the drain electrode of the switching transistor TR1 , and the other terminal is connected to the source electrode of the driving transistor TR2 . Also, the source electrode of the driving transistor TR2 is connected to the first power source ELVDD having a relatively higher voltage level than that of the second power source ELVSS.

Accordingly, the amount of light generated from the organic light emitting diode OLED is controlled by controlling the current supply from the driving transistor TR2 to the organic light emitting diode OLED according to the data voltage stored in the storage capacitor Cst.

Although a relatively simple structure constituting the pixel circuit unit of the sub-pixel is exemplified in FIG. 3 , the configuration of the pixel circuit unit may be variously changed according to a driving method required by the display device.

The gate driving circuit of the present invention can be applied even when the display panel 110 is a panel used in a liquid crystal display device or a panel used in an organic light emitting display device. Here, the case where the display panel 110 is a display panel used in a liquid crystal display will be mainly described.

TFTs disposed in each sub-pixel (SP) region of the display panel 110 are amorphous silicon (a-Si) TFT, crystalline silicon TFT, LTPS (Low Temperature Poly Silicon) TFT, oxide TFT (Oxide TFT), etc. can be implemented as

A color filter array including a black matrix (BM) and a color filter may be formed on the upper substrate of the display panel 110 . However, since this is not fixed, a color filter array can be formed on the lower substrate on which the TFTs are formed.

In the present invention, in-plane switching mode (IPS mode) or fringe field mode (FFS mode), which is a horizontal electric field driving method in which a pixel electrode and a common electrode are disposed together in a sub-pixel (SP), is mainly described, but the common electrode is a TN ( In the case of a vertical electric field driving method such as a Twisted Nematic mode and a VA (Vertical Alignment) mode, it may be formed on the upper substrate.

In addition, a polarizing plate may be attached to each of the upper and lower substrates of the display panel 110 , and an alignment layer for setting a pre-tilt angle of the liquid crystal may be formed.

In addition, the touch sensors may be disposed on the display panel 110 as an on-cell type or an add-on type. In order to drive such a touch sensor, a touch sensor driving circuit (not shown) may be added to the driving circuit of the display device 100 .

The touch sensor driving circuit may receive an output signal of the touch sensor, generate coordinates of each of the touch inputs, and transmit the generated coordinates to a host system (not shown). In particular, when the touch sensor is an on-cell type embedded in the display panel 110 , a common electrode disposed on the display panel 110 may be used as the touch electrode.

The display device of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required.

The backlight unit is disposed under the display panel 110 to uniformly irradiate light to the display panel 110 . The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

In addition, the display panel 110 may further include a gamma compensation voltage generator (not shown) for supplying the gamma reference voltage GMA to the data driving circuit 120 as a driving circuit of the display panel 110 . The gamma reference voltage GMA may be divided into a positive gamma compensation voltage and a negative gamma compensation voltage in the data driving circuit 120 to be supplied to the display panel 110 . More specifically, the voltage divided into the positive gamma compensation voltage and the negative gamma compensation voltage is a multiplexer (MUX) disposed in the data driving circuit 120 or between the data driving circuit 120 and the display panel 110 ( (not shown) may be supplied to the plurality of data lines DL.

In general, the positive data voltage is supplied to the plurality of data lines DL through a multiplexer. The positive data voltage supplied to the plurality of data lines DL is higher than the common voltage Vcom applied to the common electrode, and the negative data voltage is lower than the common voltage Vcom.

The data driving circuit 120 may include one or more source drive ICs (SICs). Each source driver IC may include a plurality of channels, and the number of source driver ICs disposed in the data driving circuit 120 may be determined according to the resolution of the display panel 110 .

For example, in the case of an 8k 120Hz model among high-resolution TV models (the number of sub-pixels is 7680*3*4320), the source drive IC has 1920 channels and the data drive circuit 120 has 24 source drive ICs. can be placed.

The gate driving circuit 130 supplies a scan signal (gate signal) to the plurality of gate lines GL under the control of the controller 150 .

The controller 150 transmits input image data received from a host system (not shown) disposed inside or outside the display device 100 to the data driving circuit 120 . The controller 150 receives timing signals synchronized with input image data from the host system.

The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock DCLK. The controller 150 controls operation timings of the data driving circuit 120 and the gate driving circuit 130 based on the timing signals Vsync, Hsync, DE, and DCLK.

The gate control signal is generated by the controller 150 to control the operation timing of the gate driving circuit 130 . The gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP controls the start operation timing of the gate driving circuit 130 . The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driving circuit 130 .

The source control signal is generated by the controller 150 to control the operation timing of the data driving circuit 120 . The source control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE).

The source start pulse SSP controls the data sampling start timing of the data driving circuit 120 . The source sampling clock SSC is a clock signal that controls the data sampling timing of the data driving circuit 120 . The polarity control signal POL controls the polarity of the data voltage output from the data driving circuit 120 . The source output enable signal SOE controls charge sharing timing and data output timing. The controller 150 transmits the gate control signal and the source control signal through separate wires, or codes information about the on/off (or high/low) level of each of the signals into the control data packet and inputs it. It can be serially transmitted to the source drive ICs along with the image data.

The controller 150 increases the frame rate to a frequency of the input image frame rate (frame rate or frame frequency)×N (N is a positive integer greater than or equal to 2) Hz to multiply the driving frequency of the display panel 110 by N times. rate can be controlled. The frame rate is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme. Recently, there is a trend to adopt a method of increasing the frame rate to 120 Hz or higher to realize high-resolution images such as UHD.

In addition, when the data of the input image is hardly changed or when the data of the input image is a still image, the controller 150 drives the display panel driving circuit at a low speed to reduce power consumption to lower the update frequency of data written to the pixels. For example, the timing controller 150 may lower the frame rate to 30 Hz or less in the low-speed driving mode. The frame rate of the low-speed driving mode may be referred to as a low refresh rate (LRR).

The controller 150 is a TV system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a phone system (Phone system), a mobile device, a host system for controlling the entire wearable device, etc. Timing signals Vsync, Hsync, DE, and CLK are transmitted together with digital video data RGB of an image from (not shown). Such a host system may execute an application program in association with coordinate information of a touch input input from a touch sensor driving circuit disposed in the display device 100 .

It is defined as a region where the data line DL and the gate line GL intersect, and in the sub-pixel SP, a thin film transistor TR, a liquid crystal capacitor Clc, a storage capacitor Cst, etc. serving as a switching element are included. include

In the present invention, the gate driving circuit 130 for supplying the scan signal to the gate line GL is disposed between the sub-pixels of the display panel 110 to reduce or remove the non-display area to realize a narrow bezel. . In particular, in the present invention, by disposing a plurality of gate drivers constituting the gate driving circuit 130 between sub-pixel rows of the display area, the problem of increasing the non-display area due to the conventional gate in panel (GIP) structure is improved. .

As described above, the present invention has the effect of maximally securing the display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of realizing a narrow bezel by minimizing the non-display area of the display panel.

The present invention has the effect of improving the output reliability of the scan signal by preventing the Q node of the gate driver from floating in the entire section in which the scan signal is output.

The present invention has the effect of enabling image display and touch driving by preventing the Q node of the gate driver from being in a floating state.

4 is a block diagram illustrating a schematic configuration of a display panel according to embodiments of the present invention. 5 is a diagram illustrating a structure in which a gate driver is disposed in a display area of a display panel according to the first embodiment of the present invention. 6 is a waveform diagram illustrating a process in which a scan signal is generated from a gate driver according to the embodiment of FIG. 5 .

Referring to FIG. 4 together with FIG. 1 , the display device 100 of the present invention includes a display panel 110 , a gate driving circuit 130 , and a data driving circuit 120 . In addition, in the display device 100 of the present invention, unlike the conventional display panel 110 in which the gate driving circuit 130 is disposed in the non-display area, the gate driving circuit 130 is disposed in the display area, so that a separate non-display area is provided. The area is not separated. That is, in the conventional gate driving circuit (GIP structure) disposed in the non-display area of the display panel 110, each of the gate lines G(1), G(2), ..., G(n)) area (n is positive integers).

The gate driving circuit 130 of the present invention includes a plurality of gate driving units GDP for supplying a scan signal to each gate line GL, and these driving units GDP include respective gate lines G(1), It is arranged to correspond to G(2), ..., G(n)). Accordingly, when the number of gate lines G(1), G(2), ..., G(n) is n, the number of gate drivers GDP may also be n.

Each gate driver GDP again includes a plurality of gate drivers 131 , and the plurality of gate drivers 131 disposed in each gate driver GDP generate the same scan signal. That is, the gate drivers 131 constituting the gate driver GDP generate the same scan signal supplied to the gate line GL corresponding to the gate driver GDP.

4 , a gate driver GDP is disposed on each of the gate lines G(1), G(2), ..., G(n), and a plurality of gate drivers constituting each gate driver GDP The gate drivers 131 are respectively connected to the gate line GL corresponding to the gate driver GDP.

Accordingly, one gate driver GDP corresponds to one gate line GL, and the plurality of gate drivers 131 disposed in the gate driver GDP corresponds to one gate line corresponding to the gate driver GDP. The same scan signal is supplied to (GL). For example, the n-th gate driver GDP is disposed on the n-th gate line G(n) of the present invention, and the gate drivers 131 disposed in the n-th gate driver GDP include the n-th gate. The nth scan signal is supplied to the line G(n).

In addition, it is preferable that at least one gate driver 131 disposed in the gate driver GDP of the present invention is disposed. This is because, as the size of the display panel 110 increases, the length of the gate line GL also increases, resulting in a delay in the supplied scan signal. For example, when the gate driver 131 disposed in the gate driver GDP is disposed only at one edge of the gate line GL, when the scan signal is supplied to the other edge area of the gate line GL, the signal delay is increased. occurs Also, when the gate driver 131 is disposed only in the central region of the gate line GL, a signal delay may occur when the scan signal is supplied to both edge regions of the gate line GL.

Accordingly, it is preferable that a plurality of gate drivers 131 disposed in the gate driver GDP of the present invention are disposed at a predetermined interval along the gate line GL. However, if the number of gate drivers 131 is too large, the area of the non-display area in the display area increases. In consideration of this point, in the present invention, the number of gate drivers 131 is preferably arranged in a range in which a delay of the scan signal does not occur, and the display panel (110) shows a uniform load over the entire area of the display panel (110). The number of gate drivers 131 disposed per arbitrary unit area of 110 is preferably the same.

As shown in the drawing, a separate non-display area is not defined in the display panel 110 of the present invention. Although not shown in the drawing, regions in which the plurality of gate lines G(1), G(2), ..., G(n) are disposed are intersected by the data lines DL, and the gate lines GL and An area where the data lines DL intersect corresponds to a display area in which a plurality of sub-pixels are disposed. Accordingly, in the display device 100 of the present invention, the non-display area in which the gate driver is disposed in the conventional GIP structure can be removed or minimized, so that the area of the display area can be increased. As described above, when the non-display area is removed or reduced in the display panel 110 , the bezel area can be reduced, thereby realizing a narrow bezel.

Referring to FIGS. 5 and 6 together with FIG. 1 , the structure of the sub-pixels SP disposed in the display panel 110 of the present invention is as follows.

In the display panel 110 of the present invention, a plurality of sub-pixels SP are disposed along rows and columns. A plurality of gate lines G(n-1), G(n), G(n+1), and G(n+2) are disposed in a first direction, and a plurality of data lines D1, D2, ...., D12 and a plurality of signal lines are disposed to define the sub-pixel SP. In the present invention, one pair of sub-pixels is disposed in each column of the display panel 110, and a plurality of data lines D1, D2, ..., D12 are disposed on both sides of the pair of sub-pixels to form a pair of sub-pixels. Provides data voltage.

In addition, the plurality of gate lines G(n-1), G(n), G(n+1), and G(n+2) are disposed one by one for each row of sub-pixels disposed on the display panel 110 . A scan signal is supplied to sub-pixels arranged in a row of each sub-pixel.

The display panel 110 of the present invention is a gate driving circuit that supplies a scan signal to a plurality of gate lines G(n-1), G(n), G(n+1), and G(n+2). Reference numeral 130 is disposed in the display area in which the sub-pixels SP are disposed. A plurality of gate drivers GDP constituting the gate driving circuit 130 is disposed one for each gate line.

In addition, in the present invention, a plurality of signals are supplied so that the gate driver GDP can generate a scan signal, and the plurality of signals are arranged in parallel with the data lines D1, D2, ..., D12. arranged in two directions) is supplied through a plurality of signal lines. The plurality of signal lines are carry signal lines Carry1, Carry2, ... for supplying carry signals related to the initial operation of the gate drivers 131 disposed in the gate driver GDP, clock signals of different phases. A gate low voltage supplied to maintain a low voltage on the clock signal lines CLKA, CLKB, ..., and the gate line GL or to maintain the Q node of the gate driver 131 at a low voltage. It includes lines VGL1, VGL2, ... and common voltage lines VCOM1, VCOM2, ... for supplying a common voltage to each sub-pixel SP.

The signal lines of the present invention may be disposed between the data lines DL disposed on both sides of a pair of sub-pixels, respectively, in the row direction. Also, signal lines may be disposed between a pair of consecutive sub-pixels. As shown in the figure, the data lines D1, D2, ..., D12 are respectively arranged in units of a pair of sub-pixels SP along the row direction, and each of the plurality of signal lines is the data line D1, D2 , ...., D12) and disposed between a pair of sub-pixels defined by two data lines. The plurality of signal lines include carry signal lines Carry1, Carry2, ..., clock signal lines CLKA, CLKB, ..., gate row voltage lines VGL1, VGL2, ..., and common voltage lines VCOM1, VCOM2, ...), which are preferably alternately arranged in units of sub-pixel columns along the row direction with the data lines D1, D2, ..., D12.

Each gate driver 131 constituting the gate driver GDP of the present invention corresponds to a predetermined number of sub-pixel column units arranged in a sub-pixel row of the corresponding gate line GL. 5 , the gate driver 131 of the gate driver GDP includes first to fourth switching elements T1 , T2 , T3 , and T4 . For example, the n-th gate driver GDP is disposed on the n-th gate line GL(n), and the gate driver 131 of the n-th gate driver GDP includes the first to fourth switching elements T1, T2, T3, T4).

That is, one gate driver 131 disposed in the gate driver GDP of the present invention is implemented with four transistors. As shown in the drawing, the first gate driver 131 of the n-th gate driver GDP has a width corresponding to the first to twelfth data lines D1 , D2 , ..., D12 . In other words, in one gate driver 131 , the first to fourth switching elements T1 , T2 , T3 , and T4 are connected to each other in a region corresponding to 22 sub-pixels SP consecutive in the first direction. A circuit that generates a scan signal is constructed.

The gate driver 131 uses the gate terminal of the second switching element T2 as a Q node, and the Q node is commonly connected to the drain terminal of the first switching element T1 and the drain terminal of the third switching element T3. do. More specifically, the gate terminal and the source terminal of the first switching element T1 are commonly connected to the previous ((n-1)-th) gate line, and the drain terminal is the gate terminal Q of the second switching element T2. node) is connected.

The gate terminal of the second switching element T2 is commonly connected to the Q node, the drain terminal of the first switching element T1, and the drain terminal of the third switching element T3, and the source terminal is connected to the first clock signal line ( CLKA), and the drain terminal is connected to the current ((n)th) gate line GL(n).

The gate terminal of the third switching element T3 is commonly connected to the gate terminal of the fourth switching element T4 and the (n+2)-th gate line GL(n+2), and the source terminal is connected to the first gate It is connected to the low voltage line VGL1, and the drain terminal is connected to the Q node.

The gate terminal of the fourth switching element T4 is commonly connected to the gate terminal of the third switching element T3 and the (n+2)-th gate line GL(n+2), and the source terminal is connected to the second It is connected to the gate row voltage line VGL2, and the drain terminal is connected to the current (n)th gate line GL(n).

A method of driving the gate driver 131 of the present invention will be described with reference to FIG. 6 as follows.

In the gate driver 131 disposed in the n-th gate driver GDP, first, the first switching element T1 receives a carry signal from the previous stage ((n-1)-th) gate line G(n-1). It is supplied and turned on. At this time, the carry signal is a scan signal of the previous ((n-1)-th) gate line G(n-1). If it is the gate driver 131 of the first gate driver GDP, the previous gate line ( GL) does not exist, so it can be turned on by receiving a carry signal from the carry signal line.

As such, when the first switching element T1 is turned on, the voltage level of the Q node rises to a high level by the scan signal of the previous ((n-1)-th) gate line G(n-1). . As the Q node voltage level rises to a high level, the first switching element T1 is turned on.

When the voltage level of the Q node is increased by the scan signal, the voltage level of the scan signal supplied from the previous stage ((n-1)th) gate line G(n-1) to the first switching element T1 is As the low level is reached, the first switching element T1 is turned off. At this time, the first clock signal CLKA is supplied from the clock signal line connected to the source terminal of the second switching element T2, and the source terminal of the second switching element T2 corresponds to the clock signal CLKA at a low voltage level. When it rises to a high voltage level, the first clock signal CLKA is supplied in the form of a scan signal to the current ((n)th) gate line G(n) while the voltage level of the Q node is further increased due to the bootstrap effect. .

Accordingly, when the Q node is at the high level, the gate driver 131 pulls up the first clock signal CLKA to the current (n)th gate line G(n) to supply the scan signal.

Then, in a period in which both the first and second clock signals CLKA and CLKB are at low levels, the voltage of the Q node maintains a high level in which the voltage level is slightly lowered, and the first clock signal CLKA is at a low level. Therefore, the first clock signal CLKA of a low level is supplied to the current ((n)th) gate line G(n). At this time, the gate terminals of the third and fourth switching elements T3 and T4 receive a scan signal from the commonly connected (n+2)-th gate line G(n+2) and are turned on. . That is, in response to the scan signal of the (n+2)-th gate line G(n+2), the third and fourth switching elements T3 and T4 are turned on, and the Q node has the first gate low A gate-low voltage is supplied from the voltage line VGL1.

Also, a gate-row voltage is supplied from the second gate-row voltage line VGL2 to the current ((n)-th) gate line G(n). Accordingly, as shown in the figure, when the Q node falls to a low level and the first and second clock signals CLKA and CLKB are in a low state, the current ((n)th) gate line G(n) ) is supplied with a gate-low voltage.

In the subsequent section, since the previous ((n-1)-th) gate line G(n-1) is at a low level, the first switching element T1 maintains a turn-off state, and the (n+2)-th gate Since the line G(n+2) is also in a low level state, the third and fourth switching elements T3 and T4 are turned off.

That is, the Q node is in a floating state that is not electrically connected to other switching elements and signal lines connected to it, and the current ((n)-th) gate line G(n) is also the fourth switching element ( Since T4) is in the turned-off state, it becomes a floating state and the previously supplied signal is maintained.

As described above, the conventional gate driver (referred to as a shift register or stage) pulls up or pulls down a control circuit composed of many switching elements and clock signals to control the voltages of the Q node and the QB node, and then supplies them to the gate line GL. However, in the present invention, the gate driver is implemented with four switching elements and the area occupied by the gate driver can be reduced.

As described above, the present invention has the effect of maximally securing the display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of realizing a narrow bezel by minimizing the non-display area of the display panel.

7 is a block diagram illustrating a schematic configuration of a display panel according to another exemplary embodiment of the present invention.

FIG. 7 relates to another embodiment of the arrangement structure of the gate driving circuit of FIG. 4 , and will be mainly described below with reference to parts distinguished from FIG. 4 .

Referring to FIG. 7 together with FIG. 1 , the gate driving circuit 130 of the present invention includes a plurality of gate driving units GDP supplying a scan signal to each gate line GL and a blank region 132 . Accordingly, one gate driver GDP includes a plurality of gate drivers 131 and a plurality of blank regions 132 . The gate driver GDP is disposed to correspond to each of the gate lines G(1), G(2), ..., G(n), respectively. Accordingly, when the number of gate lines G(1), G(2), ..., G(n) is n, the number of gate drivers GDP may also be n.

In particular, in FIG. 7 , unlike FIG. 4 , the gate drivers 131 constituting the gate driver GDP are not sequentially arranged in units of a predetermined number of successive sub-pixels, but the gate driver 131 and the blank region 132 . are alternately placed. Accordingly, the number of gate drivers 131 disposed to correspond to each gate line G(n) is reduced compared to FIG. 4 .

For example, the gate drivers of the N-th gate driver GDP corresponding to the N-th gate line are spaced apart from each other by a predetermined number of consecutive sub-pixel columns corresponding to the gate driver 131 . A blank area BA: 132 is disposed between the gate drivers 131 , and an area occupied by the blank area BA: 132 may be the same as that of the gate driver 131 . In addition, the gate drivers 131 of the gate driver corresponding to the (N+1)-th gate line G(n+1) are above and below the gate driver disposed to correspond to the N-th gate line G(n). directions (second direction or data line direction) so as not to overlap each other.

7, the gate driver 131 and the blank region 132 are alternately disposed in the gate driver GDP of the first gate line G(1), and the second gate line (G(1)) The gate driver 131 of the gate driver GDP of G(2) does not overlap with the gate driver of the first gate line G(1). Similarly, the gate drivers 131 corresponding to the third gate line GL( 3 ) do not overlap with the gate drivers 131 corresponding to the second gate line GL( 2 ). Although it has been previously said that gate drivers disposed in adjacent gate drivers GDP with respect to the gate driver 131 do not overlap each other, the blank region 132 also does not overlap each other in the same way.

As described above, in the present invention, the blank region 132 may be disposed in order to reduce the number of the plurality of gate drivers 131 disposed in each gate driver GDP. Therefore, in the embodiment of FIG. 4 , ten gate drivers 131 are arranged in one gate driver GDP, in the embodiment of FIG. 7 , five gate drivers 131 are arranged in one gate driver GDP. do.

7 exemplifies another embodiment, and in some cases, the number of blank regions between the gate drivers may be at least one. The number of gate drivers disposed in the gate driver GDP may be variously adjusted in consideration of the overall load uniformity of the display panel 110 .

A separate non-display area is not defined in the display panel 110 of the present invention. Although not shown in the drawing, regions in which the plurality of gate lines G(1), G(2), ..., G(n) are disposed are intersected by the data lines DL, and the gate lines GL and An area where the data lines DL intersect corresponds to a display area in which a plurality of sub-pixels are disposed.

Accordingly, in the display device 100 of the present invention, the non-display area in which the gate driver is disposed in the conventional GIP structure can be removed or minimized, so that the area of the display area can be increased. As described above, when the non-display area is removed or reduced in the display panel 110 , the bezel area can be reduced, thereby realizing a narrow bezel.

8 is a diagram illustrating a structure in which a gate driver is disposed in a display area of a display panel according to a second exemplary embodiment of the present invention. 9 is a waveform diagram illustrating a process in which a scan signal is generated from a gate driver according to the embodiment of FIG. 8 .

8 and 9 relate to another embodiment of FIGS. 5 and 6 , and the following description will be focused on parts distinct from FIGS. 5 and 6 .

Referring to FIGS. 8 and 9 together with FIG. 1 , the structure of the sub-pixels SP disposed in the display panel 110 of the present invention is as follows.

The gate driver GDP disposed on the display panel 110 of the present invention includes a plurality of gate drivers 231 . The gate driver 231 includes first to fourth switching elements T1 , T2 , T3 , and T4 .

The gate driver 231 uses the gate terminal of the second switching element T2 as a Q node, and the Q node is commonly connected to the drain terminal of the first switching element T1 and the drain terminal of the third switching element T3. do. More specifically, the gate terminal and the source terminal of the first switching element T1 are commonly connected to the previous ((n-1)-th) gate line, and the drain terminal is the gate terminal Q of the second switching element T2. node) is connected.

The gate terminal of the second switching element T2 is commonly connected to the Q node, the drain terminal of the first switching element T1, and the drain terminal of the third switching element T3, and the source terminal is connected to the first clock signal line ( CLKA), and the drain terminal is connected to the current ((n)th) gate line GL(n).

The gate terminal of the third switching element T3 is commonly connected to the gate terminal of the fourth switching element T4 and the (n+2)-th gate line GL(n+2), and the source terminal is connected to the first gate It is connected to the low voltage line VGL1, and the drain terminal is connected to the Q node.

The gate terminal of the fourth switching element T4 is connected to the second clock signal line CLKB, the source terminal is connected to the second gate-low voltage line VGL2, and the drain terminal is the current ((n)th) gate. It is connected to the line GL(n).

A method of driving the gate driver 131 of the present invention will be described with reference to FIG. 9 as follows.

In the gate driver 131 disposed in the n-th gate driver GDP, first, the first switching element T1 receives a carry signal from the previous stage ((n-1)-th) gate line G(n). turn-on At this time, the carry signal is a scan signal of the previous ((n-1)-th) gate line G(n-1). If it is the gate driver 131 of the first gate driver GDP, the previous gate line ( GL) does not exist, so it can be turned on by receiving a carry signal from the carry signal line.

As such, when the first switching element T1 is turned on, the voltage level of the Q node rises to a high level by the scan signal of the previous ((n-1)-th) gate line G(n-1). . As the Q node voltage level rises to a high level, the first switching element T1 is turned on.

When the voltage level of the Q node is increased by the scan signal, the voltage level of the scan signal supplied from the previous stage ((n-1)th) gate line G(n-1) to the first switching element T1 is As the low level is reached, the first switching element T1 is turned off. At this time, the first clock signal CLKA is supplied from the clock signal line connected to the source terminal of the second switching element T2, and the source terminal of the second switching element T2 corresponds to the clock signal CLKA at a low voltage level. When it rises to a high voltage level, the first clock signal CLKA is supplied in the form of a scan signal to the current ((n)th) gate line G(n) while the voltage level of the Q node is further increased due to the bootstrap effect. .

Accordingly, when the Q node is at the high level, the gate driver 131 pulls up the first clock signal CLKA to the current (n)th gate line G(n) to supply the scan signal.

Then, in a period in which both the first and second clock signals CLKA and CLKB are at low levels, the voltage of the Q node maintains a high level in which the voltage level is slightly lowered, and the first clock signal CLKA is at a low level. Therefore, the first clock signal CLKA of a low level is supplied to the current ((n)th) gate line G(n). At this time, the gate terminal of the third switching element T3 is connected to the (n+2)-th gate line G(n+2), and the gate terminal of the fourth switching element T4 is connected to the second clock signal line ( CLKB), so that the third and fourth switching elements T3 and T4 are both turned on. That is, the third switching element T3 responds to the scan signal of the (n+2)-th gate line G(n+2), and the fourth switching element T4 responds to the second clock signal CLKB. to turn-on state.

Accordingly, in the period in which the scan signal of the (n+2)-th gate line G(n+2) is supplied to the third switching element T3, the Q node is the gate supplied from the first gate-low voltage line VGL1. A low level state is generated by the low voltage. In addition, in the period in which the second clock signal CLKB is supplied to the fourth switching element T4, the gate row voltage supplied from the second gate row voltage line VGL2 is the current ((n)th) gate line G( n)).

In the subsequent section, since the previous ((n-1)-th) gate line G(n-1) is at a low level, the first switching element T1 maintains a turn-off state, and the (n+2)-th gate Since the line G(n+2) is also in a low level state, the third switching element T3 is turned off. Also, since the second clock signal CLKB is in the low level state, the fourth switching element T4 is also turned off.

That is, the Q node is in a floating state that is not electrically connected to other switching elements and signal lines connected to it, and the current ((n)-th) gate line G(n) is also the fourth switching element ( Since T4) is in the turned-off state, it becomes a floating state and the previously supplied signal is maintained.

As shown in FIG. 9 , in section A after the scan signal is output from the current ((n)-th) gate line G(n), the Q node and the current ((n)-th) gate line G( n)) is in a floating state, and a gate-low voltage is supplied to the current ((n)-th) gate line G(n) in the period B in which the second clock signal CLKB is at a high level.

That is, the source terminal and the gate terminal of the first switching element T1 are connected to the (n-1)-th gate line G(n-1), and the (n-1)-th gate line G(n-) 1)) is in a low level state, but it is turned off because it is connected with the gate terminal. In addition, since the gate terminal of the third switching element T3 is connected to the (n+2)-th gate line G(n+2), the third switching element T3 is turned off in the A section.

As described above, the conventional gate driver (referred to as a shift register or stage) pulls up or pulls down a control circuit composed of many switching elements and clock signals to control the voltages of the Q node and the QB node, and then supplies them to the gate line GL. However, in the present invention, the gate driver is implemented with four switching elements and the area occupied by the gate driver can be reduced.

As described above, the present invention has the effect of maximally securing the display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of realizing a narrow bezel by minimizing the non-display area of the display panel.

10 is a diagram illustrating a structure in which a gate driver is disposed in a display area of a display panel according to a third exemplary embodiment of the present invention. 11 is a waveform diagram for explaining a process of generating a scan signal from a gate driver according to the embodiment of FIG. 10 . 12A to 15B are diagrams for explaining a process in which a scan signal is generated in the gate driver and then supplied to the gate line according to the third embodiment of the present invention. 12A to 15B show circuit operations corresponding to the hatched area of the signal waveform.

10 to 15B are modified embodiments from the first and second embodiments of the present invention, and will be mainly described below with distinguished parts.

Referring to FIGS. 10 to 15B together with FIG. 1 , the gate driving unit GDP of the present invention is connected to a plurality of signal lines to which a plurality of signals are supplied to generate a scan signal. The plurality of signals are arranged in parallel with the data lines D1, D2, ..., D12 (in the second direction, and provide carry signals for the initial operation of the gate drivers 331 ). The carry signal lines Carry1, Carry2, …, the clock signal lines CLKA, CLKB, … for supplying the clock signals CLKA, CLKB of different phases, maintain a low voltage on the gate line GL or the gate driver Gate low voltage lines (VGL1, VGL2, ...) supplied to maintain the Q node of 131 at a low voltage and common voltage lines (VCOM1, VCOM2, ...) supplying a common voltage to each sub-pixel (SP) includes

The gate driver 331 of the gate driver GDP of the present invention includes first to fourth switching elements NT1, NT2, NT3, and PT. In particular, in the third embodiment of the present invention, unlike the first and second embodiments, the first to third switching elements NT1 , NT2 and NT3 are configured of N-MOS transistors, and the fourth switching element PT is It may consist of a P-MOS transistor. Accordingly, the gate driver 331 of the third embodiment of the present invention may be implemented as a CMOS transistor.

The gate driver 331 uses the gate terminal of the second switching element NT2 as a Q node, and the Q node is the drain terminal of the first switching element NT1 , the drain terminal of the third switching element NT3 , and the fourth switching element. It is commonly connected to the gate terminal of the element PT. More specifically, the gate terminal and the source terminal of the first switching element NT1 are commonly connected to the previous ((n-1)-th) gate line, and the drain terminal is connected to the second and fourth switching elements NT2 and PT. It is commonly connected to the gate terminals of the Q node and the drain terminal of the third switching element NT3.

The gate terminal of the second switching element NT2 is commonly connected to the Q node, the drain terminal of the first switching element NT1, the drain terminal of the third switching element NT3, and the gate terminal of the fourth switching element PT. and the source terminal is connected to the first clock signal line CLKA, and the drain terminal is connected to the current ((n)th) gate line GL(n).

The gate terminal of the fourth switching element PT is connected to the Q node, the source terminal is connected to the first gate-low voltage line VGL1, and the drain terminal is the current ((n)-th) gate line GL(n). ) is connected with

A gate terminal of the third switching element NT3 is connected to the second clock signal line CLKB, a source terminal is connected to the second gate row voltage line VGL2, and a drain terminal is connected to the Q node.

A method of driving the gate driver 331 of the present invention will be described with reference to FIGS. 9 to 15B as follows.

In the gate driver 331 disposed in the n-th gate driver GDP, first, the first switching element NT1 receives a carry signal from the previous ((n-1)-th) gate line G(n-1). It is supplied and turned on. At this time, the carry signal is a scan signal of the previous ((n-1)-th) gate line G(n-1). If it is the gate driver 331 of the first gate driver GDP, the previous gate line ( GL) does not exist, so it can be turned on by receiving a carry signal from the carry signal line.

As such, when the first switching element NT1 is turned on, the voltage level of the Q node rises to a high level by the scan signal of the previous ((n-1)-th) gate line G(n-1). . As the Q node voltage level rises to a high level, the second switching element NT2 is turned on and the fourth switching element PT is a P-MOS transistor, so it is turned off. That is, as shown in FIG. 12A , when the Q node voltage becomes a high level, the drain terminal of the first switching element NT1 , the gate terminal of the second switching element NT2 , and the drain terminal of the third switching element NT3 . and the voltage of the gate terminal of the fourth switching element PT becomes a high level.

Accordingly, the first switching element NT1 is turned on, the second switching element NT2 is turned on, and the third and fourth switching elements NT3 and PT are turned off.

13A and 13B, when the voltage level of the Q node is increased by the scan signal, the first switching element NT1 from the previous ((n-1)th) gate line G(n-1) The first switching element NT1 is turned off as the voltage level of the scan signal supplied thereto becomes a low level. However, the second switching element NT2 maintains the turned-on state because the Q node maintains the high voltage. Since the Q node high voltage is maintained, the fourth switching element PT, which is a P-MOS transistor, maintains a turn-off state, and since the second clock signal CLKB is in a low state, the third switching element NT3 is The turn-off state is maintained.

At this time, the first clock signal CLKA is supplied from the clock signal line connected to the source terminal of the second switching element NT2 , and the source terminal of the second switching element NT2 has the first clock signal CLKA at a low voltage level. When it rises to a high voltage level corresponding to , the voltage level of the Q node is additionally increased due to the bootstrap effect, and the first clock signal CLKA is transmitted as a scan signal to the current ((n)th) gate line G(n). is output

In the period in which both the first and second clock signals CLKA and CLKB are at low levels, the voltage of the Q node maintains a high level in which the voltage level is slightly lowered, and since the first clock signal CLKA is at a low level, A low level first clock signal CLKA is supplied to the (n)th) gate line G(n). At this time, since the Q node is at a high level, the fourth switching element PT maintains a turn-off state, and since the second clock signal CLKB is at a low level, the third switching element NT3 also has a turn-off state. do. That is, since the Q node maintains the high level state, the second switching element NT2 maintains the turned-on state while applying the low level voltage of the first clock signal to the current ((n)th) gate line G(n). ) is supplied to

Thereafter, referring to FIGS. 14A to 15B , the scan signal of the previous ((n-1)th) gate line G(n-1) is in a low state and in response to the high state of the second clock signal CLKB. The third switching element NT3 is turned on. At this time, since the Q node is discharged to the second gate-low voltage to become a low-level voltage, the first and second switching elements NT1 and NT2 are turned off, and the fourth switching element PT is turned on. become a state As the gate row voltage is supplied to the Q node, the fourth switching element PT, which is a P-MOS transistor, is turned on in response to the current ((n)th) gate line ( A gate-low voltage is supplied to G(n)).

In the subsequent section, since the scan signal of the previous stage ((n-1)-th) gate line G(n-1) is at a low level, the first switching element NT1 maintains the turn-off state, but the Q node Since it is discharged after supplying the second clock signal CLKB, a low level voltage is maintained. In a state in which the Q node is discharged, the second switching element NT2 is turned off, but the fourth switching element PT is turned on, and thus the gate-low voltage is passed through the first gate-low voltage line VGL1. may be continuously supplied to the current ((n)th) gate line G(n).

That is, in the third embodiment of the present invention, the Q node is supplied to the current ((n)th) gate line G(n) by the operation of the fourth switching element PT which is a P-MOS transistor even in a discharged state. The gate-low voltage can be maintained.

Therefore, in the first and second embodiments of the present invention, the gate line is also in a floating state in a form in which the Q node maintains the previous supply gate-low voltage to the current ((n)-th) gate line G(n) in the floating state. On the other hand, the third embodiment of the present invention has an advantage in that the reliability of the scan signal can be increased because the Q node and the current (n)th gate line G(n) are maintained by receiving the gate-low voltage.

In particular, the in-cell touch type display device in which the touch sensor is disposed in the display panel is divided into an image display area and a touch sensing area (AIT driving area) for touch sensing. When performing touch sensing, a plurality of gate lines (GL ), a load free drive (LFD) signal such as a square wave is applied to the plurality of data lines DL and the common electrode Vcom.

Accordingly, when the gate lines are maintained at the gate-low voltage as in the third embodiment of the present invention, it is possible to operate in the touch sensing period, and it is possible to prevent a decrease in touch sensitivity due to signal distortion caused by the signals. .

As described above, the present invention has the effect of maximally securing the display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of realizing a narrow bezel by minimizing the non-display area of the display panel.

The present invention has the effect of improving the output reliability of the scan signal by preventing the Q node of the gate driver from floating in the entire section in which the scan signal is output.

The present invention has the effect of enabling image display and touch driving by preventing the Q node of the gate driver from being in a floating state.

16 is a flowchart illustrating a method of driving a display device according to embodiments of the present invention.

Referring to FIG. 16 , in the method of driving a display device of the present invention, the display device is disposed in the display area of the display panel from the previous ((n-1)-th) gate line G(n-1) among the gate lines GL. supplying a scan signal to the gate driver (S1601); increasing the voltage level of the Q node according to the operation of the first switching element of the gate driver (S1602); driving the second switching element in response to the increased Q node voltage and supplying the first clock signal to the current ((n)th) gate line G(n) to output a scan signal (S1603); driving the third switching element in response to the second clock signal to lower the Q node voltage level (S1604); and supplying and maintaining the gate-low voltage to the current ((n)-th) gate line G(n) by driving the fourth switching element by the lowered Q-node voltage ( S1605 ).

More specifically, referring to FIGS. 10 to 15B , the method of driving a display device according to the present invention includes a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels are disposed along rows and columns. A display device comprising: supplying a scan signal to a gate driver disposed in a display area of a display panel from a previous (n−1)th gate line among the plurality of gate lines; increasing the voltage level of the Q node of the gate driver by the supplied scan signal; outputting a first clock signal as a scan signal to a current (n-th) gate line in response to the increased Q node voltage; dropping the Q node of the gate driver to a gate low voltage in response to a second clock signal; and supplying and maintaining a gate-low voltage to the current (n-th) gate line in response to the Q node voltage having the voltage level dropped.

Here, the switching elements disposed in the gate driver include three N-MOS transistors and one P-mode transistor. Accordingly, the gate driver can be implemented with CMOS transistors. In detail, the gate driver 331 includes first to third switching elements NT1 , NT2 , and NT3 composed of N-mode transistors and a fourth switching element PT composed of P-MOS transistors.

As such, the gate driver 331 includes a Q node and is disposed in a conventional shift register or gate driving circuit that supplies a clock signal to the gate line, and functions as a stage to generate a gate signal (scan signal). Accordingly, since the present invention is implemented with fewer transistors than the transistors constituting the conventional shift register or stage, there is an advantage in that the load on the display panel by the gate driver 331 can be reduced.

In the gate driver 331 , the gate terminal and the source terminal of the first switching element NT1 are connected to the previous (n-1 th) gate line, the drain terminal is connected to the Q node, and the second switching element NT2 ), the gate terminal is connected to the Q node, the source terminal is connected to the clock signal line, the drain terminal is connected to the current (n-th) gate line, the third switching element NT3 has the gate terminal connected to the second switching element It is connected to a clock signal line different from the clone signal line connected to NT2, a source terminal is connected to a gate-low voltage line, a drain terminal is connected to a Q node, and the fourth switching element PT has a gate terminal connected to a Q node. is connected to, the source terminal is connected to the gate-low voltage line, and the drain terminal is connected to the current (n) gate line.

In addition, the first switching element NT1 is turned on in response to the scan signal supplied from the previous stage (n-1 th) gate line to raise the Q node to the voltage level of the supplied scan signal, and In response, the second switching element NT2 is turned on to output the first clock signal and the scan signal to the current (n-th) gate line.

The third switching element NT3 is turned on in response to the second clock signal to supply the gate-low voltage to the Q node, and as the Q node voltage falls to the gate-low voltage, the fourth switching element PT is turned- In the on state, the fourth switching element PT supplies a gate-low voltage to the current (n-th) gate line in response to the turn-on.

As described above, the present invention has the effect of maximally securing the display area for displaying an image by arranging the driving circuit of the display panel in the display area.

The present invention has the effect of realizing a narrow bezel by minimizing the non-display area of the display panel.

The present invention has the effect of improving the output reliability of the scan signal by preventing the Q node of the gate driver from floating in the entire section in which the scan signal is output.

The present invention has the effect of enabling image display and touch driving by preventing the Q node of the gate driver from being in a floating state.

An exemplary embodiment of the present invention can be described as follows.

A display device according to an embodiment of the present invention includes a display panel including a display area in which a plurality of sub-pixels are disposed along rows and columns, one for each column of a pair of sub-pixels disposed in the display area, and both sub-pixels respectively A plurality of data lines supplying data voltages to sub-pixels arranged in a pixel column, and a plurality of data lines arranged one for each sub-pixel row arranged in the display area and supplying scan signals to sub-pixels arranged in each sub-pixel row in the display area a gate line, a plurality of gate drivers disposed one for each gate line disposed in the display area and generating a scan signal supplied by each gate line to sub-pixels, and a plurality of data lines alternately in units of each sub-pixel column It may include a plurality of signal lines disposed as , and supplying signals for an operation of the gate driver.

In a display device according to another exemplary embodiment of the present invention, the gate driver includes a plurality of gate drivers, and each gate driver is disposed in the display area to correspond to a constant number of consecutive sub-pixel columns to supply scan signals to the corresponding gate lines. can

In the display device according to another embodiment of the present invention, the gate drivers constituting the gate driver may supply the same scan signal to the gate line corresponding to the gate driver.

In a display device according to another embodiment of the present invention, the plurality of signal lines includes at least one carry signal line related to the initial operation of the gate driver, at least one clock signal line for supplying clock signals of different phases, and at least one or more It may include a gate-low voltage line.

In a display device according to another embodiment of the present invention, the gate driver may include first to third switching elements including N MOS transistors and a fourth switching element including P MOS transistors.

In a display device according to another embodiment of the present invention, the gate driver includes a Q node, a gate terminal and a source terminal of the first switching element are connected to the previous (n-1 th) gate line, and a drain terminal of the first switching element is a Q node. is connected to, the second switching element has a gate terminal connected to the Q node, a source terminal connected to a clock signal line, a drain terminal connected to a current (n-th) gate line, and a gate terminal of the third switching element The second switching element is connected to a clock signal line different from the clone signal line, the source terminal is connected to the gate-low voltage line, the drain terminal is connected to the Q node, and the fourth switching element has a gate terminal connected to the Q node. , the source terminal may be connected to the gate-low voltage line, and the drain terminal may be connected to the current (n) gate line.

In the display device according to another embodiment of the present invention, each gate driver of the gate driver disposed to correspond to each gate line may be sequentially disposed to correspond to a predetermined number of consecutive sub-pixel columns.

In a display device according to another embodiment of the present invention, the gate driver includes a plurality of gate drivers and a plurality of blank regions, and the gate drivers and the blank region of the gate driver corresponding to the nth gate line among the plurality of gate lines are provided. are alternately arranged, and the gate drivers and blank regions of the gate driver corresponding to the (n+1)-th gate line do not overlap with the gate drivers and blank regions of the gate driver corresponding to the n-th gate line. It can be placed so that

A method of driving a display device according to another embodiment of the present invention is a display device including a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels are disposed along rows and columns, the plurality of gate lines supplying a scan signal to a gate driver disposed in a display area of the display panel from the previous (n-1 th) gate line; increasing the voltage level of the Q node of the gate driver by the supplied scan signal; outputting a first clock signal as a scan signal to a current (n-th) gate line in response to the increased Q node voltage; dropping the Q node of the gate driver to a gate-low voltage in response to a second clock signal; and supplying and maintaining a gate-low voltage to the current (n-th) gate line in response to the Q node voltage whose voltage level is lowered.

In a method of driving a display device according to another embodiment of the present invention, the gate driver may include first to third switching elements including N MOS transistors and a fourth switching element including P MOS transistors.

In a display device driving method according to another embodiment of the present invention, the gate driver includes a Q node, the first switching element has a gate terminal and a source terminal connected to a previous (n-1 th) gate line, and a drain terminal is connected to the Q node, the gate terminal of the second switching element is connected to the Q node, the source terminal is connected to the clock signal line, the drain terminal is connected to the current (nth) gate line, and the third switching element is A gate terminal is connected to a clock signal line different from the Clun signal line connected to the second switching element, a source terminal is connected to a gate-low voltage line, a drain terminal is connected to a Q node, and the fourth switching element has a gate terminal connected to Q node, the source terminal may be connected to the gate-low voltage line, and the drain terminal may be connected to the current (n) gate line.

In a method of driving a display device according to another embodiment of the present invention, the first switching element is turned on in response to a scan signal supplied from the previous stage (n-1 th) gate line, and the voltage of the scan signal supplied to the Q node is applied. level can be raised.

In a method of driving a display device according to another embodiment of the present invention, the second switching element is turned on in response to the increased Q node to output a first clock signal to a current (n-th) gate line and a scan signal. have.

In a method of driving a display device according to another embodiment of the present invention, the third switching element is turned on in response to a second clock signal to supply a gate-low voltage to the Q node, and the Q-node voltage is lowered to the gate-low voltage. Accordingly, the fourth switching element may be turned on.

In the method of driving a display device according to another embodiment of the present invention, the fourth switching element may supply a gate-low voltage to the current (n-th) gate line in response to turn-on.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: gate driving circuit
130: data driving circuit
150: controller
131, 231, 331: gate driver
132: blank area
GDP: Gate Driver
SP: sub-pixel

Claims (14)

a display panel including a display area in which a plurality of sub-pixels are disposed along rows and columns;
a plurality of data lines arranged one for each column of a pair of sub-pixels arranged in the display area and supplying data voltages to sub-pixels arranged in both sub-pixel columns, respectively;
a plurality of gate lines arranged one for each row of sub-pixels arranged in the display area and supplying scan signals to sub-pixels arranged in rows of each sub-pixel;
a plurality of gate drivers disposed one for each gate line disposed in the display area and configured to generate a scan signal supplied by each gate line to sub-pixels; and
and a plurality of signal lines alternately arranged in units of each sub-pixel column with the plurality of data lines and supplying signals for an operation of the gate driver;
The gate driver includes a plurality of gate drivers, and each gate driver is disposed in a display area to correspond to a predetermined number of consecutive sub-pixel columns to supply a scan signal to a corresponding gate line.
According to claim 1,
The gate drivers constituting the gate driver supply the same scan signal to a gate line corresponding to the gate driver.
According to claim 1,
The plurality of signal lines includes at least one carry signal line related to an initial operation of the gate driver, at least one clock signal line for supplying clock signals of different phases, and at least one gate row voltage line.
4. The method of claim 3,
wherein the gate driver includes first to third switching elements including N MOS transistors and a fourth switching element including P MOS transistors.
5. The method of claim 4,
The gate driver includes a Q node,
In the first switching element, a gate terminal and a source terminal are connected to the previous (n-1 th) gate line, and a drain terminal is connected to a Q node,
The second switching element has a gate terminal connected to the Q node, a source terminal connected to the first clock signal line, and a drain terminal connected to a current (n-th) gate line,
the third switching element is connected to a second clock signal line, a source terminal is connected to a gate-low voltage line, and a drain terminal is connected to a Q node;
The fourth switching element has a gate terminal connected to a Q node, a source terminal connected to a gate-low voltage line, and a drain terminal connected to a current (n) gate line.
According to claim 1,
Each gate driver of the gate driver disposed to correspond to each of the gate lines is continuously disposed to correspond to a predetermined number of consecutive sub-pixel columns.
According to claim 1,
The gate driver includes a plurality of gate drivers and a plurality of blank regions,
Gate drivers and blank regions of the gate driver corresponding to the n-th gate line among the plurality of gate lines are alternately arranged with each other,
The (n+1)-th gate line and the blank regions of the gate driver corresponding to the gate drivers and the blank regions of the gate driver corresponding to the n-th gate line are disposed so as not to overlap with each other up and down .
A display device comprising: a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels are disposed along rows and columns,
supplying a scan signal to a gate driver disposed in a display area of the display panel from a previous (n-1 th) gate line among the plurality of gate lines;
increasing the voltage level of the Q node of the gate driver by the supplied scan signal;
outputting a first clock signal as a scan signal to a current (n-th) gate line in response to the increased Q node voltage;
dropping the Q node of the gate driver to a gate low voltage in response to a second clock signal;
and supplying and maintaining a gate-low voltage to a current (n-th) gate line in response to a Q-node voltage whose voltage level is lowered.
9. The method of claim 8,
The method of claim 1, wherein the gate driver includes first to third switching elements including N MOS transistors and a fourth switching element including P MOS transistors.
10. The method of claim 9,
The gate driver includes a Q node,
In the first switching element, a gate terminal and a source terminal are connected to the previous (n-1 th) gate line, and a drain terminal is connected to a Q node,
The second switching element has a gate terminal connected to the Q node, a source terminal connected to the first clock signal line, and a drain terminal connected to a current (n-th) gate line,
The third switching element has a gate terminal connected to the second clock signal line, a source terminal connected to a gate-low voltage line, and a drain terminal connected to a Q node,
The fourth switching element has a gate terminal connected to a Q node, a source terminal connected to a gate-low voltage line, and a drain terminal connected to a current (n) gate line.
11. The method of claim 10,
The first switching element is turned on in response to a scan signal supplied from a previous stage (n-1 th) gate line to increase the Q node to a voltage level of the supplied scan signal.
11. The method of claim 10,
A method of driving a display device, wherein the second switching element is turned on in response to the increased Q node to output a first clock signal to a current (n-th) gate line and a scan signal.
11. The method of claim 10,
The third switching element is turned on in response to the second clock signal to supply the gate-low voltage to the Q node, and as the Q node voltage falls to the gate-low voltage, the fourth switching element is turned on. How to drive the device.
14. The method of claim 13,
A method of driving a display device in which the fourth switching element supplies a gate-low voltage to a current (n-th) gate line in response to turn-on.

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