KR20210083008A - Pixel array panel and method for manufacturing the same - Google Patents

Abstract

One embodiment of the present invention provides an array panel for a digital X-ray detection device comprising a plurality of pixel regions disposed in a sensing region. The array panel for a digital X-ray detection device comprises: a switching transistor corresponding to each pixel region; a first electrode disposed on a first protection film covering the switching transistor; a PIN layer disposed on the first electrode; a second electrode disposed on the PIN layer; a second protection film covering the PIN layer and the second electrode; and a planarization film disposed on the first protection film, corresponding to the sensing region, and covering the first electrode and the second protection film.

Description

Array panel for digital X-ray detection device and manufacturing method thereof

The present invention relates to an array panel provided in a digital X-ray detector (DXD) for detecting a transmission amount of X-rays (X-rays; radiation) and a method for manufacturing the same.

X-rays (radiation) are electromagnetic waves having transparency. The amount of transmission of these X-rays corresponds to the density inside the object. Accordingly, X-ray images are widely used in fields such as medical care, security and industry. In particular, X-ray images are frequently used as a basic tool for diagnosis in the medical field.

Existing X-ray images were provided by preparing a film made of a photosensitive material, exposing the film to X-rays passing through an object, and then transferring the image of the film to photo paper. In this case, there is a problem in that it is impossible to provide real-time image information due to the printing process, and there is a problem in that image information is easily lost because it is impossible to store and preserve the film for a long time.

Recently, due to the development of image processing technology and semiconductor technology, a digital X-ray detection apparatus having a flat panel structure that can replace a film has been proposed.

The digital X-ray detection device includes an array panel in the form of a flat plate. The array panel includes a plurality of photo-sensing elements corresponding to a plurality of pixel regions, and a plurality of switching transistors connected to the plurality of photo-sensing elements.

An array panel for a digital X-ray detection device includes a photo-sensing device, and the photo-sensing device includes a first electrode, a PIN layer, and a second electrode.

A method of manufacturing such an array panel for a digital X-ray detection device includes a process of arranging a first electrode, a process of arranging a PIN layer, and a process of arranging a second electrode.

Here, the process of disposing the PIN layer includes a process of patterning a semiconductor material film covering the first electrode. At this time, the semiconductor material film is in a state in which the step difference by the boundary of the first electrode is transferred. Therefore, in order to remove the step of the semiconductor material layer corresponding to the boundary of the first electrode, the patterning process of the semiconductor material layer needs to be performed with an etching intensity higher than that corresponding to the thickness of the semiconductor material layer. That is, the patterning process of the semiconductor material film is performed by over-etching.

Due to the over-etching of the semiconductor material layer, there is a problem in that the first passivation layer supporting the first electrode may be damaged.

In addition, due to over-etching of the semiconductor material layer, there is a problem that the first electrode and the PIN layer may be easily damaged.

As the first protective film, the first electrode, and the PIN layer are damaged, the photoelectric characteristics of the photo-sensing device are deteriorated, so that the reliability of the photo-sensing device is deteriorated.

In addition, there is a problem in that the uniformity of the photoelectric characteristics of the photo-sensing device is deteriorated due to the difference in the degree of damage of the first protective film, the first electrode, and the PIN layer.

Accordingly, an object of the present invention is to provide a method of manufacturing an array panel for a digital X-ray detection device capable of improving the reliability and uniformity of a light sensing device, and an array panel manufactured by the method.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned may be understood by the following description, and will be more clearly understood by the examples of the present invention. Moreover, it will be readily apparent that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

An example of the present invention is an array panel for a digital X-ray detection device including a plurality of pixel regions disposed in a sensing region, wherein a switching transistor corresponding to each pixel region and a first protective film covering the switching transistor are disposed. a first electrode, a PIN layer disposed on the first electrode, a second electrode disposed on the PIN layer, a second protective layer covering the PIN layer and the second electrode, and disposed on the first protective layer, Provided is an array panel for a digital X-ray detection device including a planarization layer corresponding to the sensing region and covering the first electrode and the second passivation layer.

As described above, according to an exemplary embodiment of the present invention, as the second passivation layer is formed through the same patterning process as that of the first electrode, the second passivation layer is disposed to cover only the PIN layer and the second electrode. Accordingly, since the side surface of the first electrode is not covered by the second passivation layer, it is in contact with the planarization layer covering the second passivation layer.

The array panel for the digital X-ray detection device further includes a gate line in a first direction, a data line in a second direction, and a bias line in the second direction. The bias line is disposed on the planarization layer.

The array panel for the digital X-ray detection device may further include a gate pad connected to one end of the gate line. The gate pad includes a first gate pad layer disposed on the gate insulating layer, a second gate pad layer disposed on the interlayer insulating layer, and a third gate pad layer disposed on the first passivation layer and made of the same material as the bias line. may include

In addition, the array panel for the digital X-ray detection device may further include a data pad connected to one end of the data line. The data pad may include a first data pad layer disposed on the interlayer insulating layer, and a second data pad layer disposed on the first passivation layer and made of the same material as the bias line.

As such, as the first electrode is formed by the same patterning process as that of the second passivation layer, each of the gate pad and the data pad may not include a conductive layer disposed on the same layer as the first electrode. Accordingly, since each of the gate pad and the data pad may have a relatively thin stacked thickness, a process error in the process of bonding the driving circuit unit to each of the gate pad and the data pad may be reduced, thereby increasing the yield of the digital X-ray detection device. can be improved.

Another embodiment of the present invention is a method of manufacturing an array panel for a digital X-ray detection device including a plurality of pixel regions disposed in a sensing region, comprising: disposing a switching transistor corresponding to each pixel region on a substrate; disposing a first passivation film covering the switching transistor; disposing a conductive material film on the first passivation film; disposing a PIN layer and a second electrode corresponding to the respective pixel regions on the conductive material film; disposing an insulating material film covering the PIN layer and the second electrode on a conductive material film; patterning the conductive material film and the insulating material film collectively to form a first electrode corresponding to each pixel region, and the PIN layer and disposing a second passivation layer covering the second electrode, and disposing a planarization layer covering the first electrode and the second passivation layer on the first passivation layer. provide a way

In this way, by batch patterning the conductive material film and the insulating material film and disposing the first electrode and the second passivation film, the number of mask steps can be reduced compared to separately patterning the conductive material film and the insulating material film. Therefore, the easiness of the manufacturing process and the manufacturing time can be improved.

In addition, since the number of times the first passivation layer is exposed to the patterning process is reduced, the degree of damage to the first passivation layer may be reduced.

Then, before patterning the conductive material film, the PIN layer and the second electrode are disposed. Accordingly, it is possible to prevent the PIN layer from being disposed on the first electrode on which foreign substances induced in the patterning process of the conductive material film remain. That is, since foreign substances can be prevented from being disposed at the interface between the first electrode and the PIN layer, semiconductor characteristics of the PIN layer can be improved.

Accordingly, reliability and uniformity of the light sensing device may be improved.

A method of manufacturing an array panel for a digital X-ray detection device according to an embodiment of the present invention includes disposing a conductive material film on a first protective film, and disposing a PIN layer and a second electrode corresponding to each pixel area on the conductive material film. disposing a PIN layer and an insulating material film covering the second electrode on the conductive material film, patterning the conductive material film and the insulating material film collectively to form a first electrode corresponding to each pixel region, and a PIN layer and a second electrode layer and disposing a second passivation layer covering the second electrode, and disposing a planarization layer covering the first electrode and the second passivation layer on the first passivation layer.

As described above, since the first electrode and the second protective film are formed through a batch patterning process for the conductive material film and the insulating material film, the side surface of the first electrode is not covered with the second protective film.

In addition, since the first electrode and the second protective film are formed by a batch patterning process for the conductive material film and the insulating material film, the number of mask steps can be reduced by one compared to forming the first electrode and the second protective film by each patterning process. can Therefore, the easiness of the manufacturing process can be improved.

In addition to this, since the number of times the first passivation layer is exposed to the patterning process is reduced by one, the degree of damage to the first passivation layer can be reduced.

In addition, as the first electrode is formed by patterning the conductive material film after the PIN layer and the second electrode are formed, foreign substances due to the patterning of the conductive material film can be prevented from remaining between the first electrode and the PIN layer. Accordingly, since the semiconductor characteristics of the PIN layer can be improved, the reliability and uniformity of the photo-sensing device can be improved.

Meanwhile, as the first electrode and the second passivation layer are formed through a batch patterning process for the conductive material layer and the insulating material layer, each of the gate pad and the data pad does not include a conductive layer disposed on the same layer as the first electrode. Therefore, it can be provided with a relatively thin lamination thickness. Accordingly, since a process error in each bonding process of the gate pad and the data pad may be reduced, the yield of the digital X-ray detection apparatus may be improved.

1 is a view showing an X-ray imaging system according to an embodiment of the present invention.
2 is a view showing the digital X-ray detection apparatus of FIG. 1 according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of a plane of a part of the array panel of FIG. 2 .
FIG. 4 is a diagram illustrating I-I′ of FIG. 3 .
FIG. 5 is a view showing II-II' of FIG. 3 .
FIG. 6 is a view showing III-III' of FIG. 3 .
7 is a view showing a method of manufacturing an array panel for a digital X-ray detection device according to an embodiment of the present invention.
8a, 8b, 8c, 8d, 9a, 9b, 9c, 10a, 10b, 10c, 11a, 11b, 11c, 12a, 12b, 12c, 12d , FIGS. 13A, 13B, 14A, 14B, 14C and 14D are diagrams illustrating process diagrams in each step of FIG. 7 .

The above-described objects, features and advantages will be described below in detail with reference to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the present invention pertains will be able to easily implement the technical idea of the present invention. In describing the present invention, if it is determined that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to refer to the same or similar components.

In the following, that an arbitrary component is disposed on the "upper (or lower)" of a component or "upper (or below)" of a component means that any component is disposed in contact with the upper surface (or lower surface) of the component. Furthermore, it may mean that other components may be interposed between the component and any component disposed on (or under) the component.

Also, when it is described that a component is "connected", "coupled" or "connected" to another component, the components may be directly connected or connected to each other, but other components are "interposed" between each component. It is to be understood that “or, each component may be “connected,” “coupled,” or “connected” through another component.

Hereinafter, a digital X-ray detection apparatus and an array panel provided therein according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, an X-ray imaging system and a digital X-ray detection device provided therein will be described with reference to FIGS. 1 and 2 .

1 is a view showing an X-ray imaging system according to an embodiment of the present invention. FIG. 2 is a view showing the digital X-ray detection apparatus of FIG. 1 .

As shown in FIG. 1 , the X-ray imaging system 10 is for providing an X-ray image of the inside of a predetermined target object 20 . For example, the target object 20 may be a part of a living body to be tested or a part of an industrial process product to be tested.

The X-ray imaging system 10 includes a digital X-ray detection device 11 for detecting a transmission amount of X-rays, and a light source device 12 for irradiating X-rays. The light source device 12 faces the digital X-ray detection device 11 with the target object 20 interposed therebetween, and radiates X-rays in a direction toward the target object 20 .

The digital X-ray detection apparatus 11 may be formed in the form of a flat panel including a sensing area for detecting the amount of X-rays transmitted to the target object 20 .

As shown in FIG. 2 , the digital X-ray detection apparatus 11 includes an array panel 100 including a plurality of pixel areas PA arranged in a matrix form in a detection area (DA), and an array panel ( and driving units RD, GD, BD, and TC for driving 100 .

The drivers driving the array panel 100 may include a readout driver (RD), a gate driver (GD), a bias driver (BD), and a timing controller (TC). have. Here, the bias driver BD having a relatively simple circuit compared to the readout driver RD may be built in the readout driver RD.

Each pixel area PA of the array panel 100 includes a photo diode (PD) for sensing light and a switching transistor (ST) disposed between the photo sensing device PD and the data line DL. ) is included.

The array panel 100 is connected to the gate line GL and the data line DL connected to the switching transistor ST of each pixel area PA, and the photosensitive device PD of each pixel area PA. and a bias line BL.

For example, the gate line GL may be disposed in the sensing area DA in the first direction (horizontal direction and left/right direction in FIG. 2 ). That is, the gate line GL corresponds to a horizontal line formed of the pixel areas PA arranged in parallel in the first direction among the plurality of pixel areas PA, respectively. Accordingly, the gate line GL is connected to the switching transistor ST of the pixel areas PA arranged in parallel in the first direction among the plurality of pixel areas PA.

The data line DL may be disposed in the sensing area DA in the second direction (vertical direction and vertical direction in FIG. 2 ). That is, the data line DL corresponds to a vertical line each of the pixel areas PA arranged in parallel in the second direction among the plurality of pixel areas PA. Accordingly, the data line DL is connected to the switching transistor ST of the pixel areas PA arranged in parallel in the second direction among the plurality of pixel areas PA.

The bias line BL may be disposed in the sensing area DA in the second direction. That is, the bias line BL corresponds to a vertical line formed of the pixel areas PA arranged in parallel in the second direction among the plurality of pixel areas PA, respectively. Accordingly, the bias line BL is connected to the light sensing device PD of the pixel areas PA arranged in parallel in the second direction among the plurality of pixel areas PA.

In addition, the array panel 100 may further include a scintillator ( 140 of FIG. 4 ) disposed on a surface facing the light source device ( 12 of FIG. 1 ).

The scintillator 140 is disposed between the light source device 12 and the light sensing device PD, and converts X-rays emitted from the light source device 12 into visible light to be applied to the light sensing device PD. supply

A first electrode (for example, an anode electrode) of the photosensitive devices PD disposed in each pixel region P is connected to the switching transistor ST, and a second electrode (for example, a cathode electrode) is biased. It may be connected to the line BL.

The light sensing device PD absorbs visible light supplied from the scintillator 140 and generates electrons in response to the visible light, thereby generating a sensing signal corresponding to the amount of X-ray transmission in each pixel area PA.

When the switching transistor ST is turned on based on the gate signal of the gate line GL, the switching transistor ST transmits the sensing signal of the light sensing device PD to the data line DL.

The array panel 100 is disposed in the pad areas PDA1 and PDA2 formed of a part of the non-sensing area outside the sensing area DP, and the pads GP, DP, and BP are connected to the driving units GD and RD/BD. ) is included.

For example, the gate pad GP connected to one end of the gate line GL disposed in the first direction (left-right direction and horizontal direction in FIG. 2 ) is a first pad adjacent to one side of the sensing area DP in the first direction. It may be disposed in the area PDA1.

In addition, the data pad DP connected to one end of the data line DL arranged in the second direction (the vertical direction and the vertical direction in FIG. 2 ), and the bias connected to one end of the bias line BL arranged in the second direction The pad BP may be disposed in the second pad area PDA2 adjacent to one side of the sensing area DP in the second direction.

Although not shown in detail in FIG. 2 , the gate driver GD having a relatively simple circuit compared to the readout driver RD may be embedded in the array panel 100 . In this case, the array panel 100 may not include the gate pad PD.

The gate driver GD is connected to the gate pad GP and supplies a gate signal to each gate line GL corresponding to each gate pad GP.

The readout driver and the bias driver RD/BD are connected to the data pad DP and the bias pad BD, and supply a bias signal to each bias line BL corresponding to each bias pad BP. A sensing signal of each data line DL corresponding to the data pad DP is collected.

Specifically, the timing controller TC supplies the start signal STV and the clock signal CPV for controlling the driving timing of the gate driver GD to the gate driver GD. In addition, the timing controller TC supplies the readout control signal ROC and the readout clock signal CLK for controlling the driving timing of the readout driver RD to the readout driver RD.

The bias driver BD supplies a bias signal corresponding to a predetermined bias power to the bias line BL. In this case, the bias driver BD may selectively supply a bias signal for a reverse bias operation or a bias signal for a forward bias operation.

Before and after the light source device 12 irradiates X-rays, the bias driver BD supplies a bias signal to the light sensing devices PD of the plurality of pixel areas PA.

While the light source device 12 radiates X-rays, the light sensing device PD of each pixel area PA generates a sensing signal corresponding to the amount of light incident on each pixel area PA.

After the light source device 12 irradiates X-rays, the timing controller TC transmits a driving timing control signal for collecting sensing signals of the plurality of pixel areas PA to the gate driver GD and the readout driver. (RD) is supplied.

The gate driver GD sequentially supplies a gate signal for turning on the switching transistor ST of the pixel areas PA included in each horizontal line to each gate line GL.

The readout driver RD receives the sensing signal of each pixel area PA included in each horizontal line through the data line DL during each horizontal period. In addition, the readout driver RD generates an image signal based on the sensing signals of the plurality of pixel areas PA corresponding to the vertical period.

Illustratively, the readout driver RD amplifies the sensing signal, performs correction to remove the noise signal from the amplified sensing signal, converts the corrected sensing signal into a digital signal, and then converts the image from the combination of digital signals. signal can be generated. Here, the image signal may be a signal representing luminance values corresponding to the plurality of pixel areas PA as bit information.

Next, an array panel 100 for a digital X-ray detector according to an embodiment of the present invention will be described with reference to FIGS. 3, 4, 5 and 6 .

FIG. 3 is a diagram illustrating an example of a plane of a part of the array panel of FIG. 2 . FIG. 4 is a diagram illustrating I-I′ of FIG. 3 . FIG. 5 is a view showing II-II' of FIG. 3 . FIG. 6 is a view showing III-III' of FIG. 3 .

As shown in FIG. 3 , the array panel 100 includes a plurality of pixel areas PA arranged in a matrix in the sensing area DA. In addition, the array panel 100 further includes first and second pad areas PDA1 and PDA2 formed of a portion of the non-sensing area outside the sensing area DA, respectively.

The array panel 100 includes a switching transistor ST corresponding to each pixel area PA, and a photo-sensing device PD corresponding to each pixel area PA.

In addition, the array panel 100 further includes a gate line GL in a first direction, a data line DL in a second direction, and a bias line BL in the second direction.

The array panel 100 may further include a gate pad GP disposed in the first pad area PDA1 and connected to one end of the gate line GL.

The array panel 100 may further include a data pad DP disposed in the second pad area PDA2 and connected to one end of the data line DL.

The array panel 100 may further include a bias pad BP disposed in the second pad area PDA2 and connected to one end of the bias line BL.

Specifically, the switching transistor ST is an active layer ACT disposed in a cross region between the gate line GL and the data line BL, overlapping a portion of the active layer ACT and connected to the gate line GL. The gate electrode GE, one side of the active layer ACT, the source electrode SE connected to the data line DL, the other side of the active layer ACT, and the first electrode E1 of the photo-sensing device PD It may include a drain electrode DE connected to the .

For example, as shown in FIG. 3 , the gate electrode GE of the switching transistor ST may be formed of a portion branched in the second direction among the gate lines GL in the first direction.

The source electrode SE of the switching transistor ST may be formed of a portion branched in the first direction among the data lines DL in the second direction.

The source electrode SE may be connected to the active layer ACT through a source contact hole (SH) corresponding to one side of the active layer ACT.

In addition, the drain electrode DE may be connected to the active layer ACT through a drain contact hole DH corresponding to the other side of the active layer ACT.

The photosensitive device PD includes a first electrode E1 and a second electrode E2 and a PIN layer PIN disposed therebetween.

The first electrode E1 may be connected to the drain electrode DE of the switching transistor ST through a pixel contact hole PH.

The bias line BL crosses the pixel areas PA arranged in parallel in the second direction and overlaps the photosensitive device PD of the pixel areas PA arranged in parallel in the second direction.

In addition, the bias line BL is arranged in parallel in the second direction among the plurality of pixel areas PA through the bias contact hole BH exposing a portion of the light sensing device PD of each pixel area PA. It is connected to the light sensing device PD of the pixel areas PA.

The gate pad GP includes first, second, and third gate pad layers 211 , 212 and 213 connected to one side of the gate line GL and overlapping each other. Here, the first gate pad layer 211 is disposed on the same layer as the gate line GL, and the second gate pad layer 212 is disposed on the same layer as the data line DL. In addition, the third gate pad layer 213 is made of the same material as the bias line BL.

The data pad layer DP includes first and second data pad layers 221 and 222 connected to one side of the data line DL and overlapping each other. Here, the first data pad layer 221 is disposed on the same layer as the data line DL. In addition, the second data pad layer 222 is made of the same material as the bias line BL.

The bias pad layer BP is connected to one side of the bias line BL and is made of the same material as the bias line BL.

As shown in FIG. 4 , the array panel 100 includes a switching transistor ST disposed on a substrate 101 , a first passivation layer 111 covering the switching transistor ST, and a first passivation layer 111 . The photo-sensing device PD disposed thereon, the second passivation layer 121 covering the PIN layer PIN and the second electrode E2 of the photo-sensing device PD, and the first of the photo-sensing device PD A planarization layer 122 covering the electrode E1 and the second passivation layer 121 may be included.

In addition, the array panel 100 may further include a bias line BL disposed on the planarization layer 122 .

In addition, the array panel 100 may further include a third passivation layer 131 covering the bias line BL, an additional planarization layer 132 , and a scintillator 140 disposed on the additional planarization layer 132 . have.

The substrate 101 may be made of an insulating material such as glass. Alternatively, the substrate 101 may be formed of a flexible insulating material such as polyethylene terephthalate (PET), ethylene naphthalate (PEN), polyimide (PI), polymethyl methacrylate (PMMA), polycarbonate (PC), polystyrene (PS), and polyethersulfone (PES). may be made of

Although not shown in FIG. 4 , in order to more easily fix a semiconductor material or an inorganic material on the substrate 101 , the array panel 100 further includes a buffer layer (not shown) disposed entirely on the substrate 101 . can do. For example, the buffer layer (not shown) may be made of an inorganic insulating material such as SiNx or SiO.

The switching transistor ST includes an active layer ACT disposed on the substrate 101 and a gate electrode GE disposed on a gate insulating layer 102 covering a portion of the active layer ACT.

In addition, the switching transistor ST further includes a source electrode SE and a drain electrode DE disposed on the active layer ACT, the gate insulating layer 102 , and the interlayer insulating layer 103 covering the gate electrode GE. can do.

The active layer ACT includes a channel region and a source region and a drain region disposed on both sides of the channel region.

For example, the active layer ACT may be formed of any one of an amorphous silicon material, a low temperature polycrystaline silicon (LTPS) material, and an oxide semiconductor material.

The gate electrode GE is disposed on the gate insulating layer 102 covering the channel region of the active layer ACT.

In other words, the gate electrode GE overlaps the channel region of the active layer ACT, and the gate insulating layer 102 is disposed between the active layer ACT and the gate electrode GE.

As shown in FIG. 3 , the gate electrode GE is formed of a portion branched in the second direction among the gate lines GL in the first direction. Accordingly, the gate line GL is disposed on the same layer as the gate electrode GE and made of the same material as the gate electrode GE. That is, the gate line GL is disposed on the gate insulating layer 102 .

The source electrode SE is connected to the source region of the active layer ACT through a source contact hole SH passing through the interlayer insulating layer 103 .

Similarly, the drain electrode DE is connected to the source region of the active layer ACT through a drain contact hole DH penetrating the interlayer insulating layer 103 .

As shown in FIG. 3 , the source electrode SE may be formed of a portion branched in the first direction among the data lines DL in the second direction.

Accordingly, the data line DL is disposed on the same layer as the source electrode SE and is made of the same material as the source electrode SE. That is, the data line DL is disposed on the interlayer insulating layer 103 .

The source electrode SE, the drain electrode DE, and the data line DL are covered with the first passivation layer 111 disposed on the interlayer insulating layer 103 .

The first passivation layer 111 may be formed of an inorganic insulating material such as SiNx or SiO.

Although not shown in FIG. 3 , the array panel 100 may further include an overcoat layer (not shown) that flatly covers the source electrode SE, the drain electrode DE, and the data line DL. In this case, the first passivation layer 111 may be disposed on the overcoat layer.

The overcoat film (not shown) may be made of an insulating material that can be laminated to a thickness greater than or equal to a threshold in order to provide a flat surface regardless of the shape of the wiring or pattern disposed thereunder.

The first electrode E1 of the photosensitive device PD is disposed on the first passivation layer 111 .

The photosensitive device PD includes first and second electrodes E1 and E2 , and a PIN layer PIN disposed between the first and second electrodes E1 and E2 .

The first electrode E1 corresponds to each pixel area PA and is disposed on the first passivation layer 111 . Here, the first electrode E1 may be firmly fixed by the first passivation layer 111 made of the inorganic insulating material.

The first electrode E1 may be disposed in an area as wide as possible among the pixel areas PA in consideration of the fill factor.

Illustratively, the first electrode E1 may be a single layer made of an opaque metal such as molybdenum (Mo) or a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). It may be a multi-layer structure.

The PIN layer PIN is disposed on the first electrode E1 .

The PIN layer (PIN) is an N (Negative) semiconductor layer containing N-type impurities, an I (Intrinsic) semiconductor layer containing no impurities, and a P (Positive) type semiconductor layer containing P-type impurities in sequence. It may have a stacked structure. Here, the I-type semiconductor layer may be formed to be relatively thicker than the N-type semiconductor layer and the P-type semiconductor layer. The PIN layer (PIN) may have a thickness of about 1 μm.

Illustratively, the PIN layer (PIN) includes a photoelectric material capable of converting visible light generated by the scintillator 140 into an electrical signal. For example, the PIN layer PIN may include _{at least one of a-Se, HgI 2} , CdTe, PbO, PbI ₂ , BiI ₃ , GaAs, and Ge.

The second electrode E2 is disposed on the PIN layer PIN and is made of a transparent conductive material.

For example, the second electrode E2 may be formed of any one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO).

In this way, since the amount of light blocked by the second electrode E2 may be reduced, a decrease in the amount of incident light on the PIN layer PIN and a decrease in the fill factor may be improved.

The PIN layer PIN and the second electrode E2 are covered with a second passivation layer 121 disposed on the first electrode E1 . That is, the second passivation layer 121 is disposed on the first electrode E1 and covers the PIN layer PIN and the second electrode E2 .

The second passivation layer 121 may be formed of an inorganic insulating material such as SiNx or SiO.

That is, when the active layer ACT is made of an oxide semiconductor, in order to prevent deterioration of semiconductor characteristics due to the second passivation film 121 made of an inorganic insulating material, the second passivation film 121 is formed on each photosensitive device PD. covers only the PIN layer PIN and the second electrode E2. That is, the second passivation layer 121 does not overlap the switching transistor ST.

In addition, the first electrode E1 and the second passivation layer 121 are disposed on the first passivation layer 111 and are covered with a planarization layer 122 corresponding to the sensing area DA. That is, the planarization layer 122 is disposed on the first passivation layer 111 and covers the first electrode E1 and the second passivation layer 121 .

For example, the planarization layer 122 may be formed of an organic insulating material such as an acrylic resin such as photo acryl (PAC). Alternatively, the planarization layer 122 may be formed of a photo resist (PR) or the like.

In this case, the planarization layer 122 is disposed only in the sensing area DA, and is not disposed in the non-sensing area, particularly, the first and second pad areas PDA1 and PDA2. In this way, bonding failure of the gate pad GP or the data pad DP due to the planarization layer 122 having a relatively thick thickness may be prevented.

The bias line BL is disposed on the planarization layer 122 .

The bias line BL corresponds to a portion of each photo-sensing device PD and passes through a bias contact hole BH penetrating the second passivation layer 121 and the planarization layer 122 to the first of each photo-sensing device PD. It is connected to the second electrode E2. That is, the bias contact hole BH exposes at least a portion of the second electrode E2 of the light sensing device PD.

The bias line BL may be covered with a third passivation layer 131 disposed on the planarization layer 122 .

The third passivation layer 131 may be made of an inorganic insulating material such as SiNx or SiO.

In addition, the array panel 100 may further include an additional planarization layer 132 flatly disposed on the third passivation layer 131 .

The additional planarization layer 132 may be formed of an organic insulating material such as an acrylic resin such as photo acryl (PAC) or a photo resist (PR).

The scintillator 140 may be disposed on the additional planarization layer 132 .

The scintillator 140 converts X-rays into visible light.

The scintillator 140 may have a columnar structure. For example, the scintillator 140 may be formed of CsI:Tl (Cesium iodide: Talluim doped).

Meanwhile, in FIGS. 3 and 4 , among the source electrode SE and the drain electrode DE of the switching transistor ST, the source electrode SE is connected to the data line DL, and the drain electrode DE is the light sensing device. (PD) is exemplified. However, the exemplary embodiment of the present invention is not limited thereto, and the drain electrode DE may be connected to the data line DL, and the source electrode SE may be connected to the photosensitive device PD.

5 , the gate pad GP includes a first gate pad layer 211 disposed on the gate insulating layer 102 , a second gate pad layer 212 disposed on the interlayer insulating layer 103 , and a third gate pad layer 213 disposed on the first passivation layer 111 .

Here, the first gate pad layer 211 is formed through the same patterning process as that of the gate line GL, so that it is disposed on the same layer as the gate line GL and made of the same material as the gate line GL.

The second gate pad layer 212 is formed through the same patterning process as that of the data line DL, so that it is disposed on the same layer as the data line DL and made of the same material as the data line DL. Also, the second gate pad layer 212 is covered with the first passivation layer 111 like the data line DL.

The second gate pad layer 212 is connected to the first gate pad layer 211 through the first gate pad hole GPH1 penetrating the interlayer insulating layer 103 .

Meanwhile, according to an embodiment of the present invention, the first electrode E1 , the PIN layer PIN, the second electrode E2 , the second passivation layer 121 , and the planarization layer 122 are formed in the sensing area DA. placed only in

That is, according to an embodiment of the present invention, the first electrode E1 and the second passivation layer 121 are formed by the same patterning process. Here, in order to stabilize the characteristics of the switching transistor ST, the second passivation layer 121 covers the PIN layer PIN and the second electrode E2 of each photo-sensing device PD, and is removed from the rest. Accordingly, like the second passivation layer 121 , the first electrode E1 is disposed only in a portion of each pixel area PA.

In addition, the planarization layer 122 is removed from the non-sensing area, in particular, from the first and second pad areas PDA1 and PDA2 for easy bonding of the respective pads GP and DP.

Accordingly, the third gate pad layer 213 is formed through the same patterning process as that of the bias line BL, so that it is formed of the same material as the bias line BL and is disposed on the first passivation layer 111 .

In addition, the third gate pad layer 213 is connected to the second gate pad layer 212 through the second gate pad hole GPH2 penetrating the first passivation layer 111 .

Also, the third gate pad layer 213 is covered with the third passivation layer 131 like the bias line BL. Accordingly, the third gate pad layer 213 is exposed to the outside through a hole penetrating the third passivation layer 131 . Accordingly, the gate pad GP may be bonded to the gate driver GD.

As described above, according to an embodiment of the present invention, since the gate pad GP does not include a conductive layer disposed on the same layer as the first electrode E1 , it may have a relatively thin stacking thickness. Therefore, the easiness of the bonding process for the gate pad GP may be improved.

6 , the data pad DP includes a first data pad layer 221 disposed on the interlayer insulating layer 103 and a second data pad layer 222 disposed on the first passivation layer 111 . ) is included.

Here, the first data pad layer 221 is formed through the same patterning process as that of the data line DL, so that it is disposed on the same layer as the data line DL and made of the same material as the data line DL. Also, the second gate pad layer 212 is covered with the first passivation layer 111 like the data line DL.

And, as mentioned above, according to an embodiment of the present invention, the first electrode E1 , the PIN layer PIN, the second electrode E2 , the second passivation layer 121 , and the planarization layer 122 . is disposed only in the sensing area DA.

Therefore, like the third gate pad layer 213 of the gate pad GP, the second data pad layer 212 is formed through the same patterning process as that of the bias line BL, so that it is made of the same material as the bias line BL. while being formed, it is disposed on the first passivation layer 111 .

Also, the second data pad layer 222 is connected to the first data pad layer 221 through the data pad hole DPH passing through the first passivation layer 111 .

The second data pad layer 222 is covered with the third passivation layer 131 like the third gate pad layer 213 and the bias line BL. Accordingly, the second data pad layer 222 is exposed to the outside through a hole penetrating the third passivation layer 131 . Accordingly, the data pad DP may be bonded to the readout driver RD.

In addition, although not shown separately, the bias pad (BP in FIG. 3 ) may be formed of a single layer formed through the same patterning process as the bias line BL.

At this time, the bias pad (BP in FIG. 3 ) is formed through the same patterning process as the bias line BL, similarly to the third gate pad layer 213 and the second data pad layer 222 , so that the bias line BL and the bias line BL are formed. Although made of the same material, it may be formed of a single layer disposed on the first passivation layer 111 .

As described above, in the array panel 100 for a digital X-ray detection device according to an embodiment of the present invention, the first electrode E1 is formed by the same patterning process as that of the second passivation layer 121 , so that the gate pad GP and Each of the data pads DP does not include a conductive layer disposed on the same layer as the first electrode E1 . Accordingly, since each of the gate pad GP and the data pad DP may have a relatively thin stacking thickness, the easiness of the bonding process may be improved. Accordingly, since a process error of the bonding process may be reduced, the yield of the digital X-ray detection apparatus 11 may be improved.

Next, a method of manufacturing the array panel 100 according to an embodiment of the present invention will be described.

7 is a view showing a method of manufacturing an array panel for a digital X-ray detection device according to an embodiment of the present invention. 8a, 8b, 8c, 8d, 9a, 9b, 9c, 10a, 10b, 10c, 11a, 11b, 11c, 12a, 12b, 12c, 12d , FIGS. 13A, 13B, 14A, 14B, 14C and 14D are diagrams illustrating process diagrams in each step of FIG. 7 .

The arrangement method or formation method of each component described below is a technique performed by a person skilled in the art, deposition (Deposition), photoresist coating (PR Coating), exposure (Exposure), developing (Develop), etching ( Etch), a photolithography (Photoliyhography) process including a photoresist stripping (PR Strip) is used, and a detailed description thereof will be omitted. For example, in the case of deposition, a method such as sputtering for a metal material and plasma enhanced vapor deposition (PECVD) for a semiconductor or insulating film can be used separately, and in the case of etching, a dry method can be used depending on the material. A technique performed by a person skilled in the art may be applied as it can select and use etching and wet etching.

As shown in FIG. 7 , in the method of manufacturing an array panel according to an embodiment of the present invention, a switching transistor ST corresponding to each pixel area PA is disposed on a substrate 101 , and the switching transistor ST ), disposing a first passivation layer 111 covering (S10), disposing a conductive material layer on the first passivation layer 111 (S20), and a PIN corresponding to each pixel area PA on the conductive material layer. Disposing the layer (PIN) and the second electrode (E2) (S30), disposing an insulating material film covering the PIN layer (PIN) and the second electrode (E2) on the conductive material film (S40), a conductive material disposing the first electrode E1 corresponding to each pixel area PA and the second protective film 121 covering the PIN layer PIN and the second electrode E2 by batch patterning the film and the insulating material film ( and disposing a planarization layer 122 covering the first electrode E1 and the second passivation layer 121 on the first passivation layer 111 ( S60 ).

In this case, in the step of disposing the switching transistor ST ( S10 ), the gate line GL in the first direction and the data line DL in the second direction may be disposed together.

In addition, in the step of disposing the switching transistor ST ( S10 ), the first and second gate pad layers 211 and 212 of the first pad area PDA1 and the first data of the second pad area PDA2 . The pad layer 221 may be disposed together.

In the method of manufacturing the array panel 100 according to an embodiment of the present invention, a bias contact hole BH corresponding to a portion of the second electrode E2 and penetrating the second passivation layer 121 and the planarization layer 122 is formed. and disposing the bias line BL in the second direction on the planarization layer 122 ( S70 ).

Also, the method of manufacturing the array panel 100 according to an embodiment of the present invention may further include disposing a third passivation layer 131 covering the bias line BL on the planarization layer ( S80 ).

8A and 8B , after the substrate 101 is prepared, the gate line GL in the first direction and the data line DL in the second direction are located in the sensing area DA of the substrate 101 . and a switching transistor ST corresponding to each pixel area PA.

And, as shown in FIGS. 8A, 8C and 8D , the first and second gate pad layers 211 and 212 and the first data pad layer 221 in the pad areas PDA1 and PDA2 of the substrate 101 . ) is placed.

The switching transistor ST includes an active layer ACT disposed on the substrate 101 , a gate electrode GE disposed on a gate insulating layer 102 covering a portion of the active layer ACT, and an active layer ACT. , a source electrode SE and a drain electrode DE disposed on the gate insulating layer 102 and the interlayer insulating layer 103 covering the gate electrode GE.

Referring to FIG. 8B , in the step of disposing the switching transistor ST ( S10 ), an active layer ACT corresponding to a partial area of each pixel area PA is formed by patterning a semiconductor material on the substrate 101 . and patterning an insulating material and a conductive material covering the active layer ACT to form a gate insulating film 102 covering the channel region of the active layer ACT and a gate electrode GE on the gate insulating film 102 process, forming an interlayer insulating film 103 covering the active layer ACT, the gate insulating film 102 and the gate electrode GE on the substrate 101, and patterning the interlayer insulating film 103 to form the active layer A process of forming a source contact hole SH and a drain contact hole DH exposing a portion of each of the source region and the drain region of the ACT, and patterning a conductive material on the interlayer insulating layer 103 to form the source electrode SE ) and forming the drain electrode DE.

Referring to FIG. 8A , since the gate electrode GE is formed as a part of the gate line GL, the gate line GL is formed of an insulating material and a conductive material covering the active layer ACT together with the gate electrode GE. It can be formed by the process of patterning.

As shown in FIG. 8C , the first gate pad layer 211 may be formed by patterning an insulating material and a conductive material covering the active layer ACT together with the gate electrode GE and the gate line GL. can The first gate pad layer 211 is disposed in the first pad area PDA1 which is a part of the non-sensing area and is connected to one side of the gate line GL.

Referring to FIG. 8A , since the source electrode SE is formed as a part of the data line DL, the data line DL is formed on the interlayer insulating layer 103 together with the source electrode SE and the drain electrode DE. It may be formed by a process of patterning a conductive material.

8C and 8D , the second gate pad layer 212 and the first data pad layer 221 together with the source electrode SE, the drain electrode DE, and the data line DL are interlayer insulating layers. It can be formed by the process of patterning the conductive material on the (103) phase.

As shown in FIG. 8C , the second gate pad layer 212 overlaps the first gate pad layer 211 . In addition, the second gate pad layer 212 penetrates the interlayer insulating layer 103 and is connected to the first gate pad layer 211 through a contact hole (GPH1 in FIG. 5 ) exposing the first gate pad layer 211 . do.

As shown in FIG. 8D , the first data pad layer 221 is disposed in the second pad area PDA2 which is a part of the non-sensing area and is connected to one side of the data line DL.

Next, as shown in FIG. 8B , a first passivation layer 111 is disposed on the interlayer insulating layer 103 . (S10) The first passivation layer 111 covers the source electrode SE, the drain electrode DE, and the data line DL. Then, the first passivation layer 111 is patterned to form a pixel contact hole PH exposing a portion of the drain electrode DE.

Also, as shown in FIGS. 8C and 8D , the first passivation layer 111 covers the second gate pad layer 212 and the first data pad layer 221 .

As shown in FIGS. 9A, 9B and 9C , a conductive material film 401 is disposed on the first passivation film 111 . (S20)

Here, the conductive material layer 401 is a single layer or multiple layers made of an opaque metal such as molybdenum (Mo) or a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). can be a structure.

10A and 10B, a PIN layer PIN corresponding to each pixel area PA is disposed on the conductive material film 401, and a second electrode E2 is disposed on the PIN layer PIN. place the (S30)

For example, as shown in FIG. 10B , a semiconductor material on the conductive material layer 401 is patterned to form a PIN layer PIN corresponding to each pixel area PA, and then a conductive material covering the PIN layer PIN. may be patterned to form the second electrode E2 .

Alternatively, as shown in FIG. 10C, a semiconductor material and a conductive material are sequentially stacked on the conductive material film 401, and then the semiconductor material and the conductive material are collectively patterned to form a PIN layer (PIN) and a second electrode (E2). can also be formed. In this way, since the number of mask processes can be reduced, the easiness of manufacturing can be improved.

11A , 11B and 11C , an insulating material film 402 covering the PIN layer PIN and the second electrode E2 is disposed on the conductive material film 401 . (S40)

Here, the insulating material layer 402 may be made of an inorganic insulating material such as SiNx or SiO.

Then, as shown in FIGS. 12A and 12B , the conductive material film 401 and the insulating material film 402 are collectively patterned to arrange the first electrode E1 and the second protective film 121 . (S50)

The first electrode E1 corresponds to each pixel area PA. That is, the first electrode E1 faces the second electrode E2 with the PIN layer PIN interposed therebetween.

Since the PIN layer (PIN) and the second electrode E2 are patterned together with the conductive material film 401 while the insulating material film 402 is disposed on the conductive material film 401, the second protective film 121 is formed. is disposed on the first electrode E1. Accordingly, the side surface of the first electrode E1 is not covered by the second passivation layer 121 . That is, the second passivation layer 121 covers only the PIN layer PIN and the second electrode E2 .

12C and 12D , by batch patterning of the conductive material film 401 and the insulating material film 402 , the first electrode E1 and the second protective film 121 are formed in the sensing area DA. It is disposed in each pixel area PA, and is not disposed in the non-sensing area. That is, the conductive material film 401 and the insulating material film 402 in the non-sensing area are removed.

13A and 13B , a planarization layer 122 covering the first electrode E1 and the second passivation layer 121 is disposed on the first passivation layer 111 . Then, the second passivation layer 121 and the planarization layer 122 are patterned to form a bias contact hole BH corresponding to a portion of the second electrode E1 of each photo-sensing device PD. (S60)

In this case, in the process of forming the bias contact hole BH, the planarization layer 122 of the non-sensing area, particularly, the first and second pad areas PDA1 and PDA2 may be removed. In this way, since each of the stacking thicknesses of the gate pad GP and the data pad DP may be relatively thin, an error rate of the bonding process may be reduced.

As shown in FIGS. 14A and 14B , a conductive material on the planarization layer 122 is patterned, and a bias line BL in the second direction is disposed on the planarization layer 122 . ( S70 ) A third passivation layer 131 covering the bias line BL is disposed on the planarization layer 122 . (S80)

In this case, the bias line BL is connected to the second electrode E2 through the bias contact hole BH.

14A, 14C, and 14D , the third gate pad layer 213 and the second data pad layer 222 pattern the conductive material on the planarization layer 122 together with the bias line BL. It can be formed by the process of

That is, as shown in FIG. 14C , the third gate pad layer 213 penetrates the first passivation layer 111 covering the second gate pad layer 212 and the first passivation layer 111, and the second gate pad layer ( In a state in which the contact hole (GPH2 of FIG. 5 ) exposing the 212 is disposed, it may be formed together with the bias line BL. Accordingly, the third gate pad layer 213 is disposed on the first passivation layer 111 , overlaps the second gate pad layer 212 , and may be made of the same material as the bias line BL.

The third gate pad layer 213 is connected to the second gate pad layer 212 through the contact hole GPH2 penetrating the first passivation layer 111 .

Also, as shown in FIG. 14D , the second data pad layer 222 passes through the first passivation layer 111 covering the first data pad layer 221 and the first passivation layer 111 and passes through the first data pad layer ( In a state in which the contact hole (DPH of FIG. 6 ) exposing the 221 is disposed, it may be formed together with the bias line BL. Accordingly, the second data pad layer 222 may be disposed on the first passivation layer 111 , overlap the first data pad layer 221 , and may be made of the same material as the bias line BL.

The second data pad layer 222 is connected to the first data pad layer 221 through a contact hole DPH passing through the first passivation layer 111 .

Thereafter, a third passivation layer 131 is disposed on the planarization layer 122 to cover each of the bias line BL, the third gate pad layer 213 , and the second data pad layer 222 . (S80)

Then, the third passivation layer 131 is patterned to form a hole exposing a portion of each of the third gate pad layer 213 and the second data pad layer 222 .

Also, as shown in FIG. 4 , after the additional planarization layer 132 is disposed on the third passivation layer 131 , the scintillator 140 may be disposed on the additional planarization layer 132 .

Accordingly, the array panel 100 according to an embodiment of the present invention may be provided.

As described above, in the method of manufacturing the array panel 100 according to an embodiment of the present invention, the conductive material film 401 on the first passivation film 111 and the conductive material film 401 are disposed on the PIN layer (PIN). and forming the first electrode E1 and the second passivation layer 121 by collectively patterning the insulating material layer 402 covering the second electrode E2 ( S50 ).

As such, since the first electrode E1 and the second passivation layer 121 are formed by one patterning process, the number of mask processes can be reduced by one. Therefore, the easiness of the manufacturing process can be improved. In addition, since the first passivation layer 111 is exposed only in one patterning process for forming the first electrode E1 and the second passivation layer 121 , the degree of damage to the first passivation layer 111 can be reduced. .

And, after the PIN layer (PIN) is formed, as the patterning process of the conductive material film 401 for forming the first electrode E1 is performed, foreign substances caused by the patterning process of the conductive material film 401 are removed. Remaining between the first electrode E1 and the PIN layer PIN may be prevented. Accordingly, since the photoelectric characteristics of the PIN layer PIN may be improved, the reliability and uniformity of the photosensitive device PD may be improved.

As described above, the present invention has been described with reference to the illustrated drawings, but the present invention is not limited by the embodiments and drawings disclosed in this specification, and various methods can be obtained by those skilled in the art within the scope of the technical spirit of the present invention. It is obvious that variations can be made. In addition, although the effects according to the configuration of the present invention are not explicitly described and described while describing the embodiments of the present invention, it is natural that the effects predictable by the configuration should also be recognized.

: X-ray imaging system 20: object
11: digital x-ray detection device 12: light source device
100: array panel DP: detection area
TC: Timing controller GD: Gate driver
RD: Readout driving part BD: Bias driving part
DL: data line GL: gate line
BL: bias line PA: pixel area
PD: light sensing element ST: switching transistor
PDA1, PDA2: first and second pad areas
GP: Gatepad DP: Datapad
ACT: active layer
SE, DE: source electrode, drain electrode
SH, DH: source contact hole, drain contact hole
PH: pixel contact hole
E1: first electrode PIN: PIN layer
E2: second electrode BH: bias contact hole
103: interlayer insulating film
111: first passivation layer 121: second passivation layer
122: planarization film 131: third passivation film
140: scintillator

Claims (15)

An array panel for a digital X-ray detection device comprising a plurality of pixel regions disposed in a sensing region, the array panel comprising:
a switching transistor corresponding to each pixel region;
a first electrode disposed on a first passivation layer covering the switching transistor;
a PIN layer disposed on the first electrode;
a second electrode disposed on the PIN layer;
a second passivation layer disposed on the first electrode and covering the PIN layer and the second electrode; and
and a planarization layer disposed on the first passivation layer, corresponding to the sensing region, and covering the first electrode and the second passivation layer.
The method of claim 1,
An array panel for a digital X-ray detection device in which a side surface of the first electrode is in contact with the planarization film.
The method of claim 1,
a gate line connected to the switching transistor of the plurality of pixel regions arranged in parallel in a first direction;
a data line connected to the switching transistors of pixel regions arranged in parallel in a second direction crossing the first direction among the plurality of pixel regions; and
and a bias line connected to the second electrode of the plurality of pixel areas arranged in parallel in the second direction.
4. The method of claim 3,
The switching transistor is
an active layer disposed on the substrate; and
a gate electrode disposed on a gate insulating film covering a portion of the active layer;
The gate line is disposed on the same layer as the gate electrode,
the data line is disposed on the active layer, the gate insulating layer, and an interlayer insulating layer covering the gate electrode;
and the bias line is an array panel for a digital detection device disposed on the planarization layer.
5. The method of claim 4,
and a gate pad disposed in a pad area of the non-sensing area outside the sensing area and connected to one end of the gate line;
the gate pad
a first gate pad layer disposed on the gate insulating layer;
a second gate pad layer disposed on the interlayer insulating layer; and
and a third gate pad layer disposed on the first passivation layer and made of the same material as the bias line.
5. The method of claim 4,
a data pad disposed in a pad area of the non-sensing area outside the sensing area and connected to one end of the data line;
the data pad
a first data pad layer disposed on the interlayer insulating layer; and
and a second data pad layer disposed on the first passivation layer and made of the same material as the bias line.
A method for manufacturing an array panel for a digital X-ray detection device including a plurality of pixel regions disposed in a sensing region, the method comprising:
disposing a switching transistor corresponding to each pixel region on a substrate and disposing a first passivation layer covering the switching transistor;
disposing a conductive material film on the first passivation film;
disposing a PIN layer and a second electrode corresponding to each of the pixel regions on the conductive material film;
disposing an insulating material film covering the PIN layer and the second electrode on the conductive material film;
disposing a first electrode corresponding to each pixel region and a second passivation layer covering the PIN layer and the second electrode by collectively patterning the conductive material film and the insulating material film; and
and disposing a planarization film covering the first electrode and the second passivation film on the first passivation film.
8. The method of claim 7,
In the disposing of the planarization layer, a side surface of the first electrode is in contact with the planarization layer.
9. The method of claim 8,
In the step of disposing the switching transistor,
The switching transistor includes an active layer disposed on a substrate, a gate electrode disposed on a gate insulating layer covering a portion of the active layer, and a source disposed on an interlayer insulating layer covering the active layer, the gate insulating layer, and the gate electrode. It includes an electrode and a drain electrode,
disposing a gate line connected to the switching transistor of the pixel regions arranged in parallel in a first direction among the plurality of pixel regions together with the gate electrode;
An array for a digital X-ray detection device for arranging data lines connected to the switching transistors of pixel regions arranged in parallel in a second direction crossing the first direction among the plurality of pixel regions together with the source electrode and the drain electrode A method for manufacturing a panel.
10. The method of claim 9,
disposing a bias contact hole corresponding to a portion of the second electrode and penetrating the second passivation layer and the planarization layer; and
and disposing a bias line connected to the second electrode of the plurality of pixel regions arranged in parallel in the second direction on the planarization layer. Way.
11. The method of claim 10,
In the step of disposing the planarization layer, the planarization layer corresponds to the sensing area.
12. The method of claim 11,
a first gate pad layer connected to one end of the gate line is disposed in a pad region of a non-sensing region outside the sensing region together with the gate electrode and the gate line;
disposing a second gate pad layer overlapping the first gate pad layer together with the source electrode, the drain electrode, and the data line;
A method of manufacturing an array panel for a digital X-ray detection device by disposing a third gate pad layer overlapping the second gate pad layer together with the bias line.
13. The method of claim 12,
the second gate pad layer is disposed on the interlayer insulating layer and connected to the first gate pad layer through a contact hole penetrating the interlayer insulating layer;
The third gate pad layer is disposed on the first passivation layer and is connected to the second gate pad layer through a contact hole penetrating the first passivation layer.
12. The method of claim 11,
a first data pad layer connected to one end of the data line is disposed in a pad region of a non-sensing region outside the sensing region together with the source electrode, the drain electrode and the data line
A method of manufacturing an array panel for a digital X-ray detection device by disposing a second data pad layer overlapping the first data pad layer together with the bias line.
15. The method of claim 14,
The second data pad layer is disposed on the first passivation layer and is connected to the first data pad layer through a contact hole penetrating the first passivation layer.

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