KR20210079973A - Pixel array panel and digital x-ray detector comprising the same - Google Patents

Abstract

One embodiment of the present invention provides an array panel for a digital X-ray detection device which comprises: a plurality of light sensing elements corresponding to a plurality of pixel areas; and a bias line disposed in a mesh shape surrounding an outer periphery of the plurality of light sensing elements. As a result, an overlapping region between the light sensing elements and the bias line can be removed so that a decrease in a fill factor can be prevented.

Description

Array panel for digital X-ray detection device and digital X-ray detection device including same {PIXEL ARRAY PANEL AND DIGITAL X-RAY DETECTOR COMPRISING THE SAME}

The present invention relates to a digital X-ray detector (DXD) for detecting a transmission amount of X-rays (radiation) and an array panel provided therein.

X-rays (radiation) are electromagnetic waves having transparency. The amount of transmission of these X-rays corresponds to the density inside the object. Accordingly, X-ray images are widely used in fields such as medical care, security and industry. In particular, X-ray images are frequently used as a basic tool for diagnosis in the medical field.

Existing X-ray images were provided by preparing a film made of a photosensitive material, exposing the film to X-rays passing through an object, and then transferring the image of the film to photo paper. In this case, there is a problem in that it is impossible to provide real-time image information due to the printing process, and there is a problem in that image information is easily lost because it is impossible to store and preserve the film for a long time.

Recently, due to the development of image processing technology and semiconductor technology, a digital X-ray detection apparatus having a flat panel structure that can replace a film has been proposed.

A general digital X-ray detection device includes an array panel in the form of a flat plate. The array panel includes a plurality of pixel regions, and includes a switching transistor and a light sensing element corresponding to each pixel region.

The photo-sensing device corresponding to each pixel region includes a first electrode connected to a switching transistor corresponding to each pixel region and a second electrode connected to a bias line.

An array panel for a digital X-ray detection device includes a gate line and a data line connected to a switching transistor of each pixel region, and a bias line for supplying a bias power to the photo-sensing device.

In order to reduce parasitic capacitance between each of the gate line and the data line and the bias line and to easily connect the bias line and the photo-sensing device, the bias line may be disposed at a position overlapping the photo-sensing device in each pixel area.

Since the photo-sensing device is connected between the switching transistor and the bias line, the photo-sensing device may be disposed on at least one insulating layer covering the switching transistor, and the bias line may be disposed on at least one insulating layer covering the photo-sensing device.

In addition, the bias line may be made of a metal material having a relatively low resistance to reduce resistance.

Accordingly, in a region where the photo-sensing element and the bias line overlap, light incident on the photo-sensing element is blocked by the bias line, thereby reducing the fill factor of the photo-sensing element. Here, the fill factor is a parameter corresponding to a ratio of a current output from the light sensing device to an amount of light incident on each pixel area.

Also, as the resolution of the array panel increases, the plane width of the photo-sensing device decreases, so that the ratio of the overlapping area between the photo-sensing device and the bias line among the plane width of the photo-sensing device increases. Therefore, as the resolution increases, there is a problem in that the reduction of the fill factor due to the bias line overlapping the light sensing device is further increased.

Accordingly, the present invention provides an array panel for a digital X-ray detection device capable of minimizing a parasitic capacitance between each of a gate line and a data line and a bias line while preventing a decrease in a fill factor due to a bias line, and a digital X-ray detection device including the same is to provide

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned may be understood by the following description, and will be more clearly understood by the examples of the present invention. Moreover, it will be readily apparent that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

An example of the present invention provides an array panel for a digital X-ray detection device disposed in the form of a mesh surrounding a plurality of photo-sensing devices corresponding to a plurality of pixel areas, and a mesh surrounding the periphery of the plurality of photo-sensing devices, and including a bias line. do.

As described above, since the bias line is formed in a mesh shape surrounding the periphery of the plurality of light sensing elements, an overlapping area between the photo sensing element and the bias line may be removed. Therefore, a decrease in the fill factor due to the overlapping area between the light sensing element and the bias line can be prevented.

The array panel for the digital X-ray detection device includes a plurality of switching transistors corresponding to the plurality of pixel regions and connected to the plurality of photo-sensing elements, and the switching of pixel regions arranged in parallel in a first direction among the plurality of pixel regions. The display device further includes: a gate line connected to the transistor; and a data line connected to the switching transistor of pixel regions arranged in parallel in a second direction crossing the first direction among the plurality of pixel regions.

Here, the gate line may overlap the photo-sensing element of the pixel regions arranged in parallel in the first direction.

Alternatively, the data line may be overlapped with the light sensing element of the pixel areas arranged in parallel in the second direction.

Accordingly, a separation distance between each of the data line and the gate line and the bias line may be secured on a plane in which the plurality of pixel regions are arranged. Accordingly, an increase in the parasitic capacitance between each of the data line and the gate line and the bias line may be prevented, and distortion of the driving signal due to the parasitic capacitance between the lines may be prevented.

In another exemplary embodiment of the present invention, an image signal is based on the array panel, a gate driver supplying a gate signal to the gate line of the array panel, and sensing signals of a plurality of pixel areas received through the data line of the array panel. It further provides a digital X-ray detection device comprising a data driver for generating a. As described above, as the array panel having an improved fill factor is provided, the clarity and accuracy of the digital X-ray detection apparatus may be improved.

An array panel for a digital X-ray detection device according to an embodiment of the present invention includes a mesh-shaped bias line surrounding the outer portions of the plurality of light sensing elements. As described above, since the bias line does not overlap the plurality of photo-sensing elements, a decrease in the fill factor due to the overlapping area between each photo-sensing element and the bias line can be prevented.

In addition, as the resolution increases, it is possible to prevent a decrease in the fill factor due to the bias line from being deepened. That is, the influence of the resolution on the fill factor may be removed.

In addition, the array panel for a digital X-ray detection apparatus according to an embodiment of the present invention further includes a gate line in a first direction and a data line in a second direction crossing the first direction. Here, the gate line may overlap the light sensing element of the pixel areas arranged in parallel in the first direction. In addition, the data line may be overlapped with the light sensing element of the pixel areas arranged in parallel in the second direction.

In this way, the overlapping region between each of the gate line and the data line and the bias line is limited to the crossing region between each of the gate line and the data line and the bias line, so that the parasitic capacitance between each of the gate line and the data line and the bias line can be minimized. .

As described above, according to an embodiment of the present invention, a decrease in the fill factor due to the bias line can be prevented while minimizing the parasitic capacitance between each of the gate line and the data line and the bias line.

Accordingly, the sharpness and accuracy of the digital X-ray detection apparatus can be improved.

1 is a view showing an X-ray imaging system according to an embodiment of the present invention.
FIG. 2 is a view showing the digital X-ray detection apparatus of FIG. 1 .
FIG. 3 is a plan view of a part of the array panel of FIG. 2 .
FIG. 4 is a plan view of a pixel area of any one of the array panels of FIG. 3 .
FIG. 5 is a diagram illustrating II′ of FIG. 3 .
6 to 16 are views illustrating a plan view and a cross-section taken along I-I′ in some processes when an array panel is manufactured according to an embodiment of the present invention.

The above-described objects, features and advantages will be described below in detail with reference to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the present invention pertains will be able to easily implement the technical idea of the present invention. In describing the present invention, if it is determined that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

In the following, that an arbitrary component is disposed on the "upper (or lower)" of a component or "upper (or below)" of a component means that any component is disposed in contact with the upper surface (or lower surface) of the component. Furthermore, it may mean that other components may be interposed between the component and any component disposed on (or under) the component.

Also, when it is described that a component is "connected", "coupled" or "connected" to another component, the components may be directly connected or connected to each other, but other components are "interposed" between each component. It is to be understood that “or, each component may be “connected,” “coupled,” or “connected” through another component.

Hereinafter, a digital X-ray detection apparatus and an array panel provided therein according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, an X-ray imaging system and a digital X-ray detection device provided therein will be described with reference to FIGS. 1 and 2 .

1 is a view showing an X-ray imaging system according to an embodiment of the present invention. FIG. 2 is a view showing the digital X-ray detection apparatus of FIG. 1 .

As shown in FIG. 1 , the X-ray imaging system 10 is for providing an X-ray image of the inside of a predetermined target object 20 . For example, the target object 20 may be a part of a living body to be tested or a part of an industrial process product to be tested.

The X-ray imaging system 10 faces the digital X-ray detection apparatus 11 with the digital X-ray detection device 11 for detecting the amount of transmission of X-rays, and the digital X-ray detection apparatus 11 with the target object 20 interposed therebetween, and the X-ray (X) toward the target object 20 side. -ray) includes a light source device 12 for irradiating.

The digital X-ray detection apparatus 11 may be formed in the form of a flat panel including a sensing area for detecting the amount of X-rays transmitted to the target object 20 .

As shown in FIG. 2 , the digital X-ray detection apparatus 11 includes an array panel 100 including a plurality of pixel areas PA arranged in a matrix form in a detection area (DA).

In addition, the digital X-ray detection device 11 includes a readout driver (RD), a gate driver (GD), a bias driver (BD), and a timing controller (TC) for driving the array panel 100 . ; Timing Controller).

Although not shown in detail in FIG. 2 , the gate driver GD and the bias driver BD, which are relatively simple circuits compared to the readout driver RD, may be embedded in the array panel 100 .

Each pixel area PA of the array panel 100 has a photo-sensing device PD that senses light and a switching transistor ST disposed between the photo-sensing device PD (Photo Diode) and the data line DL. ) is included.

The array panel 100 is connected to the gate line GL and the data line DL connected to the switching transistor ST of each pixel area PA, and the photosensitive device PD of each pixel area PA. and a bias line BL.

For example, the gate line GL may be disposed in a first direction (horizontal direction, left and right direction in FIG. 2 ) of the array panel 100 . That is, the gate line GL corresponds to a horizontal line formed of the pixel areas PA arranged in parallel in the first direction among the plurality of pixel areas PA, respectively. Accordingly, the gate line GL is connected to the switching transistor ST of the pixel areas PA arranged in parallel in the first direction among the plurality of pixel areas PA.

The data lines DL may be disposed in the second direction (vertical direction and vertical direction in FIG. 2 ) of the array panel 100 . That is, the data line DL corresponds to a vertical line each of the pixel areas PA arranged in parallel in the second direction among the plurality of pixel areas PA. Accordingly, the data line DL is connected to the switching transistor ST of the pixel areas PA arranged in parallel in the second direction among the plurality of pixel areas PA.

The bias line BL is disposed in a mesh shape that corresponds to the first and second directions and surrounds the outer edges of the plurality of light sensing devices PD corresponding to the plurality of pixel areas PA.

In addition, the array panel 100 further includes a scintillator ( 140 of FIG. 5 ) disposed on a surface facing the light source device ( 12 of FIG. 1 ).

The scintillator 140 is disposed between the light source device 12 and the light sensing device PD, and converts X-rays emitted from the light source device 12 into visible light to be applied to the light sensing device PD. supply

A first electrode (for example, an anode electrode) of the photosensitive devices PD disposed in each pixel region P is connected to the switching transistor ST, and a second electrode (for example, a cathode electrode) is biased. It may be connected to the line BL.

The light sensing device PD absorbs visible light supplied from the scintillator 140 and generates electrons in response to the visible light, thereby generating a sensing signal corresponding to the amount of X-ray transmission in each pixel area PA.

When the switching transistor ST is turned on based on the gate signal of the gate line GL, the switching transistor ST transmits the sensing signal of the light sensing device PD to the data line DL.

The timing controller TC supplies the start signal STV and the clock signal CPV for controlling the driving timing of the gate driver GD to the gate driver GD. In addition, the timing controller TC supplies the readout control signal ROC and the readout clock signal CLK for controlling the driving timing of the readout driver RD to the readout driver RD.

The gate driver GD sequentially supplies a gate signal for turning on the switching transistor ST of the pixel areas PA included in each horizontal line to each gate line GL.

The bias driver BD supplies a bias signal corresponding to a predetermined bias power to the bias line BL. In this case, the bias driver BD may selectively supply a bias signal for a reverse bias operation or a bias signal for a forward bias operation.

The readout driver RD receives the sensing signal of each pixel area PA included in each horizontal line through the data line DL during each horizontal period, and receives the sensing signal of each pixel area PA corresponding to the vertical period. A video signal is generated based on the sensing signal.

Illustratively, the readout driver RD amplifies the sensing signal, performs correction to remove the noise signal from the amplified sensing signal, converts the corrected sensing signal into a digital signal, and then converts the image from the combination of digital signals. signal can be generated. Here, the image signal may be a signal representing luminance values corresponding to the plurality of pixel areas PA as bit information.

Next, an array panel 100 for a digital X-ray detector according to an embodiment of the present invention will be described with reference to FIGS. 3, 4 and 5 .

FIG. 3 is a view showing a plan view of a part of the array panel of FIG. 2 , and FIG. 4 is a view showing a plan view of a pixel area of any one of the array panels of FIG. 3 . FIG. 5 is a diagram illustrating II′ of FIG. 3 .

As shown in FIG. 3 , the array panel 100 includes a plurality of pixel areas PA arranged in a matrix in the sensing area (DA in FIG. 2 ).

The array panel 100 includes a plurality of photo-sensing devices PD corresponding to the plurality of pixel areas PA and a bias line BL disposed in a mesh shape surrounding the outside of the plurality of photo-sensing devices PD. do.

The bias line BL is disposed on at least one insulating layer covering the plurality of photosensitive devices PD.

Accordingly, as shown in FIG. 4 , the plurality of photo-sensing devices PD includes a bias contact hole (BH) penetrating at least one insulating layer and a bias bridge disposed on the same layer as the bias line BL. (BB; Bias Bridge) is connected to the bias line (BL).

In addition, the array panel 100 has a plurality of switching transistors ST corresponding to the plurality of pixel areas PA and connected to the plurality of photo-sensing devices PD, in a first direction (left-right direction and horizontal direction in FIG. 3 ). It further includes a gate line GL disposed as , and a data line DL disposed in a second direction (vertical direction and vertical direction in FIG. 3 ) intersecting the first direction.

Each gate line GL is connected to the switching transistor ST of the pixel areas PA arranged in parallel in the first direction among the plurality of pixel areas PA.

The gate line GL overlaps the light sensing device PD of the pixel areas PA arranged in parallel in the first direction.

In other words, the gate line GL disposed first from the top of FIG. 3 crosses the pixel areas PA of the first row. Accordingly, each of the light sensing devices PD of the pixel areas PA of the first row at least partially overlaps the first gate line GL.

That is, each photo-sensing device PD overlaps a portion of one of the gate lines GL.

At this time, since the bias line BL is disposed outside the photo-sensing device PD, and the gate line GL is disposed in the first direction in a region overlapping the photo-sensing device PD, the bias line BL and The overlapping region between the gate lines GL may be limited to only a region where the bias line BL in the second direction and the gate line GL in the first direction cross each other. Therefore, the parasitic capacitance between the bias line BL and the gate line GL may be minimized.

For example, as shown in FIG. 4 , the gate electrode of the switching transistor ST may be formed of a partial region protruding in the second direction among the gate lines GL in the first direction.

Each data line DL is connected to the switching transistor ST of the pixel areas PA arranged in parallel in the second direction among the plurality of pixel areas PA.

The data line DL overlaps the light sensing device PD of the pixel areas PA arranged in parallel in the second direction.

In other words, the data line DL disposed first from the left in FIG. 3 crosses the pixel areas PA of the first column. Accordingly, each of the light sensing devices PD of the pixel areas PA of the first column at least partially overlaps the first data line DL.

That is, each light sensing device PD overlaps a portion of any one data line DL.

At this time, since the bias line BL is disposed outside the photo-sensing device PD, and the data line DL is disposed in the second direction in a region overlapping the photo-sensing device PD, the bias line BL and The overlapping area between the data lines DL may be limited to only a region where the bias line BL in the first direction and the data line DL in the second direction cross each other. Therefore, the parasitic capacitance between the bias line BL and the data line DL may be minimized.

For example, as shown in FIG. 4 , any one of the source and drain electrodes of the switching transistor ST may be formed of a partial region protruding in the first direction among the data lines DL in the second direction.

As shown in FIG. 4 , in any one pixel area PA, the photosensitive device PD at least partially overlaps each of the gate line GL and the data line DL in the second direction in the first direction. , an outer portion of the light sensing device PD is surrounded by a mesh-shaped bias line BL.

In addition, in any one pixel area PA, the switching transistor ST may be disposed at an intersection area between the gate line GL and the data line GL.

As shown in FIG. 5 , the array panel 100 includes a switching transistor ST disposed on a substrate 101 , at least one first insulating layer 111 , 112 covering the switching transistor ST, and at least The photo-sensing device PD disposed on one first insulating layer 111, 112, at least one second insulating layer 121, 122 covering the photo-sensing device PD, and at least one second insulating layer ( A bias line BL disposed on the 121 and 122 may be included.

The array panel 100 further includes at least one third insulating layer 131 and 132 covering the bias line BL, and a scintillator 140 disposed on the at least one third insulating layer 131 and 132 . may include

The switching transistor ST includes an active layer ACT disposed on the substrate 101 and a gate electrode GE disposed on a gate insulating layer 102 covering a portion of the active layer ACT.

In addition, the switching transistor ST further includes a source electrode SE and a drain electrode DE disposed on the active layer ACT, the gate insulating layer 102 , and the interlayer insulating layer 103 covering the gate electrode GE. can do.

The substrate 101 may be made of an insulating material such as glass. Alternatively, the substrate 101 may be formed of a flexible insulating material such as polyethylene terephthalate (PET), ethylene naphthalate (PEN), polyimide (PI), polymethyl methacrylate (PMMA), polycarbonate (PC), polystyrene (PS), and polyethersulfone (PES). may be made of

In order to more easily fix the semiconductor material or the inorganic material on the substrate 101 , the array panel 100 may further include a buffer layer 101 ′ disposed entirely on the substrate 101 . That is, the buffer layer 101 ′ is disposed between the substrate 101 and the active layer ACT.

For example, the buffer layer 101 ′ may be made of an inorganic insulating material such as SiNx or SiO.

The active layer ACT includes a channel region and a source region and a drain region disposed on both sides of the channel region.

For example, the active layer ACT may be formed of any one of an amorphous silicon material, a low temperature polycrystaline silicon (LTPS) material, and an oxide semiconductor material.

The gate electrode GE is disposed on the gate insulating layer 102 covering the channel region of the active layer ACT.

In other words, the gate electrode GE overlaps the channel region of the active layer ACT, and the gate insulating layer 102 is disposed between the active layer ACT and the gate electrode GE.

As shown in FIG. 4 , the gate electrode GE is formed of a partial region protruding in the second direction among the gate lines GL in the first direction. Accordingly, the gate line GL is disposed on the same layer as the gate electrode GE. That is, the gate line GL is disposed on the gate insulating layer 102 .

The source electrode SE is connected to the source region of the active layer ACT through a source contact hole SH passing through the interlayer insulating layer 103 .

Similarly, the drain electrode DE is connected to the source region of the active layer ACT through a drain contact hole DH penetrating the interlayer insulating layer 103 .

One of the source electrode SE and the drain electrode DE (in FIG. 5, the source electrode SE) is connected to the data line DL, and the other one (in FIG. 5, the drain electrode DE) is connected to the data line DL. It is connected to the light sensing device (PD).

For example, as shown in FIG. 4 , the source electrode SE may be formed of a partial region protruding in the first direction among the data lines DL in the second direction. Accordingly, the data line DL is disposed on the same layer as the source electrode SE.

That is, the data line DL is disposed on the interlayer insulating layer 103 .

The source electrode SE, the drain electrode DE, and the data line DL are covered with at least one first insulating layer 111 and 112 disposed on the interlayer insulating layer 103 . The at least one first insulating layer 111 and 112 includes a first planarization layer 111 covering the source electrode SE, the drain electrode DE, and the data line DL, and a first planarization layer on the first planarization layer 111 . A protective layer 112 may be included.

The first planarization layer 111 may be formed of an insulating material that can be stacked to a thickness greater than or equal to a threshold in order to provide a flat surface regardless of the shape of the wiring or pattern disposed thereunder. For example, the first planarization layer 111 may be formed of an organic insulating material such as an acrylic resin such as photo acryl (PAC). Alternatively, the first planarization layer 111 may be formed of a photo resist (PR) or the like.

The first passivation layer 112 may be formed of an inorganic insulating material such as SiNx or SiO. Since penetration of moisture or oxygen may be prevented due to the first passivation layer 112 , the semiconductor characteristics of the active layer ACT may be protected.

The first electrode E1 of the photosensitive device PD is disposed on the first passivation layer 112 . Therefore, fixation of the first electrode 121 may be strengthened due to the first passivation layer 112 made of the inorganic insulating material.

The photosensitive device PD includes first and second electrodes E1 and E2 , and a PIN layer PIN disposed between the first and second electrodes E1 and E2 .

The first electrode E1 corresponds to each pixel area PA and is disposed on at least one first insulating layer 111 and 112 . The first electrode E1 may be disposed in an area as wide as possible among the pixel areas PA in consideration of the fill factor.

Illustratively, the first electrode 121 is a single layer made of an opaque metal such as molybdenum (Mo) or a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO) and zinc oxide (ZnO). It may be a multi-layer structure.

The PIN layer PIN is disposed on the first electrode E1 .

The PIN layer (PIN) is an N (Negative) semiconductor layer containing N-type impurities, an I (Intrinsic) semiconductor layer containing no impurities, and a P (Positive) type semiconductor layer containing P-type impurities in sequence. It may have a stacked structure. Here, the I-type semiconductor layer may be formed to be relatively thicker than the N-type semiconductor layer and the P-type semiconductor layer. The PIN layer (PIN) may have a thickness of about 1 μm.

Illustratively, the PIN layer (PIN) includes a material capable of converting X-rays emitted from the light source device (12 of FIG. 1 ) into electrical signals. For example, the PIN layer PIN may include _{at least one of a-Se, HgI 2} , CdTe, PbO, PbI ₂ , BiI ₃ , GaAs, and Ge.

The second electrode E2 is disposed on the PIN layer PIN.

The second electrode E2 is made of a transparent conductive material to prevent a decrease in the amount of light incident on each PIN layer PIN and a decrease in the fill factor of each pixel area PA.

For example, the second electrode E2 may be formed of any one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO).

The light sensing device PD may be covered with at least one second insulating layer 121 and 122 disposed on the first passivation layer 112 .

For example, the at least one second insulating layer 121 and 122 may include a second passivation layer 121 covering each photo-sensing device PD, and a second planarization layer 122 on the second passivation layer 121 . can

The second passivation layer 121 may be formed of an inorganic insulating material such as SiNx or SiO.

The second planarization layer 122 may be formed of an organic insulating material such as an acrylic resin such as photo acryl (PAC) or a photo resist (PR).

The bias line BL is disposed on the at least one second insulating layer 121 and 122 and corresponds to a spaced region between the photosensitive devices PD.

That is, the bias line BL may be disposed on the second planarization layer 122 .

In addition, each photo-sensing device PD is formed through a bias contact hole BH passing through at least one of the second insulating layers 121 and 122 and a bias bridge BB disposed on the same layer as the bias line BL. It is connected to the bias line BL.

The bias contact hole BH exposes at least a portion of the second electrode E2 of the photosensitive device PD.

The bias bridge BB is in contact with a portion of the second electrode E2 exposed by the bias contact hole BH and a portion of the bias line BL, respectively, and a bias line BL from a portion of the second electrode E2. extended to For example, the bias bridge BB may be disposed in at least one of the first and second directions.

4 illustrates that the bias bridge BB is disposed in the second direction parallel to the gate line GL.

The bias line BL and the bias bridge BB may be covered with at least one third insulating layer 131 and 132 disposed on the second planarization layer 122 .

The at least one third insulating layer 131 and 132 may include a third passivation layer 131 covering the bias line BL and the bias bridge BB, and a third planarization layer 132 on the third passivation layer 131 . can

The third passivation layer 131 may be formed of an inorganic insulating material such as SiNx or SiO.

The third planarization layer 132 may be formed of an organic insulating material such as an acrylic resin such as photo acryl (PAC) or a photo resist (PR).

The scintillator 140 is disposed on at least one third insulating layer 131 and 132 . That is, the scintillator 140 may be disposed on the third planarization layer 132 .

The scintillator 140 converts X-rays into visible light.

The scintillator 140 may have a columnar structure. For example, the scintillator 140 may be formed of CsI:Tl (Cesium iodide: Talluim doped).

As described above, the array panel 100 for a digital X-ray detection device according to an embodiment of the present invention includes a mesh-shaped bias line BL surrounding the outer edges of the plurality of light sensing devices PD. Accordingly, since the overlapping area between the photo-sensing device PD and the bias line BL is removed, a decrease in the fill factor due to the overlapping area between the photo-sensing device PD and the bias line BL may be prevented. Thereby, the influence of the resolution on the fill factor can be eliminated.

In addition, the array panel 100 for a digital X-ray detection apparatus according to an embodiment of the present invention includes a gate line GL and a data line DL that at least partially overlap each photo-sensing device PD. Accordingly, the parasitic capacitance between each of the gate line GL and the data line DL and the bias line BL may be minimized. Thereby, signal distortion due to the parasitic capacitance between lines can be prevented.

As such an array panel 100 is included, the digital X-ray detection apparatus 11 has an advantage of providing a more accurate and clear image signal.

Next, a manufacturing process of the array panel 100 according to an exemplary embodiment of the present invention will be described with reference to FIGS. 6 to 16 .

6 to 16 are views illustrating a plan view and a cross-section taken along I-I′ in some processes when an array panel is manufactured according to an embodiment of the present invention.

The arrangement method or formation method of each component described below is a technique performed by a person skilled in the art, deposition (Deposition), photoresist coating (PR Coating), exposure (Exposure), developing (Develop), etching ( Etch), a photolithography (Photoliyhography) process including a photoresist stripping (PR Strip) is used, and a detailed description thereof will be omitted. For example, in the case of deposition, methods such as sputtering for metal materials and plasma enhanced vapor deposition (PECVD) for semiconductors or insulating films can be divided and used. A technique performed by a person skilled in the art may be applied as it can select and use etching and wet etching.

6 and 7 , after the substrate 101 is prepared and the buffer film 101 ′ is entirely disposed on the substrate 101 , the switching transistor ST is formed on the buffer film 101 ′. and a gate line GL and a data line DL are disposed.

Specifically, the active layer ACT corresponding to a partial area of each pixel area PA is formed by patterning the semiconductor material on the buffer layer 101 ′.

The gate insulating layer 102 covering the channel region of the active layer ACT and the gate electrode on the gate insulating layer 102 by patterning the insulating material and the conductive material disposed on the buffer layer 101 ′ and covering the active layer ACT. (GE) is formed. In addition, the gate line GL in the first direction is formed on the same layer as the gate electrode GE, that is, on the gate insulating layer 102 . The gate line GL is disposed in the first direction and crosses the pixel area PA.

An interlayer insulating layer 103 covering the active layer ACT, the gate insulating layer 102 and the gate electrode GE is formed on the buffer layer 101'.

The interlayer insulating layer 103 is patterned to form a source contact hole SH and a drain contact hole DH exposing a portion of each of the source region and the drain region of the active layer ACT.

A source electrode SE, a drain electrode DE, and a data line DL are formed by patterning a conductive material on the interlayer insulating layer 103 .

The data line DL is disposed on the interlayer insulating layer 103 in the second direction and crosses the pixel area PA.

The source electrode SE may be formed as a part of the data line DL, and is connected to the source region of the active layer ACT through the source contact hole SH.

The drain electrode DE may have a pattern spaced apart from the source electrode SE, and is connected to the drain region of the active layer ACT through the drain contact hole DH.

Accordingly, a switching transistor ST corresponding to each pixel area PA and including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE is provided.

As shown in FIGS. 8 and 9 , after at least one first insulating film 111 and 112 covering the switching transistor ST is disposed, the photosensitive device PD is formed on the first insulating film 112 . One electrode E1 is disposed.

Specifically, after the first planarization layer 111 covering the source electrode SE, the drain electrode DE, and the data line DL is formed on the interlayer insulating layer 103, the first planarization layer 111 is patterned to A pixel contact hole PH is formed primarily.

Subsequently, after the first passivation layer 112 is formed on the first planarization layer 111 , the first passivation layer 112 in the region corresponding to the primary pixel contact hole PH is patterned to finally the pixel contact hole PH. ) is formed. In this case, the pixel contact hole PH passes through at least one of the first insulating layers 111 and 112 and exposes at least a portion of the drain electrode DE.

Next, a conductive material on the first passivation layer 112 is patterned to form a first electrode E1 corresponding to each pixel area PA. The first electrode E1 is connected to the drain electrode DE through the pixel contact hole PH.

10 and 11, a semiconductor material and a conductive material disposed on the first passivation layer 112 and covering the first electrode E1 are patterned to form a PIN layer (PIN) on the first electrode E1. and a second electrode E2 on the PIN layer PIN. Accordingly, the photo-sensing device PD including the first electrode E1 , the PIN layer PIN and the second electrode E2 is provided.

12 and 13 , an insulating material disposed on the first passivation layer 112 and covering the photosensitive device PD is patterned to form a second passivation layer 121 .

The second passivation layer 121 covers only the photo-sensing device PD and does not overlap at least the switching transistor ST. In this way, deterioration in characteristics of the transistor ST due to the second passivation layer 121 may be prevented.

Then, a bias contact hole BH is formed primarily by patterning the second passivation layer 121 .

Next, after the second planarization layer 122 covering the second passivation layer 121 is formed on the first passivation layer 112 , the second planarization layer 122 in the region corresponding to the primary bias contact hole BH is formed. By patterning, a bias contact hole BH is finally formed. In this case, the bias contact hole BH penetrates the at least one second insulating layer 121 and 122 and exposes at least a portion of the second electrode E2 .

14 and 15 , a bias line BL is formed by patterning a conductive material on the second planarization layer 122 .

The bias line BL has a mesh shape corresponding to the outer edge of the light sensing device PD and extending in the first and second directions. As a result, an overlapping region between the photosensitive device PD and the bias line BL can be excluded, so even if the bias line BL is made of a low-resistance conductive material, the photosensitive device PD and the bias line BL ) can be prevented from reducing the fill factor due to the overlapping area between them.

Then, a conductive material disposed on the second planarization layer 122 and covering the bias line BL is patterned to form a bias bridge BB.

In this case, the bias bridge BB contacts a portion of the bias line BL, extends into the bias contact hole BH, and contacts the second electrode E2 through the bias contact hole BH. Accordingly, the second electrode E2 may be connected to the bias line BL through the bias bridge BB and the bias contact hole BH.

In this case, the bias bridge BB overlaps the photo-sensing device PD. Accordingly, in order to reduce the degree of decrease in the fill factor caused by the bias bridge BB, the bias bridge BB may be formed of a transparent conductive material.

16 , at least one third insulating layer 131 and 132 covering the bias line BL and the bias bridge BB may be disposed on the second insulating layer 122 . The at least one third insulating layer 131 and 132 may include a third passivation layer 131 covering the bias line BL and the bias bridge BB, and a third planarization layer 132 on the third passivation layer 131 . can

Thereafter, as shown in FIG. 5 , a scintillator 130 may be disposed on the third planarization layer 116 .

Accordingly, the array panel 100 according to an embodiment of the present invention is provided.

As described above, the present invention has been described with reference to the illustrated drawings, but the present invention is not limited by the embodiments and drawings disclosed in the present specification. It is obvious that variations can be made. In addition, although the effects according to the configuration of the present invention are not explicitly described and described while describing the embodiments of the present invention, it is natural that the effects predictable by the configuration should also be recognized.

10: x-ray imaging system 20: object
11: digital x-ray detection device 12: light source device
100: array panel RD: readout driving unit
GD: Gate driver BD: Bias driver
TC: Timing Controller
DL: data line GL: gate line
BL: bias line PA: pixel area
PD: light sensing element ST: switching transistor
ACT: active layer
SE, DE: source electrode, drain electrode
SH, DH: source contact hole, drain contact hole
PH: pixel contact hole
E1: first electrode PIN: PIN layer
E2: second electrode BB: bridge pattern
BH: bias contact hole 103: interlayer insulating film
111, 112: first insulating film
121, 122: second insulating film
131, 132: third insulating film
140: scintillator

Claims (10)

An array panel for a digital X-ray detection device comprising a plurality of pixel regions, the array panel comprising:
a plurality of light sensing elements corresponding to the plurality of pixel areas; and
An array panel for a digital X-ray detection device comprising a bias line disposed in the form of a mesh surrounding the periphery of the plurality of light sensing elements.
2. The method of claim 1
a plurality of switching transistors corresponding to the plurality of pixel regions and connected to the plurality of light sensing devices;
a gate line connected to the switching transistor of the plurality of pixel regions arranged in parallel in a first direction; and
and a data line connected to the switching transistor of pixel regions arranged in parallel in a second direction crossing the first direction among the plurality of pixel regions.
3. The method of claim 2,
The gate line is an array panel for a digital X-ray detection device overlapping the photo-sensing element of the pixel areas arranged in parallel in the first direction.
3. The method of claim 2,
The data line is an array panel for a digital X-ray detection device overlapping the photo-sensing element of the pixel areas arranged in parallel in the second direction.
4. The method of claim 3,
The data line is an array panel for a digital X-ray detection device overlapping the photo-sensing element of the pixel areas arranged in parallel in the second direction.
3. The method of claim 2,
The switching transistor is
an active layer disposed on the substrate; and
a gate electrode disposed on a gate insulating film covering a portion of the active layer;
The gate line is disposed on the same layer as the gate electrode,
and the data line is disposed on the active layer, the gate insulating layer, and an interlayer insulating layer covering the gate electrode.
7. The method of claim 6,
the plurality of photo-sensing devices are disposed on at least one first insulating layer covering the data line;
The bias line is disposed on at least one second insulating film covering the plurality of photosensitive devices,
Each of the plurality of photo-sensing devices has a plurality of bias contact holes penetrating the at least one second insulating layer, and an array for a digital X-ray detection device connected to the bias line through a bias bridge disposed on the same layer as the bias line. panel.
8. The method of claim 7,
Each of the plurality of light sensing elements is
a first electrode disposed on the at least one first insulating film;
a PIN layer disposed on the first electrode; and
a second electrode disposed on the PIN layer;
the first electrode is connected to the transistor through a pixel contact hole penetrating the at least one first insulating layer;
and the second electrode is connected to the bias line through the bias contact hole and the bias bridge.
8. The method of claim 7,
at least one third insulating layer covering the bias line and the bias bridge;
The array panel for a digital X-ray detection device further comprising a scintillator disposed on an uppermost portion of the at least one third insulating layer.
The array panel according to any one of claims 2 to 9;
a gate driver supplying a gate signal to the gate line; and
and a readout driver receiving the sensing signal of each pixel region through the data line and generating an image signal based on the sensing signal of the plurality of pixel regions.

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