KR20210074684A - Circuit for preventing abnormal voltage of transmitter and control method of the transmitter - Google Patents

Abstract

The present invention relates to a transmitter excitation voltage prevention circuit that prevents an excitation voltage from being generated in a transmitter and thereby prevents an excitation voltage from being transmitted to a receiver. According to an embodiment of the present invention, an I/O voltage is first applied to a transmitter and then a core voltage is applied, and after the I/O voltage is applied, a driver is turned off before the core voltage is applied to prevent the output of the driver from being transmitted to a receiver.

Description

BACKGROUND ART Circuit for preventing abnormal voltage of transmitter and control method of the transmitter

The present invention relates to a transmitter excitation voltage prevention circuit and a transmitter control method for preventing a transmitter from generating an excitation voltage when a transmitter and a receiver are coupled.

The differential input/output (I/O) architecture of CMOS differential circuits applied to high-speed transmitters allows the transmitter to be AC or DC coupled to the receiver.

In the case of DC coupling, the output line of the transmitter is directly connected to the input line of the receiver so that any DC voltage of the output line of the transmitter can be provided to the input line of the receiver.

For AC coupling, the output line of the transmitter can be connected to the input line of the receiver through a series capacitor that acts as a DC breaker.

With AC coupling, the excitation voltage is not an issue because the capacitor acts as a DC block, but with DC coupling, the transmitter and receiver are directly connected, so if the transmitter transmits data before the receiver is ready, an excitation voltage problem may occur. have.

1 is a block diagram of a conventional transmitter and a receiver. The conventional transmitter 10 includes a level shifter 11 and a driver 12 .

The transmitter 10 applies the core voltage after applying the I/O voltage for stable power supply. When the core voltage is applied after the I/O voltage is applied to the level shifter 11, the output signal S0 can be adjusted to a logic high or a logic low with respect to the input signal, so that the driver 12 ) to adjust the driver output voltage (D_out).

At this time, in the conventional transmitter 10, after the I/O voltage is applied, the output of the level shifter is in an unknown state (hi-z) until the core voltage is applied. That is, after the I/O voltage is applied, the output of the level shifter 11 may be logic high or logic low until the core voltage is not applied, so that the output of the level shifter 11 is logic high. When the driver 12 is turned on, the excitation voltage from the transmitter 10 may be transferred to the receiver 20 .

In this way, when the transmitter and the receiver are DC-coupled, the conventional transmitter has an unwanted excitation voltage of the transmitter before the core voltage is applied when the supply order of the initial voltage is from the I/O voltage to the core voltage. There is a problem in that the transmission may cause malfunction of the receiver.

As a technology for processing induced voltage, for example, Korean Patent Registration No. 10-0891122 (Prior Document 1) discloses a timing controller reset circuit having a voltage induced voltage prevention circuit. In Prior Document 1, a circuit for removing an induced voltage applied to a timing controller reset circuit due to an LVDS output is disclosed. However, in the case of Prior Document 1, the cost increases by adding a transistor and a resistor to prevent the excitation voltage, and when the power supply voltage (DVCC) is changed, it is inconvenient to have to change the resistance value.

In addition, as another example, Korean Patent Registration No. 10-1119523 (Prior Document 2) discloses an excitation voltage blocking circuit for a liquid crystal display device. Prior Document 2 discloses a driving chip excitation voltage blocking circuit for preventing an abnormal operation of a driving chip due to an excitation voltage flowing into a driving chip for a display device. However, in the case of Prior Document 2, the cost increases by adding a transistor and a resistor to prevent an excitation voltage, and when a normal signal is applied, the signal may be distorted depending on the operating speed of the transistor. Also, there is a problem in that the excitation voltage may flow to RS by the parasitic diode of the transistor.

Furthermore, as a technique for processing an excitation voltage in a receiver, Prior Documents 1 and 2 do not disclose a technique for not generating an excitation voltage in the transmitter from the beginning.

(Prior Document 1) Korean Patent No. 10-0891122 (Prior Document 2) Korean Patent No. 10-1119523

An object of the present invention is to provide an excitation voltage prevention circuit of a transmitter that prevents the transmitter from generating an excitation voltage, and a method for controlling the transmitter.

An object of the present invention is to provide an excitation voltage prevention circuit of a transmitter and a control method of the transmitter, which prevent the receiver from generating an unwanted excitation voltage regardless of the supply order of the initial voltage when the transmitter and the receiver are DC-coupled have.

An object of the present invention is to provide an excitation voltage prevention circuit of a transmitter capable of preventing a receiver from malfunctioning by generating an unwanted excitation voltage in the receiver, and a method for controlling the transmitter.

An object of the present invention is to provide an excitation voltage prevention circuit of a transmitter that prevents an excitation voltage from being transmitted to a receiver and a control method of the transmitter.

The excitation voltage prevention circuit of the transmitter according to the embodiment of the present invention applies the I/O voltage to the transmitter first and then applies the core voltage, and turns off the driver after the I/O voltage is applied and before the core voltage is applied to the driver. It is possible to prevent the output from being delivered to the receiver. This is to prevent unwanted excitation voltage from being transmitted from the transmitter to the receiver when the transmitter is DC-coupled to the receiver.

To this end, the excitation voltage prevention circuit of the transmitter according to the present invention includes a power on control (POC), and outputs a logic high signal when an I/O voltage is applied to the POC, and a logic low signal is driven by a NOT gate. output to turn off the driver until the core voltage is applied.

After that, when the core voltage is applied, the clock CLK is output from the controller so that the power control unit outputs a logic low signal and a logic high signal is output to the driver by the NOT gate. After the core voltage is applied, the driver is turned on to turn on the driver. The output can be directed to the receiver. In this case, the core voltage is applied and the transmitter and receiver operate normally.

The excitation voltage prevention circuit of the high-speed transmitter according to the embodiment of the present invention has the following effects.

First, according to the present invention, it is possible to prevent the excitation voltage from being transmitted from the transmitter to the receiver by not generating the excitation voltage in the transmitter.

Second, according to the present invention, since the transmitter prevents the receiver from generating an unwanted excitation voltage regardless of the supply order of the initial voltage, malfunction due to the excitation voltage in the receiver can be prevented.

Third, according to the present invention, it is possible to prevent the excitation voltage from being generated from the beginning in the transmitter with a simple circuit configuration.

Fourth, according to the present invention, when the transmitter and the receiver are DC-coupled, the excitation voltage does not occur from the transmitter to the receiver even before the core voltage is applied after the I/O voltage is applied, so that malfunction of the receiver due to the excitation voltage can be prevented. have.

1 is a block diagram of a transmitter connected to a receiver in the related art;
2 is a block diagram of an excitation voltage prevention circuit of a transmitter connected to a receiver according to an embodiment of the present invention;
3 is a time chart showing the operation of the excitation voltage prevention circuit of the transmitter according to the embodiment of the present invention.
4 is a flowchart illustrating a method for controlling a transmitter according to an embodiment of the present invention;

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a connection structure between a transmitter and a receiver according to an embodiment of the present invention.

Referring to FIG. 2 , a transmitter 100 according to an embodiment of the present invention may be DC-coupled to a receiver 200 . When the transmitter 100 is DC-coupled to the receiver 200, the output line of the transmitter 100 is directly connected to the input line of the receiver 200 so that all DC voltages of the output lines of the transmitter 100 are applied to the receiver 200 may be provided on the input line of

In this case, if an excitation voltage is generated in the transmitter 100 , an unwanted excitation voltage may be applied to the receiver 200 to cause a malfunction. Accordingly, in the embodiment of the present invention, it is possible to prevent the transmitter 100 from generating such an excitation voltage in advance.

The transmitter 100 and the receiver 200 according to the present embodiment may be applied to various devices and systems. For example, it can be applied to a display device that transmits and receives an image signal.

The transmitter 100 according to this embodiment includes a controller (System on Chip, SoC) 110 , a clock detector 120 , a power on control (POC) 130 , and a NOT gate 140 . , the driver 140 may be included.

In the transmitter 100 , the core voltage may be applied after the I/O voltage is applied in order to supply a stable initial voltage. That is, the core voltage may be applied after a predetermined time after the I/O voltage is initially applied first. The predetermined time may be, for example, several ms. Of course, the predetermined time may be changed according to the specification of the transmitter.

The controller (SoC) 110 controls the overall operation of the transmitter 100 . In this embodiment, the controller 110 outputs the clock signal CLK when the core voltage is applied. The clock signal CLK may be a signal for synchronizing when an input signal (not shown) is output.

The clock detection unit 120 operates when an I/O voltage is applied to detect whether the clock signal CLK is output from the controller 110 . When the clock detection unit 120 detects that the clock signal is output from the controller 110 , the clock detection unit 120 outputs the output signal S1 as a logic high signal. If the clock signal is not detected, a logic low signal is output.

The power control unit 130 outputs a logic high output signal S2 when the I/O voltage is applied. In this case, the power control unit 130 outputs a logic high signal when the output signal S1 of the clock detection unit 120 is a logic low signal, and outputs a logic low signal when the output signal S1 is a logic high signal.

The NOT gate 140 inverts and outputs the output signal S2 output from the power control unit 140 . That is, if the output signal S2 is a logic high signal, it is inverted to output a logic low signal, and if the output signal S2 is a logic low signal, it is inverted to output a logic high signal. The output signal of the NOT gate 140 is represented by S3. The driver 150 may be turned on/off by the output of the NOT gate 140 .

The driver 150 outputs the signal of the transmitter 100 to the receiver 200 . The receiver 200 may operate according to the output signal of the driver 150 .

Hereinafter, the operation of the transmitter 100 according to the application of the I/O voltage and the core voltage will be described in detail. As described above, an example in which the I/O voltage is initially applied to the transmitter 100 according to the present invention to supply a stable initial voltage and then the core voltage is applied thereafter will be described.

First, the operation of the transmitter 100 before the I/O voltage is applied and the core voltage is applied will be described.

When I/O voltage is applied (before core voltage is applied)

When an I/O voltage is initially applied to the power control unit 130 , the power control unit 130 operates and the power control unit 130 outputs the control signal S2 as a logic high signal. At this time, since the I/O voltage is applied first and before the core voltage is applied, the controller 110 does not output the clock signal CLK. Accordingly, the clock detection unit 120 does not detect the clock signal CLK and the output signal S1 becomes a logic low. The logic high control signal S2 output from the power control unit 130 is converted into a logic low signal S3 through the NOT gate 140 and is output.

The logic low signal S3 output from the NOT gate 140 is input to the driver 150 . The driver 150 is turned off when the logic low signal S3 is input. When the driver 150 is turned off, the output D_out of the driver 150 is not transferred to the receiver 200 .

As such, when the I/O voltage is applied to the transmitter 100 , the driver 150 is turned off until the core voltage is applied, so that the excitation voltage generated in the transmitter 100 is not transmitted to the driver 150 at all.

Next, the operation of the transmitter 100 when the core voltage is applied after the I/O voltage is applied will be described.

When core voltage is applied (after I/O voltage is applied)

When the core voltage is applied after the I/O voltage is applied, the controller 110 outputs the clock signal CLK. When the clock signal CLK is output, the clock detection unit 120 detects the clock signal. The clock detection unit 120 outputs a logic high signal S1 when the clock signal is detected. This logic high signal S1 is input to the power control unit 130 .

When the logic high signal S1 is received by the power control unit 130, the logic high signal S2 output as described above is converted into a logic low signal. That is, the power control unit 130 outputs the logic high signal S2 when the I/O voltage is applied as described above, but when the logic high signal S1 is input from the clock detection unit 120, the logic low signal S2 is to output

The logic low signal S2 output from the power control unit 130 is converted into a logic high signal S3 through the NOT gate 140 and is output. The logic high signal S3 output from the NOT gate 140 is input to the driver 150 .

The driver 150 is turned on when the logic high signal S3 is input. When the driver 150 is turned on, the output D_out of the driver 150 is transmitted to the receiver 200 .

The output D_out of the driver 150 may be various control signals and operation signals (not shown) input from the controller 110 . For example, when the transmitter 100 and the receiver 200 of the present invention are applied to a display device, the output of the driver 150 may be an image signal and a control signal.

As described above, in the transmitter 100 according to the embodiment of the present invention, when the I/O voltage is applied and then the core voltage is applied to ensure the stability of the initial voltage supply, the driver 150 until the core voltage is applied. ) is turned off so that the excitation voltage of the transmitter 100 is not transferred to the receiver 200 . Thereafter, when the core voltage is applied, the driver 150 may be turned on to transmit necessary control signals and operating voltages from the transmitter 100 to the receiver 200 .

3 is a time chart showing the operation according to the voltage supply of the transmitter according to the embodiment of the present invention.

Referring to FIG. 3 , when an I/O voltage is applied from the transmitter 100 according to the embodiment of the present invention, the power control unit 130 operates so that the control signal S2 becomes a logic high signal (T1).

After a predetermined time (eg, several ms) after the application of the I/O voltage, the core voltage is applied (T2).

When the core voltage is applied to the controller 110 , the clock signal CLK is output. The clock signal CLK may be turned on/off at a set period. That is, the logic high and the logic low may be repeated at a set period.

When the clock signal CLK is output from the controller 110 , the clock detection unit 120 detects the clock signal. When the clock detection unit 120 detects the clock signal, it outputs a logic high signal S1 (T2).

This logic high signal S1 is input to the power control unit 130 . At this time, the power control unit 130 outputs the control signal S2 as a logic low signal. That is, when the I/O voltage is applied before the core voltage is applied, the power control unit 130 outputs the control signal S1 as a logic high signal, but as described above, the core voltage is applied and When the logic high signal S1 is input, the control signal S2 is converted into a logic high signal and output (T3).

As such, when the control signal S2 of the logic low signal is output from the power control unit 130 , the output of the NOT gate 140 becomes the logic high signal S3 . Accordingly, the logic high signal S3 is input to the driver 150, and the driver 150 is turned on (T2).

When the driver 150 is turned on, the output D_out of the driver 150 may be transmitted to the receiver 200 (T6).

4 is a flowchart illustrating an operation of a transmitter according to an embodiment of the present invention.

Referring to FIG. 4 , in the transmitter 100 according to an embodiment of the present invention, voltages may be initially supplied in the order in which I/O voltages are first applied and then core voltages are applied thereafter. Also, this transmitter 100 may be DC coupled to the receiver 200 .

When the I/O voltage is initially applied to the power control unit 130 (S101), the power control unit 130 operates and the control signal S2 becomes a logic high (S103).

This logic high signal S2 is converted into a logic low signal S3 by the NOT gate 140 (S105). The driver 150 is turned off by the logic low signal S3 output from the NOT gate 140 to prevent the excitation voltage from being generated (S107).

Thereafter, when the core voltage is applied (S109), the controller 110 outputs the clock signal CLK (S111). The clock signal CLK may repeat logic high/logic low according to a setting period.

When the clock detection unit 120 detects the clock signal CLK, it outputs a logic high signal S1 (S113). In addition, the power control unit 130 outputs a logic low control signal S2 according to the logic high signal S1 output from the clock detection unit 120 (S115).

That is, as described above, until the core voltage is applied, as the I/O voltage is applied to the power control unit 130 , the power control unit 130 operates and the control signal S2 becomes logic high (see S103 above). . However, as the core voltage is applied, the control signal S2 of the power control unit 130 is switched to a logic low.

The logic low control signal S2 output from the power control unit 130 is converted into a logic high signal S3 by the NOT gate 140 (S117). This logic high signal S3 is input to the driver 150 to turn on the driver 150 (S119). Accordingly, the output of the driver 150 may be transmitted to the receiver (S121).

As described above, in the present invention, for example, in a differential I/O structure that can be used in a CMOS differential circuit, when the transmitter is AC or DC coupled to the receiver, the excitation voltage is prevented from occurring in the transmitter, so that the receiver does not want the excitation voltage to prevent malfunction due to input of

In particular, in the transmitter of the present invention, when the I/O voltage is first applied and then the core voltage is applied for a stable initial voltage supply, it is designed to prevent the excitation voltage of the transmitter from being applied after the I/O voltage is applied and before the core voltage is applied. do. Therefore, when the transmitter is DC-coupled to the receiver, it is possible to remove the influence of the receiver due to the generation of the excitation voltage before the core voltage is applied to the transmitter, so that the receiver can realize stable operation.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: transmitter 110: controller
120: clock detection unit 130: power control unit
140: NOT gate 150: driver
200: receiver

Claims (11)

a controller outputting a clock signal CLK when a core voltage is applied;
a clock detection unit detecting a clock signal CLK output from the controller;
a power of control (POC) for outputting a control signal of a logic high or logic low signal depending on whether an I/O voltage is applied and the clock signal is detected;
a NOT gate for inverting the control signal output from the power control unit;
and a driver turned on/off according to the output signal of the NOT gate. According to claim 1,
An excitation voltage prevention circuit of a transmitter in which the I/O voltage is initially applied and the core voltage is applied after a predetermined time. 3. The method of claim 2,
After the I/O voltage is applied and before the core voltage is applied,
When the I/O voltage is applied to the power control unit, the power control unit outputs a first logic high signal, the first logic high signal is converted to a first logic low signal by the NOT gate, and the converted first logic signal An excitation voltage prevention circuit of a transmitter in which a low signal is input to the driver and the driver is turned off. 4. The method of claim 3,
When the core voltage is applied, the controller outputs a clock signal CLK, and when the clock detector detects the clock signal, outputs a second logic high signal. 5. The method of claim 4,
When the second logic high signal output from the clock detection unit is input, the power control unit outputs a second logic low signal, the second logic low signal is converted into a third logic high signal by the NOT gate, and the converted second logic high signal is input. 3 A circuit for preventing excitation voltage of a transmitter in which a logic high signal is input to the driver and the driver is turned on. 6. The method of claim 5,
When the driver is turned on, the output of the driver is transmitted to the receiver excitation voltage prevention circuit of the transmitter. 7. The method of claim 6,
The transmitter and the receiver are DC-coupled excitation voltage prevention circuit of the transmitter, characterized in that. applying an I/O voltage before the core voltage is applied to the transmitter;
outputting a fourth logic high signal from a power of control (POC) to a NOT gate when the I/O voltage is applied;
converting the fourth logic high signal into a third logic low signal at the NOT gate and outputting it to a driver;
and turning off the driver by the third logic low signal. 9. The method of claim 8,
When the driver is turned off, the excitation voltage control method of the transmitter is blocked from transmitting the excitation voltage of the transmitter to the receiver through the driver. 10. The method of claim 9,
The transmitter and the receiver are DC-coupled excitation voltage control method of the transmitter, characterized in that. 9. The method of claim 8,
After the driver is turned off,
outputting a clock signal CLK from a controller when the core voltage is applied;
outputting a fifth logic high signal to the power control unit when the clock detection unit detects the output of the clock signal CLK;
outputting, by the power control unit, a fourth logic low signal to the NOT gate when the fifth logic high signal is input;
converting the fourth logic low signal into a sixth logic high signal at the NOT gate and outputting it to a driver;
and turning on the driver by the sixth logic high signal.

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