KR20210060912A - Display device and driving method thereof - Google Patents

Abstract

Embodiments of the present invention relate to a display device and a driving method thereof. The display device comprises: a display unit including pixels and a timing control unit providing image data to be displayed in the pixels; a power management unit generating a driving voltage from an external input voltage and applying the driving voltage to the display unit; a reset signal supply unit applying a reset signal for starting or stopping operation of the timing control unit to the timing control unit; and a discharge circuit connected to an output terminal of the power management unit, and transmitting the driving voltage output to the output terminal to a ground electrode in response to the reset signal. Therefore, the output voltage of the power management unit can be prevented from being applied to the display unit.

Description

Display device and its driving method TECHNICAL FIELD

The present invention relates to a display device and a driving method thereof.

As the information society develops, various types of display devices are being developed. Recently, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

In general, a display device includes a power management integrated circuit (PMIC) that converts DC power generated from a power supply unit into a voltage suitable for driving the display unit and supplies it to the display unit. When the power of the display device is turned off, voltages output from the power management unit are naturally discharged to reach the ground voltage after being maintained for a certain period of time in order to prevent circuit damage due to a sudden voltage change.

Meanwhile, when the power of the display device is turned off, the timing controller that controls the image output of the display unit stops in response to a reset signal of a logic low level. If the timing control unit is stopped by the reset signal before the output voltages of the power management unit are completely discharged, the output voltages of the power management unit are abnormally applied to the display panel to recharge the pixels. This may cause an abnormal afterimage and flicker phenomenon of the display panel.

Embodiments provide a display device including a discharge circuit capable of immediately discharging a residual voltage output from a power management unit to a ground voltage when the display device is powered off, and a driving method thereof.

Embodiments provide a display device including a discharging circuit including a switching element whose on/off is controlled in response to a reset signal, and a driving method thereof.

A display device according to an exemplary embodiment includes: a display unit including pixels and a timing controller performing an operation for displaying an image on the pixels, a power management unit generating a driving voltage from an external input voltage and applying it to the display unit, The driving voltage is connected to a reset signal supply unit for applying a reset signal for starting or stopping an operation of the timing control unit to the timing control unit and an output terminal of the power management unit, and is output to the output terminal in response to the reset signal It may include a discharge circuit that transfers the power to the ground electrode.

When the input voltage is applied, the reset signal supply unit outputs a reset signal of a first level to start the operation of the timing control unit, and when the input voltage is not applied, the reset signal supply unit outputs a reset signal of a second level to the timing. It is possible to stop the operation of the control unit.

The discharge circuit may include a switching element connected between the output terminal of the power management unit and a ground electrode and turned on/off by the reset signal.

The switching element is turned off when the reset signal of the first level is applied, electrically separating the output terminal from the power management unit from the ground electrode, and is turned off when the reset signal of the second level is applied. -Is turned on, so that the output terminal of the power management unit and the ground electrode can be electrically connected.

When the input voltage is not applied, the power management unit may discharge the para-generated driving voltage to the output terminal.

When the operation of the timing controller is stopped in response to the reset signal of the second level, the discharge circuit may transmit the driving voltage discharged to the output terminal through the turned-on switching element to the ground electrode. .

The switching element may be a transistor having one electrode connected to the output terminal of the power management unit, the other electrode connected to the ground electrode, and receiving the reset signal through a gate electrode.

The discharge circuit may further include a discharge resistor connected between the switching element and the ground electrode.

The discharge circuit may further include a diode connected between the switching element and the discharge resistor and blocking a current flowing from the ground electrode to the output terminal of the power management unit.

In an embodiment, a display unit including pixels and a timing control unit, a power management unit that generates a driving voltage from an external input voltage and applies it to the display unit, a reset signal supply unit that applies a reset signal to the timing control unit, and the power management unit In the driving method of a display device including a discharge circuit connected to an output terminal of and including a switching element that is turned on/off in response to the reset signal, when the input voltage is applied, the power management unit generates the driving voltage. Applying to the display unit, the reset signal supply unit outputting a reset signal of a first level, and the timing controller performs an operation of displaying an image on the pixels in response to the reset signal of the first level. Initiating, by the discharging circuit, controlling the switching element to an off state in response to a reset signal of the first level; When the application of the input voltage is stopped, the power management unit discharging the previously generated driving voltage to the output terminal, the reset signal supply unit outputting a second level reset signal, the timing control unit, Stopping the operation in response to the reset signal of the second level, and controlling the switching element to be turned on in response to the reset signal of the second level by the discharge circuit.

The switching element may be connected between the output terminal and the ground electrode of the power management unit, and may electrically connect or disconnect the output terminal and the ground electrode in response to the on state and the off state, respectively.

The switching element may be a transistor having one electrode connected to the output terminal of the power management unit, the other electrode connected to the ground electrode, and receiving the reset signal through a gate electrode.

The discharge circuit may further include a discharge resistor connected between the switching element and the ground electrode.

The discharge circuit may further include a diode connected between the switching element and the discharge resistor and blocking a current flowing from the ground electrode to the output terminal of the power management unit.

The display device and its driving method according to the embodiments prevent the output voltage of the power management unit from being applied to the display unit by immediately discharging the output voltage of the power management unit to the ground voltage at the same time as switching the logic low level of the reset signal when the power is turned off. do.

The display device and its driving method according to embodiments may prevent abnormal afterimages and flicker of the display panel due to output voltages of the power management unit when the power is turned off.

1 is a block diagram showing a configuration of a general display device.
FIG. 2 is a circuit diagram illustrating an embodiment of the pixel illustrated in FIG. 1.
3 is a timing diagram of voltages applied to the display unit illustrated in FIG. 1.
4 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment.
5 is a circuit diagram of the discharge circuit shown in FIG. 4 according to the first embodiment.
6 and 7 are diagrams for explaining a method of controlling a current path of a discharge circuit using a reset signal.
8 is a circuit diagram of the discharge circuit shown in FIG. 4 according to a second embodiment.
9 is a circuit diagram of the discharge circuit shown in FIG. 4 according to a third embodiment.
10 is a timing diagram of voltages applied to a display unit according to an exemplary embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In this specification, when a component (or region, layer, portion, etc.) is referred to as "on", "connected", or "coupled" of another component, it is on the other component. It means that it may be directly connected/coupled or a third component may be disposed between them.

Terms such as first and second may be used to describe various constituent elements, but the constituent elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the rights of the present exemplary embodiments, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

"Comprise." Or "have." The terms such as, etc. are intended to designate the existence of features, numbers, steps, actions, components, parts, or a combination of them described in the specification, and one or more other features or numbers, steps, actions, components, parts, or It is to be understood that the possibility of the presence or addition of those combinations thereof is not preliminarily excluded.

1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment.

Referring to FIG. 1, the display device 1 may include a power supply unit 100, a power management unit 200, a reset signal supply unit 300, a panel discharge unit 400, and a display unit 500.

When the power of the display device 1 is turned on, the power supply unit 100 converts the input voltage Vin input from the outside to generate a digital driving voltage VCC and a ground voltage GND, and output the same. The input voltage Vin may have a magnitude of approximately 12V. The input voltage Vin rises from 0V to 12V when the power of the display device 1 is turned on to operate the power supply unit 100, and falls from 12V to 0V when the power of the display device 1 is turned off. Thus, the operation of the power supply unit 100 can be stopped.

The digital driving voltage VCC output from the power supply unit 100 is the power management unit 200, the reset signal supply unit 300, the panel discharge unit 400, and the display unit 500 (for example, the timing control unit 510). Can be supplied as In an embodiment, the digital driving voltage VCC may be about 3.3V, but is not limited thereto.

The power management unit 200 includes an analog driving voltage AVDD, a gate high voltage VGH, a gate low voltage VGL, and a common voltage from a digital driving voltage VCC and a ground voltage GND output from the power supply 100. (VCOM) can be created. The power management unit 200 may output the generated voltages to an output terminal.

Voltages output from the power management unit 200 are applied to the display unit 500 to drive the display unit 500. Specifically, the analog driving voltage AVDD may be applied to the data driver 530 of the display unit 500. The gate high voltage VGH and the gate low voltage VGL may be applied to the gate driver 520 of the display unit 500. The common voltage VCOM may be applied to the display panel 540 of the display unit 500.

The reset signal supply unit 300 may generate and output a reset signal RST for resetting the timing controller 510. The reset signal supply unit 300 may control the reset operation of the timing controller 510 together with the start and stop of the operation of the timing controller 510.

In an embodiment, when the power of the display device 1 is controlled to be turned on and the input voltage Vin is applied, the reset signal supply unit 300 may control the timing controller 510 to start the operation. The digital driving voltage VCC generated by converting the input voltage Vin gradually increases from 0V to reach a target voltage value after a predetermined time elapses (voltage stabilization). When the input voltage Vin is supplied, the reset signal supply unit 300 causes the timing control unit 510 to start the operation after a predetermined time required to generate the stabilized digital driving voltage VCC has elapsed. A reset signal RST of a logic high level may be applied.

In an embodiment, when the power of the display device 1 is controlled in an off state and application of the input voltage Vin is stopped, the reset signal supply unit 300 controls the operation stop and reset of the timing controller 510. . The reset signal supply unit 300 may control the timing controller 510 to stop an operation for outputting an image by applying a reset signal RST of a logic low level to the timing controller 510.

In an embodiment, the logic high level of the reset signal RST may be about 3.3V, and the logic low level may be about 0V. However, the present embodiment is not limited thereto.

The panel discharge unit 400 may apply a gate all-high signal ALL_H (eg, a gate all-high signal ALL_H of a logic low level) to the gate driver 520. Then, a gate-on voltage is applied to all the gate lines GL1 to GLn of the display panel 540 through the gate driver 520, so that transistors provided in the pixels PX may be turned on.

At the same time, the panel discharge unit 400 may apply data DSP for displaying black grayscale to the data driver 530. Then, a data voltage (eg, 0V) corresponding to the black grayscale may be applied to the pixels PX through the data driver 530 to display a black grayscale image. When the black grayscale image is displayed, the residual voltage charged in the pixels PX may be discharged. After a predetermined period of time has elapsed and the pixels PX are sufficiently discharged, a substantial display operation for displaying an image corresponding to the image signal RGB on the display panel 540 may be performed.

In an embodiment, the panel discharge unit 400 may perform the above-described panel discharge after the power of the display device 1 is controlled to the on state and after the power of the display device 1 is controlled to the off state. For example, the panel discharging unit 400 outputs a reset signal RST of a logic low level, and before the timing control unit 510 stops the operation, the black grayscale image is displayed on the display panel 540 for at least one frame. The gate driver 520 and the data driver 530 may be controlled to display.

The display unit 500 includes a timing controller 510, a gate driver 520, a data driver 530, and a display panel 540.

The timing control unit 510 is driven (controlled to an ON state) as the digital driving voltage VCC is applied from the power supply unit 100, and the operation can be started when a reset signal RST of a logic high level is applied. have. The timing controller 510 may receive an image signal RGB and a control signal CS from an external host or the like. The image signal RGB may include a plurality of grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

The timing controller 510 processes the image signal RGB and the control signal CS to be suitable for the operating condition of the display panel 540 to provide image data DATA, a gate driving control signal CONT1, and a data driving control signal. (CONT2) can be created and output.

The gate driver 520 may be connected to the pixels PX of the display panel 540 through a plurality of gate lines GL1 to GLn. The gate driver 520 may generate gate signals based on the gate driving control signal CONT1 output from the timing controller 510. At this time, the gate driver 520 generates a gate signal of a gate-on level based on a gate high voltage VGH applied from the power supply unit 100, and a gate signal of a gate off level based on the gate low voltage VGL. Can be created. The gate driver 520 may provide the generated gate signals to the pixels PX through the plurality of gate lines GL1 to GLn.

The data driver 530 may be driven when the analog driving voltage AVDD is applied from the power supply 100. The data driver 530 may be connected to the pixels PX of the display panel 540 through a plurality of data lines DL1 to DLm. The data driver 530 may generate data signals based on the image data DATA output from the timing controller 510 and the data driving control signal CONT2. The data driver 530 may provide the generated data signals to the pixels PX through the plurality of data lines DL1 to DLm.

A plurality of pixels PX are disposed on the display panel 540. The pixels PX may be arranged on the display panel 540 in a matrix form, for example.

In one embodiment, the display panel 540 is a color filter substrate on which a color filter array is formed, a TFT substrate on which a TFT array is formed, a color filter substrate and a liquid crystal layer including a liquid crystal, and a TFT substrate interposed between the color filter substrate and the TFT substrate. It may be a liquid crystal display panel including polarizing plates each attached to the outer side of the screen. However, the present embodiment is not limited thereto.

Each pixel PX may be electrically connected to a corresponding gate line and a data line. The pixels PX may emit light with a luminance corresponding to the gate signal and the data signal supplied through the gate lines GL1 to GLn and the data lines DL1 to DLm.

Each pixel PX may display any one of the first to third colors. In an embodiment, each pixel PX may display any one color of red, green, and blue. In another embodiment, each pixel PX may display any one color of cyan, magenta, and yellow. In various embodiments, the pixels PX may be configured to display any one of four or more colors. For example, each pixel PX may display any one color of red, green, blue, and white.

The timing controller 510, the gate driver 520, and the data driver 530 may each be configured as a separate integrated circuit (IC) or may be configured as an integrated circuit in which at least some of them are integrated. In addition, in FIG. 1, the gate driver 520 and the data driver 530 are shown as separate components from the display panel 540, but at least one of the gate driver 520 and the data driver 530 is the display panel 540. ) And may be configured in an In Panel method. For example, the gate driver 520 may be integrally formed with the display panel 540 according to a gate in panel (GIP) method.

According to an embodiment, the display panel 540 may be configured as an integrated touch panel that senses a touch input. In this embodiment, the display unit 500 may further include a touch driver. For example, the touch driver is formed integrally with the data driver 530 to form a touch display integrated circuit (TDDI). Can be implemented.

FIG. 2 is a circuit diagram illustrating an embodiment of the pixel illustrated in FIG. 1. 2 illustrates a pixel PXij connected to the i-th gate line GLi and the j-th data line DLj as an example.

The pixel PXij may be formed on the display panel 540 described with reference to FIG. 1. In one embodiment, the display panel 540 is a color filter substrate on which a color filter array is formed, a TFT substrate on which a TFT array is formed, a color filter substrate and a liquid crystal layer including a liquid crystal, and a TFT substrate interposed between the color filter substrate and the TFT substrate. It may be a liquid crystal display panel including polarizing plates each attached to the outer side of the screen.

Circuit elements such as a thin film transistor TFT and a storage capacitor Cst for driving the pixel PXij may be formed on the TFT substrate. Further, wirings (eg, the gate line GLi and the data line DLj) for applying a driving signal to the circuit elements may be further formed on the TFT substrate.

Referring to FIG. 2, the pixel PXij may include a thin film transistor TFT, a storage capacitor Cst, and a liquid crystal cell Clc.

One electrode of the thin film transistor TFT is connected to the j-th data line DLj, and the other electrode is connected to the pixel electrode PE. The gate electrode of the thin film transistor TFT is connected to the i-th gate line GLi. The thin film transistor TFT is turned on when a gate signal of a gate-on level is applied to the i-th gate line GLi, and transmits the data signal applied to the j-th data line DLj to the pixel electrode PE. .

The thin film transistor TFT may be an NMOS transistor or a PMOS transistor. Alternatively, the thin film transistor (TFT) may be implemented as a low temperature polysilicon (LTPS) thin film transistor, an oxide thin film transistor, or a low temperature polycrystalline oxide (LTPO) thin film transistor.

The storage capacitor Cst is connected between the pixel electrode PE and the Cs electrode SE to which the storage voltage is applied. The storage capacitor Cst may store a data voltage corresponding to the data signal when the thin film transistor TFT is turned on and a data signal is applied.

The liquid crystal cell Clc may include a pixel electrode PE, a common electrode CE, and a liquid crystal interposed between the pixel electrode PE and the common electrode CE. The liquid crystal cell Clc is driven by the data voltage stored in the storage capacitor Cst. Specifically, in response to a magnetic field formed by a data voltage stored in the storage capacitor Cst and supplied to the pixel electrode PE and a common voltage supplied to the common electrode CE, the liquid crystal of the liquid crystal cell Clc The orientation angle can be controlled.

The common electrode CE is formed on the color filter substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode. It may be formed on the TFT substrate together with the pixel electrode PE in the same horizontal electric field driving method. The common electrode CE receives a common voltage through a common voltage line.

3 is a timing diagram of voltages applied to the display unit illustrated in FIG. 1.

When the power of the display device 1 is controlled to be turned on, the input voltage Vin may be supplied from the outside. The power supply unit 100 converts the input voltage Vin and outputs a digital driving voltage VCC. The digital driving voltage VCC output from the power supply unit 100 may be supplied to the power management unit 200, the reset signal supply unit 300, and the panel discharge unit 400. Also, the digital driving voltage VCC may be applied to the timing controller 510 to control the timing controller 510 in a driving state.

When the input voltage Vin is applied from the outside, the reset signal supply unit 300 may output a reset signal RST of a logic high level after a predetermined time elapses. Here, the predetermined time may include a predetermined time t1 required for the digital driving voltage VCC to be output and stabilized from the power supply 100. The reset signal RST is applied to the timing controller 510 to control the timing controller 510 to an operation start state.

When the operation of the timing controller 510 is started, a gate all-high signal ALL_H of a logic low level may be output. The gate driver 520 applies a gate-on voltage to all of the gate lines GL1 to GLn by the gate all-high signal ALL_H. At the same time, a data voltage corresponding to the black gray level may be applied to the pixels PX through the data driver 530. Accordingly, a black grayscale image may be displayed on the display panel 540 for a period t2 of at least one frame, and a residual voltage precharged in the pixels PX may be discharged.

After the display panel 540 is discharged, the analog driving voltage AVDD, the gate high voltage VGH, the gate low voltage VGL, and the common voltage VCOM are transferred to the gate driver 520, the data driver 530, and It may be input to the display panel 540. Thereafter, the timing control unit 510 processes the image signal RGB and the control signal CS received from the outside to suit the operating conditions of the display panel 540, so that the image data DATA and the gate driving control signal CONT1 are processed. ) And a data driving control signal CONT2 may be generated and output. The gate driver 520 and the data driver 530 include image data DATA, a gate driving control signal CONT1 and a data driving control signal CONT2, a gate high voltage VGH, a gate low voltage VGL, and a common voltage. Based on (VCOM), the pixels PX are controlled to display an image corresponding to the image signal RGB.

When the power of the display device 1 is controlled to be in the off state, supply of the input voltage Vin from the outside may be stopped. Then, the output of the digital driving voltage VCC from the power supply unit 100 is stopped. The power management unit 200 does not perform voltage conversion, and the parasitic voltages (ie, analog driving voltage AVDD, gate high voltage VGH, gate low voltage VGL, and common voltage VCOM) are natural. Discharged. The voltages that are naturally discharged may gradually decrease during a predetermined discharge time to reach a ground voltage.

On the other hand, when the supply of the input voltage Vin from the outside is stopped, the reset signal supply unit 300 applies a reset signal RST of a logic low level to the timing controller 510 to stop the operation of the timing controller 510. Let it. The timing controller 510 may stop an operation for displaying an image after displaying the image of the current frame.

Before the operation of the timing controller 510 is stopped, a black grayscale image may be displayed on the display panel 540 for at least one frame period (t3), so that the residual voltage precharged in the pixels PX may be discharged. . That is, the gate all-high signal ALL_H of the logic low level is outputted before the period t3 of at least one frame from the time when the reset signal RST is converted to the logic low level, thereby discharging the display panel 540. have.

In the above embodiment, before the output voltages of the power management unit 200 during natural discharge reach the ground voltage, the reset signal RST may be converted to a logic low level. When the operation of the timing control unit 510 is stopped in response to the reset signal RST, the output voltage of the power management unit 200 during natural discharge is applied to the pixels PXs of the display panel 540, thereby causing the pixels PX to be removed. Can be recharged. In particular, when the thin film transistor TFT of the pixels PX is composed of a low-temperature polysilicon thin film transistor, etc., which has a weak off characteristic, an unwanted afterimage is displayed on the display panel 540 or a flicker phenomenon occurs due to the recharged voltage I can.

In the following embodiments, in order to solve the above-described problem, a discharge circuit is provided at the output terminal of the power management unit 200 so that the residual voltage output from the power management unit 200 is stopped when the operation of the timing control unit 510 is stopped. It provides a way to immediately discharge.

4 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment. 5 is a circuit diagram of the discharge circuit shown in FIG. 4 according to the first embodiment. 6 and 7 are diagrams for explaining a method of controlling a current path of a discharge circuit using a reset signal.

Referring to FIG. 4, the display device 2 according to an exemplary embodiment may include a power management unit 200, a reset signal supply unit 300, and a display unit 500. Also, the display device 2 may further include a discharge circuit 600. Although not shown, the display device 2 may further include the power supply unit 100 and the panel discharge unit 400 described with reference to FIG. 1.

The discharge circuit 600 may be connected between the output terminal of the power management unit 200 and the ground electrode. Referring to FIG. 5, such a discharge circuit 600 may include a switching element SW for controlling a voltage transmission path between the output terminal of the power management unit 200 and the ground electrode.

Referring to FIG. 5, the switching element SW may be formed of, for example, a transistor. However, the present embodiment is not limited thereto, and various types of switching elements capable of controlling the on/off of the current path according to the control signal may be used.

In the transistor constituting the switching element SW, one electrode (eg, a drain electrode) may be connected to an output terminal of the power management unit 200, and the other electrode (eg, a source electrode) may be connected to a ground electrode. . The gate electrode of the transistor is connected to the reset signal supply unit 300 to receive the reset signal RST output from the reset signal supply unit 300.

The transistor is turned on when a gate-on level reset signal RST is applied to the gate electrode to electrically connect the output terminal of the power management unit 200 to the ground electrode. As illustrated, when the switching element SW is composed of a PMOS transistor, the switching element SW may be turned on in response to a reset signal RST of a logic low level. That is, when the reset signal RST of the logic low level is output to stop the operation of the timing controller 510, the switching element SW is turned on.

Referring to FIG. 6, when the reset signal RST is at a logic high level, that is, while the timing controller 510 performs an operation for displaying an image, the switching element SW is turned off. Then, the output terminal of the power management unit 200 is electrically separated from the ground electrode, and the current output from the power management unit 200 is transferred to the display unit 500. In other words, the analog driving voltage AVDD, the gate high voltage VGH, the gate low voltage VGL, and the common voltage VCOM output from the power management unit 200 may be transferred to the display unit 500.

Referring to FIG. 7, when the reset signal RST is at a logic low level, that is, when the operation of the timing controller 510 is stopped, the switching element SW is turned on, and the output terminal of the power management unit 200 Is electrically connected to the ground electrode. Then, the current output from the power management unit 200 flows to the ground electrode through the switching element SW.

Accordingly, after the power of the display device 2 is controlled to be turned off, the output voltage of the power management unit 200 during natural discharge is not transmitted to the display unit 500 and may be immediately discharged to the ground node. Accordingly, after the operation of the timing control unit 510 is stopped, the residual voltage output from the power management unit 200 does not leak to the components of the display unit 500.

In the above embodiment, the switching element SW is composed of a PMOS transistor, but the present embodiment is not limited thereto. That is, in an embodiment in which the operation of the timing controller 510 is stopped when the reset signal RST is controlled to a logic high level, the switching element SW is composed of an NMOS transistor that is turned on in response to the logic high level. I can.

8 is a circuit diagram of the discharge circuit shown in FIG. 4 according to a second embodiment.

Referring to FIG. 8, in the second embodiment, the discharge circuit 600 may further include a discharge resistor R connected between the switching element SW and the ground electrode. The discharge resistor R may further increase the reliability of the discharge circuit 600 and serves to prevent an overcurrent from being applied to the switching element SW. The resistance value of the discharge resistance R is the voltage value of the output voltages of the power management unit 200, the natural discharge rate of the output voltages of the power management unit 200, and the reset signal RST from the power-off control of the display device 1 An appropriate value may be determined based on a delay time until conversion to the logic low level, or the like.

9 is a circuit diagram of the discharge circuit shown in FIG. 4 according to a third embodiment.

Referring to FIG. 9, in the third embodiment, the discharging circuit 600 may further include a diode DIODE connected between the switching element SW and the discharging resistor R. The diode DIODE controls the current input through the switching element SW to flow in the direction of the ground node, and blocks a current flowing back from the ground node toward the switching element SW. By the diode DIODE, leakage of the current backflowed from the discharge circuit 600 to the display unit 500 may be prevented, and reliability of the discharge circuit 600 may be improved.

10 is a timing diagram of voltages applied to a display unit according to an exemplary embodiment.

When the power of the display device 1 is controlled to be turned on, the input voltage Vin may be supplied from the outside. The power supply unit 100 converts the input voltage Vin and outputs a digital driving voltage VCC. The digital driving voltage VCC output from the power supply unit 100 may be supplied to the power management unit 200, the reset signal supply unit 300, and the panel discharge unit 400. Also, the digital driving voltage VCC may be applied to the timing controller 510 to control the timing controller 510 in a driving state.

When the input voltage Vin is applied from the outside, the reset signal supply unit 300 may output a reset signal RST of a logic high level after a predetermined time elapses. Here, the predetermined time may include a predetermined time t1 required for the digital driving voltage VCC to be output and stabilized from the power supply 100. The reset signal RST is applied to the timing controller 510 to control the timing controller 510 to an operation start state.

When the operation of the timing controller 510 is started, a gate all-high signal ALL_H of a logic low level may be output. The gate driver 520 applies a gate-on voltage to all of the gate lines GL1 to GLn by the gate all-high signal ALL_H. At the same time, a data voltage corresponding to the black gray level may be applied to the pixels PX through the data driver 530. Accordingly, a black grayscale image may be displayed on the display panel 540 for a period t2 of at least one frame, and a residual voltage precharged in the pixels PX may be discharged.

After the display panel 540 is discharged, the analog driving voltage AVDD, the gate high voltage VGH, the gate low voltage VGL, and the common voltage VCOM are output from the power management unit 200. While the reset signal RST is output to the logic high level, the switching element SW of the discharge circuit 600 shown in FIGS. 4 to 9 is controlled to the off state. Accordingly, voltages output from the power management unit 200 may be applied to the display unit 500.

Thereafter, the timing control unit 510 processes the image signal RGB and the control signal CS received from the outside to suit the operating conditions of the display panel 540, so that the image data DATA and the gate driving control signal CONT1 are processed. ) And a data driving control signal CONT2 may be generated and output. The gate driver 520 and the data driver 530 include image data DATA, a gate driving control signal CONT1 and a data driving control signal CONT2, a gate high voltage VGH, a gate low voltage VGL, and a common voltage. Based on (VCOM), the pixels PX are controlled to display an image corresponding to the image signal RGB.

When the power of the display device 1 is controlled to be in the off state, supply of the input voltage Vin from the outside may be stopped. Then, the output of the digital driving voltage VCC from the power supply unit 100 is stopped. The power management unit 200 does not perform voltage conversion, and the parasitic voltages (ie, analog driving voltage AVDD, gate high voltage VGH, gate low voltage VGL, and common voltage VCOM) are natural. Discharged.

On the other hand, when the supply of the input voltage Vin from the outside is stopped, the reset signal supply unit 300 applies a reset signal RST of a logic low level to the timing controller 510 to stop the operation of the timing controller 510. Let it. The timing controller 510 may stop an operation for displaying an image after displaying the image of the current frame.

When the reset signal RST is output at a logic low level, the switching element SW of the discharge circuit 600 shown in FIGS. 4 to 9 is controlled to be turned on. Then, the output voltages of the power management unit 200 during natural discharge may be immediately discharged to the ground electrode via the switching element SW. Accordingly, the residual voltage of the power management unit 200 during natural discharge is prevented from being transmitted to the display unit 500.

Meanwhile, before the operation of the timing controller 510 is stopped, a black grayscale image is displayed on the display panel 540 for at least one frame period (t3) so that the residual voltage precharged in the pixels PX is discharged. I can. That is, the gate all-high signal ALL_H of the logic low level is outputted before the period t3 of at least one frame from the time when the reset signal RST is converted to the logic low level, thereby discharging the display panel 540. have.

Those of ordinary skill in the art to which the present invention pertains will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative and non-limiting in all respects. The scope of the present invention is indicated by the scope of the claims to be described later rather than the detailed description, and all changes or modified forms derived from the meaning and scope of the claims and the concept of equivalents thereof are included in the scope of the present invention. It must be interpreted.

1: display device
100: power supply
200: power management unit
300: reset signal supply
400: panel discharge unit
500: display
510: timing control unit
520: gate driver
530: data driver
540: display panel

Claims (14)

A display unit including pixels and a timing control unit performing an operation for displaying an image on the pixels;
A power management unit generating a driving voltage from an external input voltage and applying it to the display unit;
A reset signal supply unit for applying a reset signal for starting or stopping an operation of the timing control unit to the timing control unit; And
And a discharge circuit connected to an output terminal of the power management unit and transmitting the driving voltage output to the output terminal to a ground electrode in response to the reset signal. The method of claim 1, wherein the reset signal supply unit,
When the input voltage is applied, a reset signal of a first level is output to start the operation of the timing controller, and when the input voltage is not applied, a reset signal of a second level is output to stop the operation of the timing controller. , Display device. The method of claim 2, wherein the discharge circuit,
And a switching element connected between the output terminal of the power management unit and a ground electrode and turned on/off by the reset signal. The method of claim 3, wherein the switching element,
It is turned off when the reset signal of the first level is applied, electrically separating the output terminal of the power management unit from the ground electrode, and is turned on when the reset signal of the second level is applied, and the The display device electrically connecting the output terminal of a power management unit and the ground electrode. The method of claim 4, wherein the power management unit,
When the input voltage is not applied, the para-generated driving voltage is discharged to the output terminal. The method of claim 5, wherein the discharge circuit,
When the operation of the timing controller is stopped in response to the reset signal of the second level, the driving voltage discharged to the output terminal through the turned-on switching element is transferred to the ground electrode. The method of claim 4, wherein the switching element,
A display device, wherein one electrode is connected to the output terminal of the power management unit, the other electrode is connected to the ground electrode, and a gate electrode receives the reset signal. The method of claim 4, wherein the discharge circuit,
The display device further comprising a discharge resistor connected between the switching element and the ground electrode. The method of claim 8, wherein the discharge circuit,
The display device further comprising a diode connected between the switching element and the discharge resistor and blocking a current flowing from the ground electrode to the output terminal of the power management unit. A display unit including pixels and a timing control unit, a power management unit generating a driving voltage from an external input voltage and applying it to the display unit, a reset signal supply unit applying a reset signal to the timing control unit, and an output terminal of the power management unit A driving method of a display device including a discharge circuit including a switching element that is turned on/off in response to the reset signal,
When the input voltage is applied, the power management unit generates the driving voltage and applies it to the display unit;
Outputting, by the reset signal supply unit, a reset signal of a first level;
Initiating, by the timing controller, an operation for displaying an image on the pixels in response to the reset signal of the first level;
Controlling, by the discharge circuit, the switching element to an off state in response to the reset signal of the first level;
When the application of the input voltage is stopped, discharging the driving voltage generated by the power management unit to the output terminal;
Outputting, by the reset signal supply unit, a reset signal of a second level;
Stopping, by the timing controller, the operation in response to a reset signal of the second level; And
And controlling, by the discharging circuit, the switching element to an on state in response to a reset signal of the second level. The method of claim 10, wherein the switching element,
A method of electrically connecting or disconnecting the output terminal and the ground electrode in response to the on-state and off-state, and being connected between the output terminal and the ground electrode of the power management unit. The method of claim 11, wherein the switching element,
The method of claim 1, wherein one electrode is connected to the output terminal of the power management unit, the other electrode is connected to the ground electrode, and a gate electrode receives the reset signal. The method of claim 12, wherein the discharge circuit,
The method further comprising a discharge resistor connected between the switching element and the ground electrode. The method of claim 13, wherein the discharge circuit,
The method further comprises a diode connected between the switching element and the discharge resistor and blocking a current flowing from the ground electrode to the output terminal of the power management unit.

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