KR20210053824A - Semiconductor memory device and electronic system including the same - Google Patents

Abstract

An object of the present invention is to provide a semiconductor memory device with improved performance and reliability. The semiconductor memory device of the present invention comprises: a substrate; a first memory structure, on the substrate, including a first surface and a second surface opposite to each other and including a plurality of first metallic lines stacked in a first direction and a first interlayer insulating film surrounding the first metallic line; a second memory structure, on the first memory structure, including a third surface and a fourth surface opposite to each other and including a plurality of second metallic lines stacked in the first direction and a second interlayer insulating film surrounding the second metallic line; a first channel structure passing through the first memory structure to intersect the first metallic line; a second channel structure passing through the second memory structure to intersect the second metallic line and directly connected to the first channel structure; a first contact plug connected to the first metallic line through the first interlayer insulating film; a second contact plug connected to the second metallic line through the second interlayer insulating film; and a cutting line passing through the first and second memory structures. The cutting line includes a first cut portion passing through the first memory structure, a second cut portion passing through the second memory structure, and a cut interface in which the first cut portion and the second cut portion are in contact. As the distance from the cut interface increases, the width in a second direction intersecting the first direction of the first cut portion and the width in the second direction of the second cut portion increase.

Description

A semiconductor memory device and an electronic system including the same TECHNICAL FIELD

The present invention relates to a semiconductor memory device and an electronic system including the same. More specifically, the present invention relates to a semiconductor memory device including stacked memory structures and an electronic system including the same.

It is required to increase the degree of integration of semiconductor memory devices in order to meet the excellent performance and low price demanded by consumers. In the case of semiconductor memory devices, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required.

In the case of a two-dimensional or planar semiconductor memory device, the degree of integration is largely determined by the area occupied by the unit memory cells, and thus is greatly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for miniaturization of patterns, the degree of integration of the 2D semiconductor memory device is increasing, but still limited. Accordingly, three-dimensional semiconductor memory devices including memory cells arranged three-dimensionally have been proposed.

On the other hand, due to the development of the electronic industry, demands for high functionality, high speed and miniaturization of electronic components are increasing. In response to this trend, a semiconductor package in which several semiconductor chips are stacked and mounted on a single package substrate may be used.

The technical problem to be solved by the present invention is to provide a semiconductor memory device with improved performance and reliability.

Another technical problem to be solved by the present invention is to provide an electronic system including a semiconductor memory device having improved performance and reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor memory device according to an aspect of the present invention for achieving the above technical problem includes a substrate, a first surface and a second surface opposite to each other, and a plurality of second layers stacked in a first direction. A first memory structure including 1 metallic line and a first interlayer insulating layer surrounding the first metallic line, including third and fourth surfaces opposite to each other on the first memory structure, and stacked in a first direction A second memory structure including a plurality of second metallic lines and a second interlayer insulating layer surrounding the second metallic line, a first channel structure passing through the first memory structure and crossing the first metallic line, and a second memory A second channel structure that penetrates through the structure and crosses the second metallic line, is directly connected to the first channel structure, penetrates through the first interlayer insulating layer, and penetrates the first contact plug connected to the first metallic line, and the second interlayer insulating layer. And a second contact plug connected to the second metallic line, and a cutting line passing through the first and second memory structures, wherein the cutting line includes a first cut portion passing through the first memory structure, and a second memory A second cutting portion penetrating the structure, and a cutting boundary surface in which the first cutting portion and the second cutting portion are in contact, and as it is further away from the cutting boundary surface, in a second direction intersecting the first direction of the first cutting portion The width of and the width of the second cut portion in the second direction increase.

An electronic system according to an aspect of the present invention for achieving the above technical problem includes a main substrate, a semiconductor memory device on the main substrate, and a controller electrically connected to the semiconductor memory device on the main substrate, and the semiconductor memory device is a substrate , On the substrate, a first memory including a first surface and a second surface opposite to each other, a plurality of first metallic lines stacked in a first direction, and a first interlayer insulating film surrounding the first metallic line The structure includes a plurality of second metallic lines on the first memory structure, including third and fourth surfaces opposite to each other, and stacked in a first direction, and a second interlayer insulating film surrounding the second metallic line A second memory structure that passes through the first memory structure, a first channel structure that crosses the first metallic line, and a second memory structure that passes through the second memory structure and crosses the second metallic line, and is directly connected to the first channel structure. A channel structure, a first contact plug penetrating through the first interlayer insulating layer and connected to the first metallic line, a second contact plug penetrating through the second interlayer insulating layer and connected to the second metallic line, and first and second memory structures. And a cutting line penetrating therethrough, wherein the cutting line includes a first cutting portion penetrating the first memory structure, a second cutting portion penetrating the second memory structure, and the first cutting portion and the second cutting portion contacting each other. A width of the first cut portion in a second direction intersecting with the first direction and a width of the second cut portion in a second direction increases as the cutting boundary surface is included, and as it moves away from the cutting boundary surface.

Specific details of other embodiments are included in the description and drawings of the invention.

1 is an exemplary circuit diagram for describing a semiconductor memory device according to some embodiments.
2 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments.
FIG. 3 is an enlarged view illustrating an area R1 of FIG. 2.
4 is an enlarged view for explaining the S area of FIG. 2.
5 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments.
6 is an enlarged view illustrating an area R2 of FIG. 5.
7 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments.
8 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments.
9 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments.
10 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments.
11 is a schematic block diagram illustrating an electronic system according to some embodiments.
12 is a schematic perspective view illustrating an electronic system according to some embodiments.
13 to 15 are various schematic cross-sectional views taken along line II′ of FIG. 12.
16 to 21 are intermediate views illustrating a method of manufacturing a semiconductor memory device according to some embodiments of the present invention.

Hereinafter, a semiconductor memory device according to some embodiments of the present invention will be described with reference to FIGS. 1 to 4.

In the present specification, although the first, second, etc. are used to describe various devices or components, it is a matter of course that these devices or components are not limited by these terms. These terms are only used to distinguish one device or component from another device or component. Therefore, it goes without saying that the first device or component mentioned below may be a second device or component within the technical idea of the present invention.

1 is an exemplary circuit diagram for describing a semiconductor memory device according to some embodiments.

A memory cell array of a semiconductor memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

The common source line CSL may extend in the first direction X. In some embodiments, a plurality of common source lines CSL may be two-dimensionally arranged. For example, the plurality of common source lines CSL may be spaced apart from each other and extend in the first direction X, respectively. The same voltage may be electrically applied to the common source lines CSL, or different voltages may be applied and controlled separately.

The plurality of bit lines BL may be arranged two-dimensionally. For example, the bit lines BL may be spaced apart from each other and extend in a second direction Y crossing the first direction X. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be connected in common to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

Each cell string CSTR includes a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and a ground select transistor GST and a string select transistor. A plurality of memory cell transistors MCTs disposed between (SST) may be included. Each memory cell transistor MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistor MCT may be connected in series.

The common source line CSL may be commonly connected to sources of the ground select transistors GST. In addition, a ground selection line GSL, a plurality of word lines WL1_0 to WL2_n and WL3_0 to WL4_n, and a string selection line SSL may be disposed between the common source line CSL and the bit line BL. The ground selection line GSL can be used as a gate electrode of the ground selection transistor GST, and the word lines WL1_0 to WL2_n and WL3_0 to WL4_n can be used as a gate electrode of the memory cell transistors MCT, and string selection The line SSL may be used as a gate electrode of the string selection transistor SST.

In some embodiments, the erase control transistor ECT may be disposed between the common source line CSL and the ground select transistor GST. The common source line CSL may be commonly connected to sources of the erase control transistors ECT. Also, an erase control line ECL may be disposed between the common source line CSL and the ground selection line GSL. The erase control line ECL may be used as a gate electrode of the erase control transistor ECT. The erase control transistors ECT may generate a gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

2 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments.

Referring to FIG. 2, a semiconductor memory device according to some embodiments includes a first memory structure MS1, a second memory structure MS2, a third memory structure MS3, a fourth memory structure MS4, and a peripheral memory structure. It may include a structure (PE).

The first memory structure MS1, the second memory structure MS2, the third memory structure MS3, and the fourth memory structure MS4 may be cell regions of a semiconductor memory device. The ferry structure PE may be a peripheral circuit area of a semiconductor memory device.

In some embodiments, the semiconductor memory device may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a cell region is fabricated on a first wafer, a lower chip including a peripheral circuit region is fabricated on a second wafer different from the first wafer, and then the upper chip and the lower chip are fabricated. It may mean that they are connected to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on an uppermost metal layer of an upper chip and a bonding metal formed on an uppermost metal layer of a lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

In some embodiments, the first memory structure MS1, the second memory structure MS2, the third memory structure MS3, and the fourth memory structure MS4 form a memory cell array including at least one memory block. Can provide.

The ferry structure PE may provide a peripheral circuit that controls the operation of the memory cell array. For example, the ferry structure PE may include a plurality of circuit elements PT1 to PT3, which will be described later, and a metal layer, respectively.

In some embodiments, the semiconductor memory device of the present invention may include a substrate 20. The substrate 20 may include, for example, a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the substrate 20 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The substrate 20 may include a cell array area CA, an extended area EXT, and a pad area PAD.

A memory cell array including a plurality of memory cells may be formed in the cell array area CA. The memory cell array includes a plurality of memory cells, a plurality of first to fourth channel structures CH1, CH2, CH3, and CH4 electrically connected to each of the memory cells, and a plurality of first to fourth metallic lines ( WL1_0 to WL1_n, WL2_0 to WL2_n, WL3_0 to WL3_n, WL4_0 to WL4_n, SSL, GSL, ECL), and the like may be disposed. The plurality of metallic lines WL1_0 to WL1_n, WL2_0 to WL2_n, WL3_0 to WL3_n, and WL4_0 to WL4_n may be word lines of the semiconductor memory device of the present invention.

The extended area EXT may be disposed around the cell array area CA. In the extended area EXT, a plurality of first internal fourth metallic lines ECL, GSL, WL1_0 to WL1_n, WL2_0 to WL2_n, WL3_0 to WL3_n, WL4_0 to WL4_n, SSL, which will be described later, may be stacked in a step shape.

The pad area PAD may be disposed around the cell array area CA and the extended area EXT. For example, the pad area PAD may surround the cell array area CA and the extended area EXT in a plan view. An upper input/output pad 30a and a lower input/output pad 30b described later may be disposed in the pad area PAD.

In some embodiments, a first memory structure MS1, a second memory structure MS2, a third memory structure MS3, and a fourth memory structure MS4 may be sequentially stacked on the substrate 20. .

The first memory structure MS1 may include a plurality of first metallic lines SSL and WL1_0 to WL1_n, a first interlayer insulating layer 120, and a first adhesive layer 140. The first memory structure MS1 may include a first surface 100a and a second surface 100b opposite to each other. The first surface 100a may be a surface facing the substrate 20. The second surface 100b may be a surface opposite to the substrate 20.

The plurality of first metallic lines SSL and WL1_0 to WL1_n may extend in the first direction X. The plurality of first metallic lines SSL and WL1_0 to WL1_n may be stacked on each other in the third direction Z. The third direction Z may be, for example, a direction perpendicular to the first direction X and the second direction Y. The first metallic line SSL closest to the substrate 20 among the plurality of first metallic lines SSL and WL1_0 to WL1_n may be a string selection line SSL. The plurality of first metallic lines SSL and WL1_0 to WL1_n may be arranged in a stepped manner. For example, the length of the plurality of first metallic lines SSL, WL1_0 to WL1_n in the first direction X is from the first surface 100a to the second surface 100b of the first memory structure MS1. It can be lengthened as it faces. However, the technical idea of the present invention is not limited thereto.

The first metallic lines SSL and WL1_0 to WL1_n may include, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), but the type of the metal is not limited thereto.

The first interlayer insulating layer 120 may surround the plurality of first metallic lines SSL and WL1_0 to WL1_n. The plurality of first metallic lines SSL and WL1_0 to WL1_n may be buried in the first interlayer insulating layer 120. The first interlayer insulating layer 120 may include, for example, silicon oxide, but is not limited thereto.

The first adhesive layer 140 may be disposed under the second surface 100b of the first memory structure MS1. The first adhesive layer 140 may be disposed on the plurality of first metallic lines SSL and WL1_0 to WL1_n. The first adhesive layer 140 may include, for example, silicon carbonitride (SiCN), but is not limited thereto.

The second memory structure MS2 may be disposed on the first memory structure MS1. The second memory structure MS2 may include a plurality of second metallic lines WL2_0 to WL2_n, a second interlayer insulating layer 220, and a second adhesive layer 240. The second memory structure MS2 may include a third surface 200a and a fourth surface 200b opposite to each other. The third surface 200a may be a surface facing the first memory structure MS1. The fourth surface 200b may be a surface opposite to the first memory structure MS1.

The plurality of second metallic lines WL2_0 to WL2_n may extend in the first direction X. The plurality of second metallic lines WL2_0 to WL2_n may be stacked on each other in the third direction Z. The plurality of second metallic lines WL2_0 to WL2_n may be arranged in a stepped manner. For example, the length of the plurality of second metallic lines WL2_0 to WL2_n in the first direction X is from the third surface 200a to the fourth surface 200b of the second memory structure MS2. It can be lengthened along. However, the technical idea of the present invention is not limited thereto.

The plurality of second metallic lines WL2_0 to WL2_n may include, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), but the type of the metal is not limited thereto.

The second interlayer insulating layer 220 may surround the plurality of second metallic lines WL2_0 to WL2_n. The plurality of second metallic lines WL2_0 to WL2_n may be buried in the second interlayer insulating layer 220. The second interlayer insulating layer 220 may include, for example, a silicon oxide layer, but is not limited thereto.

The second adhesive layer 240 may include a 2_1 adhesive layer 241 and a 2_2 adhesive layer 243. The 2_1 adhesive layer 241 may be disposed on the third surface 200a of the second memory structure MS2. The 2_1 adhesive layer 241 may be bonded to the first adhesive layer 140. The 2_2 adhesive layer 243 may be disposed under the fourth surface 200b of the second memory structure MS2. The second adhesive layer 240 may include, for example, silicon carbonitride (SiCN), but is not limited thereto.

The second surface 100b of the first memory structure MS1 and the third surface 200a of the second memory structure MS2 may be bonded to each other. The second surface 100b and the third surface 200a may be bonded using, for example, the first adhesive layer 140 and the 2_1 adhesive layer 241. That is, the second surface 100b of the first memory structure MS1 and the third surface 200a of the second memory structure MS2 may be located on the same plane.

The third memory structure MS3 may be disposed on the second memory structure MS2. The third memory structure MS3 may include a plurality of third metallic lines WL3_0 to WL3_n, a third interlayer insulating layer 320, and a third adhesive layer 340. The third memory structure MS3 may include a fifth surface 300a and a sixth surface 300b opposite to each other. The fifth surface 300a may be a surface facing the second memory structure MS2. The sixth surface 300b may be a surface opposite to the second memory structure MS2.

The plurality of third metallic lines WL3_0 to WL3_n may extend in the first direction X. The plurality of third metallic lines WL3_0 to WL3_n may be stacked on each other in the third direction Z. The plurality of third metallic lines WL3_0 to WL3_n may be arranged in a stepped manner. For example, the length of the plurality of third metallic lines WL3_0 to WL3_n in the first direction X is from the fifth surface 300a of the third memory structure MS3 to the sixth surface 300b. Can be reduced accordingly. However, the technical idea of the present invention is not limited thereto.

The plurality of third metallic lines WL3_0 to WL3_n may include, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), but the type of the metal is not limited thereto.

The third interlayer insulating layer 320 may surround the plurality of third metallic lines WL3_0 to WL3_n. The plurality of third metallic lines WL3_0 to WL3_n may be buried in the third interlayer insulating layer 320. The third interlayer insulating layer 320 may include, for example, a silicon oxide layer, but is not limited thereto.

The third adhesive layer 340 may include a 3_1 adhesive layer 341 and a 3_2 adhesive layer 343. The 3_1 adhesive layer 341 may be disposed on the fifth surface 300a of the third memory structure MS3. The 3_1th adhesive layer 341 may be bonded to the 2_2nd adhesive layer 243. The 3_2 adhesive layer 343 may be disposed under the sixth surface 300b of the third memory structure MS3. The third adhesive layer 340 may include, for example, silicon carbonitride (SiCN), but is not limited thereto.

The fourth surface 200b of the second memory structure MS2 and the fifth surface 300a of the third memory structure MS3 may be bonded to each other. The fourth surface 200b and the fifth surface 300a may be bonded using, for example, the 2_2 adhesive layer 243 and the 3_1 adhesive layer 341. That is, the fourth surface 200b of the second memory structure MS2 and the fifth surface 200a of the third memory structure MS3 may be positioned on the same plane.

The fourth memory structure MS4 may be disposed on the third memory structure MS3. The fourth memory structure MS4 includes a plurality of fourth metallic lines WL4_0 to WL4_n, GSL, and ECL, a fourth interlayer insulating layer 420, a fourth adhesive layer 440, and a horizontal conductive substrate 450. And, it may include a source structure 410. The fourth memory structure MS4 may include a seventh surface 400a and an eighth surface 400b opposite to each other. The seventh surface 400a may be a surface facing the third memory structure MS3. The eighth surface 400b may be a surface opposite to the third memory structure MS3.

The plurality of fourth metallic lines WL4_0 to WL4_n, GSL, and ECL may extend in the first direction X. The plurality of fourth metallic lines WL4_0 to WL4_n, GSL, and ECL may be stacked on each other in the third direction Z. The plurality of fourth metallic lines WL4_0 to WL4_n, GSL, and ECL may be arranged in a stepped manner. For example, the length of the plurality of fourth metallic lines WL4_0 to WL4_n, GSL, and ECL in the first direction X is from the seventh surface 400a to the eighth surface 400b of the fourth memory structure MS4. It can be reduced as it faces ). However, the technical idea of the present invention is not limited thereto.

The plurality of fourth metallic lines WL4_0 to WL4_n, GSL, and ECL may include, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), but the type of metal is not limited thereto. Does not.

The fourth interlayer insulating layer 420 may surround the plurality of fourth metallic lines WL4_0 to WL4_n, GSL, and ECL. The plurality of fourth metallic lines WL4_0 to WL4_n, GSL, and ECL may be buried in the fourth interlayer insulating layer 420. The fourth interlayer insulating layer 420 may include, for example, a silicon oxide layer, but is not limited thereto.

The fourth adhesive layer 440 may be disposed on the seventh surface 400a of the fourth memory structure MS4. The fourth adhesive layer 440 may be bonded to the 3_2 adhesive layer 343. The fourth adhesive layer 440 may include, for example, silicon carbonitride (SiCN), but is not limited thereto.

The sixth surface 300b of the third memory structure MS3 and the seventh surface 400a of the fourth memory structure MS4 may be bonded to each other. The sixth surface 300b and the seventh surface 400a may be bonded using, for example, the 3_2 adhesive layer 343 and the fourth adhesive layer 440. That is, the sixth surface 300b of the third memory structure MS3 and the seventh surface 400a of the fourth memory structure MS4 may be positioned on the same plane.

In some embodiments, the first to fourth metallic lines SSL, WL1_0 to WL1_n, WL2_0 to WL2_n, WL3_0 to WL3_n, WL4_0 to WL4_n, GSL, and ECL are the fourth surface 200b of the second memory structure MS2 And a symmetrical structure with respect to the fifth surface 300a of the third memory structure MS3. Here, the symmetrical structure does not mean that the upper structure and the lower structure are completely the same based on a specific plane. The symmetrical structure means that the upper structure and the lower structure have a similar shape based on a specific plane.

That is, the first and second metallic lines SSL, WL1_0 to WL1_n, and WL2_0 to WL2_n are from the first surface 100a of the first memory structure MS1 to the fourth surface 200b of the second memory structure MS2. As it faces, the length in the first direction X gradually increases. The third and fourth metallic lines WL3_0 to WL3_n, WL4_0 to WL4_n, GSL, and ECL are the eighth surface 400b of the fourth memory structure MS4 from the fifth surface 300a of the third memory structure MS3. As it faces, the length in the first direction X gradually decreases.

That is, the semiconductor memory device of the present invention may have a mirror structure. However, the technical idea of the present invention is not limited thereto.

The horizontal conductive substrate 450 may be disposed under the eighth surface 400b of the fourth memory structure MS4. The horizontal conductive substrate 450 may be a common source plate. That is, the horizontal conductive substrate 450 may serve as the common source line CSL of FIG. 1.

The horizontal conductive substrate 450 may include at least one of a conductive semiconductor film, a metal silicide film, and a metal film. When the horizontal conductive substrate 450 includes a conductive semiconductor film, the horizontal conductive substrate 450 is, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium It may contain at least one of arsenic (InGaAs), aluminum gallium arsenide (AlGaAs), or a combination thereof. The horizontal conductive substrate 450 may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline. The horizontal conductive substrate 450 may include at least one of a p-type impurity, an n-type impurity, and carbon included in the semiconductor layer.

The source structure 410 may be disposed on the horizontal conductive substrate 450. The source structure 410 may electrically connect the horizontal conductive substrate 450 and the fourth channel structure CH4. The source structure 410 may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof.

In some embodiments, the semiconductor memory device of the present invention may include a first channel structure CH1, a second channel structure CH2, a third channel structure CH3, and a fourth channel structure CH4. . The first channel structure CH1, the second channel structure CH2, the third channel structure CH3, and the fourth channel structure CH4 may be formed in the cell array area CA.

The first channel structure CH1 may penetrate the first memory structure MS1 in the third direction Z. The first channel structure CH1 may penetrate the first interlayer insulating layer 120, the first metallic lines SSL, WL1_0 to WL1_n, and the first adhesive layer 140 in the third direction Z. The first channel structure CH1 may have a tapered shape. For example, as the first channel structure CH1 faces from the first surface 100a to the second surface 100b of the first memory structure MS1, the width in the first direction X increases. May contain parts.

The second channel structure CH2 may penetrate the second memory structure MS2 in the third direction Z. The second channel structure CH2 may penetrate the second interlayer insulating layer 220, the second metallic lines WL2_0 to WL_n, and the second adhesive layer 240 in the third direction Z. The second channel structure CH2 may overlap the first channel structure CH1 in the third direction Z. The second channel structure CH2 may be directly connected to the first channel structure CH1. The second channel structure CH2 may have a tapered shape. For example, the second channel structure CH2 is a portion in which the width in the first direction X decreases from the third surface 200a to the fourth surface 200b of the second memory structure MS2. It may include. That is, the first channel structure CH1 and the second channel structure CH2 may be symmetrical with respect to the second surface 100b and the third surface 200a.

The third channel structure CH3 may penetrate the third memory structure MS3 in the third direction Z. The third channel structure CH3 may penetrate the third interlayer insulating layer 320, the third metallic lines WL3_0 to WL3_n, and the third adhesive layer 340 in the third direction Z. The third channel structure CH2 may overlap the first channel structure CH1 and the second channel structure CH2 in a third direction Z. The third channel structure CH3 may be directly connected to the second channel structure CH2. That is, the third channel structure CH3 may be connected to the first channel structure CH1. The third channel structure CH3 may have a tapered shape. For example, the third channel structure CH3 is a portion in which the width in the first direction X decreases from the fifth surface 300a to the sixth surface 300b of the third memory structure MS3. It may include.

The fourth channel structure CH4 may penetrate the fourth interlayer insulating layer 420, the fourth metallic lines WL4_0 to WL4_n, GSL, and ECL, and the fourth adhesive layer 440 in the third direction (Z). . The fourth channel structure CH4 may be electrically connected to the source structure 410. The third channel structure CH2 may overlap the first channel structure CH1, the second channel structure CH2, and the third channel structure CH3 in a third direction Z. The fourth channel structure CH4 may be directly connected to the third channel structure CH3. That is, the fourth channel structure CH4 may be connected to the first channel structure CH1 and the second channel structure CH2. The fourth channel structure CH3 may have a tapered shape. For example, the fourth channel structure CH4 is a portion in which the width in the first direction X decreases from the seventh surface 400a to the eighth surface 400b of the fourth memory structure MS4. It may include.

In some embodiments, the semiconductor memory device of the present invention may include a first contact plug PG1, a second contact plug PG2, and a third contact plug PG3.

The first contact plug PG1 may be connected to the first metallic lines WL1_0 to WL1_n or the second metallic lines WL2_0 to WL3_n. The first contact plug PG1 may penetrate the first interlayer insulating layer 120 or the second interlayer insulating layer 220 in the third direction Z.

The second contact plug PG2 may be connected to the third metallic lines WL3_0 to WL3_n or the fourth metallic lines WL4_0 to WL4_n. The second contact plug PG2 may penetrate the third interlayer insulating layer 320 and/or the fourth interlayer insulating layer 420 in the third direction Z.

The second contact plug PG2 may overlap the first contact plug PG1 in the third direction Z. That is, the first contact plug PG1 and the second contact plug PG2 are based on the fourth surface 200b of the second memory structure MS2 and the fifth surface 300a of the third memory structure MS3. It can be a symmetrical structure. However, the technical idea of the present invention is not limited thereto.

The third contact plug PG3 may extend from the first surface 100a of the first memory structure MS1 to the eighth surface 400b of the fourth memory structure MS4. That is, the third contact plug PG3 may penetrate the first interlayer insulating layer 120, the second interlayer insulating layer 220, the third interlayer insulating layer 320, and the fourth interlayer insulating layer 420. The third contact plug PG3 may be connected to the upper input/output pad 30a and the lower input/output pad 30b to be described later.

Each of the first contact plug PG1, the second contact plug PG2, and the third contact plug PG3 is, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), It may include a metal material such as nickel (Ni), but is not limited thereto.

In some embodiments, the memory device of the present invention may include a first insulating layer 500, a first metal layer 510, a second metal layer 520, and an upper input/output pad 30a.

The first insulating layer 500 may be disposed on the fourth memory structure MS4. The first insulating layer 500 may cover the eighth surface 400b of the fourth memory structure MS4. The first insulating layer 500 may include, for example, a silicon oxide layer, but is not limited thereto.

The first metal layer 510 and the second metal layer 520 may be buried in the first insulating layer 500. The first metal layer 510 may be connected to the second contact plug PG2 and the third contact plug PG3. The first and second metal layers 510 and 520 may be connected to the third contact plug PG3. Each of the first metal layer 510 and the second metal layer 520 may include, for example, a metal material such as aluminum (Al) or tungsten (W), but is not limited thereto.

The upper input/output pad 30a may be disposed on the first insulating layer 500. The upper input/output pad 30a may be formed in the pad area PAD. The upper input/output pad 30a may be connected to the third contact plug PG3. The upper input/output pad 30a may be connected to at least one of the circuit elements PT1 to PT3 described later (eg, the third circuit element PT3) through the third contact plug PG3.

The upper input/output pad 30a includes a first semiconductor chip S1 and a second semiconductor chip (S1 in FIG. 13) and a package substrate (2100 in FIG. 13) on which the second semiconductor chip (S2 in FIG. 13) is disposed. It may be used to electrically connect the semiconductor chip S2.

In some embodiments, the semiconductor memory device of the present invention may include a cut line WLC.

The cutting line WLC may cut the first to fourth metallic lines SSL, WL1_0 to WL1_n, WL2_0 to WL2_n, WL3_0 to WL3_n, WL4_0 to WL4_n, GSL, and ECL. The cutting line WLC may include a first cutting portion WLC_1, a second cutting portion WLC_2, and a cutting boundary surface WLC_IR.

The first cut portion WLC_1 may cut the first and second metallic lines SSL, WL1_0 to WL1_n, and WL2_0 to WL2_n. The first cut portion WLC_1 may penetrate through the second memory structure MS2 and the first memory structure MS1. The second cut portion WLC_2 may cut the third and fourth metallic lines WL3_0 to WL3_n, WL4_0 to WL4_n, GSL, and ECL. The second cut portion WLC_2 may penetrate through the third and fourth memory structures MS3 and MS4.

The cutting boundary surface WLC_IR may be an interface where the first cutting portion WLC_1 and the second cutting portion WLC_2 meet. The cutting boundary surface WLC_IR may be positioned on the same plane as the fourth surface 200b of the second memory structure MS2 and the fifth surface 300a of the third memory structure MS3.

The cutting line WLC may not include a conductive material. That is, the cutting line WLC may be made only of an insulating material. The cutting line WLC may include, for example, an oxide-based insulating material, but is not limited thereto.

In some embodiments, the semiconductor memory device of the present invention may include a second insulating layer 50, a third metal layer 60, and a fourth metal layer 70.

The second insulating layer 50 may be disposed under the first memory structure MS1. The second insulating layer 50 may cover the first surface 100a of the first memory structure MS1. The second insulating layer 50 may include, for example, a silicon oxide layer, but is not limited thereto.

The third metal layer 60 and the fourth metal layer 70 may be buried in the second insulating layer 50. The third metal layer 60 and the fourth metal layer 70 may be connected to the first channel structure CH1, the first contact plug PG1, and the third contact plug PG3. The third metal layer 60 and the fourth metal layer 70 may include, for example, aluminum (Al), copper (Cu), or tungsten (W), but are not limited thereto.

In some embodiments, the ferri structure PE includes the lower insulating layer 10, the substrate 20, the third insulating layer 40, the fifth metal layer 75, the sixth metal layer 80, and the seventh metal layer ( 90), a fourth contact plug 15, and first to third circuit elements PT1 to PT3.

The lower insulating layer 10 may be formed on the lower surface of the substrate 20. The lower insulating layer 10 may cover the lower surface of the substrate 20. The lower insulating layer 10 may include, for example, a silicon oxide layer, but is not limited thereto.

A plurality of circuit elements PT1 to PT3 may be formed on the upper surface of the substrate 20. The circuit elements PT1 to PT3 may provide peripheral circuits (e.g., decoder circuit 1110 of FIG. 12, page buffer 1120, logic circuit 1130, etc.) that control the operation of each memory cell. I can.

Each of the circuit elements PT1 to PT3 may include, for example, a transistor, but is not limited thereto. For example, each of the circuit elements PT1 to PT3 is not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors. ) May be included.

In some embodiments, the first to fourth channel structures CH1 to CH4 disposed in the cell array area CA may be connected to the first circuit element PT1. The first to fourth metallic lines WL1_0 to WL_n, WL2_0 to WL2_n, WL3_0 to WL3_n, WL4_0 to WL4_n, SSL, GSL, ECL disposed in the extended area EXT may be connected to the second circuit element PT2. have. The third contact plug PG3 formed in the pad area PAD may be connected to the third circuit element PT3.

The third insulating layer 40 may be formed on the upper surface of the substrate 20. A fifth metal layer 75, a sixth metal layer 80, and a seventh metal layer 90 may be buried in the third insulating layer 40. The third insulating layer 40 may include, for example, a silicon oxide layer, but is not limited thereto.

The fifth metal layer 75 may be bonded to the fourth metal layer 70. The fifth metal layer 75 may be the bonding metal. The fifth metal layer 75 may be connected to the first to fourth channel structures CH1 to CH4 and the first to third contact plugs PG1 to PG3 through the fourth metal layer 70.

The sixth metal layer 80 may be connected to the fifth metal layer 75. Like the fifth metal layer 75, the sixth metal layer 80 includes the first to fourth channel structures CH1 to CH4 and the first to third contact plugs PG1 to PG3 through the fourth metal layer 70. ) Can be connected.

The seventh metal layer 90 may be connected to the sixth metal layer 80. The seventh metal layer 90 may be connected to the substrate 20. Specifically, it may be connected to a source/drain formed in the substrate 20.

Each of the fifth metal layer 75, the sixth metal layer 80, and the seventh metal layer 90 may be formed of aluminum (Al), copper (Cu), or tungsten (W), but is not limited thereto. .

The fourth contact plug 15 may be connected to the sixth metal layer 80. The fourth contact plug 15 may be electrically connected to the lower input/output pad 30b to be described later and the first to third circuit elements PT1 to PT3. The fourth contact plug 15 may include, for example, a metal material such as aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), but is limited thereto. no.

In some embodiments, a lower input/output pad 30b disposed on the lower insulating layer 10 may be further included. The lower input/output pad 30b may be formed in the pad area PAD. The lower input/output pad 30b may be connected to the fourth contact plug 15. The lower input/output pad 30b may be connected to at least one of the first to third circuit elements PT1 to PT3 through the fourth contact plug 15.

The lower input/output pad 30b includes a first semiconductor chip S1 and a second semiconductor chip (S1 in FIG. 13) and a package substrate (2100 in FIG. 13) on which the second semiconductor chip (S2 in FIG. 13) is disposed. It may be used to electrically connect the semiconductor chip S2.

FIG. 3 is an enlarged view illustrating an area R1 of FIG. 2. The fourth channel structure CH4 will be described in detail with reference to FIG. 3. Each of the first channel structure CH1, the second channel structure CH2, and the third channel structure CH3 may be substantially the same as the fourth channel structure CH4.

2 and 3, the fourth channel structure CH4 may include a semiconductor pattern 430, a filling pattern 434, and an information storage layer 432.

The semiconductor pattern 430 may penetrate through the fourth metallic lines ECL, GSL, WL4_0 to WL4_n and the fourth interlayer insulating layer 420. The semiconductor pattern 430 may cross the fourth metallic lines ECL, GSL, and WL4_0 to WL4_n. The semiconductor pattern 430 is illustrated to have a cup shape, but this is only exemplary. For example, the semiconductor pattern 430 may have various shapes such as a cylindrical shape, a square cylinder shape, and a filled filler shape.

The semiconductor pattern 430 may include, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon, an organic semiconductor material, and a carbon nano structure, but is not limited thereto.

The information storage layer 432 may be interposed between the semiconductor pattern 430 and each of the fourth metallic lines ECL, GSL, and WL4_0 to WL4_n. For example, the information storage layer 432 may extend along a side surface of the semiconductor pattern 430.

The information storage layer 432 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a higher dielectric constant than silicon oxide. The high-k materials include, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium. oxide), lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

In some embodiments, the information storage layer 432 may be formed of multiple layers. For example, the information storage layer 432 may include a tunnel insulating layer 432a, a charge storage layer 432b, and a blocking insulating layer 432c sequentially stacked on the semiconductor pattern 430.

The tunnel insulating layer 432a may include, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )). The charge storage layer 432b may include, for example, silicon nitride. The blocking insulating layer 432c may include, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )).

The filling pattern 434 may be formed to fill the inside of the cup-shaped semiconductor pattern 430. The filling pattern 434 may include an insulating material, for example, silicon oxide, but is not limited thereto.

The source structure 410 may be formed on the horizontal conductive substrate 450. The source structure 410 may be interposed between the horizontal conductive substrate 450 and the erase control line ECL. The source structure 410 may include, for example, polysilicon or metal doped with impurities.

In some embodiments, the fourth channel structure CH4 may pass through the source structure 410 and be connected to the horizontal conductive substrate 450. For example, the lower portion of the fourth channel structure CH4 may penetrate the source structure 410 and be buried in the horizontal conductive substrate 450. The source structure 410 may be formed to be connected to the semiconductor pattern 430 of the channel structure CH4. For example, the source structure 410 may pass through the information storage layer 432 and be connected to the semiconductor pattern 430.

In some embodiments, a portion of the source structure 410 adjacent to the semiconductor pattern 430 may protrude toward the information storage layer 432. For example, in a region adjacent to the semiconductor pattern 430, a length in which the source structure 410 extends in the third direction Z may be longer. This may be due to the characteristics of the etching process of removing a part of the information storage layer 432 to form the source structure 410.

4 is an enlarged view for explaining the S area of FIG. 2. The cutting line WLC will be described in more detail with reference to FIG. 4.

2 and 4, the cutting line WLC may include a first cutting portion WLC_1, a second cutting portion WLC_2, and a cutting boundary surface WLC_IR.

The cutting boundary surface WLC_IR may be an boundary surface between the first cutting portion WLC_1 and the second cutting portion WLC_2. That is, the portion disposed above the cutting boundary surface WLC_IR based on the cutting boundary surface WLC_IR may be the second cutting portion WLC_2, and the portion disposed below the cutting boundary surface WLC_IR may be the first cutting portion WLC_1. have.

The first cut portion WLC_1 may have a first width W1 in the first direction X. The cutting boundary surface WLC_IR may have a second width W2 in the first direction X. The second cut portion WLC_2 may have a third width W3 in the first direction X.

The first width W1 of the first cutting portion WLC_1 may increase as the distance from the cutting boundary surface WLC_IR increases based on the cutting boundary surface WLC_IR. The third width W3 of the second cutting portion WLC_2 may increase as the distance from the cutting boundary surface WLC_IR increases based on the cutting boundary surface WLC_IR. That is, the second width W2 of the cutting boundary surface WLC_IR may be the smallest among the widths of the cutting line WLC. However, the technical idea of the present invention is not limited thereto.

5 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments. 6 is an enlarged view illustrating an area R2 of FIG. 5. For convenience of explanation, the description will focus on differences from those described with reference to FIGS. 2 and 3.

5 and 6, in the semiconductor memory device according to some embodiments, the source structure 410 may not be disposed.

That is, the fourth channel structure CH4 may be directly connected to the horizontal conductive substrate 450 using the semiconductor pattern 430. The fourth channel structure CH4 may be directly connected to the horizontal conductive substrate 450.

The lower surface of the semiconductor pattern 430 may be located on the same plane as the lower surface of the information storage layer 432. A part of the semiconductor pattern 430 may be buried in the horizontal conductive substrate 450. Accordingly, the semiconductor pattern 430 and the horizontal conductive substrate 450 may be directly connected.

7 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments. For convenience of explanation, the description will focus on differences from those described with reference to FIG. 2.

Referring to FIG. 7, the first to fourth metallic lines SSL, WL1_0 to WL1_n, WL2_0 to WL2_n, WL3_0 to WL3_n, WL4_0 to WL4_n, GSL, ECL are the second side 100b of the first memory structure MS1. ) And the third surface 200a of the second memory structure MS2.

That is, the length of the first metallic lines SSL, WL1_0 to WL1_n in the first direction X becomes longer as it goes from the first surface 100a to the second surface 100b of the first memory structure MS1. . The second to fourth metallic lines WL2_0 to WL2_n, WL3_0 to WL3_n, WL4_0 to WL4_n, GSL, ECL are formed from the third surface 200a of the second memory structure MS2 to the fourth memory structure MS4. The length in the first direction X decreases as it faces the eighth surface 400b.

8 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments. For convenience of explanation, the description will focus on differences from those described with reference to FIG. 2.

Referring to FIG. 8, the semiconductor memory device of the present invention may include only a first memory structure MS1, a second memory structure MS2, and a third memory structure MS3. In other words, it can have a memory structure of a three-tier stack.

In this case, the third memory structure MS3 may include a horizontal conductive substrate 450 and a source structure 410. Also, the third memory structure MS3 may include an erase control line ECL and a ground selection line GSL.

In some embodiments, the first to third metallic lines SSL, WL1_0 to WL1_n, WL2_0 to WL2_n, WL3_0 to WL3_n, ECL, GSL are the fourth surface 200b and the third memory of the second memory structure MS2. It may be symmetrical with respect to the fifth surface 300a of the structure MS3.

That is, the first and second metallic lines SSL, WL1_0 to WL1_n and WL2_0 to WL2_n are from the first surface 100a of the first memory structure MS1 to the fourth surface 200b of the second memory structure MS2. As it faces, the length in the first direction X gradually increases. The length of the third metallic lines WL3_0 to WL3_n, GSL, and ECL in the first direction X decreases from the fifth surface 300a to the sixth surface 300b of the third memory structure MS3. .

9 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments. For convenience of explanation, the description will focus on differences from those described with reference to FIGS. 2 and 8.

Referring to FIG. 9, the first to third metallic lines SSL, WL1_0 to WL1_n, WL2_0 to WL2_n, WL3_0 to WL3_n, GSL, ECL, and the second surface 100b of the first memory structure MS1 and the second It may be symmetrical with respect to the third surface 200a of the memory structure MS2.

That is, the length of the first metallic lines SSL and WL1_0 to WL1_n in the first direction X increases as the distance from the first surface 100a of the first memory structure MS1 increases. The lengths of the second and third metallic lines WL2_0 to WL2_n, WL3_0 to WL3_n, GSL, and ECL in the first direction X are away from the third surface 200a of the second memory structure MS2. The more it decreases.

In some embodiments, the cutting boundary surface WLC_IR may be disposed on the same plane as the second surface 100b of the first memory structure MS1 and the third surface 200a of the second memory structure MS2.

10 is an exemplary cross-sectional view illustrating a semiconductor memory device according to some embodiments. For convenience of explanation, the description will focus on differences from those described with reference to FIG. 2.

Referring to FIG. 10, the semiconductor memory device of the present invention may include a first memory structure MS1 and a second memory structure MS2.

In this case, the second memory structure MS2 may include a horizontal conductive substrate 450 and a source structure 410. Also, the second memory structure MS2 may include an erase control line ECL and a ground selection line GSL.

The first metallic lines SSL, WL1_0 to WL1_n and the second metallic lines WL2_0 to WL2_n, GSL, ECL are the second surface 100b of the first memory structure MS1 and the second memory structure MS2. It may be symmetrical with respect to the three sides 200a.

That is, the length of the first metallic lines SSL and WL1_0 to WL1_n in the first direction X increases as the distance from the first surface 100a of the first memory structure MS1 increases. The length of the second metallic lines WL2_0 to WL2_n, GSL, and ECL in the first direction X decreases as the distance from the third surface 200a of the second memory structure MS2 increases.

In some embodiments, the cutting boundary surface WLC_IR may be disposed on the same plane as the second surface 100b of the first memory structure MS1 and the third surface 200a of the second memory structure MS2.

11 is a schematic block diagram illustrating an electronic system according to some embodiments. 12 is a schematic perspective view illustrating an electronic system according to some embodiments. 13 to 15 are various schematic cross-sectional views taken along line II′ of FIG. 12. For convenience of description, portions overlapping with those described above with reference to FIGS. 1 to 10 are briefly described or omitted.

Referring to FIG. 11, an electronic system 1000 according to some embodiments may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device including one or more semiconductor memory devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device. .

The semiconductor memory device 1100 may be a nonvolatile memory device (eg, a NAND flash memory device), and may be, for example, the semiconductor memory device described above with reference to FIGS. 1 to 10.

The semiconductor memory device 1100 may communicate with the controller 1200 through an input/output pad 1101 electrically connected to the logic circuit 1130. The input/output pad 1101 may be electrically connected to the logic circuit 1130 through the input/output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S. The input/output pad 1101 may be, for example, at least one of the upper input/output pad 30a and the lower input/output pad 30b described above with reference to FIGS. 1 to 10. The input/output connection wiring 1135 may be, for example, the third contact plug PG3 described above with reference to FIGS. 1 to 10.

The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor memory device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. Control commands for controlling the semiconductor memory device 1100, data to be written to memory cell transistors (MCTs) of the semiconductor memory device 1100, and memory cells of the semiconductor memory device 1100 through the NAND interface 1221 Data to be read from the transistors MCTs may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

Referring to FIG. 12, an electronic system 2000 according to some embodiments includes a main substrate 2001, a main controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. ) Can be included. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 by wiring patterns 2005 formed on the main substrate 2001.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to a communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 includes interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). It can communicate with an external host according to any one of them. In some embodiments, the electronic system 2000 may be operated by power supplied from an external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) for distributing power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

The main controller 2002 may write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and may improve the operation speed of the electronic system 2000.

The DRAM 2004 may be a buffer memory for reducing a speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a type of cache memory, and may provide a space for temporarily storing data in a control operation on the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b electrically connects the package substrate 2100, the semiconductor chips 2200 on the package substrate 2100, and the semiconductor chips 2200 and the package substrate 2100. The connection structures 35a and 35b may include a molding layer 2500 covering the semiconductor chips 2200 and the connection structures 35a and 35b on the package substrate 2100.

The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each of the semiconductor chips 2200 may be, for example, a semiconductor memory device described above with reference to FIGS. 1 to 10.

In some embodiments, the connection structures 35a and 35b may be bonding wires that electrically connect the semiconductor chips 2200 and the upper package pads 2130. Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and the package upper pads 2130 of the package substrate 2100 and the Can be electrically connected.

In some embodiments, the main controller 2002 and the semiconductor chips 2200 may be included in one package. In some embodiments, the main controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor are formed by wiring formed on the interposer substrate. The chips 2200 may be connected to each other.

12 and 13, in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 is disposed on the lower surface of the package substrate body portion 2120, the upper package pads 2130 disposed on the upper surface of the package substrate body portion 2120, or exposed through the lower surface of the package substrate body portion 2120 The lower pads 2125 to be formed, and internal wirings 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120 may be included. The upper pads 2130 may be electrically connected to the connection structures 35a and 35b. The lower pads 2125 may be connected to the wiring patterns 2005 of the main substrate 2010 of the electronic system 2000 as shown in FIG. 12 through the conductive connection parts 2800.

Each of the semiconductor chips S1 and S2 may include cell structures CE1 and CE2 and ferri structures PE1 and PE2. The cell structures CE1 and CE2 may include, for example, first to fourth memory structures MS1 to MS4 described above with reference to FIGS. 1 to 10. In addition, as illustrated, the cell structures CE1 and CE2 may include a channel structure CH, a cutting line WLC, and a third contact plug PG3. The channel structure CH may include, for example, the first to fourth channel structures CH1 to CH4 described above with reference to FIG. 2. The ferry structures PE1 and PE2 may include, for example, the substrate 20 described above with reference to FIGS. 1 to 10.

In some embodiments, each of the semiconductor chips S1 and S2 may include cell structures CE1 and CE2 and ferri structures PE1 and PE2 bonded by a wafer bonding method. For example, the cell structures CE1 and CE2 and the ferri structures PE1 and PE2 may be connected by a copper-copper bonding process.

In some embodiments, the chip attachment layer 600 may attach the semiconductor chips S1 and S2 on the package substrate 2000. For example, the chip attachment layer 600 may attach the second semiconductor chip S2 on the package substrate 2000.

In some embodiments, the first semiconductor chip S1 may form an overhang region in the second semiconductor chip S2 and may be stacked on the second semiconductor chip S2. For example, the stacked first semiconductor chip S1 and the second semiconductor chip S2 may have a step shape. That is, the first semiconductor chip S1 may expose a part of the second semiconductor chip S2.

The semiconductor chips S1 and S2 may be electrically connected to each other by the connection structures 35a and 35b, and may be electrically connected to the package upper pads 2130 of the package substrate 2100. For example, the semiconductor chips S1 and S2 are electrically connected to each other through an upper bonding wire 35a or a lower bonding wire 35b, respectively, or electrically connected to the package upper pads 2130 of the package substrate 2100. Can be connected.

12, 14, and 15, in the electronic system 2000 according to some embodiments, semiconductor chips S1, S2, and S3 may be stacked to form an overhang region, respectively.

For example, as illustrated in FIG. 14, semiconductor chips S1, S2, and S3 may be stacked in a step shape. As another example, as illustrated in FIG. 15, the semiconductor chips S1, S2, and S3 may be stacked in a zigzag shape.

16 to 21 are intermediate views illustrating a method of manufacturing a semiconductor memory device according to some embodiments of the present invention. Hereinafter, a method of manufacturing a semiconductor memory according to some embodiments will be described with reference to FIGS. 16 to 21.

Referring to FIG. 16, a first memory chip MC1 is formed on the first substrate structure SUB1. The first substrate structure SUB1 may cover the first surface 100a. The first memory chip MC1 includes a first interlayer insulating layer 120, a first sacrificial layer 160, and a first adhesive layer 140. That is, the first interlayer insulating layer 120 and the first sacrificial layer 160 are intersected and stacked on the first wafer SUB1. The first adhesive layer 140 is formed under the second surface 100b. A first channel structure CH1 penetrating the first interlayer insulating layer 120, the first sacrificial layer 160, and the first adhesive layer 140 may be formed.

A second memory chip MC2 is formed on the second substrate structure SUB2. The second substrate structure SUB2 may cover the fourth surface 200b. The second memory chip MC2 includes a second interlayer insulating layer 220, a second sacrificial layer 260, and a second adhesive layer 240. That is, the second interlayer insulating layer 220 and the second sacrificial layer 260 are sequentially stacked on the second wafer SUB2. The second adhesive layer 240 includes a 2_1 adhesive layer 241 and a 2_2 adhesive layer 243.

The 2_1 adhesive layer 241 is formed on the third surface 200a. The 2_2 adhesive layer 243 is formed under the fourth surface 200b. A second channel structure CH2 penetrating the second interlayer insulating layer 220, the second sacrificial layer 260, the 2_1 adhesive layer 241, and the 2_2 adhesive layer 243 may be formed.

Subsequently, the second surface 100b and the third surface 200a may be bonded. The second surface 100b and the third surface 200a may be bonded using the first adhesive layer 140 and the 2_1 adhesive layer 241. During the bonding process, the first channel structure CH1 and the second channel structure CH2 may be directly connected.

Referring to FIG. 17, a third memory chip MC3 and a fourth memory chip MC4 may be sequentially stacked on the second memory chip MC2 using the same method.

First, the second substrate structure SUB2 may be removed to expose the fourth surface 200b. Subsequently, a third memory chip MC3 may be formed on the fourth surface 200b. The third memory chip MC3 may include a third interlayer insulating layer 320, a third sacrificial layer 360, and a third adhesive layer 340. The third adhesive layer 340 may include a 3_1 adhesive layer 341 and a 3_2 adhesive layer 343.

The second memory chip MC2 and the third memory chip MC3 may be bonded to each other. That is, the fourth surface 200b and the fifth surface 300a may be bonded to each other. The fourth surface 200b and the fifth surface 300a may be bonded using the 2_2 adhesive layer 243 and the 3_1 adhesive layer 341.

A fourth memory chip MC4 may be formed on the third memory chip MC3. The fourth memory chip MC4 may include a fourth interlayer insulating layer 420, a fourth sacrificial layer 460, and a fourth adhesive layer 440.

The third memory chip MC3 may be bonded to the fourth memory chip MC4. That is, the sixth surface 300b and the seventh surface 400a may be bonded to each other. The sixth surface 300b and the seventh surface 400a may be bonded using the 3_2 adhesive layer 343 and the fourth adhesive layer 440.

A third substrate structure SUB3 may be formed on the eighth surface 400b. The first to fourth channel structures CH1 to CH4 may be connected to each other. The first channel structure CH1 and the second channel structure CH2 are directly connected. The second channel structure CH2 and the third channel structure CH3 are directly connected. The third channel structure CH3 and the fourth channel structure CH4 are directly connected. That is, the first to fourth channel structures CH1 to CH4 may be connected to each other.

Referring to FIG. 18, the first surface 100a may be exposed by removing the first substrate structure SUB1.

Subsequently, a portion of the first sacrificial layer 160 and the second sacrificial layer 260 may be removed. The lengths of the first sacrificial layer 160 and the second sacrificial layer 260 may be shorter as the distance from the fourth surface 200b increases. That is, the first sacrificial layer 160 and the second sacrificial layer 260 may have a stepped structure.

Subsequently, a first cut portion WLC_1 penetrating the first sacrificial layer 160, the first interlayer insulating layer 120, the second sacrificial layer 260, and the second interlayer insulating layer 220 may be formed. The first cut portion WLC_1 may be formed to be spaced apart from the first channel structure CH1 and the second channel structure CH2.

Referring to FIG. 19, a first memory structure MS1, a second memory structure MS2, and a ferri structure PE may be formed.

First, the first sacrificial layer 160 may be replaced with the first metallic lines SSL and WL1_0 to WL1_n using a replacement process. The second sacrificial layer 260 may be replaced with the second metallic lines WL2_0 to WL2_n using a replacement process.

Subsequently, a first contact plug PG1 connected to the first metallic lines SSL and WL1_0 to WL1_n or the second metallic lines WL2_0 to WL2_n may be formed. A second insulating layer 50 may be formed on the first surface 100a of the first memory structure MS1. A plurality of metal layers may be buried in the second insulating layer 50.

Subsequently, a ferry structure PE may be formed on the second insulating layer 50. The ferri structure PE includes a lower insulating layer 10, a substrate 20, and a third insulating layer 40. A lower input/output pad 30b may be formed on the lower insulating layer 10.

The second insulating layer 50 and the third insulating layer 40 may be bonded to each other. Specifically, a metal layer in the third insulating layer 40 and a metal layer in the second insulating layer 50 may be bonded to each other.

Referring to FIG. 20, the third substrate structure SUB3 may be removed. The third substrate structure SUB3 may be removed to expose the eighth surface 400b.

Although not shown, after removing the third substrate structure SUB3, the fourth sacrificial layer 460 and the third sacrificial layer 360 may be removed.

Referring to FIG. 21, a third memory structure MS3 and a fourth memory structure MS4 may be formed.

The third sacrificial layer 360 may be replaced with the third metallic lines WL3_0 to WL3_n using a replacement process. The fourth sacrificial layer 460 may be replaced with the fourth metallic lines WL4_0 to WL4_n, GSL, and ECL using a replacement process.

The fourth memory structure MS4, the third memory structure MS3, the second memory structure MS2, and a third contact plug PG3 penetrating the first memory structure MS1 may be formed. The third contact plug PG3 may be connected to the lower input/output pad 30b.

The third memory structure MS3 and a second cut portion WLC_2 penetrating through the fourth memory structure MS4 may be formed. The first cut part WLC_1 and the second cut part WLC_2 may be directly connected.

Subsequently, a first insulating layer 500 and an upper input/output pad 30a may be formed on the fourth memory structure MS4. The upper input/output pad 30a may be connected to the third contact plug PG3 through the metal layers 510 and 520 in the first insulating layer 500.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those having ordinary knowledge in the technical field to which the present invention pertains. It will be understood that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting.

20: substrate first memory structure: MS1
Second memory structure: MS2 Third memory structure: MS2
Fourth memory structure: MS4 First channel structure: CH1
Cutting line: WLC 1st contact plug: PG1

Claims (10)

Board;
On the substrate, a first including a first surface and a second surface opposite to each other, a plurality of first metallic lines stacked in a first direction, and a first interlayer insulating film surrounding the first metallic line Memory structure;
On the first memory structure, a plurality of second metallic lines including third and fourth surfaces opposite to each other, and stacked in the first direction, and a second interlayer insulating layer surrounding the second metallic line are formed on the first memory structure. A second memory structure including;
A first channel structure passing through the first memory structure and crossing the first metallic line;
A second channel structure penetrating the second memory structure, crossing the second metallic line, and directly connected to the first channel structure;
A first contact plug connected to the first metallic line through the first interlayer insulating layer;
A second contact plug connected to the second metallic line through the second interlayer insulating layer; And
A cutting line penetrating the first and second interlayer insulating layers,
The cutting line includes a first cutting portion penetrating the first memory structure, a second cutting portion penetrating the second memory structure, and a cutting boundary surface contacting the first cutting portion and the second cutting portion. and,
A semiconductor memory device that increases a width of the first cut portion in a second direction crossing the first direction and a width of the second cut portion in the second direction as the distance from the cut boundary surface increases. The method of claim 1,
A semiconductor memory device having the smallest width of the cutting boundary in the second direction among the widths of the cutting line in the second direction. The method of claim 1,
A width of the second channel structure in the second direction includes a portion that decreases as it moves away from the third surface of the second memory structure,
And a width of the first channel structure in the second direction increases as a distance from the first surface of the first memory structure increases. The method of claim 1,
On the second memory structure, a plurality of third metallic lines including fifth and sixth surfaces opposite to each other, and stacked in the first direction, and a third interlayer insulating film surrounding the third metallic line are formed on the second memory structure. A semiconductor memory device further comprising a third memory structure comprising a. The method of claim 4,
Further comprising a third channel structure passing through the third memory structure and crossing the third metallic line,
The third channel structure is directly connected to the second channel structure. The method of claim 5,
The third channel structure includes a portion in which a width in the second direction decreases as a distance from the fifth surface of the third memory structure decreases. The method of claim 4,
The second contact plug penetrates the third interlayer insulating layer. The method of claim 4,
The cutting line passes through the third interlayer insulating layer. The method of claim 1,
The semiconductor memory device further comprising a third contact plug penetrating from the first surface of the first memory structure to the fourth surface of the second memory structure. Main substrate;
A semiconductor memory device on the main substrate; And
A controller electrically connected to the semiconductor memory device on the main substrate,
The semiconductor memory device includes a substrate, a plurality of first metallic lines stacked in a first direction, and including a first surface and a second surface opposite to each other on the substrate, and a first metallic line surrounding the first metallic line. A first memory structure including a first interlayer insulating layer; a plurality of second metallic lines including third and fourth surfaces opposite to each other on the first memory structure, and stacked in the first direction; and 2 A second memory structure including a second interlayer insulating layer surrounding a metallic line, a first channel structure passing through the first memory structure and crossing the first metallic line, and the second memory structure passing through the second memory structure. A second channel structure crossing a metallic line and directly connected to the first channel structure, a first contact plug connected to the first metallic line through the first interlayer insulating film, and the second channel structure through the second interlayer insulating film. A second contact plug connected to a second metallic line, and a cutting line passing through the first and second memory structures,
The cutting line includes a first cutting portion penetrating the first memory structure, a second cutting portion penetrating the second memory structure, and a cutting boundary surface contacting the first cutting portion and the second cutting portion. and,
As the distance from the cutting interface increases, a width of the first cutting portion in a second direction crossing the first direction and a width of the second cutting portion in the second direction increase.

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