KR20210045780A - Display device including current sensing function and method of controlling the same - Google Patents

Abstract

The present invention relates to a display device having a current sensing function which comprises: a display panel formed with a plurality of pixels connected to sensing lines; and a sensing unit performing a sensing operation of receiving a sensing current of the pixels through a plurality of sensing channels connected to the sensing lines and sampling the sensing current to a voltage value and a scaling operation of adjusting a range of the sampled voltage value. The sensing unit includes: an amplifier including an inverted input terminal receiving the sensing current, a non-inverted input terminal receiving a reference voltage for initialization, and an output terminal outputting an integrated value; an integration capacitor connected between the inverted input terminal and the output terminal of the amplifier during the sensing operation to store the sensing current input to the inverted input terminal and connected to a first reference voltage during the scaling operation; and an integration capacitor unit sampling the integrated value output from the amplifier during the sensing operation and connected to the integration capacitor in parallel during the scaling operation to scale and output a voltage range of the sampled integrated value. According to the present invention, although the size of the sensing circuit is reduced, the current sensing performance can be guaranteed.

Description

Display device with current sensing function and its control method {DISPLAY DEVICE INCLUDING CURRENT SENSING FUNCTION AND METHOD OF CONTROLLING THE SAME}

The present invention relates to a display device having a current sensing function and a control method thereof.

The organic light emitting display device arranges pixels, each including OLED, in a matrix form, and adjusts the luminance of the pixels according to the gradation of video data. Each of the pixels includes a driving element, that is, a driving TFT (Thin Film Transistor), which controls a driving current flowing through the OLED according to a voltage applied between the gate electrode and the source electrode. The electrical characteristics of OLEDs and driving TFTs change due to temperature or deterioration. If the electrical characteristics of the OLED and/or the driving TFT are different for each pixel, the luminance between the pixels for the same video data is different, so it is difficult to realize a desired image.

External compensation techniques are known to compensate for changes in electrical properties for OLEDs or driving TFTs. The external compensation technology senses changes in the electrical characteristics of OLEDs or driving TFTs, and modulates digital video data based on the sensing results. As an external compensation technology, a voltage sensing method and a current sensing method are known. Among them, the current sensing method using a current integrator is advantageous in relatively shortening the sensing time because it enables low current and high speed sensing. Accordingly, research for improving the performance of a current sensing circuit using a current integrator is ongoing.

An object of the present invention for solving the problems of the above-described background art is to provide a display device having a current sensing function capable of sensing current characteristics of pixels and a control method thereof.

In addition, an object of the present invention is to reduce the size of a sensing circuit capable of sensing current characteristics of pixels, and consequently, to reduce the size of a data drive IC.

In addition, an object of the present invention is to provide a display device having a current sensing function capable of ensuring a current sensing performance while reducing the size of a sensing circuit and a control method thereof.

A display device having a current sensing function according to the present invention as a means for solving the above-described problems includes: a display panel having a plurality of pixels connected to sensing lines; And a sensing operation of sampling the sensing current as a voltage value by receiving sensing currents of the pixels through a plurality of sensing channels connected to the sensing lines, and performing a scaling operation of adjusting the range of the sampled voltage value. An amplifier including an inverting input terminal receiving the sensing current, a non-inverting input terminal receiving the reference voltage for initialization, and an output terminal outputting an integral value; An integrating capacitor connected between the inverting input terminal and the output terminal of the amplifier to store the sensing current input to the inverting input terminal during the sensing operation, and connected to a first reference voltage during the scaling operation; And an integrated capacitor unit that samples the integral value output from the amplifier during the sensing operation and is connected in parallel with the integral capacitor during the scaling operation to scale and output a voltage range of the sampled integral value.

The integrating capacitor has one end connected to the inverting input terminal of the amplifier and the other end connected to the output terminal during the sensing operation, and one end connected to the first reference voltage and the other end connected to the integrated capacitor unit during the scaling operation. Can be connected to node A.

The integrating capacitor may include a plurality of unit capacitors connected in parallel to the inverting input terminal of the amplifier; And a unit capacitor switch for interconnecting or releasing the other ends of each of the unit capacitors.

It may include a first switch connected to both ends of the integrating capacitor.

The integrated capacitor unit has one end connected to the first reference voltage and the other end connected to the output terminal of the amplifier during the sensing operation, and one end connected to the first reference voltage and the other end connected to the integrating capacitor during the scaling operation. It may include an integrated capacitor connected to the node A and connected in parallel with the integrating capacitor.

The integrated capacitor unit may include a second switch for controlling a connection between the other end of the integrated capacitor and the node A; And a fourth switch controlling a connection between one end of the integrating capacitor and the first reference voltage.

로 설정되는 전류 센싱 기능을 갖는 표시장치. (여기서, CFB는 적분 커패시터의 커패시턴스, CTotal는 통합 커패시터의 커패시턴스다.)During the scaling operation, the scaling ratio is

A display device with a current sensing function set to. (Where, CFB is the capacitance of the integrating capacitor, and CTotal is the capacitance of the integrated capacitor.)

The integrated capacitor unit includes an integrated capacitor having one end connected to node A and the other end connected to node B, and in the sensing operation, one end of the integrating capacitor is connected to the node A, and the other end of the integrating capacitor is connected to the node B. Is connected and connected in parallel with the integrating capacitor, and in the scaling operation, one end of the integrating capacitor and the first reference voltage are connected to the node A, and the other end of the integrating capacitor is connected to the node B to connect the integrating capacitor to the node A. Can be connected in parallel.

The integrated capacitor unit may include a second switch for controlling a connection between one end of the integrating capacitor and the node A; And a fourth switch controlling a connection between the other end of the integrating capacitor and the node B.

로 설정될 수 있다. (여기서, CFB는 적분 커패시터의 커패시턴스, CTotal는 통합 커패시터의 커패시턴스다.)During the scaling operation, the scaling ratio is

Can be set to (Where, CFB is the capacitance of the integrating capacitor, and CTotal is the capacitance of the integrated capacitor.)

A method of controlling a display device having a current sensing function of the present invention includes: a display panel in which a plurality of pixels connected to sensing lines are formed; And a sensing operation of sampling the sensing current as a voltage value by receiving sensing currents of the pixels through a plurality of sensing channels connected to the sensing lines, and performing a scaling operation of adjusting the range of the sampled voltage value. A method for controlling a display device having a current sensing function including a unit, comprising: an inverting input terminal receiving the sensing current during the sensing operation, a non-inverting input terminal receiving the reference voltage for initialization, and an output terminal outputting an integral value Outputting an integrated value of the sensing current using an amplifier including an amplifier and an integrating capacitor connected between the inverting input terminal and the output terminal of the amplifier; Sampling the integral value in an integrated capacitor unit; And connecting the integrating capacitor and the integrated capacitor in parallel during the scaling operation to scale and output a voltage range of the sampled integral value.

During the sensing operation, an initialization period for initializing input terminals and output terminals of the amplifier to an integrator reference voltage may be included.

During the scaling operation, a scaling setting period may be included in which the integrating capacitor is floated and the integrated capacitor part is connected to a first reference voltage.

After the scaling setting period, an integral capacitor initialization period for connecting the floating integral capacitor to the first reference voltage may be included.

After the integrating capacitor initialization period, a scaling period for scaling the voltage range of the integral value stored in the integrated capacitor unit by connecting the integrating capacitor and the integrated capacitor unit in parallel may be included.

The display device having a current sensing function and a control method thereof according to an embodiment of the present invention can reduce the design area of the capacitor required when designing the sensing circuit by integrating and use the capacitors in the sensing circuit, and consequently, the size of the sensing circuit. I can make it. As the size of the sensing circuit is reduced, as a result, the size of the data drive IC can be reduced.

In addition, in the present invention, the capacity of the integrator's own capacitor is reduced, but the total capacitor capacity of the sensing circuit can be maintained, thereby ensuring the current sensing performance of the sensing circuit.

1 is a schematic block diagram of a display device having a current sensing function according to an exemplary embodiment of the present invention.
2 is a diagram schematically showing the configuration of an external compensation circuit using a timing controller and a data driver IC according to an embodiment of the present invention.
3 is a diagram schematically showing a configuration of a sensing unit according to an embodiment of the present invention.
4 is a diagram showing in detail the configuration of a sensing unit according to the first embodiment of the present invention.
5 is a diagram illustrating an operation waveform of a sensing unit according to the first embodiment of the present invention and a voltage change at each node according to the operation waveform.
6 is a diagram showing a configuration of a sensing unit according to a second embodiment of the present invention.
7 is a diagram illustrating a signal waveform input to a sensing unit according to a second embodiment of the present invention and a voltage change at each node according to the signal waveform.
8 to 12 are diagrams for explaining a method of operating a sensing unit according to a second embodiment of the present invention.
13 is a diagram showing a configuration of a sensing unit according to a third embodiment of the present invention.
14 is a diagram illustrating a signal waveform input to a sensing unit according to a third embodiment of the present invention and a voltage change at each node according to the signal waveform.
15 to 19 are diagrams for explaining a method of operating a sensing unit according to a third embodiment of the present invention.

Advantages and features of the present specification, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the present embodiments are intended to complete the disclosure of the present specification, and common knowledge in the technical field to which the present specification pertains. It is provided to completely inform the scope of the invention to those who have, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and the present specification is not limited to the illustrated matters. The same reference numerals refer to the same elements throughout the specification. When'include','have','consists of' and the like mentioned in the present specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of the two parts is described as'on the top','on the top of the ~','the bottom of the','the next to the', etc. Or, unless'direct' is used, one or more other parts may be located between the two parts.

First, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be a second component within the technical idea of the present specification.

The same reference numerals refer to substantially the same constituent elements throughout the specification.

Hereinafter, exemplary embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device includes a display panel 10 in which a plurality of pixels are formed, a scan driver 13, a data driver IC 12, a timing controller 11, and the like.

A plurality of data lines 14A, a plurality of sensing lines 14B, and a plurality of scan lines 15 are disposed on the display panel 10. Pixels PXL are disposed in an intersection area of the plurality of data lines 14A, the plurality of sensing lines 14B, and the plurality of scan lines 15. Each of the pixels PXL includes an organic light-emitting device (hereinafter, referred to as OLED) that emits light, and a driving transistor (hereinafter, referred to as a driving TFT) for driving the same.

The timing controller 11 receives a data enable signal DE or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like from the image processing unit and a data signal DATA. The timing controller 11 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 13 and a data timing control signal DDC for controlling the operation timing of the data driver IC 12 based on the driving signal. ) Is displayed.

The scan driver 13 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 11. The scan driver 13 outputs a scan signal consisting of a scan high voltage and a scan low voltage through the scan lines 15. The scan driver 13 may be formed in the form of an integrated circuit (IC) or may be formed on the display panel 10 in a gate-in panel method.

The data driver IC 12 converts the digital data signal DATA into an analog data voltage based on the gamma reference voltage in response to the data timing control signal DDC supplied from the timing controller 11.

An element such as an OLED or a driving TFT included in the pixels PXL may deteriorate in proportion to the driving time, and characteristics (eg, a threshold voltage) may be deteriorated. To compensate for this, the data driver IC 12 senses a characteristic of a device included in at least one of the pixels PXL and feeds back the sensed sensing data SD to the timing controller 11. The timing controller 11 may correct the data signal DATA to be written to the pixel P based on the sensing data SD fed back from the data driver IC 12. A circuit that senses a device included in a pixel may be implemented as a separate sensing circuit other than the data driver IC 12. However, hereinafter, the sensing circuit included in the data driver IC 12 will be described as an example.

2 is a diagram schematically showing the configuration of an external compensation circuit using a timing controller and a data driver IC according to an embodiment of the present invention.

Referring to FIG. 2, the timing controller 11 includes a compensation memory 28 in which sensing data SD for data compensation is stored, and a data signal DATA to be written in the pixel P based on the sensing data SD. It includes a compensation unit 26 to compensate for.

The timing controller 11 may control all operations for sensing driving according to a predetermined sensing process. That is, sensing driving may be performed in a state in which only the screen of the display device is turned off while the system power is applied, for example, in a standby mode, a sleep mode, a low power mode, or the like. However, it is not limited thereto.

The compensation unit 26 corrects the data signal DATA to be written to the pixel P based on the sensing data SD stored in the compensation memory 28 and then outputs the corrected data to the data drive IC 12.

The data driver IC 12 includes a voltage supply unit 20 for outputting a data voltage to be written to the pixel P and a sensing unit 24 for sensing characteristics of devices included in the pixel P.

The voltage supply unit 20 may output a display data voltage or a sensing data voltage through a data channel connected to the data line 14A. The voltage supply unit 20 may have a plurality of data channels. The voltage supply unit 20 includes a digital to analog converter (DAC) that converts a digital signal into an analog signal, and generates a display data voltage or a sensing data voltage.

The voltage supply unit 20 generates a display data voltage in response to a data timing control signal DDC provided by the timing controller 11 when driving the display. The voltage supply unit 20 supplies a display data voltage to the data line 14A. During display driving, the display data voltage supplied to the data line 14A is applied to the pixel P in synchronization with the turn-on timing of the display scan signal SCAN.

When sensing is driven, the voltage supply unit 20 generates a preset sensing data voltage. The voltage supply unit 20 supplies a sensing data voltage to the data line 14A. During sensing driving, the sensing data voltage supplied to the data line 14A is applied to the pixel P in synchronization with the turn-on timing of the sensing scan signal SCAN. The gate-source voltage of the driving TFT included in the pixel P is programmed by the sensing data voltage, and the driving current flowing through the driving TFT is determined according to the gate-source voltage of the driving TFT.

The sensing unit 24 may sense the display panel 10 through a sensing channel connected to the sensing line 14B. The sensing unit 24 may have a plurality of sensing channels. The sensing unit 24 senses a characteristic of a device included in the pixel P through the sensing line 14B. The sensing unit 24 may sense a sensing node defined between the drain electrode of the driving TFT included in the pixel P and the anode electrode of the OLED. The sensing unit 24 performs sensing driving under the control of the timing controller 11. The sensing unit 24 senses and samples a signal from the pixel P, converts the sampling result to an analog to digital converter (hereinafter, referred to as an ADC), and outputs it to the timing controller 11.

The sensing driving may be performed in a vertical blank period during display driving, in a power-on sequence period before display driving is started, or in a power-off sequence period after display driving is finished. However, the present invention is not limited thereto, and sensing driving may be performed in a vertical active period during display driving. The vertical blank period is a period in which input image data is not written, and is disposed between vertical active sections in which one frame of input image data is written. The power-on sequence period refers to a transient period from when the driving power is turned on until an input image is displayed. The power-off sequence period refers to a transient period from the end of the display of the input image until the driving power is turned off.

3 is a diagram schematically showing the configuration of the sensing unit 24 according to an embodiment of the present invention.

The sensing unit 24 may include an integrator 210, a sampler 220, a scaler 230, an analog-to-digital converter 240, and the like.

The integrator 210 integrates the sensing current IPXL input from the display panel 10 and outputs an integral value.

The sampler 220 outputs a sampling signal based on the integral value output from the integrator 210 during the sensing period.

The scaler 230 performs scaling to increase the recognition rate of the sensing current IPXL output through the sampler 220. The scaler 230 may upscale or downscale the sensing current IPXL according to an input voltage range of the analog-to-digital converter 240.

The analog-to-digital converter 240 converts the sampling signal of the sensing current IPXL output from the sampler 220 into digital sensing data SD and outputs it.

4 is a circuit diagram showing in detail the configuration of the sensing unit 24 according to the first embodiment of the present invention, and FIG. 5 is an operation waveform of the sensing unit of FIG. 4 and a voltage change at each node according to the operation waveform. It is a drawing.

Referring to FIG. 4, each sensing unit 24 receives a sensing current IPXL from each sensing channel CH. Each of the sensing channels CH is connected to the sensing line 14B to receive sensing currents IPXL of pixels connected to the sensing line 14B.

The sensing unit 24 is an integrator 210 that receives a sensing current (IPXL) and outputs an integral value, a sampler 220 that samples the output value of the integrator 210 and outputs a sampling signal, and scales the voltage range of the sampling signal. It may include a scaler 230 to perform. Sampling signals scaled in each channel CH may be transmitted to one analog-to-digital converter 240 through a multiplexer MUX, and may be output as sensing data SD in digital form.

The integrator 210 includes an amplifier (AMP) having an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal. The integrating capacitor CFB is connected between the inverting input terminal (-) of the amplifier AMP and the output terminal, and the first switch SW1 is connected to both ends of the integrating capacitor CFB. The sensing current IPXL is input to the inverting input terminal (-) of the amplifier (AMP), and the integrator reference voltage (VREF) is input to the non-inverting input terminal (+).

The sampler 220 includes a second switch SW2 and a fourth switch SW4 that are turned on during a sampling operation, and a sampling capacitor CSAM. The integral value output from the amplifier AMP is sampled by the sampling capacitor CSAM according to the on/off operation of the second switch SW2 and the fourth switch SW4. One end of the sampling capacitor CSAM is connected to a node A and the other end is connected to a second reference voltage EVREF2. The second switch SW2 connects the output terminal of the amplifier AMP to the node A, and the fourth switch SW4 is the sampling capacitor CSAM, the node C, and the second reference voltage EVREF2. Connect.

The scaler 230 scales the voltage range of the sampling signal output from the sampler 220 according to the input voltage range of the analog-to-digital converter 240. To this end, the scaler 230 includes a third switch SW3, a fourth switch SW4, a fifth switch SW5, and a scaler capacitor Cscaler. The voltage range can be scaled. One end of the scaler capacitor Cscaler is connected to a node B and the other end is connected to a first reference voltage EVREF1. The third switch (SW3) connects the node A (Node A) and the node B (Node B), and the fifth switch (SW5) is the node C (Node C) to which the scaler capacitor (Cscaler) is connected and the first reference voltage (EVREF1). ) To connect. The fourth switch SW4 connects the other end of the sampling capacitor CSAM to the node C and the second reference voltage EVREF2.

The sensing driving for obtaining a sensing value from the sensing unit 24 largely includes a sensing period Tsen and a scaling period Tscale. The sensing period Tsen includes an initialization period tini and a sensing period tsen, and the scaling period Tscale includes a scaling period tscale and a range change period tran.

5 is a waveform diagram for explaining the operation of the sensing unit 24 having the configuration of FIG. 4, including an initialization period (tini), a sensing period (tsen), a scaling period (tscale), and a range change period (tran) This is an example of performing sensing driving.

In the initialization period tini, the first switch SW1 signal of the integrator 210 and the second switch SW2 and the fourth switch SW4 signals of the sampler 220 are applied at turn-on levels. The third switch (SW3) signal and the fifth switch (SW5) signal of the scaler 230 are applied at an off level.

As the signal of the first switch SW1 of the integrator 210 is applied at the turn-on level, the first switch SW1, which is an initialization switch, is turned on. Accordingly, the amplifier AMP operates as a unit gain buffer having a gain of 1. In the initialization period tini, both the input terminals (+,-) and the output terminals of the amplifier AMP are initialized to the integrator reference voltage VREF.

As signals of the second switch SW2 and the fourth switch SW4 of the sampler 220 are applied at the turn-on level, the second switch SW2 and the fourth switch SW4 are turned on. The second switch SW2 connects the output terminal of the amplifier AMP to the node A, and the fourth switch SW4 connects the sampling capacitor CSAM and the second reference voltage EVREF2. Since the output terminal of the amplifier AMP is initialized to the integrator reference voltage VREF, the potential of the node A is also set to the integrator reference voltage VREF.

As the third switch SW3 and the fifth switch SW5 signal of the scaler 230 are applied at an off level, the third switch SW3 and the fifth switch SW5 are turned off. The fourth switch SW4 signal is applied at a turn-on level so that the node C is connected to the second reference voltage EVREF2. Accordingly, the node C is set to the second reference voltage EVREF2.

Through the above process, in the initialization period tini, both the input terminals (+,-) of the amplifier (AMP) and the node A (Node A) of the output terminal are initialized to the integrator reference voltage (VREF), and the scaler 230 A node C connected to the other end of the scaler capacitor Cscaler is set to the second reference voltage EVREF2 of the sampling capacitor CSAM.

During the sensing period tsen, the signal of the first switch SW1 of the integrator 210 is applied at the off level, and the sampler 220 and the scaler 230 maintain the previous state as it is.

As the signal of the first switch SW1 of the integrator 210 is applied at the off level, the first switch SW1, which is an initialization switch, is turned off. The potential difference between both ends of the integrating capacitor CFB by the sensing current (IPXL) flowing into the inverting input terminal (-) of the amplifier (AMP) during the sensing period (Tsen) increases as the sensing time elapses, that is, the accumulated sensing current (IPXL). It increases as is increased. However, due to the characteristics of the amplifier (AMP), the inverting input terminal (-) and the non-inverting input terminal (+) are shorted through a virtual ground, so that the potential difference between them is 0, so in the sensing period (Tsen), the inverting input terminal ( The potential of -) is maintained at the integrator reference voltage VREF regardless of an increase in the potential difference of the integrating capacitor CFB. Instead, the potential of the node A connected to the output terminal of the amplifier AMP is lowered by ΔV in response to the potential difference between both ends of the integrating capacitor CFB. With this principle, the sensing current IPXL input to the channel CH during the sensing period Tsen is output as an integral value, which is a voltage value, through the integrating capacitor CFB.

The integral value output from the integrator 210 is stored in the sampling capacitor Csam connected to the second reference voltage EVREF2.

Through the above process, the potential of the node A (Node A) in the sensing period (tsen) is set to "VREF-ΔV", the node B/(Node B) is set to 0V, and the node C (Node C) is It is set as the second reference voltage EVREF2.

During the scaling period tscale, the off-level signal is applied to the second switch SW2 of the sampler 220 and the fourth switch SW4 is applied at the turn-on level. The third switch (SW3) signal and the fourth switch (SW4) signal of the scaler 230 are applied at a turn-on level, and the fifth switch (SW5) signal is applied at an off level.

As the second switch SW2 connecting the integrator 210 and the sampler 220 is turned off, the connection between the integrator 210 and the sampler 220 is disconnected.

로 설정된다. 샘플링 커패시터(CSAM)와 스케일러 커패시터(Cscaler)에 설정되는 전압은 샘플링 커패시터(CSAM)와 스케일러 커패시터(Cscaler)의 커패시턴스 비율에 의해 결정된다. 스케일러 커패시터(Cscaler)는 샘플링 커패시터(CSAM)에 비해 커패시턴스가 큰 값을 갖기 때문에 샘플링 커패시터(CSAM)에 저장된 전압보다 낮은 전위로 스케일링된 전압이 스케일러 커패시터(Cscaler)에 저장된다.As the third switch SW3 and the fourth switch SW4 of the scaler 230 are turned on, the sampler 220 and the scaler 230 are connected. Accordingly, the sampling capacitor CSAM and the scaler capacitor Cscaler are connected in parallel so that the sensing voltage stored in the sampling capacitor CSAM is transferred to the scaler capacitor Cscaler. As the fifth switch SW5 to which the first reference voltage EVREF1 is connected remains turned off, and the fourth switch SW4 to which the second reference voltage EVREF2 is connected remains turned on, the sampling capacitor ( The second reference voltage EVREF2 is connected to the CSAM and the scaler capacitor Cscaler. Thus, the voltage of Node A and Node B is

Is set to. The voltages set in the sampling capacitor CSAM and the scaler capacitor Cscaler are determined by the capacitance ratio of the sampling capacitor CSAM and the scaler capacitor Cscaler. Since the scaler capacitor Cscaler has a larger capacitance than the sampling capacitor CSAM, a voltage scaled to a potential lower than the voltage stored in the sampling capacitor CSAM is stored in the scaler capacitor Cscaler.

Through the above process, a voltage scaled to a potential lower than the sensing voltage stored in the sampling capacitor CSAM during the scaling period tscale is stored in the scaler capacitor Cscaler.

During the range change period tran, the third switch SW3 signal and the fourth switch SW4 signal of the scaler 230 are applied at the off level, and the fifth switch SW5 signal is applied at the turn-on level.

As the third switch SW3 and the fourth switch SW4 of the scaler 230 are turned off, the connection between the sampler 220 and the scaler 230 is disconnected. The fifth switch SW5 to which the first reference voltage EVREF1 is connected is turned on, and the first reference voltage EVREF1 is connected to the scaler capacitor Cscaler. Until the previous stage, the second reference voltage EVREF2 was connected to the scaler capacitor Cscaler, but since the first reference voltage EVREF1 was connected during the range change period tran, the voltage stored in the scaler capacitor Cscaler The output range can be adjusted. The first reference voltage EVREF1 is set to change the output range of the voltage stored in the scaler capacitor Cscaler to the input voltage range of the analog-to-digital converter 240.

The sensing unit 24 according to the first embodiment of the present invention is connected to each channel CH and includes three types of capacitors: an integrating capacitor CFB, a sampling capacitor CSAM, and a scaler capacitor. As the number of capacitors decreases, the design area may be reduced, and as a result, the size of the data driver IC 12 may be reduced. In consideration of this point, the second embodiment of the present invention illustrates a design method capable of reducing the number of capacitors.

6 is a diagram showing a configuration of a sensing unit according to a second embodiment of the present invention, and FIG. 7 is a signal waveform input to the sensing unit according to the second embodiment of the present invention, and at each node according to the signal waveform. It is a diagram showing voltage change.

Referring to FIG. 6, each sensing unit 24 receives a sensing current IPXL from each sensing channel CH. Each of the sensing channels CH is connected to the sensing line 14B to receive sensing currents IPXL of pixels connected to the sensing line 14B.

The sensing unit 24 includes an integrator 210 that receives a sensing current (IPXL) and outputs an integral value, and an integrated capacitor unit 250 that samples the output value of the integrator 210 and scales the voltage range of the sampling signal. I can. Sampling signals scaled in each channel CH may be transmitted to one analog-to-digital converter 240 through a multiplexer MUX, and may be output as sensing data SD in digital form.

The integrator 210 includes an inverting input terminal (-) to which the sensing current IPXL is input, a non-inverting input terminal (+) to which the reference voltage VREF is input, and an amplifier (AMP) having an output terminal. The integrating capacitor CFB is connected between the inverting input terminal (-) of the amplifier AMP and the output terminal, and the first switch SW1 is connected to both ends of the integrating capacitor CFB.

A third switch SW3 which is synchronously operated on/off is connected to the input terminal and the output terminal of the inverting input terminal (-) of the amplifier AMP. Accordingly, when the third switch SW3 is turned on, the amplifier AMP is connected to the integrator 210 and when the third switch SW3 is turned off, the amplifier AMP is disconnected from the integrator 210 circuit.

The integrating capacitor CFB may be composed of a variable capacitor capable of adjusting capacitance. The variable capacitors are unit capacitor switches SW_CFB1, SW_CFB2....SW_CFBN that control a connection relationship between the plurality of unit capacitors CFB1, CFB2....CFBN and the unit capacitors CFB1, CFB2....CFBN. ) Can be included. The number of unit capacitor switches SW_CFB1, SW_CFB2....SW_CFBN connected according to the on/off operation of the unit capacitor switches SW_CFB1, SW_CFB2....SW_CFBN varies, and as a result, the integral capacitor CFB The capacitance of can be adjusted.

The integrated capacitor unit 250 has a second switch SW2 that controls the connection between the output terminal of the amplifier AMP and the node A, and one end is connected to the node A and has a first reference voltage EVREF1. ) And a fourth switch SW4 that controls a connection between the integrated capacitor CTotal connected to the other end and the inverting input terminal (-) of the amplifier AMP and the integrated capacitor CTotal. The integrated capacitor CTotal may perform both the function of the sampling capacitor CSAM and the function of the scaler capacitor Cscaler according to the operation of the first switch SW1 to the fourth switch SW4.

When the third switch (SW3) interposed between the input terminal and the output terminal of the inverting input terminal (-) is turned on and the amplifier (AMP) is connected to the integrator 210, the sensing current (IPXL) is the inverted input terminal of the amplifier (AMP). The integral value input as (-) and output from the amplifier AMP is output to the integrated capacitor unit 250. In this case, the integrated capacitor CTotal of the integrated capacitor unit 250 functions as a sampler that stores an integral value.

When the third switch SW3 interposed between the input terminal and the output terminal of the inverting input terminal (-) is turned off, the amplifier AMP is disconnected from the integrator 210. When the first switch SW1 and the fourth switch SW4 are turned on, the integrating capacitor CFB and the integrated capacitor CTotal are connected in parallel between the node A and the first reference voltage EVREF1. Accordingly, the voltage stored in the integrated capacitor CTotal may be scaled and output according to the capacitance ratio of the integrated capacitor CFB and the integrated capacitor CTotal.

The sensing driving for obtaining a sensing value from the sensing unit 24 having such a configuration largely includes a sensing period Tsen and a scaling period Tscale. The sensing period Tsen includes an initialization period tini and a sensing period tsen, and the scaling period Tscale includes a scaling setting period tset, a capacitor initialization period tCFBini, and a scaling period tscale.

7 is a waveform diagram for explaining the operation of the sensing unit 24 having the configuration of FIG. 6, a signal waveform applied to each switch during a sensing period (Tsen) and a scaling period (Tscale) and an output terminal of the amplifier (AMP) It shows the voltage waveform of the in-node A (Node A).

Referring to FIG. 7, an on-level signal is applied to the first switch SW1, the second switch SW2, and the third switch SW3 during the initialization period tini. An off-level signal is applied to the fourth switch SW4.

The off-level signal is applied to the first switch SW1 and the on-level signal is applied to the second switch SW2 and the third switch SW3 during the sensing period tsen. An off-level signal is applied to the fourth switch SW4.

The off-level signal is applied to the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 during the scaling setting period tset.

The on-level signal is applied to the first switch SW1 during the capacitor initialization period tCFBini. The off-level signal is applied to the second switch SW2 and the third switch SW3. The on level signal is applied to the fourth switch SW4.

During the scaling period tscale, the off-level signal is applied to the first switch SW1 and the on-level signal is applied to the second switch SW2. An off-level signal is applied to the third switch SW3 and an on-level signal is applied to the fourth switch SW4.

As described above, when the on/off level signal is applied to the switches SW1, SW2, SW3, and SW4, the operating method of the integrator 210 and the integrated capacitor 250 of the sensing unit 24 is illustrated in FIGS. This will be explained with reference to 12.

8 shows an equivalent circuit when a switch signal is applied in the initialization period tini. In the initialization period tini, the on-level signal is applied to the first switch SW1, the second switch SW2, and the third switch SW3, and the off-level signal is applied to the fourth switch SW4.

As the third switch SW3 is turned on, the integrating capacitor CFB is connected to the inverting input terminal (-) and the output terminal of the amplifier AMP.

As the first switch SW1 is turned on, the inverting input terminal (-) and the output terminal of the amplifier AMP are connected. When the first switch SW1, which is an initialization switch, is turned on, the amplifier AMP operates as a unit gain buffer having a gain of 1. Accordingly, both the input terminals (+,-) of the amplifier (AMP) and the node A (Node A) as the output terminal are initialized to the integrator reference voltage (VREF).

As the second switch SW2 is turned on, the output terminal of the amplifier is connected to the integrated capacitor CTotal. One end of the integrated capacitor CTotal is connected to a node A and the other end is connected to a first reference voltage EVREF1.

Through the above process, in the initialization period tini, both the input terminals (+,-) of the amplifier (AMP) and the node A (Node A) of the output terminal are initialized to the integrator reference voltage (VREF).

9 shows an equivalent circuit when a switch signal is applied during the sensing period tsen.

The off-level signal is applied to the first switch SW1 during the sensing period tsen, and the second switch SW2, the third switch SW3, and the fourth switch SW4 maintain their previous states.

In the sensing period tsen, when the first switch SW1, which is an initialization switch, is turned off, the amplifier AMP operates as a current integrator. The amplifier (AMP) integrates the sensing current (IPXL) input to the inverting input terminal (-). In the sensing period tsen, the potential difference between both ends of the integrating capacitor CFB due to the sensing current (IPXL) flowing into the inverting input terminal (-) of the amplifier (AMP) increases as the sensing time elapses, that is, the accumulated sensing current (IPXL). ) Increases as it increases. However, due to the characteristics of the amplifier (AMP), the inverting input terminal (-) and the non-inverting input terminal (+) are shorted through a virtual ground, so that the potential difference between them is zero. The potential of -) is maintained at the reference voltage VREF regardless of an increase in the potential difference of the integrating capacitor CFB. Instead, the potential of the output terminal of the amplifier AMP is lowered corresponding to the potential difference between both ends of the integrating capacitor CFB. That is, node A is gradually decreased at a certain rate. With this principle, the sensing current IPXL flowing into the sensing period tsen is output as an integral value ΔV in the form of a voltage through the integral capacitor CFB. The integral value ΔV output in the sensing period Tsen is stored in the integrated capacitor CTotal via the second switch SW2.

10 shows an equivalent circuit when a switch signal is applied during the scaling setting period tset. The off-level signal is applied to the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 during the scaling setting period tset.

As the off-level signal is applied to the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 during the scaling setting period tset, all the switches SW1, SW2, SW3, SW4) is turned off.

Accordingly, the integrating capacitor CFB is in a floating state while the sensing current IPXL is stored.

The integrated capacitor CTotal is in a state in which the integral value ΔV is stored, and one end is connected to the node A and the other end is connected to the first reference voltage EVREF1. Accordingly, the potential of Node A is set to "VREF-ΔV".

11 shows an equivalent circuit when a switch signal is applied during the capacitor initialization period tCFBini. The on-level signal is applied to the first switch SW1 during the capacitor initialization period tCFBini. The off-level signal is applied to the second switch SW2 and the third switch SW3. The on level signal is applied to the fourth switch SW4.

As the first switch SW1 is turned on, the integrating capacitor CFB, which was in a floating state, is connected to the first reference voltage EVREF1 through the fourth switch SW4. Accordingly, the reference voltage of the integrating capacitor CFB is initialized to the first reference voltage EVREF1.

12 shows an equivalent circuit when a switch signal is applied during a scaling period (tscale). During the scaling period tscale, the off-level signal is applied to the first switch SW1 and the on-level signal is applied to the second switch SW2. An off-level signal is applied to the third switch SW3 and an on-level signal is applied to the fourth switch SW4.

로 설정될 수 있다. 이에, 노드 A(Node A)의 전위는

로 설정된다. 여기서 적분 커패시터(CFB)는 가변 커패시터이므로, 적분 커패시터(CFB)의 커패시턴스를 조정하여 스케일링 비율을 조절할 수 있다. As the second switch SW2 and the fourth switch SW4 are turned on while the first switch SW1 and the third switch SW3 are turned off, one end of the integral capacitor CFB and the integrated capacitor CTotal is It is connected to the first reference voltage EVREF1 and the other end is connected to Node A, thereby establishing a parallel connection state. Accordingly, the integrated voltage stored in the integrated capacitor CTotal is scaled according to the capacitance ratio of the integrated capacitor CFB and the integrated capacitor CTotal. The scaling ratio is

Can be set to Thus, the potential of Node A is

Is set to. Here, since the integrating capacitor CFB is a variable capacitor, the scaling ratio can be adjusted by adjusting the capacitance of the integrating capacitor CFB.

As described above, the sensing unit 24 according to the second embodiment of the present invention comprises the sampling capacitor CSAM and the scaler capacitor Cscaler of the first embodiment as one integrated capacitor CTotal and integrated during sampling. The integrated voltage may be stored using the capacitor CTotal, and the output voltage may be scaled according to the capacitance ratio of the integrated capacitor CFB of the integrator 210 and the integrated capacitor CTotal. As described above, according to the second embodiment of the present invention, the largest proportion of the design area of the sensing unit is achieved by configuring the capacitors divided into a sampling capacitor (CSAM) and a scaler capacitor (Cscaler) as one integrated capacitor (CTotal). It is possible to reduce the size of the occupied capacitor. As a result, it becomes possible to reduce the size of the data drive IC including the sensing unit.

13 is a diagram showing a configuration of a sensing unit according to a third embodiment of the present invention, and FIG. 14 is a signal waveform input to the sensing unit according to the third embodiment of the present invention, and at each node according to the signal waveform. It is a diagram showing voltage change. The third embodiment of the present invention also illustrates a circuit implemented in a manner different from that of the second embodiment, although the sensing unit includes an integrator and an integrated capacitor unit as in the second embodiment.

Referring to FIG. 13, each sensing unit 24 receives a sensing current IPXL from each sensing channel CH. Each of the sensing channels CH is connected to the sensing line 14B to receive sensing currents IPXL of pixels connected to the sensing line 14B.

The sensing unit 24 includes an inverting input terminal (-) to which the sensing current IPXL is input, a non-inverting input terminal (+) to which the reference voltage VREF is input, and an amplifier (AMP) having an output terminal.

An integrating capacitor (CFB) is connected between the inverting input terminal (-) of the amplifier (AMP) and the output terminal. The sixth switch SW6 is connected between the inverting input terminal (-) and the integrating capacitor CFB, and the third switch SW3 is connected between the output terminal and the integrating capacitor CFB.

A first switch SW1 having one end connected to one end of the integrating capacitor CFB and the other end connected to the other end of the integrating capacitor CFB is connected to both ends of the integrating capacitor CFB.

An integrated capacitor CTotal is connected to both ends of the first switch SW1 at one end connected to a node A and the other end connected to a node B. A second switch SW2 is connected between one end of the first switch SW1 and a node A. The fourth switch SW4 is connected between the other end of the first switch SW1 and the node B.

Node A to which the integrated capacitor CTotal is connected is connected to the first reference voltage EVREF1 through the fifth switch SW5. The node B to which the integrated capacitor CTotal is connected is connected to a multiplexer (MUX).

As described above, the sensing unit 24 according to the third embodiment of the present invention comprises the capacitors divided into the sampling capacitor CSAM and the scaler capacitor Cscaler as one integrated capacitor CTotal.

The sensing driving for obtaining a sensing value from the sensing unit 24 having such a configuration largely includes a sensing period Tsen and a scaling period Tscale. The sensing period Tsen includes an initialization period tini and a sensing period tsen, and the scaling period Tscale includes a scaling setting period tset, a capacitor initialization period tCFBini, and a scaling period tscale.

14 is a waveform diagram for explaining the operation of the sensing unit 24 having the configuration of FIG. 13, a signal waveform applied to each switch during a sensing period Tsen and a scaling period Tscale and an output terminal of the amplifier AMP It shows the voltage waveform of the in-node A (Node A).

During the sensing period Tsen, an off-level signal is applied to the fifth switch SW5, and an on-level signal is applied to the sixth switch SW6. During the scaling period Tscale, the on-level signal is applied to the fifth switch SW5 and the off-level signal is applied to the sixth switch SW6. The fifth switch SW5 and the sixth switch SW6 are controlled to perform on/off operations in opposite directions.

In the sensing unit 24 according to the third embodiment, an off-level signal is applied to the fifth switch SW5 and an on-level signal is applied to the sixth switch SW6 during the sensing period Tsen in which the current integration operation is performed. do. During the sensing period Tsen, the sixth switch SW6 is turned on to connect the inverting input terminal (-) of the amplifier AMP, and the circuit including the amplifier AMP performs a current integration operation. The fifth switch SW5 is turned off, the first reference voltage EVREF1 is cut off, and the integrating capacitor CFB and the integrated capacitor connected between the inverting input terminal (-) and the output terminal of the amplifier (AMP) and the amplifier (AMP) ( Together, CTotal) functions as an integral capacitor.

During the scaling period Tscale in which the sensing unit 24 performs the scaling function, the on-level signal is applied to the fifth switch SW5 and the off-level signal is applied to the sixth switch SW6. During the scaling period (Tscale), the sixth switch (SW6) is turned off and the amplifier (AMP) is disconnected, and the first reference voltage (EVREF1) is connected through the fifth switch (SW5) to integrate with the integrating capacitor (CFB). Voltage scaling is performed using a capacitor CTotal. Here, the integrating capacitor CFB may be composed of a variable capacitor capable of adjusting capacitance. Accordingly, by adjusting the capacitance of the integrating capacitor CFB, a voltage scaling ratio using the integrating capacitor CFB and the integrated capacitor CTotal can be adjusted.

During the initializing period tini of the sensing period Tsen, the on level signal is applied to the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4.

During the sensing period tsen during the sensing period Tsen, only the first switch SW1 is changed to the off-level signal, and the remaining switches are maintained in the same state as the previous period. That is, the on-level signal is applied to the second switch SW2, the third switch SW3, and the fourth switch SW4.

The off-level signal is applied to the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 during the scaling setting period tset during the scaling period Tscale.

The on level signal is applied to the first switch SW1 and the second switch SW2 during the capacitor initialization period tCFBini during the scaling period Tscale. The off-level signal is applied to the third switch SW3 and the fourth switch SW4.

During the scaling period tscale during the scaling period Tscale, the off-level signal is applied to the first switch SW1 and the on-level signal is applied to the second switch SW2. An off-level signal is applied to the third switch SW3 and an on-level signal is applied to the fourth switch SW4.

When the on/off level signal is applied to the switches SW1, SW2, SW3, SW4, SW5, and SW6 as described above, a method of operating the sensing unit 24 will be described with reference to FIGS. 15 to 19.

15 shows an equivalent circuit of the sensing unit 24 when a switch signal is applied during the initialization period tini. The on-level signal is applied to the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 during the initialization period tini. An off-level signal is applied to the fifth switch SW5, and an on-level signal is applied to the sixth switch SW6.

As the first switch (SW1), the second switch (SW2), the third switch (SW3), the fourth switch (SW4), and the sixth switch (SW6) are turned on, the inverted input terminal (-) and the output terminal of the amplifier (AMP) are turned on. It is connected to these capacitors and can be operated as an integrator.

Both ends of the integrating capacitor CFB are connected between the inverting input terminal (-) and the output terminal of the amplifier AMP. An integrated capacitor CTotal is connected in parallel with the integrating capacitor CFB between the inverting input terminal (-) and the output terminal. A first switch SW1, which is an initialization switch, is connected between the inverting input terminal (-) and the output terminal.

When the first switch SW1, which is an initialization switch, is turned on, the amplifier AMP operates as a unit gain buffer having a gain of 1. Accordingly, the input terminals (+,-) and output terminals of the amplifier (AMP) are initialized to the integrator reference voltage (VREF), and both nodes A (Node A) and node B (Node B) connected to them are also the integrator reference voltage ( VREF).

Through the above process, in the initialization period tini, the input terminals (+,-) of the amplifier AMP, the node A and the node B are all initialized to the integrator reference voltage VREF.

16 shows an equivalent circuit when a switch signal is applied during the sensing period tsen.

In the sensing period tsen, the off-level signal is applied to the first switch SW1, only the first switch SW1 is changed to the off-level signal, and the remaining switches are maintained in the same state as in the previous period.

During the sensing period tsen, the first switch SW1, which is an initialization switch, is turned off, so that the amplifier AMP operates as a current integrator. The amplifier (AMP) integrates the sensing current (IPXL) input to the inverting input terminal (-). In the sensing period (tsen), the potential difference between both ends of the integrating capacitor (CFB) and the integrated capacitor (CTotal) due to the sensing current (IPXL) flowing into the inverting input terminal (-) of the amplifier (AMP) becomes as the sensing time elapses It increases as the accumulated sensing current IPXL increases. However, due to the characteristics of the amplifier (AMP), the inverting input terminal (-) and the non-inverting input terminal (+) are shorted through a virtual ground, and the potential difference between them is 0. Therefore, in the sensing period (tsen), the inverting input terminal ( The potential of -) is maintained as the reference voltage VREF, and as a result, the potential of the node B is also maintained as the reference voltage VREF. Instead, the potential of the output terminal of the amplifier AMP is lowered in response to the potential difference between both ends of the integrating capacitor CFB and the integrated capacitor CTotal. That is, the potential of Node A is gradually reduced at a certain rate.

17 shows an equivalent circuit of the scaling setting period tset. During the scaling setting period tset, an on-level signal is applied to the fifth switch SW5, and an off-level signal is applied to the sixth switch SW6. All other switches SW1, SW2, SW3, and SW4 are turned off.

Accordingly, the connection of the amplifier AMP is released, and the integrating capacitor CFB is in a floating state.

One end of the integrated capacitor CTotal is connected to the first reference voltage EVREF1 through the fifth switch SW5 connected to the node A, and the other end is connected to the node B. Thus, the potential of the node A (Node A) is set to "EVREF1" and the potential of the node B (Node B) is set to "Vref-ΔV". Here, β is a value stored in the integrated capacitor CTotal, and may be expressed as the first reference voltage EVREF1 is connected and adjusted from the voltage V_tsen sensed in the previous sensing period tsen.

18 shows an equivalent circuit in the capacitor initialization period tCFBini. The on-level signal is applied to the first switch SW1 and the second switch SW2 during the capacitor initialization period tCFBini.

As the first switch SW1 is turned on, both ends of the integrating capacitor CFB are connected.

The second switch SW2 is turned on so that the first reference voltage EVREF1 is connected to both ends of the integrating capacitor CFB through the node A. Accordingly, the reference voltage of the integrating capacitor CFB is initialized to the first reference voltage EVREF1.

Fig. 19 shows an equivalent circuit of a scaling period (tscale). During the scaling period tscale, the off-level signal is applied to the first switch SW1 and the on-level signal is applied to the second switch SW2 and the fourth switch SW4.

로 설정될 수 있다. 여기서 적분 커패시터(CFB)는 가변 커패시터이므로, CFB의 커패시턴스를 조정하여 스케일링 비율을 조절할 수 있다. 이에, 노드 B(Node B)의 전위는

로 설정된다.As the second switch SW2 and the fourth switch SW4 are turned on, one end of the integral capacitor CFB and the integrated capacitor CTotal is connected to the first reference voltage EVREF1 through a node A. The other end is connected to Node B and becomes a parallel connection. Accordingly, the integrated voltage stored in the integrated capacitor CTotal is scaled according to the capacitance ratio of the integrated capacitor CFB and the integrated capacitor CTotal. The scaling ratio is

Can be set to Here, since the integrating capacitor CFB is a variable capacitor, the scaling ratio can be adjusted by adjusting the capacitance of the CFB. Thus, the potential of Node B is

Is set to.

As described above, according to an embodiment of the present invention, capacitors that were divided into a sampling capacitor CSAM and a scaler capacitor CTotal are configured as one integrated capacitor CTotal, which occupies the largest proportion of the design area of the sensing unit. It is possible to reduce the size of the capacitor. As a result, it becomes possible to reduce the size of the data drive IC including the sensing unit.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art. It will be appreciated that it can be implemented. Therefore, the embodiments described above are illustrative in all respects and should be understood as non-limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

10: display panel 11: timing control unit
12: data driver IC 13: scan driver
20: voltage supply unit 24: sensing unit
26: compensation unit 28: compensation memory
210: integrator 220: sampler
230: scaler 240: ADC
250, 260: integrated capacitor unit

Claims (15)

A display panel in which a plurality of pixels connected to the sensing lines are formed; And
A sensing unit that receives sensing currents of the pixels through a plurality of sensing channels connected to the sensing lines and performs a sensing operation of sampling the sensing current as a voltage value and a scaling operation of adjusting the range of the sampled voltage value Including,
The sensing unit,
An amplifier including an inverting input terminal receiving the sensing current, a non-inverting input terminal receiving the reference voltage for initialization, and an output terminal outputting an integral value;
An integrating capacitor connected between the inverting input terminal and the output terminal of the amplifier to store the sensing current input to the inverting input terminal during the sensing operation, and connected to a first reference voltage during the scaling operation; And
An integrated capacitor unit that samples the integral value output from the amplifier during the sensing operation and is connected in parallel with the integral capacitor during the scaling operation to scale and output a voltage range of the sampled integral value;
A display device having a current sensing function comprising a. The method of claim 1,
The integrating capacitor,
During the sensing operation, one end is connected to the inverting input terminal of the amplifier and the other end is connected to the output terminal,
A display device having a current sensing function in which one end is connected to the first reference voltage and the other end is connected to a node A to which the integrated capacitor unit is connected during the scaling operation. The method of claim 2,
The integrating capacitor,
A plurality of unit capacitors connected in parallel to the inverting input terminal of the amplifier; And
A display device having a current sensing function including a unit capacitor switch for interconnecting or releasing the other ends of each of the unit capacitors. The method of claim 2,
A display device having a current sensing function including a first switch connected to both ends of the integrating capacitor. The method of claim 2,
The integrated capacitor unit,
During the sensing operation, one end is connected to the first reference voltage and the other end is connected to the output terminal of the amplifier, and during the scaling operation, one end is connected to the first reference voltage and the other end is connected to a node A to which the integrating capacitor is connected. A display device having a current sensing function including an integrated capacitor connected in parallel with the integrating capacitor. The method of claim 5,
The integrated capacitor unit,
A second switch controlling a connection between the other end of the integrated capacitor and the node A; And
A display device having a current sensing function including a fourth switch controlling a connection between one end of the integrating capacitor and the first reference voltage. The method of claim 5,
During the scaling operation, the scaling ratio is

A display device with a current sensing function set to.
(Where, CFB is the capacitance of the integrating capacitor, and CTotal is the capacitance of the integrated capacitor.) The method of claim 2,
The integrated capacitor unit,
One end is connected to node A and the other end includes an integrated capacitor connected to node B,
During the sensing operation, one end of the integrating capacitor is connected to the node A, and the other end of the integrating capacitor is connected to the node B to be connected in parallel with the integrating capacitor,
During the scaling operation, one end of the integrating capacitor and the first reference voltage are connected to the node A, and the other end of the integrating capacitor is connected to the node B and connected in parallel with the integrating capacitor. The method of claim 8,
The integrated capacitor unit,
A second switch controlling a connection between one end of the integrating capacitor and the node A; And
A display device having a current sensing function including a fourth switch controlling a connection between the other end of the integrating capacitor and the node B. The method of claim 8,
During the scaling operation, the scaling ratio is

A display device with a current sensing function set to.
(Where, CFB is the capacitance of the integrating capacitor, and CTotal is the capacitance of the integrated capacitor.) A display panel in which a plurality of pixels connected to the sensing lines are formed; And a sensing operation of sampling the sensing current as a voltage value by receiving sensing currents of the pixels through a plurality of sensing channels connected to the sensing lines, and performing a scaling operation of adjusting the range of the sampled voltage value. In the control method of a display device having a current sensing function including a unit,
During the sensing operation, an inverting input terminal receiving the sensing current, a non-inverting input terminal receiving the reference voltage for initialization, an output terminal outputting an integral value, and between the inverting input terminal and the output terminal of the amplifier Outputting the integrated value of the sensing current by using the integrating capacitor connected to;
Sampling the integral value in an integrated capacitor unit; And
Scaling and outputting a voltage range of the sampled integral value by connecting the integrating capacitor and the integrated capacitor in parallel during the scaling operation;
Control method of a display device having a current sensing function comprising a. The method of claim 11,
During the sensing operation, a control method of a display device having a current sensing function including an initialization period for initializing input terminals and output terminals of the amplifier to an integrator reference voltage. The method of claim 11,
During the scaling operation, a control method of a display device having a current sensing function including a scaling setting period for floating the integrating capacitor and connecting the integrated capacitor unit to a first reference voltage. The method of claim 13,
After the scaling setting period, a control method of a display device having a current sensing function including an integral capacitor initialization period for connecting the integral capacitor in the floating state to the first reference voltage. The method of claim 14,
After the integrating capacitor initialization period, a control method of a display device having a current sensing function including a scaling period for scaling a voltage range of the integral value stored in the integrated capacitor unit by connecting the integrating capacitor and the integrated capacitor in parallel.

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