KR20210045597A - Semiconductor package and method of manufacturing the semiconductor package - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor package to which a warpage reducer is applied for chip warpage improvement. According to the method, a first chip substrate including first semiconductor chips is formed. The first chip substrate is attached to a second chip substrate including second semiconductor chips by using an adhesion plate including adhesion layers. Sawing is performed on the first and second chip substrates and the adhesion plate. As a result, a connected semiconductor structure is formed, in which the first semiconductor chip is connected to the second semiconductor chip by the adhesion layers. The connected semiconductor structure is disposed on a mounting substrate. The connected semiconductor structure is connected to the mounting substrate using a reflow process. The second semiconductor chip is removed after the reflow process.

Description

Semiconductor package and method of manufacturing the semiconductor package

The technical idea of the present invention relates to a semiconductor package, and more particularly, to a reflow soldering method for controlling chip warpage and protecting a surface of a chip.

In accordance with the rapid development of the electronic industry and the demands of users, electronic devices including semiconductor packages have been further reduced in size and weight. Semiconductor packages used in electronic devices require high performance and large capacity along with miniaturization and weight reduction.

In order to realize high performance, in particular, research and development on a process for controlling chip warpage is continuously conducted.

The technical problem to be solved by the technical idea of the present invention is to provide a method of manufacturing a semiconductor package to which a warpage reducer is applied in order to improve chip warpage.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

An aspect of a method for manufacturing a semiconductor package according to the technical idea of the present invention for solving the above problem is to form a connection semiconductor structure in which a first semiconductor chip and a second semiconductor chip are connected, and the first semiconductor chip is a second The semiconductor chip and the adhesive layer are connected, and the width of the first semiconductor chip is the same as the width of the second semiconductor chip, and the connection semiconductor structure is placed on the mounting substrate, and a connection semiconductor structure is used using a reflow process. And connecting to the mounting substrate.

Another aspect of the method for manufacturing a semiconductor package according to the technical idea of the present invention for solving the above problem is to form a first chip substrate including a plurality of first semiconductor chips, and use an adhesive plate including a plurality of adhesive layers. , Attaching the first chip substrate to a second chip substrate including a plurality of second semiconductor chips, and sawing the first and second chip substrates and the adhesive plate, so that the first semiconductor chip is second by the adhesive layer. Forming a connection semiconductor structure connected to the semiconductor chip, arranging the connection semiconductor structure on the mounting substrate, and connecting the connection semiconductor structure to the mounting substrate using a reflow process.

Another aspect of the method for manufacturing a semiconductor package according to the technical idea of the present invention for solving the above problem is to form a first chip substrate including a plurality of first semiconductor chips, and use an adhesive plate including a plurality of adhesive layers. Thus, the first chip substrate is attached to a second chip substrate including a plurality of second semiconductor chips, and the first and second chip substrates and the adhesive plate are sawn, so that the first semiconductor chip is removed by the adhesive layer. 2 A connection semiconductor structure connected to the semiconductor chip is formed, the connection semiconductor structure is placed on the mounting substrate, and the connection semiconductor structure is connected to the mounting substrate using a reflow process. 2 Including the removal of the semiconductor chip.

Other specific details of the present invention are included in the detailed description and drawings.

1 is a diagram illustrating a step of forming a solder ball on an upper surface of a first chip substrate.
FIG. 2 is a diagram illustrating a step of mounting an adhesive plate on a first chip substrate.
3 is a view for explaining a step of attaching and sawing a second chip substrate on an adhesive plate.
4 is a view for explaining a step after sawing the first and second chip substrates and the adhesive plate.
5 is a diagram for describing a step in which a connection semiconductor structure is disposed on a mounting substrate.
6 is a diagram for explaining connection of a connection semiconductor structure to a mounting substrate using a reflow process.
7 is a diagram for describing a step in which a second semiconductor chip is removed after a reflow process.
8 is a diagram illustrating a step of forming a package molding part after a second semiconductor chip is removed.
9 is a diagram illustrating a method of manufacturing a semiconductor package that may be added between the steps of FIGS. 6 and 7.
10 and 11 are diagrams for describing a method of manufacturing a semiconductor package according to an embodiment to which the manufacturing method of FIG. 9 is added.
12 is a diagram for describing a semiconductor package according to some embodiments.

1 to 8 are diagrams for describing a method of manufacturing a semiconductor package according to an exemplary embodiment.

1 is a diagram illustrating a step of attaching a solder ball to an upper surface of a first chip substrate.

2 is a diagram illustrating a step of mounting an adhesive plate on a first chip substrate.

3 is a view for explaining a step of attaching and sawing a second chip substrate on an adhesive plate.

4 is a view for explaining a step after sawing the first and second chip substrates and the adhesive plate.

1 to 4, the first chip substrate 100 may include a plurality of first semiconductor chips 120.

The second chip substrate 200 may include a plurality of second semiconductor chips 220.

The adhesive plate 150 may include a plurality of adhesive layers 170.

Referring to FIG. 1, a plurality of connection terminals 60 may be disposed on an upper surface of the first chip substrate 100. The plurality of connection terminals 60 are illustrated as 15 having a ball shape on the first chip substrate 100, but are not limited thereto. It goes without saying that the plurality of connection terminals 60 may be of a solder bump type in which a pillar 62 and a solder 61 are combined.

The pillar 62 has a cylindrical shape, and may include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or a combination thereof. Depending on the embodiment, a diffusion barrier layer and/or an adhesive layer (not shown) may be formed between the pillar 62 and the solder 61. The diffusion barrier layer may include, for example, nickel (Ni), cobalt (Co), copper (Cu), or a combination thereof. The adhesive layer (not shown) may include, for example, nickel (Ni), copper (Cu), palladium (Pd), cobalt (Co), platinum (Pt), gold (Au), or a combination thereof.

2 to 4, the adhesive plate 150 may be disposed on the lower surface 100b facing the upper surface 100a of the first chip substrate 100. The adhesive plate 150 may be made of an easily deformable material having a lower modulus of elasticity than oxide and nitride. In addition, the adhesive plate 150 may include a material whose adhesive strength disappears by irradiation with UV light. However, it is not limited thereto.

Specifically, the principle that adhesive strength disappears due to UV light irradiation may be that a photo initiator reacts among constituents in the adhesive plate 150 to cure surrounding adhesive components, thereby weakening the adhesive strength.

The adhesive plate 150 may connect the first chip substrate 100 and the second chip substrate 200 as well as protect the surface of the first chip substrate 100.

Specifically, when the first chip substrate 100 receives a physical impact generated during a grinding process, a crack may occur or be broken, and thus a circuit-designed wafer may be damaged. Accordingly, the problem of defects can be solved by preventing chip cracks in the first chip substrate 100 through the adhesive plate 150.

In some embodiments, the first chip substrate 100 may have weak rigidity. The adhesive plate 150 may more effectively prevent chip cracks of the first chip substrate 100 having weak rigidity. However, it is not limited thereto.

3 and 4, a second chip substrate 200 including a plurality of second semiconductor chips 220 may be attached on the lower surface 150b of the adhesive plate 150.

The connection semiconductor structure 400 may include first and second semiconductor chips 120 and 220, and may include an adhesive layer 170 connecting the first semiconductor chip 120 and the second semiconductor chip 220. I can.

In some embodiments, in the grinding step of adjusting the thickness of the second chip substrate 200, an appropriate thickness of the second chip substrate 200 may be adjusted in consideration of the thickness of the first chip substrate 100. have.

A sawing process is performed to separate a plurality of semiconductor device regions formed on a wafer to obtain individual semiconductor chips. In order to perform the sawing process, a sawing blade made of diamond or cemented carbide may be used.

The composite structure may include an adhesive plate 150 connecting the first and second chip substrates 100 and 200 and the first and second chip substrates 100 and 200.

In the process of forming the connection semiconductor structure 400, the first chip substrate 100 and the adhesive plate 150 include a second chip substrate 200 connected to the rear surface of the first chip substrate 100 by the adhesive plate 150 The composite structure may be mounted on a table of a wafer sawing apparatus.

As shown in FIG. 3, in some embodiments, the sawing blade may cut the adhesive plate 150 connecting the first and second chip substrates 100 and 200 and the first and second chip substrates 100 and 200. I can.

Specifically, a sawing process may be performed while the adhesive plate 150 is disposed between the first chip substrate 100 and the second chip substrate 200. The first and second chip substrates 100 and 200 may include a chip region and a scribe region (not shown) surrounding the chip region.

Referring to FIG. 4, the adhesive layer 170 may be disposed between the first semiconductor chip 120 and the second semiconductor chip 220. Looking at the sawing process, since the first and second chip substrates 100 and 200 and the adhesive plate 150 are sawn to form a plurality of connection semiconductor structures 400, the first semiconductor chip 120 and the second semiconductor chip Both 220 and the adhesive layer 170 have the same width.

In the present specification, the width of the first semiconductor chip 120 is the first width W1, the width of the second semiconductor chip 220 is the second width W2, and the width of the adhesive layer 170 is the third width. It is defined as (W3). In the sawing process, the first width W1, the second width W2, and the third width W3 are the same.

The composite structure placed on the table by a diamond wheel blade rotated by a spindle motor rotating at high speed may be separated into a plurality of connected semiconductor structures 400 by cutting a set scribe line.

Although five connection terminals are illustrated on the first semiconductor chip 120, the present invention is not limited thereto.

5 is a diagram for describing a step in which a connection semiconductor structure is disposed on a mounting substrate.

The connection semiconductor structure 400 including the first semiconductor chip 120 on which the plurality of connection terminals 60 are formed may be mounted on the mounting substrate 50 using a flip chip bonding technique.

In the flip chip bonding technology, a connection terminal 60 electrically connected to the integrated circuit is formed on the first semiconductor chip 120 on which the integrated circuit is formed, and the first semiconductor chip 120 is mounted on the substrate 50 by using the same. It is a technology that is directly implemented in

An electronic product requiring miniaturization, weight reduction, and high-density mounting due to the fact that the electrical connection of the plurality of connection terminals 60 and the mounting of the first semiconductor chip 120 can be made simultaneously with the flip chip bonding technology, and the electrical path is short. It can be widely used in the manufacture of. However, in order to directly mount the semiconductor chip on the mounting substrate 50 by using the flip chip bonding technology, it is difficult to verify the reliability of the semiconductor chip. It can be widely applied to manufacturing a semiconductor chip package at the level of a chip size called a chip scale package or a chip size package.

The mounting substrate 50 may be a package substrate, and may be, for example, one of a printed circuit board (PCB), an interposer substrate, or a redistributed layer (RDL) substrate. Although not shown, wiring, pads, lands, etc. may be formed between the upper and lower surfaces of the mounting substrate 50.

6 is a diagram for explaining connection of a connection semiconductor structure to a mounting substrate using a reflow process.

In general, the reflow device refers to a device that melts a plurality of connection terminals 60 and solders the connection semiconductor structure 400 mounted on the mounting board 50 to the mounting board 50.

Specifically, the reflow device transfers the mounting substrate 50 on which the connection semiconductor structure 400 is mounted by a conveyor, etc., while heating in a heating chamber, and the connection terminal 60 applied on the mounting substrate 50 After melting, the molten connection terminal 60 is cooled and solidified in a cooling chamber, so that the connection semiconductor structure 400 may be soldered onto the mounting substrate 50.

The reflow device uses hot air 900 generated by a heater and a fan to heat the connection terminal 60 applied on the mounting substrate 50 to a temperature range equal to or higher than its melting point, and then cool it. By doing so, soldering can be carried out.

As shown in FIG. 6, in a reflow apparatus or a reflow oven, the solder 61 of the connection terminal 60 disposed on the first semiconductor chip 120 is melted by the hot air 900 to form a curved shape. Can be

The solder 61 is curved to cover a part of the side surface of the pillar 62, but is not limited thereto.

In the reflow process, the second semiconductor chip 220 may control the warpage of the first semiconductor chip 120.

For example, as the thickness of the first semiconductor chip 120 decreases, when the reflow process is performed without the second semiconductor chip 220, the degree of warpage of the first semiconductor chip may increase. have.

Therefore, even if the thickness of the first semiconductor chip 120 or the mounting substrate 50 increases or decreases, the reflow process proceeds while the second semiconductor chip 220 is attached to the adhesive layer 170, thereby The warpage of the chip 120 can be controlled to a desired level.

By performing the reflow process while the second semiconductor chip 220 is attached to the adhesive layer 170, the gap between the first semiconductor chip 120 and the mounting substrate 50 can be adjusted, and accordingly, the non- -Wet/Short defects may not occur. However, it is not limited thereto.

7 is a diagram for describing a step in which a second semiconductor chip is removed after a reflow process.

As a method of removing the second semiconductor chip 220, a property of the adhesive layer 170 that loses adhesion in response to UV may be utilized.

Specifically, in the case of using UV, a photo initiator, one of the constituents in the adhesive layer 170, reacts on the upper surface 170a of the adhesive layer 170 to cure the surrounding adhesive components, thereby weakening the adhesive strength. I can.

When removing the second semiconductor chip 220, in order to use UV, the second semiconductor chip 220 may be a material capable of transmitting UV. For example, the second semiconductor chip 220 may be glass or ceramic.

As another method of removing the second semiconductor chip 220, a method of losing adhesive strength by utilizing the upper surface of the second adhesive layer 170 as a material soluble only in a solvent may be used. In the case of the solvent, since it is sufficient to lose the adhesive strength of the adhesive layer 170, it is not limited to a specific solvent.

8 is a diagram illustrating a step of forming a package molding part after a second semiconductor chip is removed.

The package molding part 500 may be disposed on the mounting substrate 50 to surround the first semiconductor chip 120, the adhesive layer 170, and the plurality of connection terminals 60.

The package molding part 500 may maintain the outer shape of the semiconductor package and protect the first semiconductor chip 120 from external physical shock or moisture. The package molding part 500 may be formed by, for example, a molding process using any one selected from among epoxy molding compounds (EMC), silicone resins, polyimide, or equivalents thereof. For example, the package molding part 500 may be formed of an epoxy-based material, a thermosetting material, a thermoplastic material, a UV curable material, or the like. In the case of a thermosetting material, a phenol type, an acid anhydride type, an amine type curing agent and an additive of an acrylic polymer may be included.

In addition, the package molding part 500 is formed of resin and may contain a filler. For example, the package molding part 500 may be formed of an epoxy-based material containing about 80% of a silica filler. Of course, the content of the silica filler is not limited to the above value. For example, by appropriately adjusting the content of the filler, the modulus of the package molding part 500 can be appropriately adjusted. For reference, the modulus represents the modulus of elasticity, and a material having a small modulus may be flexible or soft, and a material having a large modulus may be firm or hard.

As illustrated, the underfill 70 may not fill the space between the first semiconductor chip 120 and the mounting substrate 50.

9 to 11 are diagrams for explaining a semiconductor package according to some embodiments in which an underfill is formed.

9 is a diagram illustrating a method of manufacturing a semiconductor package that may be added between FIGS. 6 and 7. Redundant parts will be briefly described or omitted.

9 and 10, in a method of manufacturing a semiconductor package according to some embodiments, the underfill 70 may be formed after the reflow process and before the step in which the second semiconductor chip 220 is removed.

The underfill 70 may fill a space between the first semiconductor chip 120 and the mounting substrate 50. Specifically, a plurality of connection terminals 60 in the space may be filled.

The underfill 70 may serve to redistribute stress and strain generated due to a difference in coefficient of thermal expansion between the first semiconductor chip 120 and the mounting substrate 50.

In some embodiments, when preheating of the mounting substrate 50 is performed or not, the underfill 70 flows under the package CSP/BGA package to close a gap between the semiconductor package and the mounting substrate 50 by a capillary action. It can be filled and a fillet can be formed around the semiconductor package. The liquid underfill 70 adhesive then becomes a crosslinked solid through thermal curing, thereby protecting the solder joint.

As illustrated, the underfill 70 is illustrated to cover portions of both sidewalls 120c and 120d of the first semiconductor chip 120, but is not limited thereto.

The underfill 70 may be formed of a non-conductive adhesive or a non-conductive tape that exhibits a fluxing effect. Here, the meaning of "exhibiting a fluxing effect" means that, as in the case of ordinary resin-based fluxes, a coating film formed to block the atmosphere by covering the metal surface of the soldered body is due to its active ingredient, It can mean a phenomenon in which the metal oxide on the surface is reduced, and at the same time, the coating film is pushed out by the molten solder, whereby the molten solder comes into contact with the metal surface, and the remaining coating film functions as an insulating material between the circuit elements. have.

The underfill 70 is silicon oxide, silicon nitride, silicon oxynitride, TEOS (Tetra Ethyl Ortho Silicate), FOX (Flowable Oxide), TOSZ (Tonen SilaZen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG ( PhosphoSilaca Glass), BoroPhosphoSilica Glass (BPSG), Plasma Enhanced Tetra Ethyl Ortho Silicate (PETEOS), or a low-modulus material. Low dielectric constant materials are, for example, FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide , porous polymeric material, etc. may be included, but are not limited thereto.

In particular, the reason why the underfill 70 is performed before the step of removing the second semiconductor chip 220 with a solvent is that the underfill 70 does not fill the space between the first semiconductor chip 120 and the mounting substrate 50. In this case, this is because the solvent may flow into the space between the mounting substrate 50 and the first semiconductor chip 120 to cause a connection failure. However, it is not limited thereto.

Referring to FIG. 11, as the underfill 70 is formed, the package molding part 500 is disposed on the upper surface 50a of the mounting substrate 50, so that the first semiconductor chip 120, the adhesive layer 170, and the underfill (70) can be enclosed.

12 is a diagram for describing a semiconductor package according to some embodiments.

Referring to FIG. 12, before the step of forming the package molding part 500, in some embodiments, a third semiconductor chip 120 having a width different from that of the first semiconductor chip 120 and the adhesive layer 170 is formed on the adhesive layer 170. A semiconductor chip 320 may be disposed. The meaning that the third semiconductor chip 320 having a different width can be disposed means that it is made by a process different from that of the first semiconductor chip 120. However, it is not limited thereto.

As shown, the adhesive layer 170 may be disposed between the first semiconductor chip 120 and the third semiconductor chip 320. The third semiconductor chip 320 may be electrically connected to the mounting substrate 50 by a wire 320w. Although not shown, the third semiconductor chip 320 may include a chip pad, and the mounting substrate 50 may include a mounting substrate pad.

As shown, in some embodiments, one third semiconductor chip 320 is disposed on the adhesive layer 170, but additionally, a plurality of semiconductor chips may be disposed. In stacking a plurality of semiconductor chips, a chip package technology using TSV may be used.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those skilled in the art to which the present invention pertains. It will be understood that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative and non-limiting in all respects.

50: mounting board
70: underfill
100: first chip substrate
200: second chip substrate
150: adhesive plate
120: first semiconductor chip
220: second semiconductor chip
320: third semiconductor chip
170: adhesive layer
400: connection semiconductor structure
500: package molding part

Claims (10)

A connection semiconductor structure is formed in which a first semiconductor chip and a second semiconductor chip are connected, the first semiconductor chip is connected to the second semiconductor chip by an adhesive layer, and the width of the first semiconductor chip is of the second semiconductor chip. Equal to the width,
Arranging the connection semiconductor structure on a mounting substrate,
A method of manufacturing a semiconductor package comprising connecting the connection semiconductor structure to the mounting substrate by using a reflow process. The method of claim 1,
After the reflow process, the method of manufacturing a semiconductor package further comprising removing the second semiconductor chip. The method of claim 2,
After removing the second semiconductor chip, the adhesive layer remains on the first semiconductor chip. The method of claim 2,
After removing the second semiconductor chip, the method of manufacturing a semiconductor package further comprising forming a third semiconductor chip on the adhesive layer. The method of claim 2,
After removing the second semiconductor chip, the method of manufacturing a semiconductor package further comprising forming a package molding part surrounding the first semiconductor chip and the adhesive layer. The method of claim 1,
The connection semiconductor structure includes a first chip substrate including a plurality of the first semiconductor chips, a second chip substrate including the plurality of second semiconductor chips, and an adhesive plate including the plurality of adhesive layers. A method of manufacturing a semiconductor package formed by using. Forming a first chip substrate including a plurality of first semiconductor chips,
Attaching the first chip substrate to a second chip substrate including a plurality of second semiconductor chips using an adhesive plate including a plurality of adhesive layers,
Sawing the first and second chip substrates and the adhesive plate to form a connection semiconductor structure in which the first semiconductor chip is connected to the second semiconductor chip by the adhesive layer,
Arranging the connection semiconductor structure on a mounting substrate,
A method of manufacturing a semiconductor package comprising connecting the connection semiconductor structure to the mounting substrate by using a reflow process. The method of claim 7,
After the reflow process, the method of manufacturing a semiconductor package further comprising removing the second semiconductor chip. Forming a first chip substrate including a plurality of first semiconductor chips,
Attaching the first chip substrate to a second chip substrate including a plurality of second semiconductor chips using an adhesive plate including a plurality of adhesive layers,
Sawing the first and second chip substrates and the adhesive plate to form a connection semiconductor structure in which the first semiconductor chip is connected to the second semiconductor chip by the adhesive layer,
Arranging the connection semiconductor structure on a mounting substrate,
Using a reflow process, connecting the connection semiconductor structure to the mounting substrate,
After the reflow process, a method of manufacturing a semiconductor package comprising removing the second semiconductor chip. The method of claim 9,
After removing the second semiconductor chip, the method of manufacturing a semiconductor package further comprising forming a package molding part surrounding the first semiconductor chip and the adhesive layer.

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