JP2008103520A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device by suppressing the generation of cracks in a wiring board during a severe reliability test. <P>SOLUTION: The semiconductor device 1 is constituted in such a manner that a semiconductor chip 2 is mounted to a wiring board 3 with an electrode 2a of the semiconductor chip 2 connected to a connection terminal 15 of the wiring board 3 by a bonding wire 4, and a sealing resin 5 is so formed on the top face 3a of the wiring board 3 as to coat the semiconductor chip 2 and the bonding wire 4, and solder balls 6 are connected to the bottom face 3b of the wiring board 3. The wiring board 3 is a resin substrate containing glass cloth. The softening temperature of a resin material of a substrate layer 11 of the wiring board 3 is set higher than the melting point of a solder from which the solder balls 6 which are terminals for external connection are formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique effectively applied to a semiconductor device in which a semiconductor chip is mounted on a wiring board and sealed with a resin, and a method for manufacturing the same.

  A semiconductor chip is mounted on the wiring board, the electrodes of the semiconductor chip and the connection terminals of the wiring board are electrically connected with bonding wires, the semiconductor chip and the bonding wires are sealed with resin, and solder balls are connected to the back surface of the wiring board. Thus, a semiconductor device in the form of a semiconductor package is manufactured.

Japanese Patent Laying-Open No. 2003-92374 (Patent Document 1) discloses a wiring board having a main surface, an insulating film formed on the main surface, and an electrode exposed from the insulating film and formed on the main surface. A semiconductor chip fixed on an insulating film on the main surface of the wiring board via an adhesive, a conductive wire connecting the electrode on the main surface of the wiring board and the electrode of the semiconductor chip, and the semiconductor chip and the wiring board The technology regarding the semiconductor device which has the sealing body which covers the main surface of this and an electrode is described.
JP 2003-92374 A

  According to the study of the present inventor, the following has been found.

  In recent years, the demand for reliability of semiconductor devices has been increasing. For example, in the case of a semiconductor device used in an automobile or the like, a thermal load cycle is easily applied, and high reliability is required. For this reason, increasing the reliability of the semiconductor device as much as possible is extremely important in developing and manufacturing the semiconductor device.

  As a reliability test of the semiconductor device, the present inventor conducted a thermal cycle test in which the semiconductor device was left in a high temperature and high humidity environment or heated at a high temperature and then repeatedly heated and cooled. If the load conditions of the reliability test are tightened in order to improve the reliability of the semiconductor device, cracks that could not be detected by the reliability test that is generally performed are found in the wiring board constituting the semiconductor device. It was found to occur. This is because a CSP (Chip Size) in which the size of a semiconductor chip (outer size, planar size) and the size of a wiring board (outer size, planar size) are substantially the same in order to realize miniaturization of a semiconductor device. It has been found that cracks are likely to occur in a package type semiconductor device. The reason for this is that the semiconductor chip and the wiring board are made of different materials and thus have different thermal expansion coefficients. When the size of the wiring board is larger than the size of the semiconductor chip, the influence (region) of the stress on the wiring board is small even if the expansion / contraction action acts on the semiconductor chip in the thermal cycle test. However, if the size of the semiconductor chip is almost the same as the size of the wiring board, the expansion / contraction action of the semiconductor chip affects the wide area of the wiring board, so the influence (region) of stress on the wiring board increases. Because. In such a semiconductor device, when a temperature exceeding the softening temperature (Tg) of the wiring board is applied in a high temperature region of the thermal cycle test, the core material of the wiring board is softened, and the glass wire cloth (glass Peeling occurs at the interface between the fiber and the resin (core crack). It was also found that core cracks progress during cooling. This is because the resin contained in the core material is hardened by being cooled, and stress due to the shrinkage action is applied to the hardened resin, so that cracks that have already occurred increase. The cracks in the wiring board are more greatly generated as the number of cycles in the thermal cycle test is increased. For this reason, a highly reliable semiconductor device that can suppress the occurrence of cracks in the wiring board even after a strict reliability test is desired.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the present invention, the softening temperature of the resin material constituting the wiring board of the semiconductor device is set higher than the melting point of the solder constituting the external connection terminal of the semiconductor device.

  In the present invention, the softening temperature of the resin material constituting the wiring board of the semiconductor device is set higher than the solder reflow temperature when forming the external connection terminals of the semiconductor device.

  In the present invention, the softening temperature of the resin material constituting the wiring board of the semiconductor device is set higher than the maximum temperature during the manufacturing process of the semiconductor device.

  In the present invention, the softening temperature of the resin material constituting the wiring board of the semiconductor device is higher than the solder reflow temperature when mounting the semiconductor device.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The reliability of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  A semiconductor device and a manufacturing method (manufacturing process) of an embodiment of the present invention will be described with reference to the drawings.

  1 is a top view of a semiconductor device 1 according to an embodiment of the present invention, FIG. 2 is a bottom view thereof, FIG. 3 is a cross-sectional view (overall cross-sectional view), and FIG. FIG. 5 is a side view thereof. FIG. 6 is a plan perspective view (top view) of the semiconductor device 1 when the sealing resin 5 is seen through. 1 and 6 substantially corresponds to FIG. 3, and an enlarged view of the end vicinity region of FIG. 3 substantially corresponds to FIG.

The semiconductor device 1 of the present embodiment shown in FIGS. 1 to 6 is a semiconductor device (semiconductor package) in which a semiconductor chip 2 is mounted (bonded, connected, or mounted) on a wiring board 3. This is a semiconductor device in the form of a CSP (Chip Size Package), which is a small semiconductor package that is slightly larger than the semiconductor chip 2. Here, the positioning of the semiconductor device of the CSP form, for example the distance of the end portion of the wiring board 3 from (outer edge) to the edge of the semiconductor chip (outer edge) (corresponding to D ₁ of the FIG. 4) is 0 .65 mm or less.

  The semiconductor device 1 includes a semiconductor chip 2, a wiring board 3 on which the semiconductor chip 2 is mounted (supported), a plurality of electrodes 2a on the surface of the semiconductor chip 2, and a plurality of connection terminals 15 of the wiring board 3 corresponding thereto. A plurality of bonding wires 4 to be electrically connected, a sealing resin 5 covering the upper surface 3a of the wiring substrate 3 including the semiconductor chip 2 and the bonding wires 4, and an area array arrangement as external terminals on the lower surface 3b of the wiring substrate 3 A plurality of solder balls 6.

  The semiconductor chip 2 has a square planar shape that intersects its thickness. For example, various semiconductor elements or semiconductor integrated circuits are formed on the main surface of a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like. Accordingly, after the back surface of the semiconductor substrate is ground, the semiconductor substrate is separated into the respective semiconductor chips 2 by dicing or the like. The semiconductor chip 2 has a front surface (main surface and upper surface on the semiconductor element formation side) 2b and a rear surface (main surface and lower surface opposite to the main surface on the semiconductor element formation side) 2c, which are opposite to each other. It is mounted (arranged) on the upper surface (chip support surface) 3 a of the wiring substrate 3 so as to face upward, and the back surface 2 c of the semiconductor chip 2 is attached to the upper surface 3 a of the wiring substrate 3 via an adhesive (die bond material, bonding material) 8. Glued and fixed. As the adhesive 8, for example, an insulating or conductive paste material or a film-like adhesive (die bonding film, die attach film) or the like can be used. The thickness of the adhesive material 8 can be about 20-30 micrometers, for example. The semiconductor chip 2 has a plurality of electrodes (bonding pads, pad electrodes, terminals, second electrodes) 2a on the surface 2b, and the electrodes 2a are semiconductor elements formed in the semiconductor chip 2 or in the surface layer portion. Alternatively, it is electrically connected to the semiconductor integrated circuit.

  The wiring substrate 3 includes an upper surface (first main surface) 3a that is one main surface, a lower surface (second main surface) 3b that is a main surface opposite to the upper surface 3a, and a plurality of connections formed on the upper surface 3a. It has a terminal (terminal, electrode, first electrode) 15 and a plurality of lands (land part, conductor part, connecting conductor part, terminal connecting conductor part) 16 formed on the lower surface 3b.

  The wiring substrate 3 contains a resin material and has an insulating base layer (insulating substrate, core material, base, support member) 11, and an upper surface (main surface) 11a and a lower surface (opposite side of the upper surface 11a) of the base material layer 11 Main layer) 11b formed on conductor layer (conductor pattern, conductor film pattern, wiring layer) 12 and insulating layer formed on upper surface 11a and lower surface 11b of base material layer 11 so as to cover conductor layer 12 And a solder resist layer (insulating film, insulating resist layer) 14 as an (insulator layer). That is, the wiring board 3 has a structure in which the conductor layer 12 and the solder resist layer (insulating film, insulating resist layer) 14 are formed on the upper surface 11a and the lower surface 11b of the base material layer 11 as the core material.

The wiring substrate 3 used in the semiconductor device 1 of the present embodiment is a resin substrate containing a glass woven fabric (corresponding to a glass woven fabric 61 described later). Therefore, the base material layer 11 consists of a resin layer (resin base material layer, resin substrate) containing a glass woven fabric (corresponding to a glass woven fabric 61 described later). Then, in the present embodiment, the softening temperature T _g of the resin material constituting the wiring board 3 (base layer 11) of (corresponding to the resin material 62 to be described later), the external connection terminals of the semiconductor device 1 (here In this case, the melting point T _{0 of} the solder constituting the solder ball 6) is higher (T _g > T ₀ ). In addition, the structure of the base material layer 11 of the wiring board 3 in this Embodiment is demonstrated in detail later.

  In the wiring board 3, the conductor layer 12 is patterned, and is a conductor pattern that becomes a terminal, wiring, or wiring layer of the wiring board 3. The conductor layer 12 is made of a conductive material, and can be formed of, for example, a copper thin film formed by plating. The conductor layer 12 of the wiring board 3 includes a conductor layer 12a formed on the upper surface 11a of the base material layer 11, a conductor layer 12b formed on the lower surface 11b of the base material layer 11, and an opening of the base material layer 11. 17 and a conductor layer 12c formed on the side wall.

  A plurality of connection terminals (electrodes, bonding pads, pad electrodes) 15 for connecting the bonding wires 4 are formed by the conductor layer 12 a formed on the upper surface 11 a of the base material layer 11. Also, a plurality of conductive lands (electrodes, pads, terminals) 16 for connecting the solder balls 6 are formed by the conductor layer 12b formed on the lower surface 11b of the base material layer 11. In addition, a plurality of openings (through holes, vias, through holes) 17 are formed in the base material layer 11, and a conductor layer 12 c is formed on the side wall of each opening 17.

  Thus, the wiring board 3 includes a base material layer 11 containing a resin material and a plurality of connection terminals formed on the upper surface 11a (third main surface) of the base material layer 11 corresponding to the upper surface 3a of the wiring board 3. 15, a plurality of lands 16 formed on the lower surface 11 b (fourth main surface) of the base material layer 11 corresponding to the lower surface 3 b of the wiring substrate 3, and the upper surface 11 a and the lower surface 11 b of the base material layer 11. And a solder resist layer 14.

  The connection terminal 15 on the upper surface 11 a of the base material layer 11 includes a conductor layer 12 a (leading wiring made of the conductor layer 12 a) on the upper surface 11 a of the base material layer 11, a conductor layer 12 c on the sidewall of the opening 17, and the base material layer 11. It is electrically connected to the land 16 on the lower surface 11b of the base material layer 11 through the conductor layer 12b on the lower surface 11b. Accordingly, the plurality of electrodes 2 a of the semiconductor chip 2 are electrically connected to the plurality of connection terminals 15 of the wiring board 3 through the plurality of bonding wires 4, and further, the wiring board 3 through the conductor layer 12 of the wiring board 3. The plurality of lands 16 are electrically connected. The bonding wire 4 is made of a fine metal wire such as a gold wire.

  The solder resist layer 14 has a function as an insulating layer (insulating film) for protecting the conductor layer 12, and is made of an insulating material such as an organic resin material. The solder resist layer 14 is formed on the upper surface 11 a and the lower surface 11 b of the base material layer 11 so as to cover the conductor layer 12, and the solder resist layer 14 fills the inside of the opening 17 of the base material layer 11. Yes. Since the solder resist layer 14 fills the opening 17 of the base material layer 11, the adhesive 8 for bonding the semiconductor chip 2 to the wiring board 3 leaks from the opening 17 to the lower surface 3 b side of the wiring board 3. In addition, the back surface 2c of the semiconductor chip 2 can be prevented from being exposed from the opening 17. Further, in the conductor layer 12 of the wiring board 3, the connection terminal 15 and the land 16 are exposed from the openings 19 a and 19 b of the solder resist layer 14. Moreover, the thickness of the solder resist layer 14 on the upper surface 11a and the lower surface 11b of the base material layer 11 can be about 20-30 micrometers, for example. The semiconductor chip 2 is mounted on and bonded to the solder resist layer 14 on the upper surface 3 a side of the wiring substrate 3 via an adhesive material 8. An opening 18 as a package index is also formed in the solder resist layer 14 on the upper surface 3a side of the wiring board 3. The opening 18 as a package index formed in the solder resist layer 14 is used for confirming the index direction during the manufacturing process of the semiconductor device 1 (the process until a sealing resin 5a described later is formed) and for mounting the semiconductor chip 2 It can be used for recognition. Here, it has been described that the opening 18 is formed as the package index. However, the present invention is not limited to this, and the connection terminal 15 and the plurality of lands 16 are electrically connected to a part of the upper surface 3 a of the wiring board 3. A conductor pattern that is not connected to the conductor pattern and the conductor pattern covered with the solder resist layer 14 may be used as a package index.

  The plurality of lands 16 are arranged in an array on the lower surface 3 b of the wiring board 3. An opening 17 is formed next to or near each land 16. Also, solder balls (ball electrodes, protruding electrodes, electrodes, external terminals, external connection terminals) 6 are connected (formed) to each land 16. For this reason, a plurality of solder balls 6 are arranged in an array on the lower surface 3 b of the wiring board 3. The solder ball 6 can function as an external connection terminal (external terminal) of the semiconductor device 1. For this reason, the semiconductor device 1 of the present embodiment has a plurality of external connection terminals (here, solder balls 6) respectively formed on the plurality of lands 16 on the lower surface 3b of the wiring board 3. The plurality of external connection terminals (here, solder balls 6) are made of solder.

  Accordingly, the plurality of electrodes 2 a of the semiconductor chip 2 are electrically connected to the plurality of connection terminals 15 of the wiring board 3 through the plurality of bonding wires 4, and further, the wiring board 3 through the conductor layer 12 of the wiring board 3. The plurality of lands 16 and the plurality of solder balls 6 connected to the plurality of lands 16 are electrically connected. Although the number of solder balls 6 in FIG. 2 and the number of connection terminals 15 in FIG. 6 do not match, FIGS. 1 to 6 schematically show the structure of the semiconductor device 1. The number of solder balls 6 and the number of connection terminals 15 in 1 can be variously changed as necessary, and the number of solder balls 6 and the number of connection terminals 15 in the semiconductor device 1 can be made the same. It can also be made. Also, the solder balls 6 that are not electrically connected to the electrodes 2a of the semiconductor chip 2 can be used for heat dissipation.

  In the present embodiment, the case where the solder balls 6 are formed as the external connection terminals of the semiconductor device 1 is described. However, the external connection terminals of the semiconductor device 1 may be formed by soldering. External connection terminals other than the solder balls 6, for example, solder bumps (bump electrodes) can be formed on the lands 16. Further, it is more preferable that the external connection terminal of the semiconductor device 1 is formed of solder not containing lead (lead-free solder).

  Solder resist layers 14 are formed on the upper and lower surfaces of the wiring board 3. The solder resist layer 14 formed on the upper surface 3 a of the wiring board 3 has an opening 19 a for exposing the connection terminals 15. . The bonding wire 4 is connected to the connection terminal 15 exposed from the opening 19 a of the solder resist layer 14. In order to facilitate or ensure the connection of the bonding wire 4 to the connection terminal 15, the upper surface of the connection terminal 15 exposed from the opening 19 a of the solder resist layer 14 (the connection surface of the bonding wire 4) is a gold plating layer (or A nickel plating layer (lower layer side) and a gold plating layer (upper layer side) are formed. The solder resist layer 14 formed on the lower surface 3 b of the wiring board 3 has an opening 19 b for exposing the land 16. Solder balls 6 are connected to the lands 16 exposed from the openings 19b of the solder resist layer 14.

  The sealing resin (sealing resin portion, sealing portion, sealing body) 5 is made of, for example, a resin material such as a thermosetting resin material, and can include a filler. For example, the sealing resin 5 can be formed using an epoxy resin containing a filler. The sealing resin 5 is formed on the upper surface 3 a of the wiring substrate 3 so as to cover the semiconductor chip 2 and the bonding wires 4. That is, the sealing resin 5 is formed on the upper surface 3 a of the wiring substrate 3 and seals the semiconductor chip 2 and the bonding wires 4. The semiconductor chip 2 and the bonding wire 4 are sealed and protected by the sealing resin 5.

  Next, an example of a semiconductor device manufacturing method (manufacturing process) according to the present embodiment will be described.

  FIG. 7 is a manufacturing process flow chart showing the manufacturing process of the semiconductor device of the present embodiment. 8 to 14 are explanatory views (sectional views) of the manufacturing process of the semiconductor device of the present embodiment. 8 to 14 show cross-sections of the respective process steps of the same region (region straddling the two semiconductor device regions 32a), and are cross-sectional views for easy understanding of the drawings, but hatching is omitted. Yes.

  In the present embodiment, individual semiconductor devices 1 are manufactured using a multi-piece wiring substrate (wiring substrate base) 31 formed by connecting a plurality of wiring substrates 3 (semiconductor device regions 32a) in an array. The case where it does is demonstrated. The wiring board 31 is a base body of the wiring board 3. The semiconductor device is obtained by cutting the wiring board 31 in a cutting process to be described later and separating it into each semiconductor device region (substrate region, unit substrate region, device region) 32a. This corresponds to one wiring board 3. The wiring substrate 31 has a configuration in which a plurality of semiconductor device regions 32a from which one semiconductor device 1 is formed are arranged in a matrix.

First, as shown in FIG. 8, a wiring board 31 is prepared (step S1). In step S1, the wiring substrate 31 includes a plurality of semiconductor device regions 32a, each of which is a unit substrate region from which the semiconductor device 1 is manufactured, and includes an upper surface 31a (first main surface) and an opposite side of the upper surface 31a. A wiring board 31 having a lower surface 31b (second main surface), a plurality of connection terminals 15 on the upper surface 31a of each semiconductor device region 32a, and a plurality of lands 16 on the lower surface 31b of each semiconductor device region 32a is prepared. The Further, as described above, since the wiring board 3 is a resin substrate containing a glass woven cloth (corresponding to a glass woven cloth 61 described later), the wiring board 31 prepared in step S1 is also a glass woven cloth (described later). This corresponds to the glass woven fabric 61). Further, the softening temperature T _g of the resin material constituting the wiring substrate 31 (substrate layer 11) (corresponding to the resin material 62 to be described later), the configuration (solder balls 6 in this case) terminals external connection of the semiconductor device 1 The melting point T _{0 of} the solder to be soldered is higher (T _g > T ₀ ).

  After preparing the wiring board 31 in step S1, a die bonding process is performed, and as shown in FIG. 9, the semiconductor chip 2 is bonded to the adhesive material 8 on each semiconductor device region 32a of the upper surface 31a of the wiring board 31. Are mounted and bonded (die bonding, chip mounting) (step S2). As the adhesive 8, a paste adhesive, a film adhesive, or the like can be used.

In this embodiment, the softening temperature T _g of the resin material constituting the wiring substrate 31 (substrate layer 11) (corresponding to the resin material 62 to be described later), the wiring board 31 at the time of die bonding step S2 It is higher than the heating temperature (corresponding to the die-bonding temperature T _DB to be described later).

  Next, as shown in FIG. 10, a wire bonding step is performed to electrically connect each electrode 2 a of the semiconductor chip 2 and the connection terminal 15 formed on the wiring substrate 31 corresponding thereto through the bonding wire 4. (Step S3). That is, the plurality of connection terminals 15 of each semiconductor device region 32 a on the upper surface 31 a of the wiring substrate 31 and the plurality of electrodes 2 a of the semiconductor chip 2 bonded on the semiconductor device region 32 a are electrically connected via the plurality of bonding wires 4. Connect.

In this embodiment, the softening temperature T _g of the resin material constituting the wiring substrate 31 (substrate layer 11) (corresponding to the resin material 62 to be described later), the wiring substrate 31 during wire bonding step S3 It is higher than the heating temperature (corresponding to a wire bonding temperature _TWB described later).

  Next, as shown in FIG. 11, resin sealing is performed by a molding process (resin sealing process, resin molding process, for example, transfer molding process), and the semiconductor chip 2 and bonding wires are formed on the upper surface 31 a of the wiring substrate 31. 4 is formed so as to cover 4 and the semiconductor chip 2 and the bonding wire 4 are sealed with the sealing resin 5a (step S4). The sealing resin 5a is made of, for example, a resin material such as a thermosetting resin material, and may include a filler. For example, the sealing resin 5a can be formed using an epoxy resin containing a filler.

  In the molding step of step S4, collective sealing (collective molding) can be performed in which the plurality of semiconductor device regions 32a on the upper surface 31a of the wiring substrate 31 are collectively sealed with the sealing resin 5a. That is, the sealing resin 5a is formed on the whole of the plurality of semiconductor device regions 32a on the upper surface 31a of the wiring substrate 31 so as to cover the semiconductor chip 2 and the bonding wires 4 in those semiconductor device regions 32a. For this reason, the sealing resin 5 a is formed so as to cover the whole of the plurality of semiconductor device regions 32 a on the upper surface 31 a of the wiring substrate 31. As another form, in the molding process of step S4, division sealing (individual sealing) is performed in which the sealing region is divided for each semiconductor device region 32a and the sealing resin 5a is individually formed for each semiconductor device region 32a. In this case, the sealing resin 5a is formed on each semiconductor device region 32a on the upper surface 31a of the wiring substrate 31 so as to cover the semiconductor chip 2 and the bonding wire 4 in each semiconductor device region 32a.

  A sealing body (assembly) 41 is formed by the wiring substrate 31 and the sealing resin 5a on the wiring substrate 5a (including the semiconductor chip 2 and the bonding wire 4 sealed in the sealing resin 5a). That is, a structure in which the sealing resin 5 a is formed on the multi-piece wiring substrate 31 is referred to as a sealing body 41.

In this embodiment, the softening temperature T _g of the resin material constituting the wiring substrate 31 (substrate layer 11) (corresponding to the resin material 62 to be described later) is the time of sealing resin 5a forming process of step S4 It is higher than the heating temperature of the wiring board 31 (corresponding to the resin encapsulation temperature T _MD to be described later).

  Next, as shown in FIG. 12, the solder balls 6 are connected (bonded and formed) to the lands 16 on the lower surface 31b of the wiring board 31 (step S5).

In the solder ball 6 connecting step in step S5, for example, the solder balls 6 are disposed (mounted) on the plurality of lands 16 of each semiconductor device region 32a of the lower surface 31b of the wiring board 31 with the lower surface 31b of the wiring board 31 facing upward. The solder balls 6 are temporarily fixed with a flux or the like, and then solder reflow processing (reflow processing, heat treatment) is performed to melt and resolidify the solder, and the solder balls 6 are respectively formed on the plurality of lands 16 on the lower surface 31b of the wiring board 31. Can be joined. The temperature of the solder reflow process at this time corresponds to a solder reflow temperature T _f1 described later. Thereafter, if necessary, a cleaning process can be performed to remove the flux and the like attached to the surface of the solder ball 6. In this way, the solder balls 6 as the external connection terminals (external terminals) of the semiconductor device 1 are joined (formed).

  Further, in the present embodiment, the case where the solder ball 6 is joined as the external connection terminal of the semiconductor device 1 has been described. However, the present invention is not limited to this. External connection terminals (bump electrodes, solder bumps) made of solder of the semiconductor device 1 can also be formed by supplying solder onto 16. In this case, after supplying solder onto the plurality of lands 16 of each semiconductor device region 32a on the lower surface of the wiring board 31, a solder reflow process is performed, and external connection terminals made of solder are respectively formed on the plurality of lands 16. (Bump electrode, solder bump) can be formed. Also, the external connection terminals (bump electrodes) of the semiconductor device 1 can be formed by plating (solder plating).

  The material of the external connection terminals (here, solder balls 6) of the semiconductor device 1 is preferably lead-free solder that does not contain lead.

As described above, in step S5, the external connection terminals (here, the solder balls 6) are formed on the plurality of lands 16 of the respective semiconductor device regions 32a on the lower surface 31b of the wiring board 31. In this embodiment, the softening temperature T _g of the resin material constituting the wiring substrate 31 (substrate layer 11) (corresponding to the resin material 62 to be described later), the solder reflow temperature (described later solder reflow step S5 Higher than the temperature T _f1 ).

  Next, marking is performed as necessary, and a mark such as a product number is attached to the upper surface (front surface) 5b of the sealing resin 5a (step S6). In step S6, for example, a laser mark for marking with a laser can be performed, but an ink mark for marking with ink can also be performed. Alternatively, the solder ball 6 connecting step in step S5 may be performed after the order of the solder ball 6 connecting step in step S5 and the marking step in step S6 are interchanged and the marking step in step S6 is performed. Moreover, if unnecessary, the marking process of step S6 can also be skipped.

  Next, as shown in FIG. 13, using a dicing blade (dicing saw, blade) 43 or the like, along dicing regions (dicing lines, boundaries between the semiconductor device regions 32a) 32b between the semiconductor device regions 32a. Then, dicing (cutting, cutting) is performed from the lower surface 31b side of the wiring board 31 to cut (divide) the sealing body 41 (the wiring board 31 and the sealing resin 5a) (step S7). For example, in step S7, the dicing process by the dicing blade 43 can be performed in a state where the upper surface 5b of the sealing resin 5a is attached to the package fixing tape (fixing tape) 42 and the sealing body 41 is fixed. Thereby, as shown in FIG. 14, the sealing body 41 (the wiring substrate 31 and the sealing resin 5a) is cut along the dicing region 32b, and each semiconductor device region 32a (CSP region) is individually ( The separated semiconductor device 1 (CSP) is cut and separated (divided). That is, the sealing body 41 (the wiring board 31 and the sealing resin 5a) is cut and divided into each semiconductor device region 32a, and the semiconductor device 1 is formed from each semiconductor device region 32a.

  Thus, the semiconductor device 1 as shown in FIGS. 1 to 6 can be manufactured by cutting and dividing. The wiring substrate 31 cut and separated (divided) into each semiconductor device region 32a corresponds to the wiring substrate 3, and the sealing resin 5a cut and separated (divided) into each semiconductor device region 32a corresponds to the sealing resin 5. To do.

  The semiconductor device 1 according to the present embodiment can be used by being mounted on a mounting board (wiring board, circuit board, external board, motherboard) 51 that is a wiring board for mounting the semiconductor device 1. FIG. 15 is a process flow diagram showing a mounting process of the semiconductor device 1 of the present embodiment. FIG. 16 is a side view showing a state where the semiconductor device 1 according to the present embodiment is solder-mounted on a mounting board (wiring board) 51.

  As shown in FIG. 16, the mounting substrate 51 has terminals (electrodes, conductor patterns) 52 formed on the upper surface (main surface on the side where the semiconductor device 1 is mounted) 51a. A solder resist layer (insulating film, insulating resist layer) (not shown) is formed on the upper surface 51a of the mounting substrate 51, and the terminals 52 are exposed from the openings of the solder resist layer.

  The semiconductor device 1 is prepared (manufactured) as in steps S1 to S7 (FIGS. 8 to 14) (step S11), and the semiconductor device 1 is mounted on the mounting substrate 51 (step S12). When the semiconductor device 1 is mounted on the mounting substrate 51, the plurality of lands 16 of the semiconductor device 1 are respectively connected to the plurality of terminals 52 on the upper surface 51a of the mounting substrate 51 via the solder balls 6, as shown in FIG. Joined and electrically connected.

In step S12, in order to mount the semiconductor device 1 on the mounting substrate 51, for example, the semiconductor device 1 is placed on the upper surface 51a of the mounting substrate 51 so that the solder balls 6 of the semiconductor device 1 and the terminals 52 of the mounting substrate 51 face each other. After that, solder reflow processing is performed. The temperature of the solder reflow process at this time corresponds to a solder reflow temperature _Tf2 described later. By this solder reflow process, the solder ball 6 is melted and re-solidified, whereby the semiconductor device 1 and the mounting substrate 51 are joined and fixed by the solder ball 6, and the land 16 of the semiconductor device 1 and the terminal 52 of the mounting substrate 51 are fixed. Are electrically connected via the solder balls 6.

  In step S12, before mounting the semiconductor device 1, solder paste or the like is supplied (applied) onto the terminals 52 of the mounting substrate 51, and the solder balls 6 of the semiconductor device 1 and the terminals 52 of the mounting substrate 51 are connected. It is also possible to arrange the semiconductor device 1 on the mounting substrate 51 so as to face each other through the solder paste, and then perform a solder reflow process. In this case, the solder balls 6 and the solder paste are melted and re-solidified and integrated by the solder reflow process, and the solder balls 6 after the semiconductor device 1 is mounted on the mounting substrate 51 are obtained.

As described above, the plurality of solder balls 6 of the semiconductor device 1 can function as external connection terminals (external terminals) of the semiconductor device 1, and the semiconductor device 1 is mounted on the mounting substrate 51 (another wiring substrate) or the like. In doing so, the plurality of lands 16 of the semiconductor device 1 are electrically connected to the plurality of terminals 52 of the mounting substrate 51 (another wiring substrate) via the solder balls 6, respectively. In this embodiment, the softening temperature T _g of the resin material constituting the wiring substrate 31 (substrate layer 11) (corresponding to the resin material 62 to be described later), the solder reflowing temperature (described later solder reflow step S12 Higher than the temperature T _f2 ).

  Next, the reliability test of the semiconductor device 1 examined by the present inventors will be described.

  FIG. 17 is an explanatory diagram of a reliability test performed in the present embodiment. FIG. 18 is a bottom view (corresponding to FIG. 2) of the semiconductor device 1 in which the crack 63 is generated by performing the reliability test as shown in FIG. 17 (that is, the semiconductor device 1 observed in step S25). FIG. 20 is a side view (partial enlarged side view) of the main part, and FIG. 20 is a cross-sectional view (partial enlarged cross-sectional view) of the part. FIG. 20 shows a partially enlarged cross-sectional view near the end of the semiconductor device 1. FIG. 18 is a bottom view of the semiconductor device 1, and the crack 63 does not reach the surface of the lower surface 3 b of the wiring substrate 3, but for the sake of easy understanding, the wiring substrate 3 (base material layer) is shown. 11) A hatched area is shown through a plane area where the crack 63 is generated.

  The inventor conducted a reliability test as shown in FIG. 17 to examine the reliability of the semiconductor device 1. The conditions of the reliability test performed are as follows.

First, the plurality of semiconductor devices 1 were heated at 125 ° C. for 24 hours (step S21), and then left to stand at 85 ° C./65% RH for 24 hours (step S22), so that the semiconductor device 1 absorbed moisture. And it heated at 260 degreeC for 10 second (step S23). This step S23 is a heat treatment corresponding to the solder reflow process at the time of mounting the semiconductor device 1 in step 12, and the heating temperature in step S23 is the solder reflow temperature in step 12 (corresponding to a solder reflow temperature _Tf2 described later). Same as. Therefore, step 23 can be regarded as a heat treatment in which the mounting process of the semiconductor device 1 in step S12 is performed in a pseudo manner. Then, as a thermal cycle test, cooling at -55 ° C and heating at 150 ° C are repeated (step S24). In the thermal cycle test of step S24, cooling at -55 ° C and heating at 150 ° C were performed for 15 to 30 minutes, respectively, and the time required for raising and lowering the temperature was about 5 minutes.

  A plurality of semiconductor devices 1 are prepared, and the above steps S21 to S24 are performed, and the cycle number of the thermal cycle test in step S24 is a predetermined number of times (for example, 100 cycles, 200 cycles, 500 cycles, 700 cycles, 1000 cycles, 2000 cycles). And 3,000 cycles), a predetermined number of semiconductor devices 1 were extracted, and the extracted semiconductor devices 1 were observed in detail (step S25).

  As shown in FIGS. 19 and 20, the wiring substrate 3 used in the semiconductor device 1 of the present embodiment is a resin substrate containing a glass woven fabric 61. The base material layer 11 of the wiring board 3 is composed of a glass woven fabric 61 and a resin material 62. That is, the base material layer 11 of the wiring board 3 is obtained by impregnating (impregnating) the resin material 62 into a glass woven fabric 61 formed by knitting glass fibers 61a in a cloth shape. Therefore, the base material layer 11 of the wiring board 3 includes the glass woven fabric 61 and the resin material 62, and is regarded as a resin layer (resin material, resin base material layer, resin substrate) containing the glass woven fabric 61. You can also. When the resin material 62 is an epoxy resin, the wiring substrate 3 is called a glass epoxy substrate (glass epoxy resin substrate).

  19 and 20 illustrate the case where the base material layer 11 is formed by the two glass woven fabrics 61 and the resin material 62, the glass weave constituting the base material layer 11 of the wiring board 3 is illustrated. The number of the cloths 61 is not limited to this, and can be changed as necessary. Moreover, a filler etc. can also be contained in the resin material 62 which comprises the base material layer 11 of the wiring board 3 as needed.

  In recent years, the demand for reliability of semiconductor devices has been increasing. For example, in the case of a semiconductor device used in an automobile or the like, a thermal load cycle is easily applied, and high reliability is required. For this reason, increasing the reliability of the semiconductor device as much as possible is extremely important in developing and manufacturing the semiconductor device.

  The reliability test of FIG. 17 is performed under fairly severe conditions in order to make the reliability of the semiconductor device extremely high. For example, the conditions (pre-processing conditions) of step S21 and step 22 correspond to levels 2-3 of JEDEC (Joint Electron Device Engineering Council) standards. For this reason, when the semiconductor device 1 is observed in the above step S25, when the number of cycles of the thermal cycle test in step S24 increases, cracks 63 that could not be detected in the reliability test that is generally performed become a semiconductor. It was found that this occurred in the wiring board 3 constituting the device 1.

  That is, when the reliability test as described above is performed and the number of cycles of the thermal cycle test in step S24 increases, the crack 63 as shown in FIGS. 18 to 20 becomes a base layer of the wiring board 3 of the semiconductor device 1. 11 occurs. The crack 63 is likely to occur as a state in which the vicinity of the interface between the glass woven fabric 61 and the resin material 62 of the base material layer 11 is peeled in the vicinity (peripheral portion) of the end portion of the wiring board 3.

  When this inventor examined the factor by which the crack 63 is formed in the base material layer 11 of the wiring board 3, the following thing was understood.

When the wiring board 3 is heated to a high temperature state, a minute peeling portion (interface peeling, crack) is formed between the glass woven fabric 61 (glass fiber 61a) and the resin material 62 in the base material layer 11 (interface). appear. It has been found that this minute peeling portion occurs when the temperature becomes _{equal to} or higher than the softening temperature (phase transition temperature) Tg of the resin material 62 of the base material layer 11 of the wiring board 3. When a thermal cycle test is performed in a state where such a minute peeled portion is generated, the minute peeled portion is caused by the stretching / shrinking action by repeated heating (expansion) and cooling (shrinking), particularly by the shrinking action during cooling. Is the starting point, and the separation (interface) between the glass woven fabric 61 (glass fiber 61a) and the resin material 62 in the base material layer 11 is promoted, and the resin material 62 solidifying the glass woven fabric 61 is cracked. Will occur. The crack resulting from this minute peeling part grows by the repetition of the expansion / contraction by the thermal cycle test of step S24, and reaches the crack 63 (state in which the base material layer 11 is partially separated).

In order to increase the reliability of the semiconductor device 1, it is desirable that the crack 63 does not occur in the wiring board 3 even if the number of cycles of the thermal cycle test in step S24 is increased. For this purpose, it is effective to suppress the occurrence of the minute peeling portion. Therefore, in the present embodiment, the softening temperature (phase transition temperature) T _g the external connection terminals of the semiconductor device 1 of the resin material 62 constituting the base material layer 11 of the wiring board 3 (the ball 6 solder in this case) The melting point T _{0 of} the solder to be formed is set higher (that is, T _g > T ₀ is set).

  Resins (plastics) are classified into non-crystalline resins (non-crystalline plastics) and crystalline resins (crystalline plastics). Thermosetting resins such as BT resins and epoxy resins are non-crystalline resins (non-crystalline). Plastic). In the present embodiment, a non-crystalline resin (non-crystalline plastic) is used for the resin material 62 constituting the base material layer 11 of the wiring board 3.

  In general, a crystalline substance has a regular bond, a molecular bond is broken at the melting point, a phase change from a solid state to a liquid state, and a phase transition is clear. In contrast, non-crystalline materials such as non-crystalline resins (non-crystalline plastics) are not regular crystals (bonds) and phase transitions are not clear, but as with crystalline materials, the temperature is high. Then, the molecular bond breaks.

The softening temperature _Tg of the resin material 62 is a temperature at which the amorphous resin (noncrystalline plastic) constituting the resin material 62 undergoes a phase transition, and is a temperature at which a change similar to the melting point occurs characteristically. In the softening temperature T _g, the phase transition, physical properties such as thermal expansion coefficient and elastic modulus varies discontinuously. For example, when heated from the softening temperature T _g lower temperature than the softening temperature T _g higher temperature than at the softening temperature T _g, the coefficient of thermal expansion increases discontinuously, the elastic modulus decreases discontinuously. Therefore, the softening temperature (phase transition temperature) _Tg of the resin material 62 is a temperature at which the resin material 62 undergoes phase transition, is a temperature at which the resin material 62 softens, and corresponds to the glass transition temperature in the case of glass. It is. Softening temperature _{T g} of the resin material 62 may be due to TMA (thermomechanical analysis) is measured. Softening temperature T _g of the resin material 62 constituting the base material layer 11 of the wiring board 3 are those determined by the resin constituting mainly resin material 62 itself, determined by such a filler as glass woven fabric 61 and resin material 62 It is not a thing.

The softening temperature _Tg of the resin material 62 can be controlled by adjusting the material constituting the resin material 62. For example, the resin material 62 can be made of a resin obtained by mixing BT resin (BT resin) and epoxy resin (epoxy resin). The BT resin is a resin (resin) formed by mixing a B component (bismaleimide) and a T component (triazine). Such as by adjusting the mixing ratio of the three principal components (bismaleimide and triazine and epoxy resin), it is possible to control the softening temperature T _g of the resin material 62.

Figure 21 is a graph showing the respective process temperature of the manufacturing process and the mounting process of the semiconductor device 1, the softening temperature T _g of the resin material 62 of the wiring board 3 base layer 11 (31).

In each process of the manufacturing process of the semiconductor device 1, there is a process in which the wiring board 3 (31) is heated. For example, heating at the time of die bonding in step S2 (heating for curing the adhesive 8), heating at the time of wire bonding in step S3 (heating for promoting the thermocompression bonding of the bonding wire 4), sealing at step S4 There are heating in the resin 5a forming step (heating when the sealing resin material is introduced and heating for curing the sealing resin material), and heating when forming the external connection terminal in step S5 (heating during solder reflow). . Furthermore, even after the semiconductor device 1 is manufactured, there is a heating process (heating during solder reflow) when mounting the semiconductor device 1 in step S12. An example of the heating temperature of these heating steps is shown in FIG. The die bonding temperature T _DB shown in FIG. 21 corresponds to the heating at the time of die bonding in step S2 (heating for curing the adhesive 8), and the wire bonding temperature _TWB is the heating at the time of wire bonding in step S3. Corresponding to the temperature, the resin sealing temperature _TMD corresponds to the heating temperature of the sealing resin 5a forming step in step S4. The solder reflow temperature T _f1 shown in FIG. 21 corresponds to the solder reflow temperature at the time of forming the external connection terminal (here, the solder ball 6) in step S5, and the solder reflow temperature T _f2 Corresponds to the solder reflow temperature when mounting.

Further, in FIG. 21, the softening temperature T _g of the resin material 62 of the wiring board 3 of this embodiment (31), the resin material of the wiring substrate of the first comparative example (corresponding to the resin material 62) a softening temperature T _g, and the softening temperature T _g of the resin material of the wiring substrate of the second comparative example (corresponding to the resin material 62) is shown.

As shown in FIG. 21, in the first comparative example, the softening temperature T _g of the resin material 62 of the base material layer 11 of the wiring board 3 (31) is changed to the die bonding temperature T _DB , the wire bonding temperature T _WB, and the resin. While higher than the sealing temperature _{T MD,} unlike the present embodiment, it is lower than the solder reflow temperature _{T f1, T f2 (T f1} , T f2> T g> T DB, T WB , _TMD ). Further, as shown in FIG. 21, in the second comparative example, the softening temperature T _g of the resin material 62 of the base layer 11 of the wiring board 3 (31), the die bonding temperature T _DB and resin sealing temperature T _Although it is higher than _MD, unlike the present embodiment, it is lower than the wire bonding temperature _TWB and the solder reflow temperatures _Tf1 , _Tf2 ( _Tf1 , _Tf2 , _TWB > _Tg > _Tg > T _DB , T _MD ).

In contrast, in the present embodiment, as shown in FIG. 21, the softening temperature T _g by configuring the resin material 62 by a resin that is high, the resin material 62 of the base layer 11 of the wiring board 3 (31) the softening temperature _{T g,} the die bonding temperature _{T DB,} higher than the wire bonding temperature _{T WB,} resin sealing temperature _{T MD} and the solder reflow temperature _{T f1 (T g> T DB} , T WB, T MD, T f1) is doing. That is, it is higher than the maximum temperature T _max during the manufacturing process of the semiconductor device 1 (T _g > T _max ).

In general, the maximum temperature T _max during the manufacturing process of the semiconductor device 1 is the solder reflow temperature T _f1 when the external connection terminal (here, the solder ball 6) is formed on the wiring board 31 in step S5. In particular, when lead-free solder is used, since lead-free solder has a high melting point, the solder reflow temperature T _{f1 in} step S5 becomes the maximum temperature T _max during the manufacturing process of the semiconductor device 1. Therefore, in the present embodiment, the wiring board 3 (31) of the softening temperature T _g of the resin material 62 of the base layer 11, the wiring board 3 (31) to the terminal for a plurality of external connection (solder balls here 6 ) _Is higher than the solder reflow temperature T _f1 when forming (T _g > T _f1 ), and thereby higher than the maximum temperature T _max during the manufacturing process of the semiconductor device 1 (T _g > T _max ). That is, during the manufacture of the semiconductor device 1, the wiring board 3 (31) is prevented from _reaching a temperature equal to or higher than the softening temperature Tg of the resin material 62 constituting the base material layer 11 of the wiring board 3 (31).

Further, in the present embodiment, as shown in FIG. 21, the softening temperature high T _g resins that constitute the resin material 62, the softening of the resin material 62 of the base layer 11 of the wiring board 3 (31) the temperature _{T g,} is higher than the solder reflow temperature _{T f2} when a semiconductor device is mounted _{(T g>} T f2). That is, when the semiconductor device 1 is mounted in step S <b> 12, the wiring board 3 is prevented from _reaching a temperature equal to or higher than the softening temperature Tg of the resin material 62 constituting the base material layer 11 of the wiring board 3.

FIG. 22 is a graph showing an example of a temperature curve (temperature profile) in the solder reflow process. Note that the horizontal axis of the graph of FIG. 22 is time (arbitrary unit) and the vertical axis is temperature (arbitrary unit), which shows a temperature curve during the solder reflow process. As shown in FIG. 22, when the temperature during the solder reflow process is not constant, the maximum temperature during the solder reflow process is referred to as a solder reflow temperature _Tf . The solder reflow temperatures T _f1 and T _f2 correspond to the solder reflow temperature T _f .

FIG. 23 is a table showing the results of the reliability test as shown in FIG. Figure 23 is a "present embodiment" in FIG. 21 the softening temperature T _g of the resin material 62 of the wiring board 3 base layer 11 (31), "the first comparative example" and "second comparison example FIG. 17 shows the result of the reliability test as shown in FIG. 17 described above for the semiconductor device (corresponding to the semiconductor device 1) having the three types of relations. Then, every time when the number of cycles of the thermal cycle test of Step 24 becomes 0, 1000, 2000 and 3000, 6 pieces are extracted and observed in Step 25, and the number of samples in which the crack 63 is generated (out of 6) The number of samples in which the crack 63 has occurred is shown in FIG.

In the “first comparative example”, as can be seen from FIG. 21, heating in step S5 (solder reflow process for forming the external connection terminals) and step 23 (heat treatment corresponding to the mounting process in step S12). With this heating, the wiring board 3 constituting the semiconductor device becomes a temperature _{equal to} or higher than the softening temperature (phase transition temperature) Tg of the resin material 62 of the base material layer 11 of the wiring board 3. In the “second comparative example”, as can be seen from FIG. 21, heating in step S3 (wire bonding process) and heating in step S5 (solder reflow process for forming the external connection terminals) By the heating in step 23 (heat treatment corresponding to the mounting process in step S12), the wiring board 3 constituting the semiconductor device has a softening temperature (phase transition temperature) T _g of the resin material 62 of the base material layer 11 of the wiring board 3. It becomes the above temperature.

As described above, the glass woven fabric 61 in the base material layer 11 of the wiring board 3 when the temperature becomes _{equal to} or higher than the softening temperature (phase transition temperature) Tg of the resin material 62 of the base material layer 11 of the wiring board 3. At the interface between the (glass fiber 61a) and the resin material 62, a minute peeled portion is generated. For this reason, in the semiconductor devices of the “first comparative example” and the “second comparative example”, the minute peeling portion is generated in the base material layer 11 of the wiring board 3 by step S23. The thermal cycle test of step S24 is performed in a state where such a minute peeled portion is generated. In the stage before the thermal cycle test in step S24, the peeled portion is minute. However, when the thermal cycle test is performed in step S24, the glass woven fabric 61 in the base material layer 11 starts from this minute peeled portion due to the stretching / shrinking action by repeated heating (expansion) and cooling (shrinking). Separation between the (glass fiber 61a) and the resin material 62 is promoted, and a crack is generated in the resin material 62 solidifying the glass woven fabric 61, and this crack grows to generate a crack 63 (part of the base material layer 11). Will be separated). Accordingly, as shown in FIG. 23, in the semiconductor devices of “first comparative example” and “second comparative example”, the number of cycles of the thermal cycle test in step 24 is increased to some extent (from 1000 to 2000 times). Then, a crack 63 is generated in the wiring board 3.

  On the other hand, in the semiconductor device 1 according to the present embodiment, as shown in FIG. 23, even if the number of cycles of the thermal cycle test in step 24 is increased (even 3000 times), The crack 63 hardly occurs, and the crack 63 finally occurs in the wiring substrate 3 after the number of thermal cycles exceeds 3000 times. The reason is as follows.

That is, as can be seen from FIG. 21, the semiconductor device 1 of the present embodiment is heated during the manufacturing process (steps S1 to S7) of the semiconductor device 1 and step 23 (heat treatment corresponding to the mounting process of step S12). in the heating, the wiring board 3 of the semiconductor device 1 does not enter the softening temperature (phase transition temperature) T _g above temperature of the resin material 62 of the base layer 11 of the wiring board 3. For this reason, in the semiconductor device 1 of the present embodiment, the wiring substrate is used in the heating in the manufacturing process (steps S1 to S7) of the semiconductor device 1 and the heating in step 23 (heat treatment corresponding to the mounting process in step S12). The above-described minute peeling portion does not occur at the interface between the glass woven fabric 61 (glass fiber 61a) and the resin material 62 in the three base material layers 11. Therefore, in the semiconductor device 1 of the present embodiment, the minute peeling portion that occurs in the “first comparative example” and the “second comparative example” occurs in the wiring board 3 by step S23. However, the thermal cycle test of step S24 is performed in a state where such a minute peeling portion does not occur. Thereby, even if the heating (expansion) and the cooling (shrinking) by the thermal cycle in step S24 are repeated, the above-described minute peeling portion that becomes the base point of the crack 63 does not occur, so the formation of the crack 63 in the wiring board 3 is achieved. (Generation, generation) can be suppressed or prevented. For this reason, as shown in FIG. 23, in the semiconductor device 1 of the present embodiment, even if the number of cycles of the thermal cycle test in step 24 increases (even 3000 times), The occurrence of the crack 63 can be suppressed or prevented. Therefore, the resistance to the thermal cycle can be improved, and the reliability of the semiconductor device 1 can be improved.

Thus, in this embodiment, the softening temperature T _g of the resin material 62 constituting the wiring board 3 of the semiconductor device 1 (base layer 11) of the semiconductor device 1 of the external connection terminals (solder balls here The melting point T _{0 of} the solder constituting 6) is higher (T _g > T ₀ ). Therefore, the softening temperature T _g of the resin material 62 constituting the wiring board 3 (base layer 11) of the external connection terminal to the wiring board 3 (31) (here, the solder balls 6) solder for forming the It can be higher than the reflow temperature T _f1 (T _g > T _f1 ). Therefore, the softening temperature _{T g} of the resin material 62 constituting the wiring board 3 (the base layer 11) be set higher than the maximum temperature _{T max} during the process of manufacturing the semiconductor device 1 _{(T g> T max)} it can. As a result, during the manufacturing process of the semiconductor device 1 (steps S1 to S7), the minute peeling portion serving as the base point of the crack 63 is the glass woven fabric 61 (glass fiber 61a) in the base material layer 11 of the wiring board 3. It is possible to suppress or prevent occurrence at the interface between the resin material 62 and the resin material 62. Therefore, even if a thermal cycle is applied to the semiconductor device 1, it is possible to suppress or prevent the occurrence of cracks 63 in the wiring substrate 3 of the semiconductor device 1, improve the resistance to the thermal cycle, and improve the reliability of the semiconductor device 1. Can be improved.

Further, in this embodiment, the softening temperature T _g of the resin material 62 constituting the wiring board 3 of the semiconductor device 1 (base layer 11) of external connection terminals of the semiconductor device 1 (here the solder balls 6) Is higher than the melting point T _{0 of} the solder that constitutes (T _g > T ₀ ), so that the softening temperature T _g of the resin material 62 is higher than the solder reflow temperature T _f2 when the semiconductor device 1 is mounted (T _g > T _f2 ). Thereby, during the mounting process of the semiconductor device 1 (step S12), the minute peeling portion that becomes the base point of the crack 63 is the glass woven fabric 61 (glass fiber 61a) in the base material layer 11 of the wiring substrate 3 and the resin. Occurrence at the interface with the material 62 can be suppressed or prevented. Therefore, even if a thermal cycle is applied to the semiconductor device 1 after the semiconductor device 1 is mounted, the generation of cracks 63 in the wiring substrate 3 of the semiconductor device 1 can be suppressed or prevented, and the resistance to the thermal cycle is improved. The reliability of the semiconductor device 1 can be improved.

In consideration of the influence on the environment and the like, it has been recommended to use solder that does not contain lead (lead-free solder). Also in the present embodiment, an external connection terminal (herein) Then, it is preferable to use solder containing no lead (lead-free solder) for the solder balls 6). However, lead-free solder, which is solder that does not contain lead, has a higher melting point than solder containing lead. For this reason, when the external connection terminals (here, the solder balls 6) of the semiconductor device 1 are formed of lead-free solder, the solder reflow temperatures _Tf1 and _Tf2 are higher (for example, compared to the case of using lead-containing solder) (About 260 ° C.).

If not taken into account knowledge of the occurrence of the relationship between the softening temperature T _g and the crack 63 of the resin material 62 of the present invention's heading substrate layer 11, when it is intended to lead-free solder of the wiring board 3 (31 softening temperature T _g of the resin material 62 of the base layer 11 of) is becomes lower than the solder reflow temperature T _f1, T _f2 which is higher by using a lead-free solder.

However, in the present embodiment, the external connection terminals (here, solder balls 6) of the semiconductor device 1 are preferably formed of lead-free solder having a high melting point, but the base layer 11 of the wiring substrate 3 (31) is formed. softening temperature _{T g} of the resin material 62, rather than the solder reflow temperature _{T f1, T f2} which is higher by using a lead-free solder, even higher _{(T g> T f1, T} f2) to. For example, the solder reflow temperatures T _f1 and T _f2 are set to 260 ° C. (T _f1 , T _f2 = 260 ° C.) by forming the external connection terminals (here, the solder balls 6) of the semiconductor device 1 with lead-free solder. If the softening temperature _{T g} of the resin material 62 of the wiring board 3 base layer 11 (31) is higher than _{260 ℃ (T g> 260 ℃} ) to. Thus, even if lead-free solder having a melting point higher than that of lead-containing solder is used for the external connection terminal (here, solder ball 6) of the semiconductor device 1, during the manufacturing process and the mounting process of the semiconductor device 1, It is possible to suppress or prevent the occurrence of the minute peeling portion serving as a base point of the crack 63, to prevent the crack 63 in the wiring substrate 3 due to the thermal cycle, and to improve the reliability of the semiconductor device 1. . The wiring if substrate 3 (31) higher than 260 ° C. The softening temperature _{T g} of the resin material 62 of the base layer 11 of _(T g> 260 ° C.), the semiconductor device for external connection terminals (solder here 1 The solder for mounting the balls 6) and the semiconductor device 1 can be made lead-free.

In the present embodiment, the difference between the thermal expansion coefficient α ₁ of the sealing resin 5 and the thermal expansion coefficient α ₂ of the resin material 62 constituting the wiring board 3 (base material layer 11 thereof) is further sealed. It is preferable to be 20% or less (| (α ₁ −α ₂ ) / α ₁ | ≦ 0.2) with respect to the thermal expansion coefficient α ₁ of the stop resin 5. Thermal expansion coefficient alpha ₁ of the sealing resin 5 may be controlled to a desired value, such as by adjusting the material constituting the sealing resin 5, the resin constituting the wiring board 3 (base layer 11) of The thermal expansion coefficient α ₂ of the material 62 can be controlled to a desired value by adjusting the material constituting the resin material 62.

In the present embodiment, the difference between the thermal expansion coefficient α ₁ of the sealing resin 5 and the thermal expansion coefficient α ₂ of the resin material 62 constituting the wiring board 3 (base material layer 11 thereof) is small, preferably sealed. by relative thermal expansion coefficient alpha ₁ of the resin 5 to 20% or less, when subjected to heat cycle test in step S24, the heating wiring board 3 by Shin contracting action due to repeated (expansion) and cooling (contraction) It is possible to reduce the stress generated in. Thereby, the stress applied to the wiring board 3 in the thermal cycle test in step S24 can be reduced. For this reason, even if a thermal cycle is applied to the semiconductor device 1, the generation of cracks 63 in the wiring substrate 3 of the semiconductor device 1 can be more accurately suppressed or prevented, and the resistance to the thermal cycle is further improved. 1 can be further improved.

Thus, in the present embodiment, by controlling the softening temperature T _g of the resin material 62 of the base layer 11 of the wiring board 3 (31), during the manufacturing process and the mounting process of the semiconductor device 1, the cracks It is possible to prevent the minute peeling portion serving as the base point of the 63 from occurring in the wiring board 3 (31), thereby preventing the formation of the crack 63 due to the thermal cycle. Further, by controlling the thermal expansion coefficient alpha ₂ of the resin material 62 constituting the wiring board 3 (the base layer 11 of), to reduce the stress applied to the wiring board 3 by thermal cycles, further the formation of cracks 63 Can be prevented.

  In this embodiment, since the reliability of the semiconductor device can be made extremely high in this way, the semiconductor device can be applied to a semiconductor device that requires high reliability, such as a semiconductor device for in-vehicle use (for automobile use). The effect is greater.

  24 and 25 are a principal part sectional view (partially enlarged sectional view) and a plan perspective view (top view) showing a modification of the semiconductor device 1, and correspond to FIG. 4 and FIG. 6, respectively.

  In the semiconductor device 1 shown in FIGS. 24 and 25, the solder resist layer 14 is formed on the outer peripheral portion (peripheral portion, peripheral portion) of the upper surface 3a (11a) of the wiring substrate 3 (the base material layer 11 constituting the wiring substrate 3). The outer peripheral part (peripheral part, peripheral part) of the upper surface 11 a of the base material layer 11 of the wiring substrate 31 is in contact with (in contact with or in close contact with) the sealing resin 5. Other configurations and manufacturing steps are the same as those of the semiconductor device 1 shown in FIGS.

  In the semiconductor device 1 shown in FIG. 24 and FIG. 25, a solder resist is formed on the outer peripheral portion (at least a part of the base layer 11, particularly an extension region of the connection terminal 15 formation region) of the base material layer 11 constituting the wiring substrate 3. By forming the layer 14 in contact with the sealing resin 5, the adhesion between the base material layer 11 of the wiring substrate 31 and the sealing resin 5 can be further improved on the side surface of the semiconductor device 1. it can. Thereby, when the thermal cycle test is performed in step S24, the stress generated in the wiring board 3 due to expansion and contraction can be reduced. Therefore, even if a thermal cycle is applied, the occurrence of cracks 63 in the wiring substrate 3 of the semiconductor device 1 can be more accurately suppressed or prevented, the resistance to the thermal cycle is further improved, and the reliability of the semiconductor device 1 is improved. Further improvement can be achieved.

  26 and 27 are bottom views of the semiconductor device 1, and both correspond to FIG. In FIG. 26, the planar position of the semiconductor chip 2 seen through from the lower surface 3b side of the wiring board 3 is indicated by a dotted line.

  In FIG. 26, external connection terminals (here, solder balls 6) are formed not only in a region below the semiconductor chip 2 but also in a region other than the region below the semiconductor chip 2 on the lower surface 3 b of the wiring substrate 3. This corresponds to the semiconductor device 1 (so-called fan-in / out package). In FIG. 27, all external connection terminals (here, solder balls 6) are formed in the lower region of the semiconductor chip 2 on the lower surface 3 b of the wiring substrate 3, and external connection is performed in the region other than the lower portion of the semiconductor chip 2. This corresponds to the semiconductor device 1 (so-called fan-in package) in which terminals (here, solder balls 6) are not formed.

When comparing the semiconductor device 1 of FIG. 26 with the semiconductor device 1 of FIG. 27, the semiconductor device 1 of FIG. 27 is different from the end (side surface) of the semiconductor chip 2 to the end of the wiring substrate 3 (semiconductor device 1). distance _{D 1} of the up side) becomes shorter. Therefore, in the semiconductor device 1 in FIG. 27, the portion that expands and contracts in the thermal cycle as in step S24 is shorter than in the semiconductor device 1 in FIG. 26, and the stress applied to the wiring board 3 by the thermal cycle increases. . Therefore, the crack 63 as described above is more likely to occur in the semiconductor device 1 of FIG. 27 than in the semiconductor device 1 of FIG. Therefore, the present embodiment is effective for both the semiconductor device 1 shown in FIG. 26 and the semiconductor device 1 shown in FIG. 27. However, the semiconductor device 1 shown in FIG. If applied, it is more effective.

Further, as the end portions of the semiconductor chip 2 wires from (side) substrate 3 (semiconductor device 1) is a distance D ₁ of the up (side) short portion is shortened to stretch in thermal cycles such as in step S24, The stress applied to the wiring board 3 is increased by the thermal cycle. Therefore, a crack 63 as described above, the distance D ₁ is short semiconductor device, i.e. easy to occur in the semiconductor device of the CSP (Chip Size Package) form. For this reason, in this embodiment, a distance D ₁ from the end (side surface) of the CSP-type semiconductor device, for example, the semiconductor chip 2 to the end portion (side surface) of the wiring substrate 3 (semiconductor device 1) is 0.65 mm or less. If applied to this semiconductor device (CSP type semiconductor device), the effect is greater.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a semiconductor device in the form of a semiconductor package in which a semiconductor chip is mounted on a wiring board and a manufacturing method thereof.

It is a top view of the semiconductor device which is one embodiment of the present invention. It is a bottom view of the semiconductor device which is one embodiment of the present invention. It is sectional drawing of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. It is a side view of the semiconductor device which is one embodiment of the present invention. It is a plane perspective view of the semiconductor device which is one embodiment of the present invention. It is a manufacturing process flowchart which shows the manufacturing process of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of one embodiment of this invention. FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; It is a process flowchart which shows the mounting process of the semiconductor device of one embodiment of this invention. It is a side view which shows the state which solder-mounted the semiconductor device of one embodiment of this invention to the mounting board | substrate. It is explanatory drawing of a reliability test. FIG. 18 is a bottom view of the semiconductor device after the reliability test of FIG. 17 is performed. FIG. 18 is a side view of a main part of the semiconductor device after the reliability test of FIG. 17 is performed. It is principal part sectional drawing of the semiconductor device after performing the reliability test of FIG. It is a graph which shows each process temperature of the manufacturing process and mounting process of a semiconductor device, and the softening temperature of the resin material of the base material layer of a wiring board. It is a graph which shows an example of the temperature curve of a solder reflow process. It is a table | surface which shows the result of the reliability test like FIG. It is principal part sectional drawing of the semiconductor device which is other embodiment of this invention. It is a plane perspective view of the semiconductor device which is other embodiments of the present invention. It is a bottom view of the semiconductor device which is other embodiments of the present invention. It is a bottom view of the semiconductor device which is other embodiments of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor chip 2a Electrode 2b Front surface 2c Back surface 3 Wiring board 3a Upper surface 3b Lower surface 4 Bonding wire 5, 5a Sealing resin 5b Upper surface 6 Solder ball 8 Adhesive 11 Base material layer 11a Upper surface 11b Lower surface 12, 12a, 12b, 12c Conductor layer 14 Solder resist layer 15 Connection terminal 16 Land 19a, 19b Opening 31 Wiring substrate 31a Upper surface 31b Lower surface 32a Semiconductor device region 32b Cutting region 41 Sealing body 42 Package fixing tape 43 Dicing blade 51 Mounting substrate 51a Upper surface 52 Terminal 61 Glass woven fabric 61a Glass fiber 62 Resin material 63 Crack

Claims (20)

A first main surface; a second main surface opposite to the first main surface; a plurality of first electrodes formed on the first main surface; and a plurality of land portions formed on the second main surface. A wiring board having
A semiconductor chip mounted on the first main surface of the wiring board, having a plurality of second electrodes, wherein the plurality of second electrodes are electrically connected to the plurality of first electrodes of the wiring board. Said semiconductor chip,
A sealing resin formed on the first main surface of the wiring board so as to cover the semiconductor chip;
A plurality of external connection terminals made of solder, each formed on the plurality of land portions of the second main surface of the wiring board;
A semiconductor device comprising:
A semiconductor device, wherein a softening temperature of a resin material constituting the wiring board is higher than a melting point of solder constituting the plurality of external connection terminals. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the wiring substrate is a resin substrate containing a glass woven fabric. The semiconductor device according to claim 1,
The wiring board is
A base material layer containing a resin material;
The plurality of first electrodes formed on the third main surface of the base material layer corresponding to the first main surface;
A plurality of land portions corresponding to the second main surface and formed on a fourth main surface on the opposite side of the third main surface of the base material layer;
Insulating films formed on the third and fourth main surfaces of the base material layer;
Have
The semiconductor device, wherein the softening temperature is a softening temperature of a resin material constituting the base material layer. The semiconductor device according to claim 3.
The said base material layer consists of a resin layer containing a glass woven fabric, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 3.
The insulating film is not formed on the outer peripheral portion of the third main surface of the base material layer,
An outer peripheral portion of the third main surface of the base material layer is in contact with the sealing resin. The semiconductor device according to claim 1,
The plurality of external connection terminals are formed of solder containing no lead. The semiconductor device according to claim 1,
The plurality of external connection terminals are each composed of a solder ball. The semiconductor device according to claim 1,
The semiconductor device, wherein the softening temperature is higher than a solder reflow temperature when the plurality of external connection terminals are formed on the wiring board. The semiconductor device according to claim 1,
The semiconductor device, wherein the softening temperature is higher than a maximum temperature during the manufacturing process of the semiconductor device. The semiconductor device according to claim 1,
The semiconductor device, wherein the softening temperature is higher than a solder reflow temperature when the semiconductor device is mounted. The semiconductor device according to claim 1,
The semiconductor device, wherein the softening temperature is higher than 260 ° C. The semiconductor device according to claim 1,
The difference between the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the resin material constituting the wiring board is 20% or less with respect to the thermal expansion coefficient of the sealing resin. The semiconductor device according to claim 1,
The semiconductor device is a CSP type semiconductor device. The semiconductor device according to claim 13.
The distance from the edge part of the said wiring board to the edge part of the said semiconductor chip is 0.65 mm or less, The semiconductor device characterized by the above-mentioned. (A) a first main surface and a second main surface opposite to the first main surface, the plurality of first electrodes on the first main surface, and the plurality of land portions on the second main surface; Preparing the wiring board having:
(B) mounting a semiconductor chip on the first main surface of the wiring board and electrically connecting the plurality of second electrodes of the semiconductor chip to the plurality of first electrodes of the wiring board;
(C) forming a sealing resin on the first main surface of the wiring board so as to cover the semiconductor chip;
(D) forming an external connection terminal made of solder on each of the plurality of land portions of the second main surface of the wiring board;
Have
A method of manufacturing a semiconductor device, characterized in that a softening temperature of a resin material constituting the wiring board is higher than a solder reflow temperature in the step (d). In the manufacturing method of the semiconductor device according to claim 15,
The step (d)
(D1) a step of mounting solder balls on the plurality of land portions of the second main surface of the wiring board,
(D2) After the step (d1), performing a solder reflow process, joining the solder balls on the plurality of land portions, and forming the external connection terminals made of the solder balls;
Have
The method for manufacturing a semiconductor device, wherein the softening temperature is higher than a solder reflow temperature in the step (d2). In the manufacturing method of the semiconductor device according to claim 15,
In the step (d), the plurality of external connection terminals are formed of solder not containing lead. In the manufacturing method of the semiconductor device according to claim 15,
The method of manufacturing a semiconductor device, wherein the wiring substrate prepared in the step (a) is a resin substrate containing a glass woven fabric. In the manufacturing method of the semiconductor device according to claim 15,
The method for manufacturing a semiconductor device, wherein the softening temperature is higher than 260 ° C. In the manufacturing method of the semiconductor device according to claim 1,
The difference between the thermal expansion coefficient of the sealing resin formed in the step (c) and the thermal expansion coefficient of the resin material constituting the wiring board is 20% or less with respect to the thermal expansion coefficient of the sealing resin. A method for manufacturing a semiconductor device, comprising:

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