KR20210034682A - Disruption management based on entry times - Google Patents

Abstract

The exemplary method includes determining a time between in-place writes to a particular memory cell, and calculating a disturbance count corresponding to a neighboring memory cell by a specific count increment based on the time between in-place writes to the particular memory cell. Incrementing, and determining whether to check the write disturbance state of the neighboring memory cell based on the incremented disturbance count.

Description

Disruption management based on entry times

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to disturb management based on write times.

The memory sub-system may be a storage system such as a solid-state drive (SSD), and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and/or volatile memory components. In general, the host system can use the memory sub-system to store data in and retrieve data from the memory components.

1 illustrates a block diagram of an apparatus in the form of a computing system configured to perform disturbance management in accordance with multiple embodiments of the present disclosure.
2 illustrates an example of components associated with managing neighbor disturbance in accordance with multiple embodiments of the present disclosure.
3 illustrates an example of an entry of a memory management unit address data structure configured for disturbance management according to multiple embodiments of the present disclosure.
4 illustrates an example of an entry of a drift entry data structure configured for disturbance management according to multiple embodiments of the present disclosure.
5 is an example of a curve illustrating the relationship between write interruption and time from last write to a specific location according to multiple embodiments of the present disclosure.
6 is a flowchart of an example of a method for interference management according to a number of embodiments of the present disclosure.
7 is a flowchart of an example of a method that may include write disturbance management and drift management in accordance with multiple embodiments of the present disclosure.
8 is a block diagram of an exemplary apparatus in the form of a computer system in which implementations of the present disclosure may operate in accordance with multiple embodiments of the present disclosure.

Aspects of the present disclosure relate to management of write disturbances in memory sub-systems. One example of a memory sub-system is a storage system such as a solid-state drive (SSD). In some embodiments, the memory sub-system is a hybrid memory/storage sub-system. In general, a host system may use a memory sub-system that includes one or more memory components. The host system may provide data to be stored in the memory sub-system and may request data to be retrieved from the memory sub-system.

Various embodiments provide technical improvements, such as improved handling of neighbor disturbances over the conventional approach. For example, various embodiments, by determining based on the time between writes (e.g., frequency) to the attacker (eg, the frequency), resistance variable resistance, which is neighbors (e.g., attackers) to the variable memory cells. Provides a more accurate determination of thermal write disturbance for memory cells (eg, victims). This enables a more accurate decision when refreshing victims to correct for thermal disturbances compared to conventional approaches.

For example, a write disturb count corresponding to the victim may be incremented by a count increment based on the time between write in places for the attacker. The refresh operation may be performed on the victim in response to the disturbance count reaching a threshold count.

The individual states (eg, stored data values) of the resistance variable memory cells may depend on the respective programmed resistances of the memory cells corresponding to the respective threshold voltages Vts of the cells. Resistive variable memory cells may, in some examples, be rewritten by overwriting without first erasing them. This can be referred to as in-place. The state of the resistively variable memory cell may be determined (eg, read), for example, by sensing the current through the cells in response to an applied sensing (eg, read) voltage.

As the attacker resistance variable cells are written in place, the temperature of the attacker cells may increase, and in particular, the temperature of the attacker cells increases when the attacker cells are repeatedly written within a short period of time, such as within about 10 to 20 milliseconds. can do. As the temperatures of the attacker cells increase, more heat is transferred to the victim cells, causing the temperatures of the victim cells to increase. The amount by which the temperature of the victim cells increases may depend on the time between writes to the attacker cells. For example, the shorter the time between writes to the attacker cells, the greater the temperature increase of the victim cells.

Increased temperatures can cause the programmed resistances of the victim cells to change, which makes it difficult to read the victim cells with a predetermined read voltage. This may be referred to as thermal write disturbance. For example, the amount of thermal write disturbance to victim cells may depend on the time between writes to attacker cells. Victim cells can be refreshed by rewriting the victim cells back to their correct programmed resistive states.

The disturbance counter can be used to keep track of the disturbance to the victim cells. If the disturbance count is greater than the threshold value, the victim cells may be refreshed. In conventional approaches, the counter may not depend on the time between writes to the attacker cells (e.g., consecutive writes) and is therefore incremented by increments that may not accurately account for thermal disturbance. Can be. For example, in conventional approaches, the counter can be incremented at the same rate for all victim cells. However, this may cause victim cells to be refreshed too rarely in situations in which attackers are written relatively frequently within a relatively short time interval. For example, frequent entries to attackers within a short time interval result in greater disturbance to victims than disturbance to victims caused by the same amount of entries against attackers over a longer period of time. can do. In these cases, victims who experience greater disruption are more prone to experience reading errors despite experiencing the same amount of disruption events due to writes to the attackers.

Increasing the disturbance count by a disturbance count increment based on the time between writings can be used to account for the amount of thermal disturbance to the victims. For example, the disturbance count is compared to the disturbance counts for longer times between entries (e.g., less thermal disturbances), compared to the shorter times between entries (e.g., greater thermal disturbances). ) Can be accelerated. This may provide the ability to refresh victims at more appropriate times (eg, before the victims are disturbed by a point where they store erroneous data values).

1 illustrates a block diagram of an apparatus in the form of a computing system 100 configured to perform disturbance management in accordance with multiple embodiments of the present disclosure. As used herein, “apparatus” may refer to various structures or combinations of structures, without limitation. For example, the memory system 104, the controller 108, and the memory components 110-1 through 110-N may individually be considered a “device”.

The memory system 104 includes, for example, a solid-state relative drive (SSD), an embedded Multi-Media Controller (eMMC) device, a Universal Flash Storage (UFS) device, and the like. It may be a storage system, and may include an interface 106, a controller 108, and a number of memory components 110-1 through 110-N, which may be collectively referred to as a memory 110. Memory components 110 may provide a storage volume for memory system 104; However, one or more of the memory components 110 may function as main memory for the system 100. In many embodiments, the memory system 104 is a memory sub-system, a hybrid memory/storage system, or the like.

As illustrated in FIG. 1, memory system 104 may be coupled to host 102 via interface 106. The host 102 is a personal laptop computer, a desktop computer, a digital camera, a mobile device (eg, a mobile phone), a network server, an Internet of Things (IoT) capable device, among various other types of hosts. , Or a host system such as a memory card reader. Host 102 may include multiple memory access devices (eg, multiple processors) capable of accessing memory components 110 (eg, via controller 108).

In the example illustrated in FIG. 1, the controller 108 is coupled to the memory components 110 via a number of channels, and the memory system 104 and host 102 (e.g., via interface 106). ) Can be used to transfer data between. The interface 106 may be in the form of a standardized interface. For example, when the memory system 104 is used for data storage in the computing system 100, the interface 106 may be a serial advanced technology attachment (SATA), among other connectors and interfaces. It may be a peripheral component interconnect express (PCIe), or a universal serial bus (USB). However, in general, the interface 106 is an interface for transferring control, address, data, and other signals between the memory system 104 and the host 102 having compatible receptors for the interface 106. Can provide.

The controller 108 may communicate with the memory components 110 to control data read, write, and erase operations, among other operations. Although not specifically illustrated, in some embodiments, controller 108 may include a separate memory channel controller for each channel coupling controller 108 to memory components 110. The controller 108 may be configured with hardware (e.g., for facilitating data transfer between the host 102 and the memory components 110 and/or for controlling access to multiple memory components 110). For example, it may include multiple components in the form of one or more integrated circuits) and/or software (eg, instructions that may be in the form of firmware). In general, the controller 108 may receive commands (e.g., operations) from the host system 102 and issue commands to achieve the desired access to the memory components 110. Can be converted to instructions or appropriate instructions.

As further described herein, the controller 108 provides, among other operations, memory management operations, such as disturbance management (eg, mitigation), among various other operations associated with the memory components 110. Operations, drift management operations, error detection and/or correction operations, and address translation operations. The controller may perform memory management in association with performing background operations and/or foreground operations. Foreground operations may include operations initiated by the host (eg, host 102), such as read and/or write access commands. Background operations, such as neighbor disturbance mitigation operations performed in accordance with embodiments of the present disclosure, its execution may be transparent to a host (e.g., host 102) and/or a controller (e.g. For example, it may include operations initiated by 108).

Memory components 110 may include arrays of multiple memory cells. The memory components 110 may include two-dimensional (2D) and/or three-dimensional (3D) array structures, such as cross-point array structures. The memory cells may be resistance variable memory cells. Memory cells may include, for example, various types of resistance variable storage elements and/or switch elements. For example, the cells may be phase change random access memory (PCRAM) cells or resistive random access memory (RRAM) cells.

As used herein, a storage element may refer to a programmable portion of a memory cell. For example, the memory components 110 may be 3D cross-point devices, the cells of which are switches whose storage element may be referred to herein as a 3D phase change material and switch (PCMS) device. It may include a "stack" structure coupled in series with the element. 3D PCMS cells are a two-terminal chalcogenide-based storage element coupled in series with a two-terminal chalcogenide-based switch element, e.g., an ovonic threshold switch (OTS). It may include. In many embodiments, the memory cells may be self-selecting memory (SSM) in which a single material may serve as both a storage element and a memory element. The SSM cell may contain a chalcogenide alloy; However, embodiments are not limited thereto.

As a non-limiting example, the memory cells of the memory components 110 may include a phase change material (e.g., a phase change chalcogenide alloy) such as indium (In)-antimony (Sb)-tellurium (Te) ( IST) material (e.g., In ₂ Sb ₂ Te ₅ , In ₁ Sb ₂ Te ₄ , In ₁ Sb ₄ Te ₇ , etc.) or gallium (Ge)-antimony (Sb)-tellurium (Te) (GST) Materials (eg, Ge ₂ Sb ₂ Te ₅ , Ge ₁ Sb ₂ Te ₄ , Ge ₁ Sb ₄ Te ₇ , etc.) may be included. As used herein, the hyphenated chemical composition designation refers to the elements contained within a particular mixture or compound, and is intended to indicate all stoichiometry including the indicated elements. Other memory cell materials include GeTe, In-Se, Sb ₂ Te ₃ , GaSb, InSb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb, among various other materials. -Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge -Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi -Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn- It may contain Pt.

As shown in FIG. 1, controller 108 includes a processing device 109 and a memory management component 111 configured to perform various memory management operations in accordance with embodiments described herein. In this example, the memory management component 111 is a neighbor disturbance management component 113, a drift management component 117, and an error detection/correction component 115 (e.g., an error correction code (ECC)). ) Engine). The memory management component 111 also includes a number of data structures 114. As used herein, “data structure” refers to a format for organizing and/or storing data, examples of which include tables, arrays, files, list records, views (ques), trees. , Etc. As will be described further below, the data structures 114 may include a physical managed unit that stores logical managed unit addresses (MUA) addresses in the memory 110; It may include a logical to physical (L2P) address mapping data structure (eg, a table) and a drift table for mapping to PMUs. In some examples, the data structures 114 are a disturbance increment to increment the disturbance counts corresponding to memory cells neighboring the memory cell being written in place as a function of times between writes to the location to the memory cell. May include look-up tables to determine the values. It should be noted that the terms “table” and “list” used to describe particular data structures 114 are intended only as non-limiting examples.

The various components 113, 114, 115, and 117 of the memory management component 111 may be separate components, such as application specific integrated circuits (ASICs), or the components must be a controller ( It may reflect the functionality provided by the circuitry within the controller 108 that does not need to have a separate physical form separate from the other parts of the 108). Although illustrated as components within the memory management component 111 in FIG. 1, each or portions thereof of the components 113, 114, 115, and 117 are external to the memory management component 111 and/or external to the controller 108. Can exist in For example, the error detection/correction component 115 may include a number of error correction coding circuits located on the controller 108 and a number of error correction coding circuits located outside the controller 108.

2 illustrates an example of components associated with managing neighbor disturbance, such as thermal write disturbance, in accordance with multiple embodiments of the present disclosure. In FIG. 2, a management unit address (MUA) table 220 represents a logical address to physical address (L2P) data structure associated with mapping physical memory 210. Table 220 may be one of data structures 114 maintained by a controller such as controller 108, and memory 210 may represent a memory such as memory 110 shown in FIG. 1.

In operation, the host (eg, host 102) may use logical addressing (eg, logical block addressing) to identify logical regions (eg, sectors) of data. As an example, the logical address may correspond to 256 bytes, 512 bytes, 1,024 bytes, or the like. Logical addresses (e.g., logical block addresses (LBAs)) can be organized into managed units (MUs) managed by a controller (e.g., controller 108), This may refer to a unit (eg, size) of memory that is managed by the controller (eg, through an L2P table). As an example, a logical MUA (LMUA) may correspond to a plurality of host LBAs so that the MU may correspond to 2 KB, 4 KB, 8 KB, and the like. The size of the MU may also be correlated with the write and/or read size associated with the memory being mapped (eg, memory 210). The MU may correspond to a number of memory cells, such as, for example, a group of resistance variable memory cells (eg, a physical MU (PMU)). For example, the MU size may be a multiple of the physical page size of the memory, a multiple of the codeword size associated with the memory, and the like.

2, MUA entries 221-1 to 221-M of table 220 may be indexed by LMUAs, where each entry is the corresponding PMU in memory 210. It contains a physical managed unit address (PMUA) indicating a location (eg, pointing to it). For example, as shown in FIG. 2, PMUA-1 in the MUA entry 221-1 points to the PMU 217-1, and PMUA-2 in the MUA entry 221-2 is the PMU 217-2. ). In many embodiments, the data stored in the group of cells corresponding to the PMU 217 is user data and/or user data as well as various metadata that may include the LMUA current mapping for the PMUA corresponding to the PMU 217. Alternatively, it may include parity data.

FIG. 2 also illustrates an example of a drift entry table (DET) 225, which may be a data structure 114. DET 225 may include a drift entry 226 that may be referenced (e.g., may be pointed to) by a drift entry index within a MUA entry, such as MUA entry 221-1, while A number of memory cells in the PMU (eg, PMU 217-1) corresponding to the MUA entry 221-1 are drifting. In some examples, the drift tail is the next drift entry in DET 225 to be retired from the drift, and the drift head may be the next drift entry in DET 225 to be written.

When resistance variable cells are written (e.g., programmed), for example, their resistive state changes (e.g., during a certain period of time (e.g., a drift time period) until a stable resistive state is reached). For example, you can drift). For example, reading data during a drift time period may be unreliable.

2 further illustrates an example of a drift data buffer (DDB) 230 such as a DRAM buffer. The location 232 in the DDB 230 with the address specified in the drift entry 226 temporarily loses data during the drift time period while multiple cells in the PMU 217-1 storing the same data are simultaneously drifting. Can be saved. For example, in response to a read command specifying an LMUA corresponding to (e.g., indexing) MUA entry 221-1, memory management component 108 detects a drift indicator in MUA entry 221-1. From reading it can be determined whether the PMU 217-1 is drifting.

In response to determining that the PMU 217-1 is drifting, the memory management component 111 can activate the drift management component 117 to perform a drift management operation. For example, the drift management component 117 can read the drift entry 226 in response to reading the drift entry in the MUA entry 221-1 that refers to the drift entry 226. The drift management component 117 can then read data from the location 232 in response to reading the address of the location 232 from the drift entry 226.

As long as it is determined that the PMU 217-1 is drifting, data can be read from the DDB 230 instead of the PMU 217-1. After a specific time period corresponding to the drift period, the memory management component 111 may set the drift indicator to indicate that the PMU 217-1 is not drifting. The memory management component 111 can then read data from the PMU 217-1 in response to determining that the PMU 217-1 is not drifting from reading the drift indicator.

3 illustrates an example of a MUA entry 321 that may be a MUA entry 221 and may be configured for disturbance management according to multiple embodiments of the present disclosure. The MUA entry 321 includes a field 340 that may store a PMUA capable of addressing the PMU 217, for example. The MUA entry 321 may refer to a disturbance counter field 342, a drift indicator field 344 that may store a drift indicator such as a flag, and a drift entry in the DET 225 such as a drift entry 226. Includes a drift entry index field 346 that can store a drift entry index (eg, can be pointed to).

4 illustrates an example of a drift entry 426 that may be a drift entry 226 and may be configured for disturbance management according to multiple embodiments of the present disclosure. The drift entry 426 includes an LMUA field 450 that can store an LMUA that can be referenced back to a MUA entry, such as MUA entry 221-1, whose drift entry index refers to drift entry 426. can do. For example, the drift entry index in the field 346 may refer to the drift entry 426, and the LMUA in the field 450 may be the LMUA of the MUA entry 321. The drift entry 426 includes a timestamp field 452 that can store a timestamp that can be a time when a number of memory cells in the PMU 217 corresponding to the LMUA in field 450 were last written. Includes. For example, the LMUA may correspond to the MUA entry 221-1 corresponding to the PMU 217-1, and the timestamp may be the last time memory cells in the PMU 217-1 were written. The drift entry 426 may include a DDB address field 454 that may store the DDB address of a location in the DDB 230.

In the example in which the LMUA in the field 450 corresponds to the MUA entry 221-1, when the timestamp is greater than the threshold drift time, this means that the memory cells in the PMU 217-1 are no longer drifting. And, the drift management component 117 may discard the drift entry, such as the drift entry 426, referenced by the MUA entry 221-1. For example, when the drift indicator in the MUA entry 221-1 indicates a drift tail (e.g., when the drift entry 426 is a drift tail), the drift entry 426 is activated and discarded, and the drift tail It is incremented to the next drift entry, thereby freeing the position and drift entry 426 in DDB 230 with the DDB address in field 454 for further writing. For example, drift management component 117 may set a drift indicator in MUA entry 221-1 to indicate that PMU 217-1 is not drifting in response to discarding drift entry 426. . If the drift indicator in the MUA entry 221-1 does not point to a drift tail (e.g., if the drift entry 426 is not a drift tail), then the drift entry 426 is inactive (e.g., old It is stale, and the drift indicator in the MUA entry 221-1 is left unchanged.

In some examples, multiple memory cells in PMU 217-2 may be neighbors to multiple memory cells in PMU 217-1. For example, memory cells in PMU 217-2 may be write disturbed by in-place writes to memory cells of PMU 217-1. The amount by which memory cells in PMU 217-2 are disturbed may depend on the frequency of writes to memory cells in PMU 217-1. For example, the higher the frequency of writings, the greater the disturbance. For example, the smaller the time interval between writings, the higher the frequency and the greater the disturbance. In some examples, the count increment by which the disturbance count corresponding to the memory cells in the PMU 217-2 can be incremented is the time interval between successive writes to the memory cells in the PMU 217-1 (e.g., , Its frequency). In examples where the MUA 321 is the MUA 221-2, the disturbance count of the disturbance counter in field 342 is based on the time interval between writes to the memory cells of the PMU 217-1, the disturbance. It can be incremented by count increments, such as count increments.

5 is an example of a curve illustrating the relationship between write interruption and time from last write to a specific location according to multiple embodiments of the present disclosure. For example, curve 560 is a quantity for incrementing a disturbance count corresponding to a memory cell, such as a number of memory cells in a PMU (e.g., PMU 221-2) (e.g., incrementing the disturbance count). S) and successive write time intervals, such as the time between in-place successive writes to neighboring memory cells, such as in a neighboring PMU (e.g., PMU 221-1). In some examples, curve 560 may correspond to an exponential decay function. However, the present disclosure is not limited thereto, and the time between the obstruction count increment versus writes may be a linear relationship among other functional relationships. In some examples, the disturbance count increment may be tabulated as a function of successive write time intervals (eg, indexed by) within the look-up table, which may be the data structure 114. As shown in Fig. 5, the disturbance count increment decreases as successive write time intervals increase (eg, as write frequencies decrease). In some examples, the successive write time interval may be a time difference between a time when a memory cell was last written, such as a timestamp in field 452 and a current time at which the memory cells are currently being written.

Successive write time intervals can be divided into ranges of successive write time intervals, which can be referred to as bins. In FIG. 5, for example, ranges of consecutive write time intervals 562-1 to 562-4 may be referred to as bins 1 to 4, respectively. Individual disturbance count increments corresponding to successive write time intervals (eg, lowest consecutive write time intervals) at the beginning of the individual ranges may be individual disturbance count increments for the individual ranges. For example, individual disturbance count increments corresponding to data symbols 564-1 to 564-4, respectively, may be for ranges 562-1 to 562-4, respectively. In some examples, disturbance count increments, such as at the beginning of ranges (e.g., at the lowest consecutive write time intervals of ranges), are a function of ranges in the look-up table, which may be data structure 114. Can be tabulated. In one example, if the determined time between writings lies within a specific range, such as range 562-3, the disturbance count increment is the disturbance count for that range, such as the disturbance count corresponding to data point 564-3. It is a count increment.

A memory array that may be in memory 110 may be a 3D intersection memory array that may include multiple stacks of planes of memory cells, such as the resistance variable cells described above. In each plane, groups of memory cells, which may be referred to as rows of memory cells, may be commonly coupled to access lines, which may be referred to as word lines. Each plane is also referred to as a column of memory cells that can be commonly coupled to access lines, which can be referred to as data lines (e.g., bit lines) that can be coupled to sensing amplifiers. It may contain groups of memory cells that may be. For example, columns can traverse (eg, cross) rows.

In some examples, neighboring cells that are neighbors to the attacker cell may be direct neighbors immediately adjacent to the attacker cell without any intermediate cells. For example, an attacker cell may have direct neighbors with the same plane or different planes.

The amount of interference to neighboring cells can depend on their spatial relationship to the attacker cell. For example, interference to neighboring cells may depend on the direction from the attacker cell. For example, interference to a neighboring cell along a bit line may be greater than an interference to a neighboring cell along a word line. Thus, for the same time between writes, the disturbance count increment may be larger for a neighboring cell along a bit line than for a neighboring cell along a word line. As such, different functional relationships may exist between the time between writes and the obstruction count increment for different spatial relationships. For example, there may be a different look-up table of disturbance count increments versus times between entries for each spatial relationship. The disturbance management component 113 selects a functional relationship (e.g., a look-up table) for a particular spatial relationship and then determines the disturbance count increment from the time between entries by the selected functional relationship. You can determine the count increment.

6 is a flowchart of an example of a method 670 for disturbance management in accordance with multiple embodiments of the present disclosure. For example, method 670 may be performed by disturbance management component 113.

At block 671, the time between writes to the memory cells is determined. For example, the time between writes may be a time difference between a current time at which the memory cell is currently being written and a time at which the memory cell is last written. For example, the time the memory cell was last written may be a timestamp in the drift entry referenced by the MUA entry corresponding to the PMU containing the memory cell. The timestamp can be read to determine when the memory cell was last written. The timestamp can be updated with the current time after it has been read.

In some examples, when a write occurs to a memory cell that is already drifting, the current DET entry in the DET 225 referenced by the MUA entry corresponding to the PMU containing the memory cell indicates the time the memory cell was last written. Can be read to determine. The timestamp may be updated to the current time after it has been read, for example by writing the updated timestamp in a new DET entry in DET 225. Then, the current DET entry is invalidated, and the MUA entry corresponding to the PMU including the memory cell may be updated to refer to the new DET entry.

At block 672, the disturbance count corresponding to the neighboring memory cell may be incremented by a specific amount based on the time between writes. The disturbance count increment can be determined from a relationship between a certain amount and time between writings, for example from the relationship in FIG. 5. For example, a specific amount corresponds to a data point 564-3 that corresponds to a range of consecutive write time intervals, such as range 562-3, which includes a disturbance count increment, e.g., a determined time between writes. May be an increment of the disturbance count. At block 673, a refresh operation is performed on the neighboring cell in response to the disturbance count reaching a threshold count.

7 is a flow chart of an example of a method 775 that may include write disturbance management and drift management in accordance with multiple embodiments of the present disclosure. For example, method 775 may be performed, at least in part, by disturbance management component 113 and drift management component 117.

A MUA entry, such as MUA entry 221-1 in table 220 corresponding to the LMUA in the received write command, is read at block 776. At block 777, it is determined that a number of memory cells in a PMU, such as PMU 217-1, corresponding to a PMUA in a MUA entry, such as PMUA-1, are drifting from a drift indicator in the MUA entry. At block 778, the last time the PMU was written is determined from the timestamp in the drift entry, such as the drift entry 226 in the table 225 referenced by the drift entry index in the MUA entry. For example, the timestamp may be read in response to determining that memory cells in the PMU are drifting.

At block 779, a time difference between the current time associated with the write command and the last time the PMU was written is determined. For example, the time difference may be a continuous write time interval for such as the time between successive writes to multiple cells in the PMU, and may indicate the frequency of writes to the PMU.

At block 780, the disturbance count in the MUA entry in the table 220 corresponding to the PMU, such as the PMU 217-2 containing a number of neighboring memory cells, is determined, e.g., as part of the disturbance management. ), it is incremented by an increment of the disturbance count based on the time difference. For example, neighboring memory cells in PMU 217-2 may be neighbors to memory cells in PMU 217-1. In some examples, after the disturbance count has been incremented, the drift entry index in the MUA entry 221-1 is set to indicate that the drift entry is inactive (e.g., by the drift manager 117). ) Can be. In addition, the drift indicator may be set to indicate that memory cells in the PMU 217-1 are not drifting.

The disturbance count increment can be determined by a functional relationship between the disturbance count increments and successive write time intervals, as discussed above. For example, the disturbance count increment may correspond to a range of consecutive write time intervals including the continuous write time interval. In some examples, the functional relationship may be selected based on a spatial relationship within the PMU 217-1 and between memory cells within the PMU 217-2. At block 781, a refresh operation is performed on the PMU comprising multiple neighboring memory cells in response to the disturbance count reaching a threshold count. In some examples, a disturbance count corresponding to a PMU including multiple neighboring memory cells may be reset in response to performing a refresh operation.

In some examples, data in the write command is written to an entry in DDB 230 and to a PMU corresponding to a PMUA in a MUA entry that simultaneously corresponds to an LMUA. For example, the data is drifted after the drift entry index in the MUA entry 221-1 is set (e.g., cleared) to indicate that the drift entry is inactive and the drift indicator in the MUA entry 221-1 May be written after it is set to indicate that there is no.

The drift indicator in the MUA entry 221-1 may be set to indicate that cells in the PMU 217-1 are drifting, and the drift entry index in the MUA entry 221-1 is (e.g., the drift entry ( 226) after) may be set to refer to the next drift entry. The timestamp field in the drift entry may be set to the current time. Then, the DDB address in the drift entry can be set to a location in the DDB 230, and data in the write command can be simultaneously written to a location in the DDB 230 having the DDB address and to the PMU 217-1. have.

8 is a block diagram of an exemplary apparatus in the form of a computer system 883 in which implementations of the present disclosure may operate. For example, computer system 883 may include or use a memory system such as memory system 104 (eg, SSD, eMMC device, UFS) of FIG. 1. System 883 may also be a system such as computing system 100 shown in FIG. 1. The system 883 includes a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web device, a server, It may be a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or other) specifying actions to be taken by the machine. In addition, although a single machine has been illustrated, the term “machine” also refers to any of the machines that individually or together execute a set of instructions (or multiple sets) for performing any one or more of the methods discussed herein. Should be considered to contain a set of.

The exemplary computer system 883 includes a processing device 809, main memory 884 (e.g., read-only memory (ROM), flash memory, synchronous DRAM (SDRAM)) in communication with each other via a bus 886. Or dynamic random access memory (DRAM) such as Rambus DRAM (RDRAM), etc.), static memory 885 (e.g., flash memory, static random access memory (SRAM), etc.) , And a data storage device 810.

Processing device 809 represents one or more general purpose processing devices such as a microprocessor, a central processing unit, or the like. More specifically, the processing device includes a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW). It may be a microprocessor, or a processor that implements other instruction sets, or processors that implement a combination of instruction sets. The processing device 809 may also include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or similar. May be one or more special-purpose processing devices such as. The processing device 809 is configured to execute instructions 887 to perform the operations and steps discussed herein. Computer system 883 may further include a network interface device 888 for communicating over a network 889.

The data storage device 810 may include a disturbance management component 813, which may be similar to (eg, be the same as) the disturbance management component 113. The data storage system 810 is a machine-readable storage medium 897 on which one or more sets of instructions 887 (e.g., software) embodying one or more of the various methods or functions described herein are stored. ) (Also referred to as a computer-readable storage medium). Instructions 887 may also reside in main memory 884 and/or in processing device 808, completely or at least partially, during its execution by computer system 883, and main memory 884 And processing device 808 also constitutes a machine-readable storage medium. Machine-readable storage medium 897, data storage system 810, and/or main memory 884 may correspond to memory system 104 of FIG. 1.

The present disclosure also relates to an apparatus for performing the operations herein. Such an apparatus may be specially configured for its intended purposes, or it may comprise a general purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. Such computer programs can be any type of computer readable storage medium, including, but not limited to, floppy disks, optical disks, CD-ROMs, and magneto-optical disks, each coupled to a computer system bus. It may be stored on disk, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions.

The algorithms and displays provided herein are essentially not associated with any particular computer or other device. Various general purpose systems may be used with a program according to the techniques herein, or it may prove convenient to construct a more specialized apparatus for performing the method. The structure for these various systems will appear as described in the description below. In addition, specific disclosures are not described with reference to any specific programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

The present disclosure is provided as a computer program product or software that may include a machine-readable medium having stored instructions that may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. I can.

As used herein, “one (a or an)” may refer to one or more of any, and any “a number of” may refer to one or more of these. For example, multiple memory cells may refer to one or more memory cells. Some "plural" means more than one. As used herein, multiple actions performed simultaneously refers to actions that, at least in part, overlap over a specific period of time. As used herein, the term “coupled” is electrically coupled, directly coupled, and/or (e.g., by direct physical contact) directly coupled or having intermediate elements without any intermediate elements. It may include indirectly linked and/or indirectly linked thereto. The term combined may further include two or more elements that operate together or interact with each other (eg, such as a cause and effect relationship).

Various methods of the present disclosure, such as the methods described in FIGS. 6 and 7, include hardware (e.g., processor, control circuitry, dedicated logic, programmable logic, integrated circuit, etc.) and/or software (e.g., Instructions that may include firmware), which may be executed by the processing device, and/or combinations thereof.

While specific embodiments have been illustrated and described herein, those skilled in the art will recognize that an arrangement calculated to achieve the same results may be substituted with the specific embodiments shown. This disclosure is intended to cover adaptations or variations of multiple embodiments of the disclosure. It will be appreciated that the above description has been made in an illustrative and not restrictive manner. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those skilled in the art upon reviewing the above description. The scope of multiple embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the multiple embodiments of the present disclosure should be determined with reference to the appended claims along with the full scope of equivalents to which these claims refer.

In the previous detailed description, several features are grouped together in a single embodiment to simplify the present disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the disclosure should employ more features than are specifically recited in each claim. Rather, in light of the following claims, the subject matter of the invention is less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the detailed description, with each claim relying on itself as a separate embodiment.

Claims (20)

As a way to manage disturbances,
Determining a time between writes in place to the memory cell;
Incrementing a disturbance count corresponding to a neighboring memory cell by a specific amount based on the time between the in-place writes to the memory cell; And
In response to the disturbance count reaching a threshold count, performing a refresh operation on the neighboring cell. The method of claim 1, further comprising incrementing the disturbance count corresponding to the neighboring cell by different specific amounts based on time between writes to the memory cell. The method according to claim 2,
Incrementing the disturbance count corresponding to the memory cell by a first specific amount in response to the time between the in-place writes to the memory cell being a first value; And
Incrementing the disturbance count corresponding to the memory cell by a second specific amount in response to the time between the in-place writes to the memory cell being a second value,
In response to the first value being less than the second value, the first specific amount is greater than the second specific amount, and in response to the first value being greater than the second value, the first specific amount is Method, smaller than the second specific amount. The method of claim 2, wherein performing the refresh operation on the neighboring cell comprises reading a data value from the neighboring cell, and rewriting the data value read from the neighboring cell to a neighboring memory cell. How to. The method of claim 2, further comprising resetting the disturbance count corresponding to the neighboring cell in response to performing the refresh operation. The method of claim 1, further comprising determining the specific amount by accessing a data structure indexed by successive write time intervals, the successive write time intervals corresponding to different individual disturbance count increment amounts. . The method of claim 6, wherein different individual disturbance count increment amounts decrease as the corresponding successive write time intervals increase, and the method comprises: the successive write to which the time between the in-place writes to the memory cell belongs. Selecting the specific disturbance count increment amount based on time intervals. The memory cell according to any one of claims 1 to 7, wherein incrementing the disturbance count corresponding to the neighboring memory cell by the specific amount based on the time between the in-place writes to the memory cell Determining the specific amount based on a spatial relationship between the and the neighboring memory cells. 8. The method of any of claims 1-7, wherein the method comprises determining whether the memory cell is currently drifting. The method of claim 9, further comprising determining whether the memory cell is currently drifting by accessing a data structure including entries corresponding to physical addresses of managed units currently drifting. The method of claim 17, wherein incrementing the disturbance count corresponding to the neighboring memory cell by the specific amount comprises: in an entry of a data structure including a physical address for a physically managed unit corresponding to the neighboring memory cell. And incrementing the disturbance count in the disturbance count field. As a system,
A memory component including a plurality of physically managed units;
A processing device coupled to the memory component, the processing device comprising:
In response to a received write command for a particular physical managed unit, determine an amount of time from when the particular physical managed unit was last written;
Incrementing a disturbance count corresponding to a neighboring physically managed unit by a specific amount based on the determined amount of time; And
In response to the disturbance count reaching a threshold count, configured to perform a refresh operation on the neighboring physical managed unit. The method of claim 12, wherein the processing device,
Determine the amount of time from when the specific physical managed unit was last written based on a difference between a current time and a time when the specific physical managed unit was last written; And
And configured to determine whether the specific physical managed unit is drifting based on the difference between the current time and a time at which the specific physical managed unit was last written. 14. The method of any of claims 12 to 13, wherein the system comprises a memory management component configured to maintain a data structure whose entries correspond to individual physically managed units, each entry comprising:
Physical addresses corresponding to individual physically managed units; And
And a drift indicator corresponding to the individual physically managed unit, and
And the processing device is configured to determine whether the particular physical managed unit is currently drifting based on the drift indicator. 15. The system of claim 14, wherein each entry of the data structure includes a separate disturbance count field, and wherein the processing device is configured to increment the disturbance count corresponding to the neighboring physical managed unit by the specified amount. The method of claim 14,
The data structure is a first data structure;
The memory management component is configured to maintain a second data structure whose entries are referenced by indexes in individual entries within the first data structure;
The processing device may determine the specific physical managed unit from a timestamp in an entry in the second data structure referenced by the index in the individual entry in the first data structure corresponding to the specific physical managed unit. Configured to determine the time last entered; And
The entry in the second data structure is the individual in the first data structure only while the corresponding drift indicator in the individual entry in the first data structure indicates that the particular physical managed unit is drifting. Referenced by the index in the entry. 17. The system of claim 16, wherein the processing device is configured to write data to the specific physical managed unit and to a location in a buffer designated within the entry within the second data structure. As a device,
Memory component;
A controller coupled to the memory component, the controller comprising:
Determine a time between successive in-place writes to a memory cell in the memory component;
Incrementing a disturbance count corresponding to a neighboring memory cell in the memory component by a specific amount based on the time between the successive in-place writes to the memory cell; And
In response to the disturbance count reaching a threshold count, configured to perform a refresh operation on the neighboring cell. The method of claim 18,
Individual ranges of successive write time intervals correspond to individual count increments; And
Wherein the controller is configured to determine the specific amount from the respective count increment corresponding to a range including a continuous write time interval corresponding to the determined time between successive writes. 20. The apparatus of any of claims 18-19, wherein the specific amount is further based on a spatial relationship between the memory cell and the neighboring memory cell.

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