KR20210009211A - Light emitting diode with high process margin - Google Patents

Abstract

According to one embodiment of the present invention, a light emitting diode with a vertical structure capable of decreasing the performance deviation between light emitting diodes comprises: a substrate; a semiconductor laminate disposed on the substrate; a finger structure disposed on the semiconductor laminate and including a plurality of fingers extending from one edge of the substrate to the other edge of the substrate; a current block layer disposed between the semiconductor laminate and the substrate and having a plurality of holes exposing the semiconductor laminate; and a metal layer disposed between the substrate and the current block layer and electrically connected to the semiconductor laminate through holes in the current block layer. The holes of the current block layer are disposed under regions between the fingers not to overlap the fingers. The maximum spacing between the fingers parallel to each other is less than 120 μm, and the minimum spacing is 90 μm or more.

Description

Light emitting diode with large process margin{LIGHT EMITTING DIODE WITH HIGH PROCESS MARGIN}

The present invention relates to a light emitting diode having a large process margin, and in particular, to a light emitting diode capable of reducing a deviation of a forward voltage between light emitting diodes manufactured in the same process on one wafer.

Light-emitting diodes are inorganic semiconductor light-emitting devices that convert electrical energy into light energy. In general, a light emitting diode includes an active layer between an n-type semiconductor layer and a p-type semiconductor layer, and current is injected through electrodes that make ohmic contact with the n-type semiconductor layer and the p-type semiconductor layer, and through recombination of electrons and holes in the active layer. Light is generated.

Since semiconductor layers have a higher specific resistance than metal, it is necessary to disperse current in the horizontal direction of the light emitting diode. Fingers are generally used for current dissipation.

In addition, when the electrodes overlap each other vertically, a current block layer is used to distribute the current in the horizontal direction. The current blocking layer is specifically arranged opposite to the finger so that the current is distributed horizontally from the finger.

Meanwhile, the light emitting diode is formed by depositing semiconductor layers on a wafer, and a plurality of light emitting diodes are formed together on one wafer. Light-emitting diodes fabricated on the same wafer need to have a small performance variation, and thus, a light-emitting diode having a large process margin is required.

The problem to be solved by the present invention is to provide a light emitting diode having a vertical structure capable of reducing a performance deviation between light emitting diodes manufactured by the same process due to a large process margin.

A light emitting diode according to an embodiment of the present invention includes a substrate; A semiconductor laminate disposed on the substrate; A finger structure disposed on the semiconductor laminate and including a plurality of fingers extending from one edge of the substrate to the other edge; A current block layer disposed between the semiconductor laminate and the substrate and having a plurality of holes exposing the semiconductor laminate; And a metal layer disposed between the substrate and the current blocking layer and electrically connected to the semiconductor stack through holes in the current blocking layer, wherein the holes in the current blocking layer do not overlap with the fingers. It is disposed under the regions between them, the maximum distance between the fingers parallel to each other is less than 120um, the minimum distance is more than 90um.

According to embodiments of the present invention, it is possible to provide a light emitting diode having a vertical structure capable of reducing a performance deviation between light emitting diodes and a deviation in forward voltage by increasing a process margin.

1 is a schematic plan view of a vertical light emitting diode according to an embodiment of the present invention.
2A is a schematic cross-sectional view taken along the cut line AA of FIG. 1.
FIG. 2B is a schematic cross-sectional view taken along line BB of FIG. 1.
FIG. 3 is a plan view illustrating samples used to check forward voltage and light output according to the number of fingers and p contact area.
4A is a graph showing forward voltage according to the number of fingers and p contact area.
4B is a graph showing light output according to the number of fingers and p contact area.
5 is a graph for explaining changes in forward voltage and light output according to deformation of a finger structure.
6 is a graph for explaining changes in forward voltage and light output according to a branch structure of a finger.
7 is a graph for explaining changes in forward voltage and light output depending on whether or not an additional pad layer is applied.
8 is a graph for explaining external quantum efficiency according to a finger width.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples in order to sufficiently convey the spirit of the present disclosure to those skilled in the art to which the present disclosure pertains. Accordingly, the present disclosure is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the width, length, and thickness of the component may be exaggerated for convenience. In addition, when one component is described as "above" or "on" another component, not only when each part is "directly above" or "directly" of another component, as well as each component and other components It includes a case where another component is interposed. The same reference numbers throughout the specification denote the same elements.

According to an embodiment of the present disclosure, a substrate; A semiconductor laminate disposed on the substrate; A finger structure disposed on the semiconductor laminate and including a plurality of fingers extending from one edge of the substrate to the other edge; A current block layer disposed between the semiconductor laminate and the substrate and having a plurality of holes exposing the semiconductor laminate; And a metal layer disposed between the substrate and the current blocking layer and electrically connected to the semiconductor stack through holes in the current blocking layer, wherein the holes in the current blocking layer do not overlap with the fingers. A light emitting diode is provided that is disposed below the regions between them and has a maximum distance between fingers parallel to each other of less than 120 μm and a minimum distance of 90 μm or more.

By setting the spacing between the fingers in the above range, even if the spacing between the fingers fluctuates due to fluctuations in the manufacturing process, it is possible to reduce the performance deviation between the light emitting diodes manufactured together.

The total contact area of the metal layer connected to the semiconductor laminate through the holes may be within a range of 1 to 4% of a lower surface area of the semiconductor laminate.

By setting the contact area of the metal layer within this range, it is possible to reduce the performance variation between the light emitting diodes.

Furthermore, the total contact area of the metal layer may be in the range of 1 to 2% of the lower surface area of the semiconductor laminate. By limiting the total contact area of the metal layer within this range, it is possible to suppress a decrease in the light output of the light emitting diode.

In one embodiment, the number of fingers may be 9 or more.

On the other hand, the minimum spacing in the transverse direction between the holes and the fingers may be 20 μm or more.

Furthermore, the spacing between the holes may be larger than the minimum spacing between the holes and the fingers.

The holes may have a width (or diameter) smaller than the maximum gap between the hole and the finger.

The finger structure may include a pad disposed near a center of an edge of one side of the semiconductor laminate; Connection portions extending to both sides of the pad along one edge of the semiconductor laminate; Fingers extending from the connection portion toward the other edge of the semiconductor laminate; And at least one finger extending from the pad toward the other edge of the semiconductor laminate.

Furthermore, the light emitting diode may further include an additional pad layer disposed on the pad.

In one embodiment, the pad may be formed of AuGe or AuGe-Ni, and the additional pad layer may be formed of Au.

On the other hand, the connection portion has a predetermined width and a first connection portion extending from the pad; And a second connection part extending from the pad in contact with the first connection part, and the second connection part is shorter than the first connection part.

In some embodiments, a plurality of fingers may extend from the pad.

In addition, at least one of the fingers extending from the pad may include an extension portion extending toward an edge other than one edge and the other edge of the semiconductor laminate structure.

Meanwhile, the metal layer may include an ohmic layer and a reflective metal layer.

In one embodiment, the line width of each of the fingers may be in the range of 4um to 5um.

In an embodiment, the semiconductor laminate may include at least two active layers.

The light emitting diode semiconductor stack may include an n-type semiconductor layer and a p-type semiconductor layer, the finger structure may contact the n-type semiconductor layer, and the metal layer may contact the p-type semiconductor layer.

In a specific embodiment, the n-type and p-type semiconductor layers may include AlGaAs, and the active layer may include GaAs.

Furthermore, the n-type semiconductor layer may include a roughened surface.

It may further include a protective layer covering the finger structure and the semiconductor laminate.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the drawings.

1 is a schematic plan view of a vertical light emitting diode according to an embodiment of the present invention, FIG. 2A is a schematic cross-sectional view taken along the cut line AA of FIG. 1, and FIG. 2B is a schematic plan view taken along the cut line BB of FIG. It is a cross-sectional view.

1, 2A, and 2B, the light emitting diode includes a substrate 51, a semiconductor stack 30, a current blocking layer 33, a metal layer 35, a bonding layer 53, and a finger structure 55. , A protective layer 57 and an additional pad layer 59 may be included.

The substrate 51 is a support substrate for supporting the semiconductor laminate 30 and is not particularly limited. In one embodiment, the substrate 51 has electrical conductivity, and may be, for example, a silicon substrate or a metal substrate. In another embodiment, the substrate 51 may be an insulating substrate such as a sapphire substrate, a quartz substrate, or a glass substrate.

The substrate 51 is distinguished from a growth substrate used to grow the semiconductor laminate 30, and the semiconductor laminate 30 grown on the growth substrate is moved to the substrate 51. The growth substrate may be separated from the semiconductor laminate 30.

The semiconductor laminate 30 is disposed on one surface of the substrate 51. As shown in FIGS. 2A and 2B, the semiconductor laminate 30 may have a size smaller than the area of the substrate 51, and thus, the substrate 51 may be exposed around the semiconductor laminate 30. .

The semiconductor laminate 30 may have a multi-stack structure having a plurality of active layers 23 and 29. The upper active layer 23 is interposed between the upper first conductivity-type semiconductor layer 21 and the upper second conductivity-type semiconductor layer 25, and the lower active layer 29 includes the lower first conductivity-type semiconductor layer 27 and the lower It may be interposed between the second conductivity-type semiconductor layers 31. Meanwhile, a tunnel layer 26 may be disposed between the upper second conductivity type semiconductor layer 25 and the lower first conductivity type semiconductor layer 27.

The upper first conductivity type semiconductor layer 21 may be formed of a III-V series compound semiconductor, for example, AlGaAs. The lower first conductivity type semiconductor layer 21 may be formed as a single layer, but is not limited thereto and may be formed as multiple layers.

The upper first conductive type semiconductor layer 21 may include an n-type impurity, Si in the range may include the n-type impurity, for example, 5E17 / cm ³ to 5E19 / cm ^3. In this range, the carrier injection efficiency into the upper active layer 23 can be improved, and light absorption by the carrier can be reduced.

The upper first conductivity type semiconductor layer 21 may have irregularities on the upper surface. The irregularities may in particular be formed in the region between the fingers 55d and 55e. The irregularities improve light extraction efficiency.

The upper active layer 23 generates light by recombining electrons and holes. The upper active layer 23 may have a single quantum well structure having a single well layer or a multiple quantum well structure having a barrier layer together with a plurality of well layers. The well layer has a band gap narrower than that of the upper first conductivity type semiconductor layer 21 and the upper second conductivity type semiconductor layer 25. The well layer may be formed of a III-V compound semiconductor represented by AlGaInAsP, and may be formed of, for example, GaAs. The upper active layer 23 may have, for example, a multiple quantum well structure in which GaAs/AlGaAs are repeatedly stacked.

The upper second conductivity type semiconductor layer 25 may be formed of a III-V compound semiconductor, and may have p-type impurities such as C, Mg, or Zn. The upper second conductivity type semiconductor layer 25 has a wider band gap than that of the upper active layer 23. The upper second conductivity-type semiconductor layer 25 may be formed of a compound semiconductor having the same composition as the upper first conductivity-type semiconductor layer 21, such as AlGaAs, but is not limited thereto.

The upper second conductivity type semiconductor layer 25 may be formed as a single layer, but is not limited thereto, and may be formed as multiple layers.

The lower first conductivity type semiconductor layer 27 may be formed of a III-V compound semiconductor, for example, AlGaAs. The lower first conductivity type semiconductor layer 27 may be formed as a single layer, but is not limited thereto and may be formed as multiple layers.

The lower active layer 29 may have a single quantum well structure or a multiple quantum well structure. The well layer of the lower active layer 29 may be formed of a III-V compound semiconductor represented by AlGaInAsP, provided that it is formed of a compound semiconductor having a band gap equal to or smaller than that of the well layer of the upper active layer 23. Like the upper active layer 23, the lower active layer 29 may have a multiple hard well structure in which GaAs/AlGaAs are repeatedly stacked. Light generated by the lower active layer 29 passes through the upper active layer 23 and is emitted to the outside. In order to prevent the light generated in the lower active layer 29 from being absorbed by the upper active layer 23, the band gap of the well layer in the upper active layer 23 is similar to or greater than that of the well layer in the lower active layer 29. It needs to be wide.

The lower second conductivity-type semiconductor layer 31 may be formed of a III-V compound semiconductor, and may have p-type impurities such as C, Mg, or Zn. The lower second conductivity type semiconductor layer 31 may be formed of a III-V series compound semiconductor having the same composition as the lower first conductivity type semiconductor layer 27, for example, AlGaAs, but is not limited thereto.

Meanwhile, the tunnel layer 26 tunnels the lower first conductivity type semiconductor layer 27 and the upper second conductivity type semiconductor layer 25. The tunnel layer 26 is a thin film-grown layer of a III-V series compound semiconductor doped with n/p type impurities at a high concentration, and may be, for example, AlGaAs. The tunnel layer 26 may have, for example, an n/p-type impurity doping concentration in the range of 1E20/cm ³ to 1E21/cm ³ . The forward voltage can be reduced by a doping concentration in this range.

The tunnel layer 26 contains an n/p-type impurity at a high concentration, so that the lower first conductivity type semiconductor layer 27 and the upper second conductivity type semiconductor layer 25 are tunneled together. Accordingly, current may flow from the lower first conductivity type semiconductor layer 25 to the upper second conductivity type semiconductor layer 27.

In this embodiment, the tunnel layer 26 is described as being disposed between the lower first conductivity type semiconductor layer 27 and the upper second conductivity type semiconductor layer 25 for tunnel junction, but the tunnel layer 26 is It may be omitted, and the lower first conductivity type semiconductor layer 27 may contain a high concentration impurity to perform the function of a tunnel layer.

By stacking the upper active layer 23 and the lower active layer 29, it is possible to improve the light output of the light emitting diode through double light emission.

The current blocking layer 33 is disposed between the lower second conductivity type semiconductor layer 31 and the substrate 51. The current blocking layer 33 may be formed of, for example, silicon oxide or silicon nitride. The current block layer 33 may be formed to have a thickness capable of transmitting light in a corresponding wavelength band, and may be formed of, for example, about 1500 Å of silicon oxide. In another embodiment, the current blocking layer 33 may be formed of a distributed Bragg reflector.

The current blocking layer 33 has holes 33a exposing the lower second conductivity type semiconductor layer 31. The holes 33a may be disposed not to vertically overlap the finger structure 55. For example, the holes 33a may have a diameter of about 10 μm and may be separated from the fingers 55d and 55e by 20 μm or more in the transverse direction. Meanwhile, the interval between the holes 33a may be greater than the minimum interval between the hole and the finger, and may be, for example, 50 μm or more.

The contact area between the metal layer 35 and the second conductivity type semiconductor layer 31 is determined by the holes 33a. The contact area determined by the holes 33a may be 1% or more with respect to the lower surface area of the entire semiconductor stack 30. When the ratio of the contact area is greater than or equal to 1% of the lower surface area of the semiconductor laminate 30, it is possible to reduce a performance variation of the light emitting diode due to a variation in the contact area, for example, a variation in forward voltage. On the other hand, as the contact area increases, the performance variation of the light emitting diode can be reduced, but when the contact area is excessively increased, the light output greatly decreases. Accordingly, the contact area may be 4% or less, further, 2% or less of the lower surface area of the semiconductor laminate 30.

The metal layer 35 may be disposed between the current blocking layer 33 and the substrate 51. The metal layer 35 may include an ohmic layer contacting the lower second conductivity type semiconductor layer 31. The ohmic layer may be formed of, for example, TiAu or AuBe. The ohmic layer makes contact with the lower second conductivity type semiconductor layer 31 in the holes 33a. The ohmic layer may be formed to be about 3000 Å, for example.

Meanwhile, the metal layer 35 may include a reflective metal layer covering the ohmic layer. For example, the reflective metal layer may include Au, Cu, Ag, Al, Pd, and may be formed of an alloy such as AgPdCu. The reflective metal layer may be formed to a thickness of, for example, about 0.5 μm.

The bonding layer 53 bonds the semiconductor laminate 30 to the substrate 51. The bonding layer 53 may bond the metal layer 35 and the substrate 51. The material of the bonding layer 53 is not particularly limited, and may be formed of, for example, an eutectic alloy such as Au-In or Au-Sn.

Meanwhile, the finger structure 55 is disposed on the semiconductor stack 30 and may include a pad 55a, a first connection 55b, a second connection 55c, and finger portions 55d and 55e. have. The finger structure 55 may be formed of an AuGe or AuGe-Ni alloy layer, and may make ohmic contact with the upper first conductivity type semiconductor layer 21.

The pad 55a may be disposed near the center of one edge of the semiconductor laminate 30. The pad 55a may have a relatively large area for bonding the wire.

The first connection part 55b may extend from the pad 55a to both sides along the one edge. The first connection part 55b may have a wider width than the fingers 55d and 55e. The first connection part 55b may extend with a width of 30 μm or more, for example.

The second connection portion 55c extends from the pad 55a to both sides. The second connecting portion 55c extends attached to the first connecting portion 55b, and is shorter than the first connecting portion 55b. Accordingly, the first connecting portion 55b and the second connecting portion 55c provide a connecting portion 55bc having a stepped portion formed thereon. That is, a connection portion having a relatively wide width is formed around the pad 55a, and a connection portion having a relatively narrow width is formed outside the pad 55a.

The length of the second connection part 55c is smaller than that of the first connection part 55b, and in particular, may be less than 1/2 of the first connection part 55b. The width of the second connector 55c may be less than or equal to the width of the first connector 55b. The second connection part 55c may have a width of, for example, about 10 μm.

The fingers 55d and 55e extend from the one edge toward the opposite edge at substantially the same distance from each other. The finger portions 55d extend from the pad 55a, and the fingers 55e extend from the connection portion 55bc.

One of the fingers 55d may be disposed in the center of the semiconductor laminate 30. The fingers 55d disposed in the center may be linear. Meanwhile, the fingers 55d other than the fingers 55d disposed in the center are generally straight, but may have a shape that is firstly bent near the pad 55a. In order for the fingers 55d to be spaced apart from each other at the same interval, the fingers 55d extend from the pad 55a in a diagonal direction toward the other edge other than the one edge and the other edge, and then a straight line toward the opposite edge. Can be extended to The extension part extending in the diagonal direction may be a straight line or a curved line.

Meanwhile, the fingers 55e extend toward the edge of the opposite layer from the connection portion 55bc. All of the fingers 55e may be linear.

The widths of the fingers 55d and 55e may be selected according to the current density. In general, when the bottom surface area of the semiconductor stack 30 is about 1 mm×1 mm, the widths of the fingers 55d and 55e may be selected within a range of, for example, 4um to 5um. When a current of 500mA is injected under a high current density, for example, under the area of the semiconductor stack 30, the widths of the fingers 55d and 55e may be closer to about 4um than 5um, thereby increasing the internal quantum efficiency. I can make it. In contrast, when a current of 100 mA is injected under a low current density, for example, under the area of the semiconductor laminate 30, the width may be closer to about 5 μm than 4 μm. When operating under both conditions of high current density and low current density, the width may be close to about 4.5 μm. Both the fingers 55d and the fingers 55e may have the same width, but are not limited thereto.

As shown in FIG. 1, the fingers 55d and 55e are spaced apart from each other at substantially the same interval except for the pad 55a. The spacing between the fingers 55d and 55e affects the forward voltage of the light emitting diode. In particular, the spacing between the fingers 55d and 55e may affect the deviation of the forward voltage between the light emitting diodes according to the change in process conditions. During the light emitting diode manufacturing process, a large number of light emitting diodes are simultaneously manufactured under the same conditions. These light-emitting diodes have a variation in their performance due to a slight difference in process conditions, and it is advantageous that the performance of the LEDs does not vary significantly even with fluctuations in process conditions.

To this end, the performance deviation of the LEDs is different according to the interval between the fingers 55d and 55e, and in particular, the performance deviation of the LEDs can be reduced when the interval between the fingers is less than about 120 μm. Here, the spacing between fingers means the spacing between parallel fingers. By adjusting the number of fingers under the width of the upper fingers 55d and 55e, the spacing between the fingers 55d and 55e can be adjusted. For example, the number of fingers 55d and 55e may be 9 or more under the area of the semiconductor laminate 30 above. The interval between the fingers 55d and 55e may be substantially constant, but is not limited thereto. At this time, the maximum distance between the fingers parallel to each other may be less than about 120um.

On the other hand, as the number of fingers 55d and 55e increases, the forward voltage may be lowered, but the fingers 55d and 55e block light, thereby reducing light output. Accordingly, the interval between the fingers 55d and 55e may be 90 μm or more, and the number of the fingers 55d and 55e may be 11 or less under the area of the semiconductor stack 30 above. The interval between the fingers 55d and 55e may be substantially constant, but is not limited thereto. At this time, the minimum distance between the fingers parallel to each other may be about 90um or more.

The protective layer 57 covers the finger structure 55 and the upper first conductivity type semiconductor layer 21. The protective layer 57 may be formed along the irregularities formed on the surface of the first conductivity type semiconductor layer 21. The protective layer 57 may also cover a side surface of the semiconductor stack 30, and may cover the substrate 51 exposed around the semiconductor stack 30. The protective layer 57 may have an opening exposing the pad 55a.

The protective layer 57 may be formed of silicon oxide or silicon nitride, may be formed to have a thickness capable of transmitting light in a corresponding wavelength band, and may be formed of, for example, silicon oxide having a thickness of about 4500 Å.

The additional pad layer 59 may be formed on the pad 55a. The additional pad layer 59 may be disposed in the opening of the protective layer 57. The additional pad layer 59 may be formed of, for example, an Au layer having a thickness of about 1 μm.

(Experimental Example 1)

3 are plan views for explaining samples used to check forward voltage and light output according to the number of fingers and p contact area.

Light-emitting diodes having 7 to 11 fingers were fabricated on the semiconductor laminate 30 having an area of about 1×1 mm ² . The width of the fingers was the same as about 4.5um, and the connection part 55bc was made a constant width without a stepped part. Structures of light emitting diodes other than the finger structure were all manufactured under the same conditions as previously described with reference to FIGS. 1, 2A, and 2B. Forward voltage and light output of a light emitting diode having 7 fingers and a ratio of p contact area to a semiconductor stack of 0.5% were set to 100%, respectively, and the forward voltage and light output of other light emitting diodes were expressed as percentages.

FIG. 4A is a graph showing forward voltage according to the number of fingers and p contact area, and FIG. 4B is a graph showing light output according to the number of fingers and p contact area.

First, referring to FIG. 4A, as the number of fingers increases, the forward voltage of the light emitting diode decreases. It can be seen that the width of the forward voltage decrease according to the increase in the number of fingers increases as the number of fingers decreases and the p contact area decreases. That is, the decrease in forward voltage is considerably larger when the number of fingers increases from 7 to 8, compared to when the number of fingers increases from 9 to 10, or from 10 to 11. Even when increasing from 8 to 9, it can be seen that the forward voltage decreases considerably. Therefore, 9 or more fingers are appropriate in terms of forward voltage reduction.

Furthermore, as the p contact area increases from 0.5% to 4%, the width of the forward voltage decrease according to the difference in the contact area decreases. That is, when the p-contact area increases from 1% to 1.5% than when the p contact area increases from 0.5% to 1%, the forward voltage change is small. As the number of fingers increases, the forward voltage change according to the p contact area increases becomes smaller. That is, as the number of fingers and the p contact area increase, it is possible to reduce the forward voltage deviation between the LEDs.

Meanwhile, referring to FIG. 4B, the light output decreases as the number of fingers increases and the p contact area increases. As the number of fingers increases, the decrease in light output is generally constant, and therefore, it can be seen that the decrease in light output does not decrease even if the number of fingers increases. On the other hand, as the p contact area increases, the change in light output tends to decrease, but the difference is not large. That is, even as the p contact area increases, the light output decreases to a substantially constant width. Therefore, in order to prevent a decrease in light output, it is necessary to reduce the number of fingers and reduce the p contact area.

In conclusion, to reduce the deviation of the forward voltage, it is recommended that the number of fingers is 9 or more and the p contact area is 1% or more, but to prevent a significant decrease in light output, the number of fingers exceeds 11 or the p contact area is 4 It is not recommended to increase it to more than %. Moreover, under the above conditions, 9 fingers and 1~2% of p contact area are suitable.

5 is a graph for explaining changes in forward voltage and light output according to deformation of a finger structure. A reference sample (comparative example) in which a finger structure was formed using only the first connection part 55b without the second connection part 55c, and a sample of an embodiment in which a stepped connection part 55bc was formed by adding the second connection part 55c (Example) was prepared and the forward voltage and light output were measured.

Referring to FIG. 5, the sample of the example showed a decrease in forward voltage of 0.3% and an increase in light output of 0.6% compared to the comparative example. That is, by adding the second connector 55c, the forward voltage may be reduced and the light output may be increased.

6 is a graph for explaining changes in forward voltage and light output according to a branch structure of a finger. Except for the fingers extending in a straight line directly from the pad 55a, all the remaining fingers were prepared to extend from the connection portion, and as described in FIG. 1, a sample of an embodiment in which a plurality of fingers extend from the pad 55a. It was fabricated to measure the forward voltage and light output.

Referring to FIG. 6, the sample of the example showed a decrease in forward voltage of 5.5% and an increase in light output of 0.5% compared to the comparative example. That is, by increasing the fingers extending from the pad 55a, it is possible to decrease the forward voltage and increase the light output.

7 is a graph for explaining changes in forward voltage and light output depending on whether or not an additional pad layer is applied. A sample of the example in which the additional pad layer 59 of Au was formed on the pad 55a together with the sample of the comparative example in which the wire was directly bonded to the pad 55a was prepared. The additional pad layer 59 was formed of Au to a thickness of about 1 μm.

Referring to FIG. 7, by disposing the additional pad layer 59, a reduction in forward voltage of 4.9% and an increase in light output of 1.4% could be achieved. Moreover, it was possible to increase the wire bonding strength in the wire bonding process of the package.

8 is a graph for explaining external quantum efficiency according to a finger width. The number of fingers was equal to 9, and samples with only the widths of the fingers of 4um, 5um and 6um were produced to derive the external quantum efficiency according to the finger width.

Referring to FIG. 8, under the condition of a low current density of 100 mA, the width has a good value at about 5 μm and a relatively low value at 4 μm. On the other hand, under the condition of a high current density of 500mA, the external quantum efficiency tended to decrease as the width increased.

That is, it shows that the closer the finger width is to 5um under the low current density condition, and the closer the finger width is to 4um under the low current density condition, the higher the external quantum efficiency.

In addition, in determining the finger width, the optimum finger width for the device injection current may be determined through the change in external quantum efficiency at low and high current.

In the above, various embodiments of the present disclosure have been described, but the present disclosure is not limited to these embodiments. In addition, matters or components described for one embodiment may be applied to other embodiments as long as it does not depart from the technical spirit of the present disclosure.

Claims (20)

Board;
A semiconductor laminate disposed on the substrate;
A finger structure disposed on the semiconductor laminate and including a plurality of fingers extending from one edge of the substrate to the other edge;
A current block layer disposed between the semiconductor laminate and the substrate and having a plurality of holes exposing the semiconductor laminate; And
A metal layer disposed between the substrate and the current blocking layer, and electrically connected to the semiconductor laminate through holes in the current blocking layer,
The holes of the current block layer are disposed under regions between the fingers so as not to overlap the fingers,
Light-emitting diodes with a maximum gap of less than 120um and a minimum gap of 90um or more between fingers parallel to each other. The method according to claim 1,
A light emitting diode in which a total contact area of the metal layer connected to the semiconductor laminate through the holes is within a range of 1 to 4% of a lower surface area of the semiconductor laminate. The method according to claim 2,
A light emitting diode having a total contact area of the metal layer within a range of 1 to 2% of a lower surface area of the semiconductor laminate. The method according to claim 1,
A light emitting diode having nine fingers. The method according to claim 1,
A light emitting diode having a minimum spacing between the holes and the fingers in a transverse direction of 20 μm or more. The method of claim 5,
A light emitting diode having a spacing between the holes is greater than a minimum spacing between the holes and the fingers. The method of claim 5,
The holes are light-emitting diodes having a width smaller than the maximum gap between the hole and the finger. The method according to claim 1,
The finger structure
A pad disposed near the center of one edge of the semiconductor laminate;
Connection portions extending to both sides of the pad along one edge of the semiconductor laminate;
Fingers extending from the connection portion toward the other edge of the semiconductor laminate; And
A light emitting diode comprising at least one finger extending from the pad toward the other edge of the semiconductor laminate. The method of claim 8,
A light emitting diode further comprising an additional pad layer disposed on the pad. The method of claim 9,
The pad is formed of AuGe or AuGe-Ni,
The additional pad layer is a light emitting diode formed of Au. The method of claim 8,
The connection portion has a predetermined width and a first connection portion extending from the pad; And
And a second connection part extending from the pad in contact with the first connection part,
The second connection part is a light emitting diode shorter than the first connection part. The method of claim 8,
A light emitting diode having a plurality of fingers extending from the pad. The method of claim 12,
At least one of the fingers extending from the pad includes an extension portion extending toward an edge other than one edge and the other edge of the semiconductor laminate structure. The method according to claim 1,
The metal layer is a light emitting diode comprising an ohmic layer and a reflective metal layer. The method according to claim 1,
A light emitting diode having a line width of each of the fingers in a range of 4um to 5um. The method according to claim 1,
The semiconductor laminate includes at least two active layers. The method of claim 16,
The semiconductor stack includes an n-type semiconductor layer and a p-type semiconductor layer, wherein the finger structure contacts the n-type semiconductor layer, and the metal layer contacts the p-type semiconductor layer. The method of claim 17,
The n-type and p-type semiconductor layers include AlGaAs,
The active layer is a light emitting diode containing GaAs. The method of claim 17,
The n-type semiconductor layer is a light emitting diode comprising a roughened surface. The method according to claim 1,
A light emitting diode further comprising a protective layer covering the finger structure and the semiconductor laminate.

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