KR20200133131A - Time to digital converter and distance measuring device comprising the same - Google Patents

Abstract

The present invention provides a distance measuring device which facilitates the design of an analog front end and has high accuracy. According to an embodiment of the present invention, the distance measuring device comprises: a transmission unit providing a pulse laser signal and a start signal at the same time; a reception unit detecting a reflection signal of the pulse laser and outputting a corresponding electric signal; an amplifier unit amplifying the electric signal and outputting a stop signal amplified to have a predetermined amplitude; and a time-digital converter which receives the start signal and the stop signal, detects a time difference between the start signal and the stop signal by performing coarse detection and fine detection, and outputs the corresponding digital code.

Description

Time to digital converter and distance measuring device including the same

The present technology relates to a time digital converter and a distance measuring device including the same.

A time-to-digital converter (TDC) is a device that converts a measured time into a corresponding digital code. For example, the time digital converter measures a time from a first point in time to a second point in time, converts it into a digital code, and outputs it.

As a field using a time digital converter, there may be a field of distance measurement. A signal is provided to a target, and the distance to the target, direction, and speed of the target are sensed by measuring the time and intensity until the signal reflected from the target is received. In general, time-to-digital converters are used to measure the time from when a signal is transmitted to when a signal is received.

In conventional distance measurement, a signal reflected from a target is received and converted into a corresponding electric signal. The amplitude of the electrical signal depends on the distance between the transmission point and the target. Accordingly, the electric signal was amplified by an amplifier having a linear gain to obtain distance information from the amplitude, and the distance information was obtained by comparing the amplitude of the electric signal with a plurality of threshold values.

According to the existing technology, an amplifier having a linear gain over a wide input dynamic range must be placed at the analog front-end to obtain error-free distance information, but an amplifier having a linear gain over a wide input range. It was difficult to design. One of the problems to be solved by the present embodiment is to provide a distance measuring device having high accuracy while facilitating the design of the analogue first end by overcoming the difficulties of the prior art described above.

In addition, in the conventional time-to-digital converter, a comparison error occurs due to a magnitude relationship of amplitude and interference of disturbances in a process of comparing an input signal and an output signal. One of the problems to be solved by this embodiment is to overcome the difficulties of the prior art described above to provide a time digital converter that is robust to differences in signal amplitudes and disturbances.

The time digital converter according to the present embodiment is an edge detector that outputs an enable signal having an active period corresponding to between a first edge of a start signal and a first edge of a stop signal. detector), a sync controller that outputs a synchronized activation signal by synchronizing the edge of the activation signal with the edge of the clock signal, and clock signals that are activated by the synchronized activation signal and are delayed by a controllable phase by receiving a clock signal. A delay locked loop (DLL) that outputs a thermometer code during an active period and an encoder that converts the thermometer code into a corresponding binary code and outputs the binary code. It corresponds to the time difference of the first edge of the stop signal.

The time digital converter according to the present embodiment delays the start edge signal formed from the start signal with a first delay time, delays the stop edge signal formed from the stop signal with a second delay time shorter than the first delay time, and delays the delayed start edge signal. A coarse detection unit that outputs a code corresponding to the time difference between the start signal and the stop signal at the first delay time and the second delay time when the signal precedes the delayed stop edge signal, and the time difference between the start signal and the stop signal And a precision detection unit that detects a signal having a higher resolution than the second delay time, and a determination unit that compares the output signal of the precision detection unit with an output signal of the detection unit that has passed through to verify validity.

The range finder according to this embodiment provides a pulse laser signal and a transmitter that provides a start signal at the same time, a receiver that detects the reflected signal of the pulsed laser and outputs a corresponding electrical signal, and amplifies the electrical signal, but with a predetermined amplitude. A limiting amplifier that outputs a stop signal amplified to have an amplified stop signal and a start signal and a stop signal are provided, and coarse detection and fine detection are performed to determine the time difference between the start signal and the stop signal. And a time-to-digital converter that detects and outputs a corresponding digital code.

According to the time digital converter according to the present embodiment, since the time is converted into a digital code using the start edge signal and the stop edge signal formed from the edges of the start signal and the stop signal, the advantage of being strong against disturbance is provided.

According to the time digital converter according to the present embodiment, since a signal output from a delay locked loop having a high resolution is used, it is possible to convert time into a digital code with a high resolution.

Further, according to the distance measuring apparatus according to the present embodiment, it is easy to design an analog front end, and it is possible to measure a distance with high precision.

1 is a diagram showing an outline of an embodiment of a time digital converter according to the present embodiment.
2(A) is a schematic circuit diagram of a resettable T latch used as a start latch and a stop latch, and FIG. 2(B) is a timing diagram for explaining the operation of the resettable T latch.
3 is a timing diagram for explaining the operation of the time-to-digital converter of this embodiment.
4 is a diagram showing an outline of an embodiment of a time digital converter according to this embodiment.
5(A) is a schematic circuit diagram of an edge detector, and FIG. 5(B) is a timing diagram for signals related to the edge detector.
FIG. 6(A) is a gate level circuit diagram showing an outline of the sync controller, and FIG. 6(B) is a schematic timing diagram of the sink controller.
7 is a schematic timing diagram of a precision detection unit according to the present embodiment.
8 is a block diagram showing an outline of a distance measuring apparatus according to the present embodiment.
9 is a block diagram showing an outline of a time-to-digital converter according to this embodiment.
10 is a flow chart schematically showing the operation of the determination unit according to the present embodiment.

Hereinafter, the TDC 10 according to the present embodiment will be described with reference to the accompanying drawings. 1 is a diagram showing an outline of an embodiment of a time digital converter 100 according to the present embodiment. 1, the time digital converter 100 is reset by providing a start signal (START), a start latch 112 providing a start edge signal (T_START), and a plurality of first unit delays A start delay unit including a start delay line 114 that delays and outputs the start edge signals T_START by connecting the elements D1 in a cascade, and a stop signal STOP is provided and reset, and a stop edge signal A stop latch 122 that provides (STOP edge signal, T_STOP) and a stop delay line 124 that delays and outputs the stop edge signals T_STOP by cascading a plurality of second unit delay elements D2 ), a comparator unit 130 for comparing the preceding and following of a plurality of delayed start edge signals T_START and a plurality of delayed stop edge signals T_STOP, and a digital corresponding to the comparison result It includes an encoder 140 that provides the codes B0, B1, ..., B3.

2A is a schematic circuit diagram of a resettable T latch used as the start latch 112 and the stop latch 122. 2B is a timing diagram for explaining the operation of the resettable T latch. Referring to FIG. 2(B), the conventional T latch toggles the logic low state output to the logic high state when an input signal is provided, and then maintains the output q in a logic high state regardless of the input signal ( dotted line).

However, the resettable T latch according to the present embodiment toggles the output after a predetermined reset time (τ _RESET ) when an initial input signal is provided to maintain the logic high state. Thereafter, when an input signal is provided, the latch is reset for a reset time (τ _RESET ) to provide an output (Q) in a logic low state, and then invert to provide an output in a logic high state. Hereinafter, it is assumed that the start latch 112 and the stop latch 122 are the same, so that the reset time τ _RESET is the same.

Referring to FIG. 2A, the resettable T latch includes a t latch TL, an inversion delay line DL, and an XOR gate. The t-latch TL holds the output Q as it is when the input maintains the logic low state. However, when the input first transitions from the logic low state to the logic high state, the output Q is toggled to the logic high state. Subsequently, even if a logic low or logic high input is provided, the output Q is held in a high state. That is, the t latch TL maintains the output of the logic high state except when the input is initially switched from the logic low state to the logic high state.

The inversion delay line DL may include a plurality of inverters (inv) for inverting and outputting an input signal, and the number of inverters inv included in the delay line may be an odd number. In addition, the inverter (inv) included in the delay line functions as a unit delay device and performs a function of delaying a signal by a unit delay time, respectively. The reset time τ _RESET may be determined by the number of inverters included in the delay line.

For example, when a logic high input is provided to the inversion delay line DL, a logic high input is provided as one input of the AND gate, but the inverted input is delayed by cascaded inverters as the other input. Therefore, when an input for transitioning from a logic low state to a logic high state is provided, The NAND gate (NAND) outputs a logic low as an input in a logic high state and an output inverted by cascaded inverters are provided to the NAND gate (NAND) input, and is output in a logic high state by INV1.

Accordingly, when the output of the t latch TL input to the XOR gate and the output of the delay inversion circuit are mutually exclusive, the XOR gate outputs a logic high signal.

When a start signal (START) is provided as an input to the resettable T latch, the latch outputs a start edge signal (T_START) with a rising edge, and the logic state of the start edge signal (T_START) is until another start signal is provided. maintain. Similarly, when a stop signal STOP is provided as an input to the resettable T latch, the latch outputs a stop edge signal T_STOP having a rising edge, and maintains a logic state until another start signal is provided.

According to an embodiment not shown, when a start signal START is provided as an input to a resettable T latch, the latch maintains an output in a logic low state until another start signal is provided. Accordingly, the latch outputs a start edge signal T_START having a falling edge until the start signal is input thereafter. Likewise, if a stop signal STOP is provided as an input to the resettable T latch, the latch outputs a signal having only a falling edge until another start signal is provided.

When noise intervenes in the start signal (START) and/or the stop signal (STOP), there is a case that the noise is erroneously recognized as a new start signal (START) and/or the stop signal (STOP) and malfunctions. However, the start edge signal (T_START) and/or the stop edge signal (T_STOP) formed by the resettable T latch are signals that have a single edge and a single level before being reset, so malfunction due to intervening noise is excluded. In addition, when the start edge signal (T_START) and the stop edge signal (T_STOP) intersect, even the comparison ambiguity can be removed.

Referring back to FIG. 1, in the start delay line 114, a plurality of first unit delay elements D1 are connected in a cascade to each other, and each of the first unit delay elements D1 delays a signal provided as an input by a first unit. Output is delayed by time (τ1). In the stop delay line 124, a plurality of second unit delay elements D2 are cascaded to each other, and each of the second unit delay elements D2 delays a signal provided as an input by a second unit delay time (τ2). Print.

The first unit delay time τ1 may be greater than the second unit delay time τ2. Accordingly, the start edge signal T_START propagating through the start delay line 114 propagates faster than the stop edge signal T_STOP propagating through the stop delay line 124. In an embodiment, the first unit delay element D1 and the second unit delay element D2 may be formed as buffers having different sizes, respectively.

The comparator unit 130 includes a plurality of comparators C11, C21, ..., C73. In the embodiment illustrated in FIG. 1, the comparator unit 130 may further include a dummy comparator (D) disposed at a position in the comparator unit 130 where resolution is degraded.

3 is a timing diagram for explaining the operation of the time digital converter 100 of the present embodiment. 1 and 3, as a start signal START is provided to the start latch 112, a start edge signal having a rising edge is formed and input to the start delay line 114, as indicated by a solid line. It is delayed while passing through the unit delay element of and supplied to the comparator. As the stop signal (STOP) is provided to the stop latch 122, a stop edge signal having a rising edge is formed and input to the stop delay line 124, and is delayed while passing through a plurality of unit delay elements as indicated by a dotted line. Provided to the comparator.

Each of the comparators included in the comparator unit 130 includes a signal output from the start delay line 114 through one or more unit delay elements, and a stop edge signal T_STOP, one or more unit delay elements. Compare the relationship between the signals output through For example, in the comparator C11, a start edge signal T_START is output through one first unit delay element D1 and a stop edge signal T_STOP is output through one second unit delay element D2. The signal is compared before and after and the comparison result is output as TC[0]. For example, when the start edge signal (T_START) arrives earlier than the stop edge signal (T_STOP), the comparator C11 outputs a logic high state as the output signal TC[0]. In this case, the start signal (START) and the stop signal ( The time difference (ΔT) of STOP) is smaller than τ1-τ2, which is the difference between the first unit delay time τ1 and the second unit delay time τ2.

As another example, the comparator C53 compares the start edge signal T_START passing through the five first unit delay elements D1 and the stop edge signal T_STOP signal passing through the three second unit delay elements D2. When the start edge signal (T_START) arrives earlier than the stop edge signal (T_STOP), a logic high state is output with the output signal TC[8]. In this case, the time difference between the start signal (START) signal and the stop signal (STOP) (ΔT) is less than 5τ1-3τ2, which is the difference between the first unit delay time 5τ1 of five times and the second unit delay time 3τ2 of three times.

Each of the comparators includes a start edge signal T_START delayed through one or more first unit delay elements D1 indicated by a solid line and a stop edge signal T_STOP delayed through one or more second unit delay elements D2 indicated by a broken line. Is entered. As an example, each comparator provides an output in a logic low state when the input start edge signal T_START is slower than the stop edge signal T_STOP, and the start edge signal T_START is faster than the stop edge signal T_STOP. In this case, it can provide a logic high output. As another example, each comparator provides an output in a logic high state when the input start edge signal T_START is slower than the stop edge signal T_STOP, and the start edge signal T_START is faster than the stop edge signal T_STOP. In this case, it can provide a logic low output.

The start edge signal T_START indicated by a solid line is a start delay line 114 in which a first unit delay element having a delay time greater than the second unit delay time of the second unit delay element through which the stop edge signal T_STOP propagates is cascaded. ), so that C51, C62, and C73 after the comparator C63 all output a logic low signal. Therefore, signals TC[0], TC[1], ..., TC[14] output from the comparator 130 may be thermometer codes. The thermometer code TC output from the comparator 130 is as illustrated in Table 1 below.

The thermometer code illustrated in Table 1 is 15 bits, and TC[0, 1, 2, ..., 14] is from [0, 0, ..., 0] to [1, 0, ..., 0], [ 1, 1, ..., 0], ..., [1, 1, 1, ..., 1] to illustrate the change.

The thermometer code output from the comparator 130 (TC, exemplified in Table 1) is from [0, 0, ..., 0] to [1, 0, ..., 0], ..., [1, 1, 1, ..., 1] may be different from the thermometer code output from the encoder 240 (TF, see Table 2).

The encoder 140 receives the thermometer code TC[0, 1, 2, ..., 14] output from the comparator 130 and converts it to the corresponding binary code BC[0, 1, 2, 3] Print. In one embodiment, the encoder 140 converts the thermometer code TC[0, 1, 2, ..., 14] to the gray code GC[0, 1, 2, 3], and the gray code GC[0, 1 , 2, 3] can be converted to binary code BC[0, 1, 2, 3] and output.

In one embodiment, the encoder 140 is provided with a thermometer code TC[0, 1, 2, ..., 14], and performs an operation corresponding to Equation 3 to obtain a gray code GC[0, 1, 2, ..., 14]. 3] is formed.

The encoder 140 performs an operation corresponding to Equation 2 from the formed Gray code GC[0, 1, 2, 3], and a binary code corresponding to the thermometer code TC[0, 1, 2, ..., 14] BC[0, 1, 2, 3] is formed.

In the timing diagram illustrated in FIG. 3, the start edge signal T_START up to the input provided to the comparator C52 is slower than the stop edge signal T_STOP, and the start edge signal T_START and the stop edge signal T_STOP from the input provided to the comparator C63 ) Has been reversed. Therefore, the time difference (ΔT) between the start signal (START) signal and the stop signal (STOP) is greater than 5τ1-2τ2, which is the difference between 5τ1, which is 5 times the first unit delay time, and the second unit delay time τ2, which is 2 times. It is smaller than the difference between 6τ1, which is 6 times the delay time of 1 unit, and 3τ2, which is the second unit delay time 3 times (refer to Equation 3). If identified as the output signal of the comparator, the output signals TC[0] to TC[10] of the comparator may be signals in the logic high state, and the output signals TC[11] to TC[14] may be signals in the logic low state.

The encoder 140 receives the thermometer code TC[0, 1, 2, ..., 14], which is an output signal of the comparator, and performs the same operation as the above equation, so that the start edge signal (T_START) and the stop edge signal ( The signal difference (ΔT) of T_STOP) is roughly calculated. The encoder 140 forms and outputs the binary code BC[0, 1, 2, 3] corresponding to the calculated result. As an example, the resolution of the binary code output by the encoder 140 may have a resolution of nanoseconds.

4 is a diagram showing an outline of an embodiment of a time digital converter 200 according to another embodiment. The embodiment illustrated in FIG. 4 may have a higher resolution than the temporal digital converter described previously. Referring to FIG. 4, an edge detector outputting an enable signal (en) having an active period corresponding to between a first edge of a start signal and a first edge of a stop signal. , 210), a sync arrange 220 for outputting a synchronized activation signal EN by synchronizing the edge of the activation signal en and the edge of the clock signal CLK, and a synchronized activation signal EN A delay locked loop (DLL) and a thermometer that is activated as a clock signal (CLK) and outputs a thermometer code (TF) consisting of clock signals delayed by a controllable phase during the active period. And an encoder 240 that converts and outputs the code TF into a corresponding binary code BF, wherein the binary code BF corresponds to a time difference between the first edge of the start signal and the first edge of the stop signal. .

5(A) is a schematic circuit diagram of the edge detector 210, and FIG. 5(B) is a timing diagram for signals related to the edge detector 210. As shown in FIG. 5(A) and 5(B), the edge detector 210 includes an XOR gate to which a start signal (START) and a stop signal (STOP) are input, and a first SR in which the output of the XOR gate is provided as a clock. The flip-flop 212 and the Q and Q'outputs of the first SR flip-flop are provided as S and R inputs, respectively, and the second SR flip-flop 214 is provided as a clock with the output of the inverted XOR gate, The inverted output of the second SR flip-flop 214 is provided as the S input of the first first flip-flop 212, and the non-inverted output of the second SR flip-flop 214 is provided as the R input of the first flip-flop. do. In the illustrated embodiment, both the start signal START and the stop signal STOP are shown to be directly input to the XOR gate, but according to another embodiment not shown, the signal START and the stop signal STOP use a buffer. Then, it can be provided as an XOR gate. The buffer may be, for example, an inverter.

Referring to FIG. 5B, when the rising edge of the start signal START is input to the edge detector 210, the output signal X1 of the XOR gate is converted to a logic high state through the rising edge. Since the non-inverting output (Q2) and the inverting output (Q2') of the second SR latch are in the logic high and logic low states, respectively, the first SR flip-flop 212 provided with the rising edge of the X1 signal is the non-inverting output (Q1). ) Outputs a signal in a logic low state, and outputs a signal in a logic high state to an inverting output Q1'.

As the falling edge of the start signal START is input, the output of the XOR gate is converted to a logic low state through the falling edge, and a rising edge formed by inverting by the inverter is provided to the second SR flip-flop 214. Therefore, since the S input and R input of the second SR flip-flop 214 input signals in the logic low and logic high states, respectively, the non-inverting output Q2 and the inverting output Q2' of the second SR flip-flop 214 are input. ) Transitions to logic low and logic high states, respectively.

Subsequently, when the rising edge of the stop signal STOP is input to the edge detector 210, the output signal X1 of the XOR gate is converted to a logic high state through the rising edge. Since the non-inverting output (Q2) and the inverting output (Q2') of the second SR latch are in the logic high and logic low states, respectively, the first SR flip-flop 212 provided with the rising edge of the X1 signal is the non-inverting output (Q1). ) Outputs a signal in a logic high state, and outputs a signal in a logic low state to an inverting output Q1'.

As the falling edge of the stop signal STOP is input, the output signal X1 of the XOR gate is converted to a logic low state through the falling edge, and a rising edge formed by inverting by the inverter is provided to the second SR flip-flop 214. . Therefore, since the S input and R input of the second SR flip-flop 214 input signals in the logic high and logic low states, respectively, the non-inverting output Q2 and the inverting output Q2' of the second SR flip-flop 214 are input. ) Transitions to logic high and logic low states, respectively.

As shown in FIG. 5(B), if the interval between the rising edge of the start signal START and the rising edge of the stop signal STOP is T1, the edge of the activation signal en output from the edge detector 210 The spacing T2 of the active section formed therebetween also corresponds to T1. In addition, although the active period of the activation signal en in FIG. 2 is illustrated as a logic high state, in another embodiment not shown, the active period may be in a logic low state.

6(A) is a gate level circuit diagram showing an outline of the sync controller 220, and FIG. 6(B) is a schematic timing diagram of the sink controller 220. For easy understanding, the period of the clock signal CLK is exaggerated on the timing diagram. Referring to FIG. 6A, the sync controller 220 includes a NAND gate NANDa to which an activation signal en and a clock signal CLK are provided as inputs, an inverted activation signal en' and a clock signal. A NAND gate NANDb provided with (CLK) as an input, a cross-feedback SR latch 222 through which outputs of the two NAND gates are input, and an inverter for inverting and outputting the output Q of the SR latch.

6(A) and 6(B), the NANDa gate to which an activation signal en in a logic low state is input in section ① outputs a signal S in a logic high state, and inverted activation in a logic high state. The NANDb gate to which the signal en' is input outputs a clock signal inverted to the output signal R. In the period 1, the input S provided to the SR latch 222 is logic high, so if the input R is logic low, the output Q is a logic low, and if the input R is logic high, the output Q maintains its previous state. Therefore, in the period ①, output Q maintains a logic low state.

The NANDa gate to which the logic high state activation signal (en) is inputted in the section ② outputs the inverted clock signal CLK that alternates between the logic high state and the logic low state as an output signal S, and outputs the inverted logic low state activation signal ( en') is inputted to the NANDb gate and outputs a logic high signal R. In section ②, input R provided to SR latch 222 is logic high, and input S alternates between logic high and logic low, so when input S is logic low, output Q is logic high, and if input S is logic high Output Q maintains its previous state. Therefore, in section ②, output Q maintains a logic high state.

The edge at which the active period () of the synchronized activation signal EN formed by inverting the output Q is synchronized with the rising edge of the clock signal CLK. Accordingly, a synchronized activation signal EN provided to the delay locked loop 230 to activate the delay locked loop 230 is synchronized with the clock signal CLK. As illustrated, since the rising edge of the activation signal en and the rising edge of the clock do not coincide with each other, the synchronized activation signal EN may have an error between the active section as much as Δt. However, as described above, the period of the clock signal is exaggerated and the maximum value of the error Δt is less than one period of the clock signal, and can be ignored. The signal input in section ③ is the same as section ①, and the synchronized activation signal (EN) is in a logic high state as in section ①.

7 is a schematic timing diagram of the precision detection unit 200 according to the present embodiment. 4 and 7, a delay locked loop (DLL) 230 is activated by receiving a synchronized activation signal EN, and a plurality of signals in which the phase of the input clock signal CLK is delayed. TF[0, 1, 2, ..., 14] is output.

In one embodiment, the delay locked loop 230 may be activated by the low state of the synchronized activation signal EN, and the cascaded third unit delay elements D3 transmit the input signal by a preset delay time. Delayed output. The time for delaying the input signal by the third unit delay elements is shorter than that of the second unit delay elements included in the coarse detector. As an example, delay times of the first and second unit delay elements may have a unit of nsec, but delay times of the third unit delay elements may have a unit of psec. As an embodiment, the delay time of the first unit delay element may be 18 nsec, the delay time of the second unit delay element may be 12 nsec, and the delay time of the third unit delay element may be 625 psec.

The final output TF[14] of the cascaded third unit delay elements D3 is input to a phase detector PD together with a clock signal CLK. The phase detector PD detects the phase difference between the phase of the final output TF[14] and the clock signal CLK, and when the output of the delay locked loop 230 is out of phase compared to the clock signal CLK, the pump-up signal (Not shown) is output, and if the phase of the output of the phase detector is ahead of the clock signal CLK, a pump down signal is output to control a subsequent charge pump (CP).

When a pump-up signal is provided to the charge pump CP, the charge pump CP increases a bias provided to each unit delay element to reduce the delay time of the cascaded third unit delay elements. When a pump down signal is provided to the charge pump CP, the charge pump CP decreases a bias provided to each unit delay element to increase the delay time of the cascaded third unit delay elements. Accordingly, the phase of the plurality of signals TF[0, 1, 2, ..., 14] output from the delay locked loop 230 can be controlled.

TF[0, 1, 2, ..., 14] output from the delay locked loop 230 constitutes a thermometer code, and these are as exemplified in Table 2 below. However, the thermometer code TF output by the delay locked loop 230 is a code corresponding to decimal number 9, and TF[1, 2, ..., 15] contains 0 again, such as [0000 0011 1111 110], and 0 Is included up to [1111 1111 0000 000] corresponding to the decimal number 15. In this respect, it may be different from the thermometer code output by the comparator unit 130 illustrated in Table 1.

The encoder 240 receives the thermometer code TF[0, 1, 2, ..., 14] output from the delay locked loop 230 and converts it to the corresponding binary code F[1, 2, 3, 4]. And print it out. In one embodiment, the encoder 240 converts the thermometer code TF[0, 1, 2, ..., 14] to the gray code GF[0, 1, 2, 3], and the gray code GF[0, 1 , 2, 3] can be converted to binary code BF[0, 1, 2, 3] and output.

In one embodiment, the encoder 240 is provided with a thermometer code TF[0, 1, 2, ..., 14], and performs an operation corresponding to Equation 1 to form a gray code. The encoder 240 performs an operation corresponding to Equation 2 from the formed Gray code GF[0, 1, 2, 3] to obtain a binary code BF[ corresponding to the thermometer code TF[1, 2, ..., 15]]. 0, 1, 2, 3] is formed and output.

The time digital converter 200 according to the present embodiment detects a time difference between the start signal START and the stop signal STOP by using the output signal of the delay lock loop 230 having a high resolution of the delay lock loop Output as Therefore, an advantage of being able to obtain a high resolution is provided.

Fig. 8 is a block diagram showing an outline of the distance measuring device 1 according to the present embodiment. Referring to FIG. 8, the distance measuring apparatus 1 according to the present embodiment provides a pulse laser signal (Laser) and at the same time, a transmitter 10 that provides a start signal (START), and a pulsed laser is applied to a target. A receiving unit 20 that detects a reflected laser and outputs an electric signal, and an amplifier unit 30 that amplifies the electric signal and outputs an amplified stop signal (STOP) to have a predetermined amplitude. And a time-to-digital converter (TDC, 40) that receives a start signal (START) and a stop signal (STOP), detects a time difference between the start signal and the stop signal, and outputs a corresponding digital code.

The transmission unit 10 provides a pulsed laser. As an example, the transmitter 10 drives a laser diode (LD) and a laser diode (LD) that provide a laser with a specific wavelength or variable wavelength in a wavelength range of 250 nm to 11 μm to output a laser and start at the same time. It may include an LD driver 12 that provides a signal (START). The wavelength of the pulsed laser output from the laser diode LD may directly affect the transmittance of the atmosphere, clouds, rain, etc. and the sight of a pedestrian. Therefore, the wavelength of the pulsed laser may be any one wavelength selected from a wavelength range of 250 nm to 11 μm or other regions.

The provided laser reaches the target, is reflected, and is incident on the receiving unit 20. The receiving unit 20 forms an electrical signal corresponding to the incident laser. As an example, the receiving unit 20 may include a photodiode PD that provides a current signal corresponding to the incident laser.

The amplifier unit 30 includes a transimpedance amplifier 32 and a limiting amplifier 34 for converting and amplifying a current signal provided by the receiving unit 20 into a voltage signal. The transfer impedance amplifier 32 receives the current signal, converts it into a corresponding voltage signal, and provides it to the limiting amplifier 34.

The limiting amplifier 34 amplifies the input signal to have a predetermined amplitude to form a stop signal STOP and provides it to the time-to-digital converter 40. A typical amplifier amplifies and outputs an input signal with a predetermined gain. Thus, if the gain is constant, the amplitude of the output signal depends on the amplitude of the input signal. However, the limiting amplifier 34 amplifies and outputs the input signal so that the amplitude of the output signal has a predetermined amplitude.

Fig. 9 is a block diagram showing an outline of the time digital converter 40 according to the present embodiment. Referring to FIG. 9, the time digital converter 40 includes a coarse detection unit 100, a fine detection unit 200, and a decision unit 5 and 300.

The coarse detection unit 100 corresponds to the time digital converter 100 described with reference to FIGS. 1 to 3 above, and the precision detection unit 200 is the time digital converter 200 described with reference to FIGS. 4 to 7 above. Corresponds to Therefore, for a concise and clear description of the present technology, a description of redundant elements will be omitted.

10 is a flowchart schematically illustrating an operation of the determination unit 300 according to the present embodiment. Referring to FIG. 10, the determination unit 300 receives an output signal BC of the coarse detection unit 100 and an output signal BF of the precision detection unit 200 (S100).

The determination unit 300 calculates an error between the output signal BC of the coarse detection unit 100 and the output signal BF of the precision detection unit 200, and τ1-τ2, which is the maximum error of the detection unit 100 with a rough error Compare (S200). The coarse detector 100 includes a start edge signal and a second unit delay time τ2 propagating through the start delay line 114 in which the first unit delay element D1 delayed by the first unit delay time τ1 is cascaded. Since the second unit delay element (D2) delayed by the second unit delay element (D2) is to compare the front and rear of the stop edge signal propagating through the cascaded stop delay line 124, the maximum error of detection is the first unit delay time and the second unit delay time It corresponds to the difference of τ1-τ2.

Since the precision detector 200 uses a third unit delay element that delays the signal with a third unit delay time (τ3) shorter than the first unit delay time (τ1) and the second unit delay time (τ2), The precision is higher. Therefore, the measured value is smaller than the measured value of the coarse detection unit 100. Therefore, when there is no error, the difference between the output signal BC of the coarse detection unit 100 and the output signal BF of the precision detection unit 200 is greater than 0, and the error is τ1, which is the maximum error of the coarse detection unit 100 Less than or equal to -τ2.

If the difference between the output signal BC of the coarse detection unit 100 and the output signal BF of the precision detection unit 200 is greater than 0 or the error is greater than τ1-τ2, which is the maximum error of the coarse detection unit 100 Since an error has occurred in at least one of the output signal BC of the coarse detection unit 100 and the output signal BF of the precision detection unit 200, the calculation is performed with new output signals by returning to the previous step.

The determination unit 300 has a difference between the output signal BC of the coarse detection unit 100 and the output signal BF of the precision detection unit 200 is greater than 0, and the error is τ1-, which is the maximum error of the coarse detection unit 100 When it is less than τ2, the determination unit 300 provides the output signal FB of the precision detection unit 200.

For example, the determination unit 300 may calculate a distance to a target (refer to FIG. 8) from an output signal FB, which is a binary signal output by the precision detection unit 200, and output the calculated distance information.

In the first end of the analog circuit of the conventional distance measuring apparatus, an amplifier having a linear gain was used. The amplitude of the reflected laser decreases as the reciprocation distance from the pulsed laser to the output and reflected from the target to reach the receiver increases, and the amplitude of the electric signal formed by detecting this decreases. Therefore, the amplitude of the electrical signal has information on the distance between the light source and the target, and it is necessary to amplify the electrical signal linearly.

In the case of detecting a target at a distance of several tens to several hundred meters from a target at a distance of several to tens of cm using a conventional distance measuring device, it has been requested to amplify the electrical signal with minimal distortion to minimize the distance error. These amplifiers must have high-gain linearity, and designing them was not easy.

However, this embodiment amplifies the input signal to have a predetermined amplitude by using the limiting amplifier 300, thus providing the advantage of facilitating the design of the first analog end, and the coarse detection unit 100 and the precision detection unit Since the distance to the target is detected using 200, the advantage of being able to detect more precisely is provided.

Although it has been described with reference to the embodiment shown in the drawings in order to help understand the present invention, this is an embodiment for implementation, is only illustrative, and a person having ordinary knowledge in the art therefrom various modifications and equivalent It will be appreciated that other embodiments are possible. Accordingly, the true technical scope of the present invention should be determined by the appended claims.

10: transmitting unit 20: receiving unit
30: limiting amplifier 40: time digital converter
100: coarse detection unit, time digital converter 112: start latch
114: start delay line 122: stop latch
124: stop delay line 130: comparator
140: encoder
200: precision detection unit, time digital converter 210: edge detector
220: sync control unit 230: delay lock loop
240: encoder

Claims (22)

A start delay unit cascaded with a first unit delay element that delays and outputs a start edge signal formed by the start signal by a first delay time;
A start delay unit cascaded with a second unit delay element for delaying and outputting a stop edge signal formed by the stop signal by a second delay time shorter than the first delay time;
A comparator unit including comparators for comparing the delayed start edge signal and the delayed stop edge signal, and
And an encoder that converts the output of the comparator into a corresponding digital code, and outputs a digital code corresponding to the start signal and the stop signal. The method of claim 1,
The start edge signal is a time digital converter that is a signal including one of a rising edge and a falling edge of the start signal. The method of claim 1,
The stop edge signal is a signal including any one of a rising edge and a falling edge of the stop signal. The method of claim 1,
The time digital converter,
A time digital converter further comprising a start latch that is a resettable T latch (toggle latch) for receiving the start signal and outputting the start edge signal. The time digital converter,
A time digital converter further comprising a stop latch that is a resettable T latch (toggle latch) for receiving the stop signal and outputting the stop edge signal. The method of claim 1,
The output of the comparator part is a thermometer code,
The encoder is a time digital converter for outputting a binary code corresponding to the thermometer code. The method of claim 6,
The encoder converts the thermometer code into a gray code,
Time-to-digital converter for converting the gray code into the binary code and outputting the converted gray code. An edge detector for outputting an enable signal having an active period corresponding to between a first edge of the start signal and a first edge of the stop signal;
A sync controller configured to output a synchronized activation signal by synchronizing the edge of the activation signal with the edge of the clock signal;
A delay locked loop (DLL) for outputting a thermometer code consisting of clock signals delayed by a controllable phase by receiving the clock signal and being activated by the synchronized activation signal during the active period; and
It includes an encoder that converts the thermometer code into a corresponding binary code and outputs it,
The binary code is a time digital converter corresponding to a time difference between the first edge of the start signal and the first edge of the stop signal. The method of claim 8,
A time digital converter in which a first edge of the start signal and a first edge of the stop signal are a rising edge. The method of claim 8,
A time digital converter in which a first edge of the start signal and a first edge of the stop signal are a rising edge. The method of claim 8,
The activation signal output from the edge detector has a rising edge at the first edge of the start signal, a falling edge at the first edge of the stop signal, and the active period is in a logic high state. The method of claim 8,
The activation signal output from the edge detector has a falling edge at the first edge of the start signal, a rising edge at the first edge of the stop signal, and the active period is in a logic low state. The start edge signal formed from the start signal is delayed by a first delay time, the stop edge signal formed from the stop signal is delayed by a second delay time shorter than the first delay time, and the delayed start edge signal is delayed by the stop edge signal A coarse detection unit for outputting a code corresponding to a time difference between the start signal and the stop signal at the first delay time and the second delay time when preceded by;
A precision detection unit that detects the time difference between the start signal and the stop signal as a signal having a higher resolution than the second delay time, and
Time digital converter comprising a determination unit (decision unit) for verifying validity by comparing the output signal of the precision detection unit with the output signal of the coarse detection unit. The method of claim 13,
The coarse detection unit includes a start delay unit and a stop delay unit,
The start delay unit is connected in a cascade to a first unit delay element that delays and outputs the start edge signal by the first delay time,
The time digital converter in which the second unit delay element for outputting the stop delay unit delaying the stop edge signal by the second delay time is cascaded. The method of claim 13,
The coarse detection unit includes a comparator unit including comparators and an encoder,
The comparator unit compares the delayed start edge signal with the delayed stop edge signal using comparators and outputs a thermometer code corresponding to a time difference between the start signal and the stop signal,
The encoder converts the thermometer code output from the comparator into a corresponding digital code and outputs a time digital converter. The method of claim 13,
The stop edge signal is a signal including any one of a rising edge and a falling edge of the stop signal. The method of claim 13,
The start edge signal is a time digital converter that is a signal including one of a rising edge and a falling edge of the start signal. The method of claim 13,
The precision detection unit,
An edge detector that outputs an enable signal having an active period corresponding to between a first edge of the start signal and a first edge of the stop signal,
A sync control unit for synchronizing the edge of the activation signal and the edge of the clock signal to output an activation signal synchronized with the synchronized clock signal;
A delay locked loop (DLL) for outputting a thermometer code including clock signals delayed by a controllable phase by receiving the synchronized clock signal and being activated by the synchronized activation signal during the active period; and
It includes an encoder that converts the thermometer code into a corresponding binary code and outputs it,
The binary code is a time digital converter corresponding to a time difference between the first edge of the start signal and the first edge of the stop signal. The method of claim 13,
The determination unit,
A temporal digital converter that calculates a difference between the output signal of the coarse detection unit and the output signal of the precision detection unit to determine whether the output of the coarse detection unit and the output of the precision detection unit are in error. A transmitter for providing a pulse laser signal and a start signal at the same time;
A receiver configured to detect the reflected signal of the pulsed laser and output a corresponding electric signal;
A limiting amplifier that amplifies the electrical signal but outputs a stop signal amplified to have a predetermined amplitude, and
Time to receive the start signal and the stop signal, perform coarse detection and fine detection to detect a time difference between the start signal and the stop signal, and output a corresponding digital code- Range finder with digital converter. The method of claim 20,
The time digital converter,
A coarse detection unit that performs the coarse detection, wherein the coarse detection unit:
A start delay line for delaying and outputting a start edge signal formed by the start signal by a first unit delay time;
A start delay line for delaying and outputting a stop edge signal formed by the stop signal by every second unit delay time;
A comparator unit comparing the preceding and following of the plurality of delayed start edge signals and the plurality of delayed stop edge signals,
Including an encoder for converting the output of the comparator into a corresponding digital code, when the delayed start edge signal precedes the delayed stop edge signal, a difference between a first unit delay time and a second unit delay time is detected to perform coarse detection. A range finder to perform. The method of claim 20,
The time digital converter,
A fine detection unit for performing the fine detection, wherein the fine detection unit:
An oscillator that delays the pulse train by each unit delay time and provides
Including an encoder that converts the sum of the unit delay times into a digital code,
A range finder for performing fine detection by calculating a sum of the unit delay times corresponding to a difference between the start edge signal and the stop edge signal.

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