KR20200132512A - Wiring substrate and semiconductor package comprising the same - Google Patents

Abstract

The present disclosure relates to a wiring board and a semiconductor package including the same. The wiring board comprises: a wiring board including one or more wiring layers; and a first test member embedded in the wiring board and electrically connected to the one or more wiring layers. The first test member is an IC chip including a BIST circuit.

Description

A wiring board and a semiconductor package including the same {WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME}

The present disclosure relates to a wiring board and a semiconductor package including the same.

In general, in the IC (Integrated Circuit) manufacturing step, a metal pattern is formed on a silicon wafer, and only known good die (KGD) is classified through EDS (Electrical Die Sort). Thereafter, when a substrate is attached or a re-distribution layer (RDL) circuit is formed through a packaging process, the final product is selected using a set-up test facility based on the IC data sheet. However, since the defect generated at this time is a defect generated at the package level, there is a problem that a relatively expensive KGD is discarded when a defect occurs.

In particular, recently, the chipset market for HPC (High Performance Computing) is growing, and accordingly, expensive CPU (Central Processing Unit) or HBM (High Bandwidth Memory) used for this may be discarded due to the above-described package defect. The burden on Ross is growing.

One of the various objects of the present disclosure is to provide a wiring substrate (or package substrate) and a semiconductor package including the same, capable of determining whether a function is defective after the semiconductor chip is disposed even before the semiconductor chip is disposed.

One of the various solutions proposed through the present disclosure is to construct a wiring board or a package board by embedding a test member including a BIST (Built In Self Test) circuit in the wiring board.

For example, the wiring board according to an example includes a wiring board including one or more wiring layers, and a first test member embedded in the wiring board and electrically connected to the one or more wiring layers, and the first test member is a BIST It may be an IC (Integrated Circuit) chip including a circuit.

In addition, the semiconductor package according to an example includes a wiring board including one or more wiring layers and a first bridge that is embedded in the wiring board and is electrically connected to the one or more wiring layers, and is embedded in the wiring board and is electrically connected to the one or more wiring layers. A wiring board including a first test member, a first semiconductor chip disposed on the wiring board and having a plurality of first connection pads electrically connected to the one or more wiring layers, and the one or more wiring layers disposed on the wiring board And a second semiconductor chip having a plurality of second connection pads electrically connected to each other, wherein at least some of the plurality of first connection pads and at least some of the plurality of second connection pads are electrically connected to each other through the first bridge. It may be connected by.

As one of the effects of the present disclosure, a wiring substrate (or package substrate) capable of determining whether a function defect after the semiconductor chip is disposed even before the semiconductor chip is disposed, and a semiconductor package including the same may be provided.

1 is a block diagram schematically showing an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3 is a schematic cross-sectional view showing a case where a 3D BGA package is mounted on a main board of an electronic device.
4 is a schematic cross-sectional view illustrating a case in which a 2.5D silicon interposer package is mounted on a main board.
5 is a schematic cross-sectional view illustrating a case in which a 2.5D organic interposer package is mounted on a main board.
6 is a schematic cross-sectional view of an example of a semiconductor package.
7 is a plan view schematically illustrating a top view of the semiconductor package of FIG. 6.
FIG. 8 is a schematic cut-away plan view of the semiconductor package of FIG. 6.
9 to 11 are cross-sectional views schematically illustrating various examples of bridges of the semiconductor package of FIG. 6.
FIG. 12 is a process diagram schematically illustrating a functional test process of the wiring board (or package board) used in the semiconductor package of FIG. 6.
13 is a flowchart schematically illustrating a functional test process of a wiring board (or package board) used in the semiconductor package of FIG. 6.
14 is a schematic cross-sectional view of another example of a semiconductor package.
15 is a schematic cross-sectional view of another example of a semiconductor package.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawings, the electronic device 1000 accommodates a main board 1010. A chip set-related part 1020, a network-related part 1030, and other parts 1040 are physically and/or electrically connected to the main board 1010. These are also combined with other components to be described later to form various signal lines 1090.

The chip set related parts 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as a central processor (eg, a CPU), a graphics processor (eg, a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) are included, but are not limited thereto, and other types of chip-related components may be included in addition to this. In addition, of course, these chip set-related components 1020 may be combined with each other.

Network-related parts 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such and beyond, including, but not limited to, many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, it goes without saying that the network-related parts 1030 may be combined with each other together with the chip set-related parts 1020.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filters, and MLCC (Multi-Layer Ceramic Condenser). , It is not limited thereto, and in addition, passive components used for various other purposes may be included. In addition, it goes without saying that the other parts 1040 may be combined with each other together with the chip set related parts 1020 and/or the network related parts 1030.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. For example, camera 1050, antenna 1060, display 1070, battery 1080, audio codec, video codec, power amplifier, compass, accelerometer, gyroscope, speaker, mass storage device (e.g. , Hard disk drives), compact disks (CDs), digital versatile disks (DVDs), and the like, but are not limited thereto, and other parts used for various purposes according to the type of electronic device 1000 Of course, etc. may be included.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( computer), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, the present invention is not limited thereto, and, of course, it may be any other electronic device that processes data in addition to these.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, a semiconductor package may be applied to various electronic devices as described above for various purposes. For example, the motherboard 1110 is accommodated in the body 1101 of the smart phone 1100, and various components 1120 may be physically and/or electrically connected to the motherboard 1110. In addition, other components that may or may not be physically and/or electrically connected to the motherboard 1110 such as the camera 1130 may be accommodated in the body 1101. Some of the components 1120 may be chipset related components, and some of them may be a semiconductor package 1121 including an interposer. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and of course, other electronic devices may be used.

Semiconductor package

In general, a semiconductor chip is integrated with a number of microelectronic circuits, but cannot itself serve as a finished semiconductor product, and there is a possibility of being damaged by an external physical or chemical impact. Therefore, the semiconductor chip itself is not used as it is, but the semiconductor chip is packaged and used in an electronic device.

The reason why semiconductor packaging is necessary is because there is a difference in circuit width between the semiconductor chip and the main board of the electronic device from the viewpoint of electrical connection. Specifically, in the case of a semiconductor chip, the size of the connection pad and the gap between the connection pads are very small, whereas in the case of a main board used in electronic devices, the size of the component mounting pad and the gap between the component mounting pads are much larger than the scale of the semiconductor chip . Therefore, it is difficult to directly mount a semiconductor chip on such a main board, and a packaging technology capable of buffering the difference in circuit width between each other is required.

Hereinafter, the use of an interposer among semiconductor packages manufactured by such packaging technology will be described in more detail with reference to the drawings.

3 is a schematic cross-sectional view illustrating a case in which a 3D BGA package is mounted on a main board of an electronic device.

Among semiconductor chips, application specific integrated circuits (ASICs), such as graphics processing units (GPUs), are very important to package at high yields because the price of each chip is very high. For this purpose, before mounting a semiconductor chip, a ball grid array (BGA) substrate 2210, which can rewire thousands to millions of connection pads, is first prepared, and expensive The semiconductor chip is subsequently mounted and packaged on the BGA substrate 2210 using a surface mounting technology (SMT) or the like, and then finally mounted on the main board 2110.

Meanwhile, in the case of the GPU 2220, it is necessary to minimize a signal path to a memory, for example, a high bandwidth memory (HBM). To this end, a semiconductor chip such as HBM 2240 is mounted on the interposer 2230 and then packaged, and then stacked on the package on which the GPU 2220 is mounted in a package on package (POP) form. What to do is being used. However, in this case, there is a problem that the thickness of the device becomes too thick, and there is a limit to minimizing the signal path.

4 is a schematic cross-sectional view illustrating a case in which a 2.5D silicon interposer package is mounted on a main board.

As a solution to the above-described problem, a first semiconductor chip such as GPU 2220 and a second semiconductor chip such as HBM 2240 are side-by-side on the silicon interposer 2250. As a 2.5D interposer technology for packaging after mounting, it may be considered to manufacture a semiconductor package 2310 including a silicon interposer. In this case, the GPU 2220 having thousands to millions of connection pads and the HBM 2240 can be rewired through the interposer 2250, and they can be electrically connected with a minimum path. In addition, if the semiconductor package 2310 including the silicon interposer is mounted again on the BGA substrate 2210 and rewired, it can be finally mounted on the main board 2110. However, in the case of the silicon interposer 2250, not only is it very difficult to form a through silicon via (TSV), but also the manufacturing cost is considerable, which is disadvantageous in reducing a large area and reducing cost.

5 is a schematic cross-sectional view illustrating a case where a 2.5D organic interposer package is mounted on a main board.

As a solution to the above-described problem, it may be considered to use the organic interposer 2260 instead of the silicon interposer 2250. For example, on the organic interposer 2260, a first semiconductor chip such as GPU 2220 and a second semiconductor chip such as HBM 2240 are surface-mounted side by side, and then packaged with 2.5D interposer technology. It may be considered to manufacture a semiconductor package 2320 including. In this case, the GPU 2220 having thousands to millions of connection pads and the HBM 2240 can be rewired through the interposer 2260, and they can be electrically connected with a minimum path. In addition, when the semiconductor package 2320 including the organic interposer is mounted again on the BGA substrate 2210 and re-wired, it can be finally mounted on the main board 2110. In addition, it is advantageous for a large area and low cost. However, in the case of the semiconductor package 2320 including the organic interposer, when the molding process is performed, the interposer 2260 and the semiconductor chips 2220, 2240 and the molding material and the thermal expansion coefficient (CTE) mismatch, etc. Problems such as occurrence of sebum, deterioration of filling properties of the underfill resin, and occurrence of cracks between the die and the molding material may occur. In addition, the organic interposer may be disadvantageous in implementing a fine pattern.

As a method for solving the above-described problem, although not specifically shown in the drawings, it may be considered to separately form a silicon-based interconnection bridge having a fine pattern, and insert it into a cavity of a BGA substrate to be embedded. However, in this case, it is difficult to form a cavity and to implement a corresponding microcircuit in the BGA substrate, and thus a problem of process and yield decline may occur. Therefore, there is a need for a new type of semiconductor package that can solve all of these problems.

6 is a schematic cross-sectional view of an example of a semiconductor package.

7 is a plan view schematically illustrating a top view of the semiconductor package of FIG. 6.

FIG. 8 is a schematic cut-away plan view of the semiconductor package of FIG. 6.

Referring to the drawings, a semiconductor package 500A according to an example is disposed on a wiring board 100A, a wiring board 100A, and includes a first semiconductor chip 221 including a plurality of first connection pads 221P, and It includes a plurality of second semiconductor chips 222 each disposed on the wiring board 100A and each including a plurality of second connection pads 222P. A printed circuit board 300 may be further disposed under the wiring board 100A. The wiring board 100A may be mounted on the printed circuit board 300 and used as a package board 400A along with it. If necessary, the printed circuit board 300 may be omitted, and in this case, the wiring board 100A itself may be used as the package board 400A. That is, the wiring board 100A may be the package board 400A. If necessary, the state in which the wiring board 100A is mounted on the printed circuit board 300 may be referred to as the wiring board 400A instead of the package board 400A. That is, in the present disclosure, both terms may be used interchangeably, and it is understood that there is no particular limitation.

On the other hand, in general, a function test is a process of verifying whether a package operates according to an intended logic function, and uses a test pattern or vector. Since such a functional test needs to evaluate a signal or the like through a semiconductor chip in an actual use environment, a situation where packaging is usually completed is required. However, in this case, even if a wiring board that is good for open and short inspection is not verified, if a minute defect enough to affect the function is not verified, it may lead to malfunction after packaging, and eventually, even expensive KGD may be discarded together.

On the other hand, in the semiconductor package 500A according to an example, the wiring board 100A according to the example includes the first test member 150. The first test member 150 may be an IC chip including a BIST circuit. BIST may be, for example, pBIST (programmable BIST). If necessary, the wiring board 100A may further include a second test member 160, and the second test member 160 may be an IC chip including a logic analysis circuit. In this case, before the semiconductor chips 221 and 222 are disposed, it is possible to inspect the wiring board 100A and/or the package board 400A to fine factors that may affect the function. That is, it is possible to reduce the discarding of KGD due to defects in the wiring board 100A and/or the package board 400A after assembly through the determination of whether the semiconductor chips 221 and 222 are functional before assembling. For example, a chipset composed of several IC combinations, such as heterogeneous integration, may degrade or cause errors due to the IC combination, even if it is a KGD, and this can be verified in advance through a pre-test. In addition, in the case of a method embedded in the IC in the form of logic, the logic must be configured with the same node as the main IC, whereas the test IC has no node restrictions, so BIST can be configured at lower cost.

On the other hand, the wiring board 100A according to an example includes a connection structure 140 having a first side and a second side opposite to the first side, and a plurality of bridges disposed on the first side of the connection structure 140. 120), first and second test members 150 and 160 respectively disposed on the first side of the connection structure 140, a plurality of bridges 120 on the first side of the connection structure 140, and the first and second 2The frame 110 disposed around the test members 150 and 160, and the first side of the connection structure 140, and the frame 110 and the plurality of bridges 120 and the first and second test members ( 150 and 160) and a suture material 130 covering at least a portion of each. The connection structure 140 includes one or more wiring layers 142. Each of the plurality of bridges 120 and the first and second test members 150 and 160 is electrically connected to one or more wiring layers 142, respectively. The frame 110 includes a plurality of wiring layers 112a, 112b, and 112c electrically connected to one or more wiring layers 142. Meanwhile, a plurality of first connection pads 221P of the first semiconductor chip 221 and a plurality of second connection pads 222P of each of the plurality of second semiconductor chips 222 are illustrated in FIGS. 7 and 8. As illustrated, they are electrically connected to each other in various relationships through a plurality of bridges 120. For example, the second connection pads 222P of each of the plurality of second semiconductor chips 222 may be electrically connected to the first connection pads 221P of the first semiconductor chip 221 through the bridge 120.

In this way, in the semiconductor package 500A according to an example, the wiring board 100A according to the example includes the frame 110 and a plurality of bridges 120 are disposed using the frame 110. Electrical connection between the semiconductor chips 221 and 222 is possible through the fine patterns of the plurality of bridges 120, and through this, high speed and low latency interconnection can be implemented. In one example, the frame 110 has a plurality of first through portions 110H1, and a plurality of bridges 120 are disposed on the plurality of first through portions 110H1, respectively. After this arrangement, the plurality of bridges 120 are each sealed with a suture material 130. In this case, only good products may be selected and placed among a plurality of separately manufactured bridges 120. In addition, the manufactured wiring board 100A may be electrically connected to the printed circuit board 300, the first semiconductor chip 221, and the plurality of second semiconductor chips 222, respectively, without a separate carrier. Accordingly, loss of the expensive first and second semiconductor chips 221 and 222 and the expensive printed circuit board 300 may be reduced as the yield of the wiring board 100A decreases. In addition, since the plurality of bridges 120 can be manufactured in a small size, the size of the ultra-fine wiring area can be reduced, and as a result, a decrease in the yield of the wiring board 100A can be further prevented. In addition, as described above, the wiring board 100A can be electrically connected to the printed circuit board 300, the first semiconductor chip 221, and the plurality of second semiconductor chips 222 without a separate carrier. Simplification is also possible. In addition, since the frame 110 controls the process warpage, warpage control is also possible.

On the other hand, the wiring board 100A according to an example passes through the backside wiring layer 132 disposed on the side opposite to the side on which the connection structure 140 of the encapsulant 130 is disposed, and the encapsulant 130, and the frame 110 A backside via 133 electrically connecting the plurality of wiring layers 112a, 112b, and 112c and the backside wiring layer 132 may be further included. In this case, the pads for the electrical connection bump 180 can be arranged in more various positions through the backside wiring design. Therefore, by improving the number of electrical connection bumps 180, it is possible to improve the electrical connection path with the printed circuit board 300. The backside wiring layer 132 is disposed on the side opposite to the side on which the connection structure 140 of the encapsulant 130 is disposed and may be protected by a passivation layer 170 covering at least a part of the backside wiring layer 132. An opening exposing at least a portion of each of the backside wiring layers 132 may be formed in the passivation layer 170, and an electrical connection bump 180 may be disposed in each opening to be electrically connected to the exposed backside wiring layer 132 .

Meanwhile, the wiring board 100A according to an example may further include a passive component. For example, the passive component may be disposed on a separate penetrating portion of the frame 110 and covered with a suture material 130. Alternatively, it may be built into the frame 110. The passive component may be a known passive component such as a capacitor or an inductor. In this way, when the passive components are disposed in various locations within the wiring board 100A, the electrical path can be minimized, and thus power integrity can be supplemented and improved.

Hereinafter, each configuration included in the semiconductor package 500A according to an example will be described in more detail with reference to the drawings.

First, the wiring board 100A according to an example includes a frame 110, a plurality of bridges 120, a sealing material 130, a connection structure 140, and a test member 150, 160, as described above. do. Also, if necessary, a backside wiring layer 132, a backside via 133, and/or an electrical connection bump 180 may be further included.

The frame 110 may further improve the rigidity of the wiring board 100A according to the specific material of the first and second insulating layers 111a and 111b, and serves to secure uniformity of the thickness of the encapsulant 130. Can be done. The frame 110 may have first to third through portions 110H1, 110H2 and 110H3 penetrating through the first and second insulating layers 111a and 111b. In addition to the first and second insulating layers 111a and 111b, the frame 110 includes first to third wiring layers 112a, 112b, and 112c, and first and second wiring vias 113a and 113b. It may function as an electrical connection member providing an electrical connection path. If necessary, the frame 110 may be composed of a plurality of frame units. Each frame unit may independently include first and second insulating layers 111a and 111b, first to third wiring layers 112a, 112b, and 112c, and first and second wiring vias 113a and 113b. I can. Each frame unit may be disposed around the plurality of bridges 120 and the first and second test members 150 and 160, respectively. When composed of a plurality of frame units, the first to third through portions 110H1, 110H2 and 110H3 may be formed between the frame units, respectively, and may be connected to each other.

A bridge 120, a first test member 150, and a second test member 160 may be disposed in the first to third through portions 110H1, 110H2, 110H3 of the frame 110 according to design. . For example, each of the bridges 120 may be disposed in the first through portion 110H1. However, the present invention is not limited thereto, and a plurality of bridges 120 may be disposed together in one first through part 110H1. The first test member 150 may be disposed in the second through portion 110H2. A second test member 160 may be disposed in the third through portion 110H3. The bridge 120, the first test member 150, and the second test member 160 are disposed on the first to third through portions 110H1, 110H2, and 110H3, respectively, and are continuously formed by the inner wall of the frame 110. It may be surrounded, but is not limited thereto. For example, the frame 110 itself may be composed of a plurality of units, and in this case may be discontinuously surrounded.

The frame 110 includes a first insulating layer 111a in contact with the first side of the connection structure 140 and a first wiring layer 112a in contact with the first side of the connection structure 140 and buried in the first insulating layer 111a. ), a second wiring layer 112b disposed on the opposite side of the side where the first wiring layer 112a of the first insulating layer 111a is buried, and a second wiring layer 112b disposed on the first insulating layer 111a And a second insulating layer 111b covering at least a portion of the second insulating layer 111b, and a third wiring layer 112c disposed on a side opposite to the side where the second wiring layer 112b of the second insulating layer 111b is buried. The first and second wiring layers 112a and 112b and the second and third wiring layers 112b and 112c are formed with first and second wiring vias 113a penetrating through the first and second insulating layers 111a and 111b, respectively. 113b). The first to third wiring layers 112a, 112b, and 112c are connected to the bridge 120, the first test member 150, and/or the second through the wiring layer 142 and the connection via 143 of the connection structure 140. It may be electrically connected to the test member 160.

The material of the first and second insulating layers 111a and 111b is not particularly limited. For example, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, for example, ABF (Ajinomoto Build- up Film), etc. can be used. Alternatively, a material in which the above-described resin is impregnated into a core material such as glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with an inorganic filler, for example, a prepreg may be used.

The first to third wiring layers 112a, 112b, and 112c may provide a vertical electrical connection path for the wiring board 100A together with the first and second wiring vias 113a and 113b. Materials for forming the first to third wiring layers 112a, 112b, and 112c include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead ( Metal materials such as Pb), titanium (Ti), or alloys thereof may be used. The first to third wiring layers 112a, 112b, and 112c may perform various functions according to the design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like may be included. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. Also, each of the first to third wiring layers 112a, 112b, and 112c may include various types of via pads.

The thickness of each of the first to third wiring layers 112a, 112b, and 112c may be thicker than the thickness of each of the wiring layers 142. Specifically, in order to maintain rigidity, the frame 110 selects a prepreg as a material for the first and second insulating layers 111a and 111b, and the first to third wiring layers 112a, 112b, and 112c formed therein ) Can also be relatively thick. On the other hand, the connection structure 140 requires a microcircuit and high-density design, and therefore, a photosensitive insulating material (PID) is selected as the material of the insulating layer 141, and the thickness of the wiring layer 142 formed therein is also relatively It can be thin.

The first wiring layer 112a may be recessed into the first insulating layer 111a. In this case, the first wiring layer 112a is recessed into the first insulating layer 111a, so that the surface of the first insulating layer 111a in contact with the first side of the connection structure 140 and the first wiring layer 112a A surface of the connection structure 140 in contact with the first side may have a step. Therefore, when covering the frame 110 and the bridge 120 with the encapsulant 130, the material forming the encapsulant 130 is bleed to prevent contamination of the first wiring layer 112a of the frame 110. have.

The first and second wiring vias 113a and 113b electrically connect the first to third wiring layers 112a, 112b, and 112c formed on different layers, thereby forming an electrical path in the frame 110. Materials for forming the first and second wiring vias 113a and 113b include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead (Pb). ), titanium (Ti), or an alloy thereof may be used. The first and second wiring vias 113a and 113b may include a signal via, a power via, a ground via, and the like, and the power via and the ground via may be the same via. Each of the first and second wiring vias 113a and 113b may be a field type via filled with a metallic material, or a conformal type via in which a metallic material is formed along the wall surface of the via hole. In addition, each may have a tapered shape.

When forming a hole for the first wiring via 113a, some pads of the first wiring layer 112a may serve as a stopper. As shown in the drawing, the first wiring via 113a is It may be advantageous in the process to have a tapered shape whose width is smaller than the width of the underside. In this case, the first wiring via 113a may be integrated with the pad pattern of the second wiring layer 112b. In addition, when a hole for the second wiring via 113b is formed, some pads of the second wiring layer 112b may serve as a stopper. As shown in the drawing, the second wiring via 113b has the width of the upper surface. It may be advantageous in process to have a tapered shape smaller than the width of the underside. In this case, the second wiring via 113b may be integrated with the pad pattern of the third wiring layer 112c.

The bridge 120 includes microcircuit wiring for electrically connecting the first and second connection pads 221P and 222P of the first and second semiconductor chips 221 and 222, respectively. To this end, the bridge 120 may be disposed to overlap the first and second semiconductor chips 221 and 222 at least partially on a plane, as shown in FIGS. 7 and 8, respectively. Since the bridge 120 includes microcircuit wiring, the circuit inside the bridge 120 may be thinner than the thickness of the wiring layer 142 of the connection structure 140. In addition, circuits may be electrically connected vertically through vias having a pitch smaller than the pitch between the connection vias 143 of the connection structure 140. The bridge 120 may be various types of bridges, for example, a silicon interconnect bridge, a glass interconnect bridge, a ceramic interconnect bridge, or an organic interconnect bridge. It may be, but is not limited thereto. If necessary, at least one bridge 120 may be additionally designed for vertical electrical connection therein. For example, when the bridge 120 is a silicon interconnect bridge, compared to the bridge 120, through silicon vias (TSVs) may be further formed.

The suture material 130 covers at least a portion of each of the frame 110 and the bridge 120 and the first and second test members 150 and 160. In addition, the suture material 130 fills at least a part of each of the first to third through portions 110H1, 110H2, and 110H3. The encapsulant 130 includes an insulating material. In this case, the insulating material may be a non-photosensitive insulating material, more specifically, a non-photosensitive insulating material including an inorganic filler and an insulating resin. For example, it may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin including a reinforcing material such as an inorganic filler, specifically a non-photosensitive insulating material such as ABF or EMC. If necessary, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler and a glass fiber, for example, a prepreg may be used. If necessary, PIE (Photo Image-able Encapsulant) may be used.

The backside wiring layer 132 may be introduced for backside wiring design. The backside wiring layer 132 is also copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof It may contain metal materials such as. The backside wiring layer 132 can also perform various functions in design design. For example, a pad for a ground (GND) pattern, a pad for a power (PWR) pattern, a pad for a signal (S) pattern, and the like may be included. The ground (GND) pattern pad and the power (PWR) pattern pad may have the same pattern. The backside wiring layer 132 may be evenly distributed and disposed as necessary over the entire area of the lower surface of the encapsulant 130. When at least a part of the backside wiring layer 132 is disposed to overlap the bridge 120 on a plane, heat generated from the bridge 120 may be more easily discharged through the electrical connection bump 180 or the like.

The backside via 133 may provide an electrical connection path between the first to third wiring layers 112a, 112b, and 112c of the frame 110 and the backside wiring layer 132. The backside via 133 is also copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof It may contain metal materials such as. The backside via 133 may also be a field type via filled with a metal material, or a conformal type via in which a metal material is formed along a wall surface of the via hole. In addition, it may have a tapered shape in the same direction as the first and second wiring vias 113a and 113b. The backside via 133 may also include a signal via, a ground via, and a power via, and the power via and the ground via may be the same via.

The connection structure 140 may redistribute the first and second connection pads 221P and 222P of the first and second semiconductor chips 221 and 222, respectively. In addition, according to the arrangement of the first and second connection pads 221P and 222P of each of the first and second semiconductor chips 221 and 222, the bridge 120, the first test member 150, and the second test member It can be electrically connected to 160. The connection structure 140 includes an insulating layer 141, a wiring layer 142 disposed on the insulating layer 141, and a connection via 143 passing through the insulating layer 141 and connected to the wiring layer 142. The connection vias 143 electrically connect the wiring layers 142 disposed on different layers to each other. In addition, the wiring layer 142 is electrically connected to the bridge 120 or the first to third wiring layers 112a, 112b, and 112c of the frame 110. The insulating layer 141, the wiring layer 142, and the connection via 143 of the connection structure 140 may be more or less than those shown in the drawings, respectively.

An insulating material may be used as the material of the insulating layer 141, and in this case, a photosensitive insulating material (PID) may be used as the insulating material. In this case, it is possible to introduce a fine pitch through a photo via, which is advantageous for fine circuits and high-density design. When the insulating layer 141 is a multilayer, the boundary may be separated from each other, or the boundary may be unclear.

The wiring layer 142 may actually perform a rewiring function. The material for forming the wiring layer 142 is also copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or these Metal materials such as an alloy of can be used. The wiring layer 142 may also perform various functions according to a design design. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. In addition, the wiring layer 142 may include various types of via pads and electrical connection metal pads.

The connection via 143 electrically connects the wiring layers 142 formed on different layers, and also connects the wiring layer 142 to the first to third wiring layers 112a, 112b, and 112c of the bridge 120 or the frame 110. ) And electrically. As a material for forming the connection via 143, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) , Or a metal material such as an alloy thereof may be used. The connection via 143 may include a signal via, a power via, and a ground via, and the power via and the ground via may be the same via. The connection vias 143 may also be field-type vias each filled with a metallic material, or conformal-type vias in which metallic materials are formed along the walls of the via holes. In addition, the first and second wiring vias 113a and 113b may have a tapered shape in a direction opposite to that of the first and second wiring vias 113a and 113b.

The first test member 150 may be a BIST, for example, an IC chip including a pBIST circuit. The second test member 160 may be an IC chip including a logic analysis circuit. Through these, it is possible to inspect the wiring board 100A and/or the package board 400A to fine factors that may affect the function before the semiconductor chips 221 and 222 are disposed. The first and second test members 150 and 160 may be configured as a multi-channel and multi-function that can be used universally.

The passivation layer 170 is an additional component for protecting the backside wiring layer 132 from external physical and chemical damage. The passivation layer 170 may include a thermosetting resin. For example, the passivation layer 170 may be ABF, but is not limited thereto. The passivation layer 170 has an opening that opens at least a portion of the backside wiring layer 132. There may be tens to tens of thousands of openings, and may have a number of more or less. Each opening may be composed of a plurality of holes. If necessary, a surface mount component such as a Land Side Capacitor (LSC) may be disposed on the lower surface of the passivation layer 170.

The electrical connection bump 180 may physically and/or electrically connect the wiring board 100A to the printed circuit board 300 or the like. The electrical connection bumps 180 are disposed on the openings of the passivation layer 170 and may be electrically connected to the backside wiring layer 132, respectively. Each of the electrical connection bumps 180 may be composed of a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn). More specifically, it may be formed of solder or the like, but this is only an example, and the material is not particularly limited thereto. The electrical connection bump 180 may be a land, a ball, a pin, or the like. The electrical connection bump 180 may be formed in multiple layers or a single layer. When formed in multiple layers, a copper filler and solder may be included, and when formed as a single layer, tin-silver solder or copper may be included, but this is also only an example and is not limited thereto. . The number, spacing, and arrangement form of the electrical connection bumps 180 are not particularly limited, and may be sufficiently modified according to design matters.

Next, the package board 400A according to an example includes a printed circuit board 300 and a wiring board 100A according to an example mounted on the printed circuit board 300. If necessary, a passive component may be surface mounted on the printed circuit board 300 around the wiring board 100A according to an example. A passive component may be embedded in the printed circuit board 300 as well. The printed circuit board 300 may be mounted on a main board of an electronic device through electrical connection bumps 320 such as solder balls. The printed circuit board 300 may be a High Density Interconnection (HDI) type BGA board, but is not limited thereto. The printed circuit board 300 may be omitted as described above, and in this case, depending on the configuration, the wiring board 100A may soon become the package board 400A.

Next, in the semiconductor package 500A according to an example, a first semiconductor chip 221 and a plurality of second semiconductor chips 222 may be disposed in parallel with each other on the second side of the wiring board 100A according to the example. . The plurality of first connection pads 221P of the first semiconductor chip 221 and the plurality of second connection pads 122P of each of the plurality of second semiconductor chips 222 are provided with a wiring board 100A according to an example according to their function. ) May be electrically connected to one or more wiring layers 142 of the connection structure 140, respectively. For example, a plurality of first connection pads 221P of the first semiconductor chip 221 may be electrically connected to a protruding pad among one or more wiring layers 142 through a plurality of first electrical connection metals 221B, respectively. I can. Similarly, the plurality of second connection pads 222P of each of the plurality of second semiconductor chips 222 are electrically connected to the protruding pads among the one or more wiring layers 142 through the plurality of second electrical connection metals 222B, respectively. Can be connected. As a result, it may be electrically connected to the plurality of bridges 120 through one or more wiring layers 142. Each of the first and second electrical connection metals 221B and 222B may be formed of a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn). More specifically, it may be formed of solder or the like, but is not limited thereto.

The first semiconductor chip 221 may be in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated in one chip. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as the base material forming the body. Various circuits may be formed in the body. The first connection pad 221P of the first semiconductor chip 221 is for electrically connecting the first semiconductor chip 221 with other components, and the forming material is copper (Cu) or aluminum (Al). Metallic materials can be used without special restrictions. A passivation film exposing the first connection pad 221P may be formed on the body, and the passivation film may be an oxide film or a nitride film, or a double layer of an oxide film and a nitride film. An insulating film or the like may be further disposed at other required positions.

The second semiconductor chip 222 may also be in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated in one chip. If necessary, the second semiconductor chip 222 may have a form in which a plurality of such integrated circuits (ICs) are stacked. The stacked integrated circuits (ICs) may be electrically connected to each other through a TSV (Through Silicon Via) or the like. The second semiconductor chip 222 may also have a second connection pad 122P for electrically connecting to other components, and at this time, the second connection pad 122P is the wiring board 100A of the second semiconductor chip 222. It means that it is placed at the bottom facing the ).

The first semiconductor chip 221 may be an application specific integrated circuit (ASIC). Alternatively, the first semiconductor chip 221 may be a field programmable gate array (FPGA). Alternatively, the first semiconductor chip 221 may be a chip set of an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA). Alternatively, the first semiconductor chip 221 may be a graphics processing unit (GPU). Alternatively, the first semiconductor chip 221 may be a chip set of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a graphics processing unit (GPU). In addition, the second semiconductor chips 222 may each be a stacked memory such as a high-bandwidth memory (HBM). That is, the first and second semiconductor chips 221 and 122 may be expensive chips each having tens to millions of I/Os, but are not limited thereto. The second semiconductor chips 222 may be disposed in a greater number than the first semiconductor chips 221, and may be disposed around the first semiconductor chips 221, respectively. For example, as shown in FIG. 7, two second semiconductor chips 222 may be disposed on both sides of the first semiconductor chip 221, respectively, but the present invention is not limited thereto.

Meanwhile, the semiconductor package 500A according to an example is an underfill covering at least a portion of the lower side of each of the first semiconductor chip 221 and the plurality of second semiconductor chips 222 on the second side of the wiring board 100A according to the example. Resin 210 may be further disposed. The underfill resin 210 may fill between each of the first semiconductor chip 221 and the plurality of second semiconductor chips 222 and the second side of the wiring board 100A according to an example. In addition, the underfill resin 210 may cover a plurality of first electrical connection metals 221B and a plurality of second electrical connection metals 222B. The first semiconductor chip 221 and the plurality of second semiconductor chips 222 may be fixed through the underfill resin 210. In addition, on the second side of the wiring board 100A according to an example, a molding material covering at least a portion of each of the first semiconductor chip 221 and the plurality of second semiconductor chips 222 may be further disposed, if necessary, If necessary, the molding material as a result of grinding may expose one surface of each of the first semiconductor chip 221 and the plurality of second semiconductor chips 222.

9 to 11 are cross-sectional views schematically illustrating various examples of bridges of the semiconductor package of FIG. 6.

Referring to FIG. 9, the bridge 120 according to an example includes a base layer 120a, an insulating layer 120b disposed on the base layer 120a, a circuit layer 120c disposed on the insulating layer 120b, and It includes a pad layer 120d disposed above the insulating layer 120b. The base layer 120a may control warpage, and in this respect, may include silicon (Si), glass, ceramic, or the like. The insulating layer 120b may include an insulating material. The circuit layer 120c and the pad layer 120d may include a metallic material. The circuit layer 120c may include a wiring part and a via part. The pad layer 120d may be connected to the connection via 143 of the connection structure 140. That is, the bridge 120 according to an example may be a silicon interconnect bridge, a glass interconnect bridge, or a ceramic interconnect bridge.

Referring to FIG. 10, the bridge 120 according to another example is disposed under the through-via 120e penetrating the base layer 120a and the base layer 120a in the bridge 120 according to the above-described example. The pad layer 120f may be further included. The through via 120e and the pad layer 120f may also include a metal material. The pad layer 120f may be connected to the backside via 133. That is, in the bridge 120 according to another example, pad layers 120d and 120f are present on both upper and lower sides, and they are electrically connected to each other through a through via 120e, etc., a silicon interconnect bridge, a glass interconnect bridge, or a ceramic It may be an interconnect bridge or the like. When such a bridge 120 is applied, the above-described backside wiring layer 132 may be connected to the bridge 120 through the backside via 133.

Referring to FIG. 11, the bridge 120 according to another example includes at least one insulating layer 120g, a pattern layer 120h disposed on or in each of the at least one insulating layer 120g, and at least one insulating layer 120g. ) And electrically connecting the pattern layers 120h disposed at different levels to each other may include one or more via layers 120i. The pattern layer 120h and the via layer 120i may be used as circuit layers. The uppermost and lowermost pattern layers 120h may be used as a pad layer, and may be connected to the connection via 143 and the backside via 133, respectively. That is, the bridge 120 according to another example may be an organic interconnect bridge. Even when the bridge 120 is applied, the above-described backside wiring layer 132 may be connected to the bridge 120 through the backside via 133.

Meanwhile, the types of bridges described in FIGS. 9 to 11 may be combined with each other. For example, the bridge 120 described in FIG. 9 and the bridge 120 described in FIG. 10 may be used in combination. Alternatively, the bridge 120 described in FIG. 9 and the bridge 120 described in FIG. 11 may be combined. Alternatively, the bridge 120 described in FIG. 10 and the bridge 120 described in FIG. 11 may be combined. The example is not limited thereto.

FIG. 12 is a process diagram schematically illustrating a functional test process of the wiring board (or package board) used in the semiconductor package of FIG. 6.

Referring to the drawings, first, as a first step (Level 0 Test), a pattern open (break) or short (foreign matter, interlayer connection) of the wiring board 100A is inspected. Through this inspection, it is possible to first check whether there is a problem in the design of the wiring board 100A itself. Next, as a second step (Level 1 Test), BIST (or pBIST) and logic analysis are performed using the first test member 150 and/or the second test member 160. For example, by applying signals and power to the wiring board 100A in an environment similar to the operation of a semiconductor chip, a malfunction that may occur after IC assembly is predicted in advance. Through this, it is possible to prevent KGD disposal by selecting whether or not the wiring board 100A has a malfunction before assembling the semiconductor chip. Next, as a third step (Level 2 Test), complete functional evaluation after the semiconductor chips 221 and 222 are assembled is performed. Through a series of processes, it can be determined whether the wiring board is good.

13 is a flowchart schematically illustrating a functional test process of a wiring board (or package board) used in the semiconductor package of FIG. 6.

Referring to the drawings, as described above, first, it is determined whether the specification is met by going through a first step (Level 0 Test), and if it does, the process proceeds to a second step (Level 1 Test). If it does not match, it is determined whether to proceed with rework. In the second step (Level 1 Test), BIST (or pBIST) and logic analysis are performed, and if they match after the teaming check, the third step (Level 2 Test) is performed. If it doesn't match, you judge again whether to proceed with rework. After that, the semiconductor chip is assembled and the third step (Level 2 Test) is performed, and at this time, it is determined whether it conforms to this through a complete functional test. Through a series of processes, it can be determined whether the wiring board is good.

14 is a schematic cross-sectional view of another example of a semiconductor package.

Referring to the drawings, in the semiconductor package 500B according to another example, a wiring board 400B has a multilayered board shape, and a separate printed circuit board is omitted. That is, the wiring board 400B becomes the package board 400B. On the other hand, if necessary, for example, between the main board and another known printed circuit board may be further disposed under the wiring board (400B). The wiring board 400B according to another example includes a core layer 411, first and second core wiring layers 412a and 412b disposed on one surface and the other surface of the core layer 411, respectively, and one surface of the core layer 411 A plurality of first build-up layers 421 disposed thereon, a plurality of first build-up wiring layers 422 disposed on the plurality of first build-up layers 421, respectively, and disposed on the other surface of the core layer 411 A plurality of second build-up layers 431 and a plurality of second build-up wiring layers 432 respectively disposed on the plurality of second build-up layers 431 are included. The plurality of bridges 120 and the first and second test members 150 and 160 are buried in at least one first build-up insulating layer 421, respectively. For example, the plurality of bridges 120 and the first and second test members 150 and 160 are each disposed in a cavity penetrating at least one of the plurality of first build-up insulating layers 421, respectively, Each of the first build-up insulating layers 421 may be covered with at least one.

The core layer 411 functions as a core of the wiring board 400B and can impart rigidity. The material of the core layer 411 is not particularly limited. For example, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are impregnated in a core material such as glass fiber together with an inorganic filler, for example For example, prepreg or the like can be used. The core layer 411 may be introduced through CCL (Copper Clad Laminate). The core layer 411 may have a higher elastic modulus than the first and second build-up layers 421 and 431. That is, the core layer 411 may have excellent rigidity. The core layer 411 may be thicker than each of the first and second build-up layers 421 and 431.

The first and second build-up layers 421 and 431 may be introduced on both sides of the core layer 411 for build-up. Materials of the first and second build-up layers 421 and 431 are also not particularly limited. For example, an insulating material may be used. In this case, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a core material such as glass fiber or the like are mixed with an inorganic filler. A resin impregnated in, for example, ABF or prepre may be used. The first and second build-up layers 421 and 431 may be equally built up on both sides based on the core layer 411 and thus may have the same number of layers. The number of layers of the first and second build-up layers 421 and 431 is not particularly limited, and may be variously changed according to design.

Passivation layers 440 and 450 may be disposed on the outermost sides of the first and second build-up layers 421 and 431, respectively, and the passivation layers 440 and 450 may protect internal components. Each of the passivation layers 440 and 450 may have a plurality of openings exposing a portion of the wiring layers 422 and 432. The material of the passivation layers 440 and 450 is not particularly limited. For example, an insulating material may be used. In this case, a solder resist may be used as the insulating material. However, it is not limited thereto, and the above-described prepreg, ABF, etc. may be used. Each under bump metal 445 may be disposed on the opening of the passivation layer 440, and the under bump metal 445 may include an under bump metal pad 442 and an under bump metal via 443 of a metal material, respectively. I can. The first semiconductor chip 221 and the plurality of second semiconductor chips 222 may be electrically connected to the under bump metal through a plurality of first and second electrical connection metals 221B and 222B, respectively.

The core wiring layers 412a and 412b and the first and second buildup wiring layers 422 and 432 perform various functions within the wiring board 400B according to the design of the corresponding layer. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. In addition, various pads may be included. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) as forming materials for the core wiring layers 412a and 412b and the first and second buildup wiring layers 422 and 432, respectively , Nickel (Ni), lead (Pb), titanium (Ti), or a conductive material such as an alloy thereof, specifically a metal material may be used.

The core wiring layers 412a and 412b may be electrically connected to each other through a through via 413 penetrating the core layer 411. The through via 413 may be a plated through hole (PHT) in which a conductive material 413a is formed by plating in a conformal shape along a wall surface of a vertical cylindrical through hole. In this case, the space of the through hole between the conductive materials 413a may be filled with the plugging material 413b. As the plugging material 413b, a known plugging material such as an insulating material or conductive ink may be employed. The plurality of first and second build-up wiring layers 422 and 432 are formed through a plurality of first and second wiring vias 423 and 433 passing through the plurality of first and second build-up layers 421 and 431, respectively. They can be electrically connected to each other. The first and second wiring vias 423 and 433 may have a tapered shape in opposite directions. The plurality of first and second build-up wiring layers 422 and 432 may also be electrically connected to the core wiring layers 412a and 412b through the first and second wiring vias 423 and 433. The first and second wiring vias 423 and 433 are respectively copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium. (Ti), or a conductive material such as an alloy thereof, specifically a metal material. The through vias 413 and the first and second wiring vias 423 and 433 perform various functions according to the design of the corresponding layer. For example, it may include a ground via, a power via, a signal via, or the like.

Other descriptions are substantially the same as those described for the semiconductor package according to the example described above, and detailed descriptions will be omitted.

15 is a schematic cross-sectional view of another example of a semiconductor package.

Referring to the drawings, a semiconductor package 500C according to another example includes a wiring board 400C or a wiring board 400C that is substantially the same as the semiconductor package 500B according to another example described above. However, the interposer 250 is additionally disposed on the wiring board 400C, and the third semiconductor chip 223 is disposed on the interposer 250. The interposer 250 may be electrically connected to the under bump metal 445 through a plurality of third electrical connection metals 250B. The interposer 250 may also be fixed by the underfill resin 210. The third connection pad 223P of the third semiconductor chip 223 may be electrically connected to the interposer 250 through the fourth electrical connection metal 223B. The first semiconductor chip 221 may be a CPU, the second semiconductor chip 222 may be a GPU, and the third semiconductor chip 223 may be a stack memory connected by TSV such as HBM, but is limited thereto. no.

Other descriptions are substantially the same as those described for the semiconductor package according to the above example and the semiconductor package according to another example, and detailed descriptions will be omitted.

In the present disclosure, the lower side, the lower side, the lower side, etc. are used to mean the direction toward the mounting surface of the semiconductor package including the organic interposer based on the cross section of the drawing for convenience, and the upper side, the upper side, and the upper surface are used in the opposite direction. I did. However, this defines a direction for convenience of explanation, and it is of course not to say that the scope of the claims is not specifically limited by the description of such direction.

In the present disclosure, the meaning of connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both physically connected and unconnected cases. In addition, expressions such as first and second are used to distinguish one component from another, and do not limit the order and/or importance of the corresponding components. In some cases, without departing from the scope of the rights, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

The expression example used in the present disclosure does not mean the same embodiment as each other, and is provided to emphasize and describe different unique features. However, the examples presented above are not excluded from being implemented in combination with other example features. For example, even if a matter described in a specific example is not described in another example, it may be understood as a description related to another example unless there is a description contradicting or contradicting the matter in another example.

The terms used in the present disclosure are used only to describe an example, and are not intended to limit the present disclosure. In this case, the singular expression includes a plural expression unless it clearly means differently in the context.

Claims (15)

A wiring board including one or more wiring layers; And
A first test member embedded in the wiring board and electrically connected to the one or more wiring layers; Including,
The first test member is an integrated circuit (IC) chip including a built in self test (BIST) circuit,
Wiring board.
The method of claim 1,
A second test member embedded in the wiring board and electrically connected to the one or more wiring layers; It further includes,
The second test member is an IC chip including a logic analysis circuit,
Wiring board.
The method of claim 1,
A bridge buried in the wiring board and electrically connected to the one or more wiring layers; Further comprising,
Wiring board.
The method of claim 3,
The wiring board includes a connection structure including the one or more wiring layers, a frame disposed on the connection structure and having first and second through portions in which the bridge and the first test member are respectively disposed, and on the connection structure A suture material disposed and covering at least a portion of each of the bridge and the first test member and filling at least a portion of each of the first and second through portions,
Wiring board.
The method of claim 4,
The frame includes a plurality of wiring layers electrically connected to each other,
The plurality of wiring layers of the frame are electrically connected to one or more wiring layers of the connection structure,
Wiring board.
The method of claim 5,
The wiring board includes a backside wiring layer disposed on the encapsulant, a plurality of backside vias each penetrating the encapsulant and electrically connecting the backside wiring layer to a lowermost wiring layer among a plurality of wiring layers of the frame, and the encapsulant A passivation layer disposed thereon and covering at least a portion of the backside wiring layer and having a plurality of openings each exposing at least a portion of the backside wiring layer, and the exposed backside wiring layer respectively disposed on a plurality of openings of the passivation layer A plurality of electrical connection bumps, each electrically connected, further comprising,
Wiring board.
The method of claim 6,
Printed circuit board; It further includes,
The wiring board is disposed on the printed circuit board and connected to the printed circuit board through the plurality of electrical connection bumps,
Wiring board.
The method of claim 3,
The wiring board may include a core layer, first and second core wiring layers disposed on one side and the other side of the core layer, respectively, a plurality of first build-up layers disposed on one side of the core layer, and the plurality of first builds. A plurality of first build-up wiring layers each disposed on the up layer, a plurality of second build-up layers disposed on the other surface of the core layer, and a plurality of second build-up wiring layers each disposed on the plurality of second build-up layers , Including,
The one or more wiring layers include the first and second core wiring layers, and the plurality of first and second build-up wiring layers,
The bridge and the first test member are each buried in at least one of the plurality of first build-up layers,
Wiring board.
The method of claim 8,
The thickness of the core layer is thicker than the thickness of each of the first and second buildup layers,
Wiring board.
A wiring board including a wiring board including one or more wiring layers, a first bridge embedded in the wiring board and electrically connected to the one or more wiring layers, and a first test member embedded in the wiring board and electrically connected to the one or more wiring layers Board;
A first semiconductor chip disposed on the wiring board and having a plurality of first connection pads electrically connected to the one or more wiring layers; And
A second semiconductor chip disposed on the wiring board and having a plurality of second connection pads electrically connected to the one or more wiring layers; Including,
At least a portion of the plurality of first connection pads and at least a portion of the plurality of second connection pads are electrically connected to each other through the first bridge,
Semiconductor package.
The method of claim 10,
The wiring board further includes a second test member embedded in the wiring board and electrically connected to the one or more wiring layers,
The first test member is an IC chip including a pBIST circuit,
The second test member is an IC chip including a logic analysis circuit,
Semiconductor package.
The method of claim 10,
A plurality of first electrical connection metals disposed on the wiring board and electrically connecting the plurality of first connection pads to the one or more redistribution layers;
A plurality of second electrical connection metals disposed on the wiring board and electrically connecting the plurality of second connection pads to the one or more redistribution layers; And
An underfill resin disposed on the wiring board and covering at least a portion of each of the plurality of first and second electrical connection metals; Further comprising,
Semiconductor package.
The method of claim 10,
The wiring board further includes a second bridge embedded in the wiring board and electrically connected to the one or more wiring layers,
Semiconductor package.
The method of claim 13,
An interposer disposed on the wiring board and electrically connected to the one or more wiring layers; And
A third semiconductor chip disposed on the interposer and having a plurality of third connection pads electrically connected to the one or more wiring layers through the interposer; It further includes,
At least a portion of the plurality of first connection pads and at least a portion of the plurality of third connection pads are electrically connected to each other through the second bridge,
Semiconductor package.
The method of claim 14,
A plurality of first electrical connection metals disposed on the wiring board and electrically connecting the plurality of first connection pads to the one or more redistribution layers;
A plurality of second electrical connection metals disposed on the wiring board and electrically connecting the plurality of second connection pads to the one or more redistribution layers; And
A plurality of third electrical connection metals disposed on the wiring board and electrically connecting the interposer to the one or more redistribution layers; And
An underfill resin disposed on the wiring board and covering at least a portion of each of the plurality of first to third electrical connection metals; Further comprising,
Semiconductor package.

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